mirror of https://github.com/hak5/openwrt-owl.git
142 lines
3.1 KiB
C
142 lines
3.1 KiB
C
/*
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* Atheros AR934X SoCs built-in NAND flash controller support
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*
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* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/dma-mapping.h>
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#include <linux/etherdevice.h>
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#include <linux/platform_device.h>
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#include <linux/platform/ar934x_nfc.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "dev-nfc.h"
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static struct resource ath79_nfc_resources[2];
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static u64 ar934x_nfc_dmamask = DMA_BIT_MASK(32);
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static struct ar934x_nfc_platform_data ath79_nfc_data;
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static struct platform_device ath79_nfc_device = {
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.name = AR934X_NFC_DRIVER_NAME,
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.id = -1,
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.resource = ath79_nfc_resources,
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.num_resources = ARRAY_SIZE(ath79_nfc_resources),
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.dev = {
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.dma_mask = &ar934x_nfc_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = &ath79_nfc_data,
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},
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};
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static void __init ath79_nfc_init_resource(struct resource res[2],
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unsigned long base,
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unsigned long size,
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int irq)
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{
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memset(res, 0, sizeof(struct resource) * 2);
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res[0].flags = IORESOURCE_MEM;
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res[0].start = base;
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res[0].end = base + size - 1;
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res[1].flags = IORESOURCE_IRQ;
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res[1].start = irq;
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res[1].end = irq;
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}
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static void ar934x_nfc_hw_reset(bool active)
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{
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if (active) {
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ath79_device_reset_set(AR934X_RESET_NANDF);
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udelay(100);
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ath79_device_reset_set(AR934X_RESET_ETH_SWITCH_ANALOG);
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udelay(250);
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} else {
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ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH_ANALOG);
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udelay(250);
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ath79_device_reset_clear(AR934X_RESET_NANDF);
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udelay(100);
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}
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}
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static void ar934x_nfc_setup(void)
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{
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ath79_nfc_data.hw_reset = ar934x_nfc_hw_reset;
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ath79_nfc_init_resource(ath79_nfc_resources,
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AR934X_NFC_BASE, AR934X_NFC_SIZE,
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ATH79_MISC_IRQ(21));
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platform_device_register(&ath79_nfc_device);
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}
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static void qca955x_nfc_hw_reset(bool active)
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{
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if (active) {
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ath79_device_reset_set(QCA955X_RESET_NANDF);
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udelay(250);
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} else {
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ath79_device_reset_clear(QCA955X_RESET_NANDF);
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udelay(100);
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}
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}
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static void qca955x_nfc_setup(void)
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{
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ath79_nfc_data.hw_reset = qca955x_nfc_hw_reset;
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ath79_nfc_init_resource(ath79_nfc_resources,
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QCA955X_NFC_BASE, QCA955X_NFC_SIZE,
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ATH79_MISC_IRQ(21));
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platform_device_register(&ath79_nfc_device);
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}
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void __init ath79_nfc_set_select_chip(void (*f)(int chip_no))
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{
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ath79_nfc_data.select_chip = f;
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}
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void __init ath79_nfc_set_scan_fixup(int (*f)(struct mtd_info *mtd))
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{
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ath79_nfc_data.scan_fixup = f;
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}
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void __init ath79_nfc_set_swap_dma(bool enable)
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{
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ath79_nfc_data.swap_dma = enable;
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}
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void __init ath79_nfc_set_ecc_mode(enum ar934x_nfc_ecc_mode mode)
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{
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ath79_nfc_data.ecc_mode = mode;
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}
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void __init ath79_nfc_set_parts(struct mtd_partition *parts, int nr_parts)
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{
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ath79_nfc_data.parts = parts;
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ath79_nfc_data.nr_parts = nr_parts;
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}
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void __init ath79_register_nfc(void)
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{
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if (soc_is_ar934x())
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ar934x_nfc_setup();
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else if (soc_is_qca955x())
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qca955x_nfc_setup();
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else
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BUG();
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}
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