mirror of https://github.com/hak5/openwrt-owl.git
72 lines
2.4 KiB
Diff
72 lines
2.4 KiB
Diff
From ca56b6fab9cfc0beca2a706193f1c158e124c1f9 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Tue, 26 Apr 2016 12:39:45 -0700
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Subject: [PATCH] clk: bcm2835: Skip PLLC clocks when deciding on a new clock
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parent
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If the firmware had set up a clock to source from PLLC, go along with
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it. But if we're looking for a new parent, we don't want to switch it
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to PLLC because the firmware will force PLLC (and thus the AXI bus
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clock) to different frequencies during over-temp/under-voltage,
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without notification to Linux.
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On my system, this moves the Linux-enabled HDMI state machine and DSI1
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escape clock over to plld_per from pllc_per. EMMC still ends up on
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pllc_per, because the firmware had set it up to use that.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
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---
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drivers/clk/bcm/clk-bcm2835.c | 23 +++++++++++++++++++++++
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1 file changed, 23 insertions(+)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -1020,16 +1020,28 @@ static int bcm2835_clock_set_rate(struct
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return 0;
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}
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+static bool
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+bcm2835_clk_is_pllc(struct clk_hw *hw)
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+{
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+ if (!hw)
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+ return false;
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+
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+ return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0;
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+}
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+
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static int bcm2835_clock_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
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struct clk_hw *parent, *best_parent = NULL;
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+ bool current_parent_is_pllc;
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unsigned long rate, best_rate = 0;
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unsigned long prate, best_prate = 0;
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size_t i;
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u32 div;
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+ current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw));
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+
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/*
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* Select parent clock that results in the closest but lower rate
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*/
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@@ -1037,6 +1049,17 @@ static int bcm2835_clock_determine_rate(
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parent = clk_hw_get_parent_by_index(hw, i);
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if (!parent)
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continue;
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+
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+ /*
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+ * Don't choose a PLLC-derived clock as our parent
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+ * unless it had been manually set that way. PLLC's
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+ * frequency gets adjusted by the firmware due to
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+ * over-temp or under-voltage conditions, without
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+ * prior notification to our clock consumer.
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+ */
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+ if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc)
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+ continue;
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+
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prate = clk_hw_get_rate(parent);
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div = bcm2835_clock_choose_div(hw, req->rate, prate, true);
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rate = bcm2835_clock_rate_from_divisor(clock, prate, div);
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