Commit Graph

4 Commits (ebc71a4d1646eb88cf71e301c085a2dfa5d1efcf)

Author SHA1 Message Date
Jo-Philipp Wich 67e1c87012 all: drop old uci-defaults.sh
Replace former uci-defaults.sh implementation with the uci-defaults-new.sh one
and update all users accordingly.

Signed-off-by: Jo-Philipp Wich <jow@openwrt.org>

SVN-Revision: 47867
2015-12-11 15:26:06 +00:00
Jo-Philipp Wich 08848936dd all: remove redundant board.d/00_model files
Signed-off-by: Jo-Philipp Wich <jow@openwrt.org>

SVN-Revision: 47753
2015-12-04 11:07:06 +00:00
Jo-Philipp Wich 3348308afd arc770: switch from uci-defaults to board.d
Signed-off-by: Jo-Philipp Wich <jow@openwrt.org>

SVN-Revision: 47743
2015-12-03 23:08:02 +00:00
Felix Fietkau 576621f1e3 linux: add support of Synopsys ARC770-based boards
This patch introduces support of new boards with ARC cores.

 [1] Synopsys SDP board
     This is a new-generation development board from Synopsys that
     consists of base-board and CPU tile-board (which might have a real
     ASIC or FPGA with CPU image).
     It sports a lot of DesignWare peripherals like GMAC, USB, SPI, I2C
     etc and is intended to be used for early development of ARC-based
     products.

 [2] nSIM
     This is a virtual board implemented in Synopsys proprietary
     software simulator (even though available for free for open source
     community). This board has only serial port as a peripheral and so
     it is meant to be used for runtime testing which is especially
     useful during bring-up of new tools and platforms.
     What's also important ARC cores are very configurable so there're
     many variations of options like cache sizes, their line lengths,
     additional hardware blocks like multipliers, dividers etc. And this
     board could be used to make sure built software still runs on
     different HW configurations.

Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Jo-Philipp Wich <jow@openwrt.org>
Cc: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

SVN-Revision: 47589
2015-11-22 19:06:07 +00:00