mirror of https://github.com/hak5/openwrt-owl.git
ipq806x: disable i2c device on gsbi4
Patch cherry-picked from the following location: https://chromium-review.googlesource.com/#/c/269931/ Disable the i2c device on gsbi4 and mark gsbi4_h and gsbi4_qup clks as unused. If they are enabled, clock framework will turn them off at end of probe. On ipq806x by design gsbi4_qup, gsbi4_h clks and i2c on gsbi4 are meant for RPM usage. So turning them off in kernel is incorrect. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 45728owl
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1c6d332d8f
commit
f74477de48
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@ -0,0 +1,53 @@
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -46,15 +46,12 @@
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serial@16340000 {
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status = "ok";
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};
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-
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- i2c4: i2c@16380000 {
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- status = "ok";
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-
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- clock-frequency = <200000>;
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-
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- pinctrl-0 = <&i2c4_pins>;
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- pinctrl-names = "default";
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- };
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+ /*
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+ * The i2c device on gsbi4 should not be enabled.
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+ * On ipq806x designs gsbi4 i2c is meant for exclusive
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+ * RPM usage. Turning this on in kernel manifests as
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+ * i2c failure for the RPM.
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+ */
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};
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gsbi5: gsbi@1a200000 {
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--- a/drivers/clk/qcom/gcc-ipq806x.c
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+++ b/drivers/clk/qcom/gcc-ipq806x.c
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@@ -794,7 +794,7 @@ static struct clk_rcg gsbi7_qup_src = {
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.parent_names = gcc_pxo_pll8,
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.num_parents = 2,
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.ops = &clk_rcg_ops,
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- .flags = CLK_SET_PARENT_GATE,
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+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
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},
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},
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};
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@@ -810,7 +810,7 @@ static struct clk_branch gsbi7_qup_clk =
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.parent_names = (const char *[]){ "gsbi7_qup_src" },
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.num_parents = 1,
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.ops = &clk_branch_ops,
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- .flags = CLK_SET_RATE_PARENT,
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+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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},
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},
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};
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@@ -858,7 +858,7 @@ static struct clk_branch gsbi4_h_clk = {
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.hw.init = &(struct clk_init_data){
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.name = "gsbi4_h_clk",
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.ops = &clk_branch_ops,
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- .flags = CLK_IS_ROOT,
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+ .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
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},
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},
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};
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@ -1,6 +1,6 @@
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -112,5 +112,29 @@
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@@ -109,5 +109,29 @@
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sata@29000000 {
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sata@29000000 {
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status = "ok";
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status = "ok";
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};
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};
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@ -38,7 +38,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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spi_pins: spi_pins {
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spi_pins: spi_pins {
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mux {
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mux {
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pins = "gpio18", "gpio19", "gpio21";
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pins = "gpio18", "gpio19", "gpio21";
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@@ -136,5 +152,19 @@
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@@ -133,5 +149,19 @@
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usb30@1 {
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usb30@1 {
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status = "ok";
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status = "ok";
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};
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};
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@ -42,7 +42,7 @@
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};
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};
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gsbi@16300000 {
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gsbi@16300000 {
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@@ -92,6 +118,7 @@
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@@ -89,6 +115,7 @@
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#size-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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spi-max-frequency = <50000000>;
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reg = <0>;
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reg = <0>;
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@ -50,7 +50,7 @@
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partition@0 {
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partition@0 {
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label = "lowlevel_init";
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label = "lowlevel_init";
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@@ -166,5 +193,66 @@
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@@ -163,5 +190,66 @@
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pinctrl-0 = <&pcie2_pins>;
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pinctrl-0 = <&pcie2_pins>;
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pinctrl-names = "default";
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pinctrl-names = "default";
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};
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};
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@ -0,0 +1,53 @@
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -46,15 +46,12 @@
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serial@16340000 {
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status = "ok";
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};
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-
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- i2c4: i2c@16380000 {
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- status = "ok";
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-
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- clock-frequency = <200000>;
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-
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- pinctrl-0 = <&i2c4_pins>;
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- pinctrl-names = "default";
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- };
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+ /*
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+ * The i2c device on gsbi4 should not be enabled.
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+ * On ipq806x designs gsbi4 i2c is meant for exclusive
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+ * RPM usage. Turning this on in kernel manifests as
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+ * i2c failure for the RPM.
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+ */
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};
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gsbi5: gsbi@1a200000 {
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--- a/drivers/clk/qcom/gcc-ipq806x.c
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+++ b/drivers/clk/qcom/gcc-ipq806x.c
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@@ -805,7 +805,7 @@ static struct clk_rcg gsbi7_qup_src = {
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.parent_names = gcc_pxo_pll8,
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.num_parents = 2,
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.ops = &clk_rcg_ops,
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- .flags = CLK_SET_PARENT_GATE,
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+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
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},
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},
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};
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@@ -821,7 +821,7 @@ static struct clk_branch gsbi7_qup_clk =
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.parent_names = (const char *[]){ "gsbi7_qup_src" },
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.num_parents = 1,
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.ops = &clk_branch_ops,
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- .flags = CLK_SET_RATE_PARENT,
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+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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},
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},
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};
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@@ -869,7 +869,7 @@ static struct clk_branch gsbi4_h_clk = {
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.hw.init = &(struct clk_init_data){
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.name = "gsbi4_h_clk",
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.ops = &clk_branch_ops,
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- .flags = CLK_IS_ROOT,
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+ .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
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},
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},
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};
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@ -38,7 +38,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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spi_pins: spi_pins {
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spi_pins: spi_pins {
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mux {
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mux {
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pins = "gpio18", "gpio19", "gpio21";
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pins = "gpio18", "gpio19", "gpio21";
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@@ -112,5 +128,19 @@
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@@ -109,5 +125,19 @@
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sata@29000000 {
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sata@29000000 {
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status = "ok";
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status = "ok";
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};
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};
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@ -42,7 +42,7 @@
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};
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};
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gsbi@16300000 {
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gsbi@16300000 {
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@@ -92,6 +118,7 @@
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@@ -89,6 +115,7 @@
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#size-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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spi-max-frequency = <50000000>;
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reg = <0>;
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reg = <0>;
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@ -50,7 +50,7 @@
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partition@0 {
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partition@0 {
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label = "lowlevel_init";
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label = "lowlevel_init";
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@@ -142,5 +169,66 @@
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@@ -139,5 +166,66 @@
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pinctrl-0 = <&pcie2_pins>;
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pinctrl-0 = <&pcie2_pins>;
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pinctrl-names = "default";
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pinctrl-names = "default";
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};
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};
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