mirror of https://github.com/hak5/openwrt-owl.git
ramips: fold gic patch into mt7621 support patch
All gic patch was doing is removing code added by mt7621 support patch. Signed-off-by: Nikolay Martynov <mar.kolya@gmail.com> SVN-Revision: 47839owl
John Crispin
parent
ed8775d3c3
commit
e4ee2402cb
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@ -22,9 +22,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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create mode 100644 arch/mips/ralink/malta-amon.c
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create mode 100644 arch/mips/ralink/mt7621.c
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diff --git a/arch/mips/include/asm/mach-ralink/irq.h b/arch/mips/include/asm/mach-ralink/irq.h
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new file mode 100644
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index 0000000..4321865
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ralink/irq.h
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@@ -0,0 +1,9 @@
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@ -37,9 +34,6 @@ index 0000000..4321865
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+#include_next <irq.h>
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+
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+#endif
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diff --git a/arch/mips/include/asm/mach-ralink/mt7621.h b/arch/mips/include/asm/mach-ralink/mt7621.h
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new file mode 100644
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index 0000000..21c8dc2
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ralink/mt7621.h
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@@ -0,0 +1,39 @@
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@ -82,8 +76,6 @@ index 0000000..21c8dc2
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+#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
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+
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+#endif
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diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c
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index b8ceee5..b97de1d 100644
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--- a/arch/mips/kernel/mips-cm.c
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+++ b/arch/mips/kernel/mips-cm.c
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@@ -232,7 +232,7 @@ int mips_cm_probe(void)
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@ -104,8 +96,6 @@ index b8ceee5..b97de1d 100644
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/* probe for an L2-only sync region */
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mips_cm_probe_l2sync();
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diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
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index 07d32a4..86c6284 100644
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--- a/arch/mips/kernel/vmlinux.lds.S
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+++ b/arch/mips/kernel/vmlinux.lds.S
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@@ -51,6 +51,7 @@ SECTIONS
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@ -116,8 +106,6 @@ index 07d32a4..86c6284 100644
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TEXT_TEXT
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SCHED_TEXT
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LOCK_TEXT
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diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
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index e9bc8c9..d078e61 100644
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--- a/arch/mips/ralink/Kconfig
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+++ b/arch/mips/ralink/Kconfig
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@@ -12,6 +12,11 @@ config RALINK_ILL_ACC
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@ -142,9 +130,9 @@ index e9bc8c9..d078e61 100644
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+ select SYS_SUPPORTS_MULTITHREADING
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+ select SYS_SUPPORTS_SMP
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+ select SYS_SUPPORTS_MIPS_CMP
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+ select MIPS_GIC
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+ select IRQ_GIC
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+ select HW_HAS_PCI
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+
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endchoice
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choice
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@ -159,8 +147,6 @@ index e9bc8c9..d078e61 100644
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endchoice
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endif
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diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
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index a6c9d00..ca501db 100644
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--- a/arch/mips/ralink/Makefile
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+++ b/arch/mips/ralink/Makefile
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@@ -6,16 +6,21 @@
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@ -175,7 +161,7 @@ index a6c9d00..ca501db 100644
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obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
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+obj-$(CONFIG_IRQ_INTC) += irq.o
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+obj-$(CONFIG_IRQ_GIC) += irq-gic.o
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+obj-$(CONFIG_MIPS_GIC_IPI) += irq-gic.o
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+obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
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+
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obj-$(CONFIG_SOC_RT288X) += rt288x.o
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@ -186,11 +172,9 @@ index a6c9d00..ca501db 100644
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
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index 6d9c8c4..6095fcc 100644
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--- a/arch/mips/ralink/Platform
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+++ b/arch/mips/ralink/Platform
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@@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt
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@@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctr
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#
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load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
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cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
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@ -199,12 +183,9 @@ index 6d9c8c4..6095fcc 100644
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+#
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+load-$(CONFIG_SOC_MT7621) += 0xffffffff80001000
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+cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
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diff --git a/arch/mips/ralink/irq-gic.c b/arch/mips/ralink/irq-gic.c
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new file mode 100644
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index 0000000..f1c541b
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--- /dev/null
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+++ b/arch/mips/ralink/irq-gic.c
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@@ -0,0 +1,268 @@
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@@ -0,0 +1,42 @@
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+#include <linux/init.h>
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+#include <linux/sched.h>
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+#include <linux/slab.h>
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@ -223,248 +204,22 @@ index 0000000..f1c541b
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+#include <asm/irq.h>
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+#include <asm/setup.h>
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+
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+#include <asm/gic.h>
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+#include <asm/mips-cm.h>
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+#include <linux/irqchip/mips-gic.h>
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+
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+#include <asm/mach-ralink/mt7621.h>
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+#define GIC_BASE_ADDR 0x1fbc0000
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+
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+unsigned long _gcmp_base;
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+static int gic_resched_int_base = 56;
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+static int gic_call_int_base = 60;
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+static struct irq_chip *irq_gic;
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+static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS];
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+extern int __init gic_of_init(struct device_node *node,
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+ struct device_node *parent);
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+
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+#if defined(CONFIG_MIPS_MT_SMP)
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+static int gic_resched_int_base;
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+static int gic_call_int_base;
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+
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+#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
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+#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
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+
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+static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
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+unsigned int get_c0_compare_int(void)
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+{
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+ scheduler_ipi();
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static irqreturn_t
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+ipi_call_interrupt(int irq, void *dev_id)
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+{
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+ smp_call_function_interrupt();
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static struct irqaction irq_resched = {
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+ .handler = ipi_resched_interrupt,
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+ .flags = IRQF_DISABLED|IRQF_PERCPU,
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+ .name = "ipi resched"
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+};
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+
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+static struct irqaction irq_call = {
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+ .handler = ipi_call_interrupt,
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+ .flags = IRQF_DISABLED|IRQF_PERCPU,
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+ .name = "ipi call"
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+};
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+
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+#endif
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+
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+static void __init
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+gic_fill_map(void)
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+{
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+ int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
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+ gic_intr_map[i].cpunum = 0;
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+ gic_intr_map[i].pin = GIC_CPU_INT0;
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+ gic_intr_map[i].polarity = GIC_POL_POS;
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+ gic_intr_map[i].trigtype = GIC_TRIG_LEVEL;
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+ gic_intr_map[i].flags = 0;
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+ }
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+
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+#if defined(CONFIG_MIPS_MT_SMP)
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+ {
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+ int cpu;
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+
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+ gic_call_int_base = ARRAY_SIZE(gic_intr_map) - nr_cpu_ids;
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+ gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
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+
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+ i = gic_resched_int_base;
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+
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+ for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
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+ gic_intr_map[i + cpu].cpunum = cpu;
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+ gic_intr_map[i + cpu].pin = GIC_CPU_INT1;
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+ gic_intr_map[i + cpu].trigtype = GIC_TRIG_EDGE;
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+
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+ gic_intr_map[i + cpu + nr_cpu_ids].cpunum = cpu;
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+ gic_intr_map[i + cpu + nr_cpu_ids].pin = GIC_CPU_INT2;
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+ gic_intr_map[i + cpu + nr_cpu_ids].trigtype = GIC_TRIG_EDGE;
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+ }
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+ }
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+#endif
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+}
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+
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+void
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+gic_irq_ack(struct irq_data *d)
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+{
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+ int irq = (d->irq - gic_irq_base);
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+
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+ GIC_CLR_INTR_MASK(irq);
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+
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+ if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
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+ GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
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+}
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+
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+void
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+gic_finish_irq(struct irq_data *d)
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+{
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+ GIC_SET_INTR_MASK(d->irq - gic_irq_base);
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+}
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+
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+void __init
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+gic_platform_init(int irqs, struct irq_chip *irq_controller)
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+{
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+ irq_gic = irq_controller;
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+}
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+
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+static void
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+gic_irqdispatch(void)
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+{
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+ unsigned int irq = gic_get_int();
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+
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+ if (likely(irq < GIC_NUM_INTRS))
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+ do_IRQ(MIPS_GIC_IRQ_BASE + irq);
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+ else {
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+ pr_debug("Spurious GIC Interrupt!\n");
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+ spurious_interrupt();
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+ }
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+
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+}
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+
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+static void
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+vi_timer_irqdispatch(void)
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+{
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+ do_IRQ(cp0_compare_irq);
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+}
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+
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+#if defined(CONFIG_MIPS_MT_SMP)
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+unsigned int
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+plat_ipi_call_int_xlate(unsigned int cpu)
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+{
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+ return GIC_CALL_INT(cpu);
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+}
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+
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+unsigned int
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+plat_ipi_resched_int_xlate(unsigned int cpu)
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+{
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+ return GIC_RESCHED_INT(cpu);
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+}
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+#endif
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+
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+asmlinkage void
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+plat_irq_dispatch(void)
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+{
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+ unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
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+
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+ if (unlikely(!pending)) {
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+ pr_err("Spurious CP0 Interrupt!\n");
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+ spurious_interrupt();
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+ } else {
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+ if (pending & CAUSEF_IP7)
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+ do_IRQ(cp0_compare_irq);
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+
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+ if (pending & (CAUSEF_IP4 | CAUSEF_IP3 | CAUSEF_IP2))
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+ gic_irqdispatch();
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+ }
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+}
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+
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+unsigned int __cpuinit
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+get_c0_compare_int(void)
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+{
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+ return CP0_LEGACY_COMPARE_IRQ;
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+}
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+
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+static int
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+gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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+{
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+ irq_set_chip_and_handler(irq, irq_gic,
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+#if defined(CONFIG_MIPS_MT_SMP)
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+ (hw >= gic_resched_int_base) ?
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+ handle_percpu_irq :
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+#endif
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+ handle_level_irq);
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+
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+ return 0;
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+}
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+
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+static const struct irq_domain_ops irq_domain_ops = {
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+ .xlate = irq_domain_xlate_onecell,
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+ .map = gic_map,
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+};
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+
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+static int __init
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+of_gic_init(struct device_node *node,
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+ struct device_node *parent)
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+{
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+ struct irq_domain *domain;
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+ struct resource gcmp = { 0 }, gic = { 0 };
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+ unsigned int gic_rev;
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+ int i;
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+
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+ if (of_address_to_resource(node, 0, &gic))
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+ panic("Failed to get gic memory range");
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+ if (request_mem_region(gic.start, resource_size(&gic),
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+ gic.name) < 0)
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+ panic("Failed to request gic memory");
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+ if (of_address_to_resource(node, 2, &gcmp))
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+ panic("Failed to get gic memory range");
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+ if (request_mem_region(gcmp.start, resource_size(&gcmp),
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+ gcmp.name) < 0)
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+ panic("Failed to request gcmp memory");
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+
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+ _gcmp_base = (unsigned long) ioremap_nocache(gcmp.start, resource_size(&gcmp));
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+ if (!_gcmp_base)
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+ panic("Failed to remap gcmp memory\n");
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+
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+ /* tell the gcmp where to find the gic */
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+ write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK);
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+ gic_present = 1;
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+ if (cpu_has_vint) {
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+ set_vi_handler(2, gic_irqdispatch);
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+ set_vi_handler(3, gic_irqdispatch);
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+ set_vi_handler(4, gic_irqdispatch);
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+ set_vi_handler(7, vi_timer_irqdispatch);
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+ }
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+
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+ gic_fill_map();
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+
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+ gic_init(gic.start, resource_size(&gic), gic_intr_map,
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+ ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
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+
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+ GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
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+ pr_info("gic: revision %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
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+
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+ domain = irq_domain_add_legacy(node, GIC_NUM_INTRS, MIPS_GIC_IRQ_BASE,
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+ 0, &irq_domain_ops, NULL);
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+ if (!domain)
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+ panic("Failed to add irqdomain");
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+
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+#if defined(CONFIG_MIPS_MT_SMP)
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+ for (i = 0; i < nr_cpu_ids; i++) {
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+ setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
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+ setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
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+ }
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+#endif
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+
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+ change_c0_status(ST0_IM, STATUSF_IP7 | STATUSF_IP4 | STATUSF_IP3 |
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+ STATUSF_IP2);
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+ return 0;
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+ return gic_get_c0_compare_int();
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+}
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+
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+static struct of_device_id __initdata of_irq_ids[] = {
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+ { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
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+ { .compatible = "ralink,mt7621-gic", .data = of_gic_init },
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+ { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
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+ { .compatible = "mti,gic", .data = gic_of_init },
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+ {},
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+};
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+
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@ -473,9 +228,6 @@ index 0000000..f1c541b
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+{
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+ of_irq_init(of_irq_ids);
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+}
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diff --git a/arch/mips/ralink/malta-amon.c b/arch/mips/ralink/malta-amon.c
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new file mode 100644
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index 0000000..1e47844
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--- /dev/null
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+++ b/arch/mips/ralink/malta-amon.c
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@@ -0,0 +1,81 @@
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@ -560,9 +312,6 @@ index 0000000..1e47844
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+ smp_rmb(); /* Target will be updating flags soon */
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+ pr_debug("launch: cpu%d gone!\n", cpu);
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+}
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diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
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new file mode 100644
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index 0000000..c28743b
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--- /dev/null
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+++ b/arch/mips/ralink/mt7621.c
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@@ -0,0 +1,209 @@
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@ -775,6 +524,14 @@ index 0000000..c28743b
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+ if (!register_vsmp_smp_ops())
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+ return;
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+}
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--
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1.7.10.4
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--- a/drivers/irqchip/irq-mips-gic.c
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+++ b/drivers/irqchip/irq-mips-gic.c
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@@ -862,7 +862,7 @@ void __init gic_init(unsigned long gic_b
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__gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL);
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}
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-static int __init gic_of_init(struct device_node *node,
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+int __init gic_of_init(struct device_node *node,
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struct device_node *parent)
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{
|
||||
struct resource res;
|
||||
|
|
|
|||
|
|
@ -1,305 +0,0 @@
|
|||
From 7b042645c1bd6407b1f7d9aa5785868e7e14b860 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Mon, 7 Dec 2015 18:40:16 +0100
|
||||
Subject: [PATCH 53/53] gic
|
||||
|
||||
---
|
||||
arch/mips/ralink/Kconfig | 1 +
|
||||
arch/mips/ralink/Makefile | 2 +-
|
||||
arch/mips/ralink/irq-gic.c | 212 ++------------------------------------------
|
||||
3 files changed, 11 insertions(+), 204 deletions(-)
|
||||
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -51,9 +51,9 @@
|
||||
select SYS_SUPPORTS_MULTITHREADING
|
||||
select SYS_SUPPORTS_SMP
|
||||
select SYS_SUPPORTS_MIPS_CMP
|
||||
+ select MIPS_GIC
|
||||
select IRQ_GIC
|
||||
select HW_HAS_PCI
|
||||
-
|
||||
endchoice
|
||||
|
||||
choice
|
||||
--- a/arch/mips/ralink/Makefile
|
||||
+++ b/arch/mips/ralink/Makefile
|
||||
@@ -13,7 +13,7 @@
|
||||
obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
|
||||
|
||||
obj-$(CONFIG_IRQ_INTC) += irq.o
|
||||
-obj-$(CONFIG_IRQ_GIC) += irq-gic.o
|
||||
+obj-$(CONFIG_MIPS_GIC_IPI) += irq-gic.o
|
||||
obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
|
||||
|
||||
obj-$(CONFIG_SOC_RT288X) += rt288x.o
|
||||
--- a/arch/mips/ralink/irq-gic.c
|
||||
+++ b/arch/mips/ralink/irq-gic.c
|
||||
@@ -16,248 +16,22 @@
|
||||
#include <asm/irq.h>
|
||||
#include <asm/setup.h>
|
||||
|
||||
-#include <asm/gic.h>
|
||||
+#include <asm/mips-cm.h>
|
||||
+#include <linux/irqchip/mips-gic.h>
|
||||
|
||||
#include <asm/mach-ralink/mt7621.h>
|
||||
-#define GIC_BASE_ADDR 0x1fbc0000
|
||||
|
||||
-unsigned long _gcmp_base;
|
||||
-static int gic_resched_int_base = 56;
|
||||
-static int gic_call_int_base = 60;
|
||||
-static struct irq_chip *irq_gic;
|
||||
-static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS];
|
||||
-
|
||||
-#if defined(CONFIG_MIPS_MT_SMP)
|
||||
-static int gic_resched_int_base;
|
||||
-static int gic_call_int_base;
|
||||
+extern int __init gic_of_init(struct device_node *node,
|
||||
+ struct device_node *parent);
|
||||
|
||||
-#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
|
||||
-#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
|
||||
-
|
||||
-static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
|
||||
-{
|
||||
- scheduler_ipi();
|
||||
-
|
||||
- return IRQ_HANDLED;
|
||||
-}
|
||||
-
|
||||
-static irqreturn_t
|
||||
-ipi_call_interrupt(int irq, void *dev_id)
|
||||
-{
|
||||
- smp_call_function_interrupt();
|
||||
-
|
||||
- return IRQ_HANDLED;
|
||||
-}
|
||||
-
|
||||
-static struct irqaction irq_resched = {
|
||||
- .handler = ipi_resched_interrupt,
|
||||
- .flags = IRQF_DISABLED|IRQF_PERCPU,
|
||||
- .name = "ipi resched"
|
||||
-};
|
||||
-
|
||||
-static struct irqaction irq_call = {
|
||||
- .handler = ipi_call_interrupt,
|
||||
- .flags = IRQF_DISABLED|IRQF_PERCPU,
|
||||
- .name = "ipi call"
|
||||
-};
|
||||
-
|
||||
-#endif
|
||||
-
|
||||
-static void __init
|
||||
-gic_fill_map(void)
|
||||
-{
|
||||
- int i;
|
||||
-
|
||||
- for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
|
||||
- gic_intr_map[i].cpunum = 0;
|
||||
- gic_intr_map[i].pin = GIC_CPU_INT0;
|
||||
- gic_intr_map[i].polarity = GIC_POL_POS;
|
||||
- gic_intr_map[i].trigtype = GIC_TRIG_LEVEL;
|
||||
- gic_intr_map[i].flags = 0;
|
||||
- }
|
||||
-
|
||||
-#if defined(CONFIG_MIPS_MT_SMP)
|
||||
- {
|
||||
- int cpu;
|
||||
-
|
||||
- gic_call_int_base = ARRAY_SIZE(gic_intr_map) - nr_cpu_ids;
|
||||
- gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
|
||||
-
|
||||
- i = gic_resched_int_base;
|
||||
-
|
||||
- for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
|
||||
- gic_intr_map[i + cpu].cpunum = cpu;
|
||||
- gic_intr_map[i + cpu].pin = GIC_CPU_INT1;
|
||||
- gic_intr_map[i + cpu].trigtype = GIC_TRIG_EDGE;
|
||||
-
|
||||
- gic_intr_map[i + cpu + nr_cpu_ids].cpunum = cpu;
|
||||
- gic_intr_map[i + cpu + nr_cpu_ids].pin = GIC_CPU_INT2;
|
||||
- gic_intr_map[i + cpu + nr_cpu_ids].trigtype = GIC_TRIG_EDGE;
|
||||
- }
|
||||
- }
|
||||
-#endif
|
||||
-}
|
||||
-
|
||||
-void
|
||||
-gic_irq_ack(struct irq_data *d)
|
||||
-{
|
||||
- int irq = (d->irq - gic_irq_base);
|
||||
-
|
||||
- GIC_CLR_INTR_MASK(irq);
|
||||
-
|
||||
- if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
|
||||
- GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
|
||||
-}
|
||||
-
|
||||
-void
|
||||
-gic_finish_irq(struct irq_data *d)
|
||||
-{
|
||||
- GIC_SET_INTR_MASK(d->irq - gic_irq_base);
|
||||
-}
|
||||
-
|
||||
-void __init
|
||||
-gic_platform_init(int irqs, struct irq_chip *irq_controller)
|
||||
-{
|
||||
- irq_gic = irq_controller;
|
||||
-}
|
||||
-
|
||||
-static void
|
||||
-gic_irqdispatch(void)
|
||||
-{
|
||||
- unsigned int irq = gic_get_int();
|
||||
-
|
||||
- if (likely(irq < GIC_NUM_INTRS))
|
||||
- do_IRQ(MIPS_GIC_IRQ_BASE + irq);
|
||||
- else {
|
||||
- pr_debug("Spurious GIC Interrupt!\n");
|
||||
- spurious_interrupt();
|
||||
- }
|
||||
-
|
||||
-}
|
||||
-
|
||||
-static void
|
||||
-vi_timer_irqdispatch(void)
|
||||
-{
|
||||
- do_IRQ(cp0_compare_irq);
|
||||
-}
|
||||
-
|
||||
-#if defined(CONFIG_MIPS_MT_SMP)
|
||||
-unsigned int
|
||||
-plat_ipi_call_int_xlate(unsigned int cpu)
|
||||
-{
|
||||
- return GIC_CALL_INT(cpu);
|
||||
-}
|
||||
-
|
||||
-unsigned int
|
||||
-plat_ipi_resched_int_xlate(unsigned int cpu)
|
||||
-{
|
||||
- return GIC_RESCHED_INT(cpu);
|
||||
-}
|
||||
-#endif
|
||||
-
|
||||
-asmlinkage void
|
||||
-plat_irq_dispatch(void)
|
||||
-{
|
||||
- unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
|
||||
-
|
||||
- if (unlikely(!pending)) {
|
||||
- pr_err("Spurious CP0 Interrupt!\n");
|
||||
- spurious_interrupt();
|
||||
- } else {
|
||||
- if (pending & CAUSEF_IP7)
|
||||
- do_IRQ(cp0_compare_irq);
|
||||
-
|
||||
- if (pending & (CAUSEF_IP4 | CAUSEF_IP3 | CAUSEF_IP2))
|
||||
- gic_irqdispatch();
|
||||
- }
|
||||
-}
|
||||
-
|
||||
-unsigned int __cpuinit
|
||||
-get_c0_compare_int(void)
|
||||
-{
|
||||
- return CP0_LEGACY_COMPARE_IRQ;
|
||||
-}
|
||||
-
|
||||
-static int
|
||||
-gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
|
||||
-{
|
||||
- irq_set_chip_and_handler(irq, irq_gic,
|
||||
-#if defined(CONFIG_MIPS_MT_SMP)
|
||||
- (hw >= gic_resched_int_base) ?
|
||||
- handle_percpu_irq :
|
||||
-#endif
|
||||
- handle_level_irq);
|
||||
-
|
||||
- return 0;
|
||||
-}
|
||||
-
|
||||
-static const struct irq_domain_ops irq_domain_ops = {
|
||||
- .xlate = irq_domain_xlate_onecell,
|
||||
- .map = gic_map,
|
||||
-};
|
||||
-
|
||||
-static int __init
|
||||
-of_gic_init(struct device_node *node,
|
||||
- struct device_node *parent)
|
||||
+unsigned int get_c0_compare_int(void)
|
||||
{
|
||||
- struct irq_domain *domain;
|
||||
- struct resource gcmp = { 0 }, gic = { 0 };
|
||||
- unsigned int gic_rev;
|
||||
- int i;
|
||||
-
|
||||
- if (of_address_to_resource(node, 0, &gic))
|
||||
- panic("Failed to get gic memory range");
|
||||
- if (request_mem_region(gic.start, resource_size(&gic),
|
||||
- gic.name) < 0)
|
||||
- panic("Failed to request gic memory");
|
||||
- if (of_address_to_resource(node, 2, &gcmp))
|
||||
- panic("Failed to get gic memory range");
|
||||
- if (request_mem_region(gcmp.start, resource_size(&gcmp),
|
||||
- gcmp.name) < 0)
|
||||
- panic("Failed to request gcmp memory");
|
||||
-
|
||||
- _gcmp_base = (unsigned long) ioremap_nocache(gcmp.start, resource_size(&gcmp));
|
||||
- if (!_gcmp_base)
|
||||
- panic("Failed to remap gcmp memory\n");
|
||||
-
|
||||
- /* tell the gcmp where to find the gic */
|
||||
- write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK);
|
||||
- gic_present = 1;
|
||||
- if (cpu_has_vint) {
|
||||
- set_vi_handler(2, gic_irqdispatch);
|
||||
- set_vi_handler(3, gic_irqdispatch);
|
||||
- set_vi_handler(4, gic_irqdispatch);
|
||||
- set_vi_handler(7, vi_timer_irqdispatch);
|
||||
- }
|
||||
-
|
||||
- gic_fill_map();
|
||||
-
|
||||
- gic_init(gic.start, resource_size(&gic), gic_intr_map,
|
||||
- ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
|
||||
-
|
||||
- GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
|
||||
- pr_info("gic: revision %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
|
||||
-
|
||||
- domain = irq_domain_add_legacy(node, GIC_NUM_INTRS, MIPS_GIC_IRQ_BASE,
|
||||
- 0, &irq_domain_ops, NULL);
|
||||
- if (!domain)
|
||||
- panic("Failed to add irqdomain");
|
||||
-
|
||||
-#if defined(CONFIG_MIPS_MT_SMP)
|
||||
- for (i = 0; i < nr_cpu_ids; i++) {
|
||||
- setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
|
||||
- setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
|
||||
- }
|
||||
-#endif
|
||||
-
|
||||
- change_c0_status(ST0_IM, STATUSF_IP7 | STATUSF_IP4 | STATUSF_IP3 |
|
||||
- STATUSF_IP2);
|
||||
- return 0;
|
||||
+ return gic_get_c0_compare_int();
|
||||
}
|
||||
|
||||
static struct of_device_id __initdata of_irq_ids[] = {
|
||||
- { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
|
||||
- { .compatible = "ralink,mt7621-gic", .data = of_gic_init },
|
||||
+ { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
|
||||
+ { .compatible = "mti,gic", .data = gic_of_init },
|
||||
{},
|
||||
};
|
||||
|
||||
--- a/drivers/irqchip/irq-mips-gic.c
|
||||
+++ b/drivers/irqchip/irq-mips-gic.c
|
||||
@@ -864,7 +864,7 @@
|
||||
__gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL);
|
||||
}
|
||||
|
||||
-static int __init gic_of_init(struct device_node *node,
|
||||
+int __init gic_of_init(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
struct resource res;
|
||||
Loading…
Reference in New Issue