mirror of https://github.com/hak5/openwrt-owl.git
ar71xx: add kernel support for the OpenMesh OM2Pv4/-HSv4
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>owl
parent
019276a9c6
commit
e1b50457b0
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@ -1013,6 +1013,7 @@ config ATH79_MACH_OM2P
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bool "OpenMesh OM2P board support"
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select SOC_AR724X
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select SOC_AR933X
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select SOC_QCA953X
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select ATH79_DEV_AP9X_PCI if PCI
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select ATH79_DEV_ETH
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select ATH79_DEV_GPIO_BUTTONS
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@ -46,6 +46,16 @@
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#define OM2P_LC_GPIO_LED_WAN 17
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#define OM2P_LC_GPIO_BTN_RESET 12
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#define OM2Pv4_GPIO_LED_POWER 0
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#define OM2Pv4_GPIO_LED_GREEN 2
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#define OM2Pv4_GPIO_LED_RED 4
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#define OM2Pv4_GPIO_LED_YELLOW 3
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#define OM2Pv4_GPIO_LED_LAN 14
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#define OM2Pv4_GPIO_LED_WAN 13
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#define OM2Pv4_GPIO_BTN_RESET 1
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#define OM2P_WMAC_CALDATA_OFFSET 0x1000
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static struct flash_platform_data om2p_flash_data = {
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.type = "s25sl12800",
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.name = "ar7240-nor0",
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@ -224,3 +234,87 @@ static void __init om2p_hs_setup(void)
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MIPS_MACHINE(ATH79_MACH_OM2P_HS, "OM2P-HS", "OpenMesh OM2P HS", om2p_hs_setup);
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MIPS_MACHINE(ATH79_MACH_OM2P_HSv2, "OM2P-HSv2", "OpenMesh OM2P HSv2", om2p_hs_setup);
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MIPS_MACHINE(ATH79_MACH_OM2P_HSv3, "OM2P-HSv3", "OpenMesh OM2P HSv3", om2p_hs_setup);
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static struct flash_platform_data om2pv4_flash_data = {
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.type = "s25sl12800",
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};
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static struct gpio_led om2pv4_leds_gpio[] __initdata = {
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{
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.name = "om2p:blue:power",
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.gpio = OM2Pv4_GPIO_LED_POWER,
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.active_low = 1,
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}, {
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.name = "om2p:red:wifi",
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.gpio = OM2Pv4_GPIO_LED_RED,
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.active_low = 1,
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}, {
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.name = "om2p:yellow:wifi",
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.gpio = OM2Pv4_GPIO_LED_YELLOW,
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.active_low = 1,
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}, {
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.name = "om2p:green:wifi",
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.gpio = OM2Pv4_GPIO_LED_GREEN,
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.active_low = 1,
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}, {
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.name = "om2p:blue:lan",
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.gpio = OM2Pv4_GPIO_LED_LAN,
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.active_low = 1,
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}, {
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.name = "om2p:blue:wan",
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.gpio = OM2Pv4_GPIO_LED_WAN,
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.active_low = 1,
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}
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};
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static struct gpio_keys_button om2pv4_gpio_keys[] __initdata = {
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{
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.desc = "reset",
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.type = EV_KEY,
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.code = KEY_RESTART,
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.debounce_interval = OM2P_KEYS_DEBOUNCE_INTERVAL,
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.gpio = OM2Pv4_GPIO_BTN_RESET,
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.active_low = 1,
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}
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};
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static void __init om2pv4_setup(void)
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{
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u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
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u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN);
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u8 *art = (u8 *)KSEG1ADDR(0x1ffc0000);
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u8 wmac[6];
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ath79_register_m25p80(&om2pv4_flash_data);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(om2pv4_leds_gpio),
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om2pv4_leds_gpio);
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ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(om2pv4_gpio_keys),
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om2pv4_gpio_keys);
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ath79_init_mac(wmac, art, 0x02);
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ath79_register_wmac(art + OM2P_WMAC_CALDATA_OFFSET, wmac);
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ath79_setup_ar933x_phy4_switch(false, false);
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ath79_register_mdio(0, 0x0);
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/* LAN */
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ath79_switch_data.phy4_mii_en = 1;
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
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ath79_eth0_data.duplex = DUPLEX_FULL;
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ath79_eth0_data.speed = SPEED_100;
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ath79_eth0_data.phy_mask = BIT(4);
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ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
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ath79_register_eth(0);
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/* WAN */
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ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
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ath79_eth1_data.duplex = DUPLEX_FULL;
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ath79_switch_data.phy_poll_mask |= BIT(4);
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ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
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ath79_register_eth(1);
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}
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MIPS_MACHINE(ATH79_MACH_OM2Pv4, "OM2Pv4", "OpenMesh OM2Pv4", om2pv4_setup);
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MIPS_MACHINE(ATH79_MACH_OM2P_HSv4, "OM2P-HSv4", "OpenMesh OM2P HSv4", om2pv4_setup);
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@ -130,9 +130,11 @@ enum ath79_mach_type {
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ATH79_MACH_NBG6716, /* Zyxel NBG6716 */
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ATH79_MACH_OM2P, /* OpenMesh OM2P */
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ATH79_MACH_OM2Pv2, /* OpenMesh OM2Pv2 */
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ATH79_MACH_OM2Pv4, /* OpenMesh OM2Pv4 */
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ATH79_MACH_OM2P_HS, /* OpenMesh OM2P-HS */
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ATH79_MACH_OM2P_HSv2, /* OpenMesh OM2P-HSv2 */
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ATH79_MACH_OM2P_HSv3, /* OpenMesh OM2P-HSv3 */
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ATH79_MACH_OM2P_HSv4, /* OpenMesh OM2P-HSv4 */
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ATH79_MACH_OM2P_LC, /* OpenMesh OM2P-LC */
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ATH79_MACH_OM5P, /* OpenMesh OM5P */
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ATH79_MACH_OM5P_AC, /* OpenMesh OM5P-AC */
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