mirror of https://github.com/hak5/openwrt-owl.git
ipq40xx: OpenMesh A42 overhaul
Sort the soc entries in the dts by address and use dtc labels whenever possible. Adjust the DTS files, the OpenMesh A42 is actually an IPQ4018 and not an IPQ4019. Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com> Signed-off-by: Christian Lamparter <chunkeey@gmail.com>openwrt-18.06
Christian Lamparter
Mathias Kresin
parent
a44d435c1d
commit
d0e9621404
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@ -47,6 +47,14 @@
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};
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soc {
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mdio@90000 {
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status = "okay";
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};
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ess-psgmii@98000 {
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status = "okay";
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};
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tcsr@194b000 {
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/* select hostmode */
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compatible = "qcom,tcsr";
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@ -55,87 +63,34 @@
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status = "ok";
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};
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ess_tcsr@1953000 {
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compatible = "qcom,tcsr";
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reg = <0x1953000 0x1000>;
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qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
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};
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tcsr@1949000 {
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compatible = "qcom,tcsr";
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reg = <0x1949000 0x100>;
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qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
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};
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ess_tcsr@1953000 {
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compatible = "qcom,tcsr";
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reg = <0x1953000 0x1000>;
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qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
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};
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tcsr@1957000 {
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compatible = "qcom,tcsr";
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reg = <0x1957000 0x100>;
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qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
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};
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pinctrl@1000000 {
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serial_pins: serial_pinmux {
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mux {
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pins = "gpio60", "gpio61";
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function = "blsp_uart0";
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bias-disable;
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};
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};
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spi_0_pins: spi_0_pinmux {
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pinmux {
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function = "blsp_spi0";
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pins = "gpio55", "gpio56", "gpio57";
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};
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pinmux_cs {
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function = "gpio";
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pins = "gpio54";
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};
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pinconf {
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pins = "gpio55", "gpio56", "gpio57";
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drive-strength = <12>;
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bias-disable;
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};
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pinconf_cs {
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pins = "gpio54";
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drive-strength = <2>;
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bias-disable;
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output-high;
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};
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};
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};
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blsp_dma: dma@7884000 {
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usb2: usb2@60f8800 {
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status = "ok";
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};
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spi_0: spi@78b5000 {
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "ok";
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cs-gpios = <&tlmm 54 0>;
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m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <24000000>;
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/* partitions are passed via bootloader */
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};
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};
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serial@78af000 {
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pinctrl-0 = <&serial_pins>;
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pinctrl-names = "default";
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status = "ok";
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};
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cryptobam: dma@8e04000 {
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status = "ok";
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};
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crypto@8e3a000 {
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status = "ok";
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};
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@ -144,39 +99,13 @@
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status = "ok";
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};
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usb2_hs_phy: hsphy@a8000 {
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status = "ok";
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};
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usb2: usb2@60f8800 {
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status = "ok";
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};
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mdio@90000 {
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status = "okay";
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};
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ess-switch@c000000 {
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status = "okay";
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};
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ess-psgmii@98000 {
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status = "okay";
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};
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edma@c080000 {
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status = "okay";
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};
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wifi@a000000 {
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status = "okay";
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qcom,ath10k-calibration-variant = "OM-A42";
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};
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wifi@a800000 {
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status = "okay";
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qcom,ath10k-calibration-variant = "OM-A42";
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};
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};
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gpio-keys {
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@ -227,6 +156,56 @@
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};
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};
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&tlmm {
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serial_pins: serial_pinmux {
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mux {
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pins = "gpio60", "gpio61";
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function = "blsp_uart0";
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bias-disable;
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};
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};
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spi_0_pins: spi_0_pinmux {
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pin {
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function = "blsp_spi0";
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pins = "gpio55", "gpio56", "gpio57";
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drive-strength = <12>;
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bias-disable;
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};
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pin_cs {
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function = "gpio";
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pins = "gpio54";
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drive-strength = <2>;
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bias-disable;
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output-high;
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};
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};
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};
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&blsp_dma {
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status = "ok";
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};
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&spi_0 {
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "ok";
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cs-gpios = <&tlmm 54 0>;
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m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <24000000>;
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/* partitions are passed via bootloader */
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};
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};
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&cryptobam {
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status = "ok";
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};
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&gmac0 {
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qcom,phy_mdio_addr = <4>;
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qcom,poll_required = <1>;
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@ -242,3 +221,17 @@
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qcom,forced_duplex = <1>;
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vlan_tag = <1 0x10>;
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};
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&usb2_hs_phy {
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status = "ok";
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};
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&wifi0 {
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status = "okay";
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qcom,ath10k-calibration-variant = "OM-A42";
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};
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&wifi1 {
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status = "okay";
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qcom,ath10k-calibration-variant = "OM-A42";
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};
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@ -61,7 +61,7 @@ TARGET_DEVICES += glinet_gl-b1300
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define Device/openmesh_a42
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$(call Device/FitImageLzma)
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DEVICE_DTS := qcom-ipq4019-a42
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DEVICE_DTS := qcom-ipq4018-a42
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BLOCKSIZE := 64k
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SUPPORTED_DEVICES := openmesh,a42
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DEVICE_TITLE := OpenMesh A42
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@ -14,7 +14,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
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qcom-apq8074-dragonboard.dtb \
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qcom-apq8084-ifc6540.dtb \
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qcom-apq8084-mtp.dtb \
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+ qcom-ipq4019-a42.dtb \
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+ qcom-ipq4018-a42.dtb \
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qcom-ipq4019-ap.dk01.1-c1.dtb \
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+ qcom-ipq4019-ap.dk04.1-c1.dtb \
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+ qcom-ipq4019-fritz4040.dtb \
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