mirror of https://github.com/hak5/openwrt-owl.git
remove the brcm-2.4 target, it will no longer be supported in future releases. please use brcm47xx with broadcom-wl instead
SVN-Revision: 21946owl
Felix Fietkau
parent
812f026323
commit
cfbefb4b87
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@ -1,25 +0,0 @@
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#
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# Copyright (C) 2006 OpenWrt.org
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#
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# This is free software, licensed under the GNU General Public License v2.
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# See /LICENSE for more information.
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#
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include $(TOPDIR)/rules.mk
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ARCH:=mipsel
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BOARD:=brcm-2.4
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BOARDNAME:=Broadcom BCM947xx/953xx [2.4]
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FEATURES:=squashfs
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KERNEL:=2.4
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include $(INCLUDE_DIR)/target.mk
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DEFAULT_PACKAGES += kmod-switch kmod-diag nvram
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define Target/Description
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Build firmware images for Broadcom based routers
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(e.g. Linksys WRT54G(S), Asus WL-500g, Motorola WR850G)
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endef
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$(eval $(call BuildTarget))
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@ -1,5 +0,0 @@
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define Package/base-files/install-target
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rm -f $(1)/etc/config/network
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endef
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@ -1,28 +0,0 @@
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#!/bin/sh
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# Copyright (C) 2006 OpenWrt.org
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set_led() {
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local led="$1"
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local state="$2"
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[ -f "/proc/diag/led/$1" ] && echo "$state" > "/proc/diag/led/$1"
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}
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set_state() {
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case "$1" in
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preinit)
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set_led dmz 1
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set_led diag 1
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set_led power 0
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;;
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failsafe)
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set_led diag f
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set_led power f
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set_led dmz f
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;;
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done)
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set_led dmz 0
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set_led diag 0
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set_led power 1
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;;
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esac
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}
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@ -1,248 +0,0 @@
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#!/bin/sh /etc/rc.common
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# Copyright (C) 2006 OpenWrt.org
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START=05
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start() {
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[ -e /etc/config/network ] && {
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local batch
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config_cb() {
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case "$1" in
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switch)
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option_cb() {
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case "$1" in
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vlan[0-9]|vlan1[0-5])
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local id="${1#vlan}"
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local ports="${2%\*}"
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append batch "delete network.eth0.${1}${N}"
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append batch "set network.eth0_${id}=switch_vlan${N}"
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append batch "set network.eth0_${id}.device=eth0${N}"
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append batch "set network.eth0_${id}.vlan=${id}${N}"
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append batch "set network.eth0_${id}.ports='${ports}'${N}"
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;;
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esac
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}
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;;
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switch_vlan)
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option_cb() { :; }
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batch=""
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;;
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esac
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}
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config_load network
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[ -n "$batch" ] && {
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logger -t netconfig "migrating switch config to new format ..."
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echo "$batch${N}commit network" | uci batch
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}
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exit 0
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}
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mkdir -p /etc/config
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(
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if grep -E 'mtd0: 000(6|a)0000' /proc/mtd 2>&- >&-; then
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# WGT634u
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echo boardtype=wgt634u
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else
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strings "$(find_mtd_part nvram)"
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fi
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) | awk '
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function p(cfgname, name) {
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if (c[name] != "") print " option " cfgname " \"" c[name] "\""
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}
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function vlan(id, name) {
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if (c[name] != "") {
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print "config switch_vlan eth0_" id
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print " option device \"eth0\""
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print " option vlan " id
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print " option ports \"" c[name] "\""
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print ""
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}
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}
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function macinc(mac, maca, i, result) {
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split(mac, maca, ":")
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for (i = 1; i <= 6; i++) maca[i] = "0x" maca[i]
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if (++maca[6] > 0xff) {
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maca[5]++
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maca[6] = 0
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}
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for (i = 1; i <= 6; i++) {
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if (i != 1) result = result ":"
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result = result sprintf("%02x", maca[i])
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}
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return result
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}
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BEGIN {
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FS="="
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c["lan_ifname"]="eth0.0"
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c["wan_ifname"]="eth0.1"
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c["vlan0ports"]="1 2 3 4 5"
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c["vlan1ports"]="0 5"
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getline < "/proc/diag/model"
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model=$0
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for (i = 0; i < 6; i++) {
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if (mac_check != "") mac_check = mac_check ":"
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mac_check = mac_check "[0-9a-fA-F][0-9a-fA-F]"
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}
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}
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($1 == "boardnum") || ($1 == "boardtype") || ($1 == "boardflags") || ($1 ~ /macaddr/) {
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nvram[$1] = $2
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}
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END {
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if ((model == "ASUS WL-HDD") || (model == "ASUS WL-300g") || (model == "Linksys WAP54G V1")) {
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c["wan_ifname"] = ""
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c["lan_ifname"] = "eth1"
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}
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if (model == "ASUS WL-330gE") {
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c["wan_ifname"] = ""
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c["lan_ifname"] = "eth0"
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c["vlan0ports"] = ""
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c["vlan1ports"] = ""
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}
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if ((model == "ASUS WL-500g") || (model == "Microsoft MN-700")) {
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c["wan_ifname"] = "eth1"
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c["lan_ifname"] = "eth0"
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}
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if ((model == "ASUS WL-500g Premium V2") || (model == "Dell TrueMobile 2300 v2") || (model == "Buffalo WHR-G125")) {
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c["vlan0ports"] = "0 1 2 3 5"
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c["vlan1ports"] = "4 5"
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}
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if (model == "Dell TrueMobile 2300") {
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c["lan_ifname"] = "eth0"
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c["wan_ifname"] = "eth1"
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c["vlan0ports"] = "0 1 2 3 4 5u"
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c["vlan1ports"] = ""
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}
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if (nvram["boardtype"] == "bcm94710r4") {
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# Toshiba WRC-1000
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c["lan_ifname"] = "eth0"
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c["wan_ifname"] = "eth1"
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}
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if ((nvram["boardtype"] == "wgt634u") || (nvram["boardtype"] == "0x0467")) {
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c["vlan0ports"] = "0 1 2 3 5"
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c["vlan1ports"] = "4 5"
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}
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if ((nvram["boardtype"] == "0x042f") || (nvram["boardtype"] == "0x0472")) {
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if (nvram["boardnum"] == "45") {
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# WL-500gP
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c["vlan0ports"] = "1 2 3 4 5"
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c["vlan1ports"] = "0 5"
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} else {
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# Generic BCM94704
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c["vlan0ports"] = "0 1 2 3 4 5u"
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c["vlan1ports"] = ""
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c["lan_ifname"] = "eth0"
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c["wan_ifname"] = "eth1"
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# MAC addresses on 4704 tend to be screwed up. Add a workaround here
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if (nvram["et0macaddr"] ~ mac_check) {
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c["lan_macaddr"] = nvram["et0macaddr"]
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c["wan_macaddr"] = macinc(c["lan_macaddr"])
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}
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}
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}
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# Buffalo WBR-B11 and Buffalo WBR-G54
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if (nvram["boardtype"] == "bcm94710ap") {
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c["vlan0ports"] = "0 1 2 3 4 5u"
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c["vlan1ports"] = ""
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c["lan_ifname"] = "eth0"
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c["wan_ifname"] = "eth1"
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}
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# generic broadcom 4705/4785 processor with 5397 switch?
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# EXCEPT Linksys WRT300N V1.1
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if ((nvram["boardtype"] == "0x478") && \
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(model != "Linksys WRT300N V1.1")) {
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c["vlan0ports"] = "1 2 3 4 8*"
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c["vlan1ports"] = "0 8"
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}
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# WAP54G
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if ((nvram["boardnum"] == "2") || \
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(nvram["boardnum"] == "1024")) {
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c["lan_ifname"]="eth0"
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c["wan_ifname"]=""
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}
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# Sitecom WL-105b
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if ((nvram["boardum"] == "2") && \
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(nvram["GemtekPmonVer"] == "1")) {
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c["lan_ifname"]="eth0"
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c["wan_ifname"]=""
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}
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# ASUS WL-700gE
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# These are actually same as defaults above. For some reason this script applies
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# Generic BCM94704 settings instead so we revert to proper settings here.
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# Hopefully someone will fix this properly soon.
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if (model == "ASUS WL-700gE") {
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c["lan_ifname"]="eth0.0"
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c["wan_ifname"]="eth0.1"
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c["vlan0ports"]="1 2 3 4 5"
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c["vlan1ports"]="0 5"
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}
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if (model == "Motorola WR850G V2/V3") {
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c["vlan0ports"]="0 1 2 3 5"
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c["vlan1ports"]="4 5"
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}
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if (model == "ASUS WL-500W") {
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c["lan_ifname"] = "eth0"
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c["wan_ifname"] = "eth1"
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c["vlan0ports"] = "0 1 2 3 4 5u"
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c["vlan1ports"] = ""
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}
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if (model == "OvisLink WL-1600GL") {
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c["lan_ifname"] = "eth0.0"
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c["wan_ifname"] = "eth0.1"
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c["vlan0ports"] = "0 1 2 3 5"
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c["vlan1ports"] = "4 5"
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}
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if (c["vlan0ports"] || c["vlan1ports"]) {
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print "#### VLAN configuration "
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print "config switch eth0"
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print " option enable 1"
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print ""
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vlan(0, "vlan0ports")
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vlan(1, "vlan1ports")
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}
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print "#### Loopback configuration"
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print "config interface loopback"
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print " option ifname \"lo\""
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print " option proto static"
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print " option ipaddr 127.0.0.1"
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print " option netmask 255.0.0.0"
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print ""
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print ""
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print "#### LAN configuration"
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print "config interface lan"
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print " option type bridge"
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p("ifname", "lan_ifname")
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p("macaddr", "lan_macaddr")
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print " option proto static"
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print " option ipaddr 192.168.1.1"
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print " option netmask 255.255.255.0"
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print ""
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print ""
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if (c["wan_ifname"]) {
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print "#### WAN configuration"
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print "config interface wan"
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p("ifname", "wan_ifname")
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p("macaddr", "wan_macaddr")
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print " option proto dhcp"
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} else {
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print "#### WAN configuration (disabled)"
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print "#config interface wan"
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print "# option proto dhcp"
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}
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}' > /etc/config/network
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}
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@ -1,33 +0,0 @@
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#!/bin/sh /etc/rc.common
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# Copyright (C) 2010 OpenWrt.org
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START=41
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boot() {
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[ -d /sys/class/ieee80211 ] || exit
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commit=0
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fixup_wmac() {
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local cfg="$1"
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local cfmac
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config_get cfmac "$cfg" macaddr
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[ "$cfmac" != "00:90:4c:5f:00:2a" ] || {
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local nvmac="$(nvram get il0macaddr 2>/dev/null)"
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[ -n "$nvmac" ] && [ "$nvmac != "$cfmac ] && {
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uci set wireless.$cfg.macaddr="$nvmac"
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commit=1
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}
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}
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}
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config_load wireless
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config_foreach fixup_wmac wifi-device
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[ "$commit" = 1 ] && uci commit wireless
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}
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start() { :; }
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stop() { :; }
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@ -1,9 +0,0 @@
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#!/bin/sh
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init_hotplug_failsafe() {
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echo '/sbin/hotplug.failsafe' > /proc/sys/kernel/hotplug
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}
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boot_hook_add preinit_main init_hotplug_failsafe
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@ -1,37 +0,0 @@
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#!/bin/sh
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set_preinit_iface() {
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ifname=eth0
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insmod diag
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# hardware specific overrides
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case "$(cat /proc/diag/model)" in
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"Linksys WAP54G V1") ifname=eth1;;
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"ASUS WL-HDD") ifname=eth1;;
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"ASUS WL-300g") ifname=eth1;;
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"ASUS (unknown, BCM4702)") ifname=eth1;;
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"Sitecom WL-105b") ifname=eth1;;
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esac
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ifconfig $ifname 0.0.0.0 up
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}
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check_module () {
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module="$1"; shift; params="$*"
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insmod "$module" "$params"
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sleep 1
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grep "^$module" /proc/modules
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return $?
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}
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init_iface() {
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check_module tg3
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insmod switch-core
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check_module switch-robo || check_module switch-adm || {
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check_module bcm57xx activate_gpio=0x4 && cpu_port="8u*"
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} || rmmod switch-core
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}
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boot_hook_add preinit_main set_preinit_iface
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boot_hook_add preinit_main init_iface
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@ -1,15 +0,0 @@
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#!/bin/sh
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failsafe_ip() {
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[ -d /proc/switch/eth0 ] && [ "$ifname" = "eth0" ] && {
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ifconfig eth0 0.0.0.0 down
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echo "0 1 2 3 4 ${cpu_port:-5u*}" > /proc/switch/eth0/vlan/0/ports
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}
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[ -n "$pi_ifname" ] && grep -q "$pi_ifname" /proc/net/dev && {
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ifconfig $pi_ifname $pi_ip netmask $pi_netmask broadcast $pi_broadcast up
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}
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}
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boot_hook_add failsafe failsafe_ip
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@ -1,6 +0,0 @@
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#!/bin/sh
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do_mount_procfs() {
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mount none /proc -t proc
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}
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@ -1,39 +0,0 @@
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#!/bin/sh
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port_net_echo() {
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[ -n "$pi_ifname" ] && grep -q "$pi_ifname" /proc/net/dev && {
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if [ "$pi_preinit_net_messages" = "y" ] || [ "$pi_failsafe_net_message" = "true" ] && [ "$pi_preinit_no_failsafe_netmsg" != "y" ]; then
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netmsg $pi_broadcast "$1"
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fi
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}
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}
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preinit_ip_deconfig() {
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if [ -z "$pi_ifname" ]; then
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ifconfig $ifname 0.0.0.0 down
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else
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grep -q "$pi_ifname" /proc/net/dev && {
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ifconfig $pi_ifname 0.0.0.0 down
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}
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fi
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}
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preinit_net_echo() {
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preinit_ip
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[ -d /proc/switch/eth0 ] && [ "$pi_ifname" = "eth0" ] && {
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echo 1 > /proc/switch/eth0/reset
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# this would be easier if we blasted the message across all ports
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# but we don't want packets leaking across interfaces
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for port in $(seq 0 4); do {
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echo "$port ${cpu_port:-5u*}" > /proc/switch/eth0/vlan/0/ports
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port_net_echo $1
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}; done
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echo "0 ${cpu_port:-5u*}" > /proc/switch/eth0/vlan/0/ports
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} || port_net_echo $1
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}
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@ -1,12 +0,0 @@
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#!/bin/sh
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indicate_failsafe() {
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preinit_net_echo() {
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port_net_echo $1
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}
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echo "- failsafe -"
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preinit_net_echo "Entering Failsafe!\n"
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indicate_failsafe_led
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}
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|
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@ -1,14 +0,0 @@
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#!/bin/sh
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. /etc/functions.sh
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set_boot_wait() {
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[ -x "/usr/sbin/nvram" ] && {
|
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[ "$(nvram get boot_wait)" != "on" ] && {
|
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nvram set boot_wait=on
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nvram commit
|
||||
}
|
||||
}
|
||||
}
|
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|
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boot_hook_add failsafe set_boot_wait
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|
|
@ -1,16 +0,0 @@
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PART_NAME=linux
|
||||
|
||||
platform_check_image() {
|
||||
[ "$ARGC" -gt 1 ] && return 1
|
||||
|
||||
case "$(get_magic_word "$1")" in
|
||||
# .trx files
|
||||
4844) return 0;;
|
||||
*)
|
||||
echo "Invalid image type. Please use only .trx files"
|
||||
return 1
|
||||
;;
|
||||
esac
|
||||
}
|
||||
|
||||
# use default for platform_do_upgrade()
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
#!/bin/sh
|
||||
case "$1" in
|
||||
button) kill -USR1 1;;
|
||||
esac
|
||||
|
|
@ -1,376 +0,0 @@
|
|||
# CONFIG_60XX_WDT is not set
|
||||
# CONFIG_6PACK is not set
|
||||
# CONFIG_8139CP is not set
|
||||
# CONFIG_8139_OLD_RX_RESET is not set
|
||||
# CONFIG_8139TOO_8129 is not set
|
||||
# CONFIG_8139TOO is not set
|
||||
# CONFIG_8139TOO_PIO is not set
|
||||
# CONFIG_8139TOO_TUNE_TWISTER is not set
|
||||
# CONFIG_ACQUIRE_WDT is not set
|
||||
# CONFIG_ADAPTEC_STARFIRE is not set
|
||||
# CONFIG_ADVANTECH_WDT is not set
|
||||
# CONFIG_AIRO_CS is not set
|
||||
# CONFIG_AIRO is not set
|
||||
# CONFIG_ALIM1535_WDT is not set
|
||||
# CONFIG_ALIM7101_WDT is not set
|
||||
# CONFIG_AMD74XX_OVERRIDE is not set
|
||||
# CONFIG_AMD8111_ETH is not set
|
||||
# CONFIG_APRICOT is not set
|
||||
# CONFIG_ATM is not set
|
||||
# CONFIG_AX25_DAMA_SLAVE is not set
|
||||
CONFIG_AX25=m
|
||||
CONFIG_B44=y
|
||||
# CONFIG_BAYCOM_EPP is not set
|
||||
# CONFIG_BAYCOM_PAR is not set
|
||||
# CONFIG_BAYCOM_SER_FDX is not set
|
||||
# CONFIG_BAYCOM_SER_HDX is not set
|
||||
CONFIG_BCM4310=y
|
||||
CONFIG_BCM4704=y
|
||||
CONFIG_BCM4710=y
|
||||
CONFIG_BCM5365=y
|
||||
CONFIG_BCM947XX=y
|
||||
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
|
||||
# CONFIG_BLK_DEV_ADMA100 is not set
|
||||
CONFIG_BLK_DEV_AEC62XX=m
|
||||
# CONFIG_BLK_DEV_ALI15X3 is not set
|
||||
# CONFIG_BLK_DEV_AMD74XX is not set
|
||||
# CONFIG_BLK_DEV_ATARAID_HPT is not set
|
||||
# CONFIG_BLK_DEV_ATARAID is not set
|
||||
# CONFIG_BLK_DEV_ATARAID_MEDLEY is not set
|
||||
# CONFIG_BLK_DEV_ATARAID_PDC is not set
|
||||
# CONFIG_BLK_DEV_ATARAID_SII is not set
|
||||
# CONFIG_BLK_DEV_ATIIXP is not set
|
||||
# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
|
||||
# CONFIG_BLK_DEV_CMD640 is not set
|
||||
# CONFIG_BLK_DEV_CMD64X is not set
|
||||
# CONFIG_BLK_DEV_CS5530 is not set
|
||||
# CONFIG_BLK_DEV_CY82C693 is not set
|
||||
# CONFIG_BLK_DEV_DELKIN is not set
|
||||
# CONFIG_BLK_DEV_GENERIC is not set
|
||||
# CONFIG_BLK_DEV_HD_IDE is not set
|
||||
# CONFIG_BLK_DEV_HPT34X is not set
|
||||
# CONFIG_BLK_DEV_HPT366 is not set
|
||||
# CONFIG_BLK_DEV_IDECD is not set
|
||||
# CONFIG_BLK_DEV_IDECS is not set
|
||||
CONFIG_BLK_DEV_IDEDISK=m
|
||||
# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
|
||||
CONFIG_BLK_DEV_IDEDMA_PCI=y
|
||||
CONFIG_BLK_DEV_IDEDMA=y
|
||||
# CONFIG_BLK_DEV_IDEFLOPPY is not set
|
||||
CONFIG_BLK_DEV_IDE=m
|
||||
CONFIG_BLK_DEV_IDEPCI=y
|
||||
# CONFIG_BLK_DEV_IDE_SATA is not set
|
||||
# CONFIG_BLK_DEV_IDESCSI is not set
|
||||
# CONFIG_BLK_DEV_IDETAPE is not set
|
||||
# CONFIG_BLK_DEV_ISAPNP is not set
|
||||
# CONFIG_BLK_DEV_NS87415 is not set
|
||||
CONFIG_BLK_DEV_OFFBOARD=y
|
||||
# CONFIG_BLK_DEV_OPTI621 is not set
|
||||
# CONFIG_BLK_DEV_PDC202XX_NEW is not set
|
||||
CONFIG_BLK_DEV_PDC202XX_OLD=m
|
||||
CONFIG_BLK_DEV_PDC202XX=y
|
||||
# CONFIG_BLK_DEV_PIIX is not set
|
||||
# CONFIG_BLK_DEV_RZ1000 is not set
|
||||
# CONFIG_BLK_DEV_SC1200 is not set
|
||||
# CONFIG_BLK_DEV_SIIMAGE is not set
|
||||
# CONFIG_BLK_DEV_SIS5513 is not set
|
||||
# CONFIG_BLK_DEV_SLC90E66 is not set
|
||||
# CONFIG_BLK_DEV_SVWKS is not set
|
||||
# CONFIG_BLK_DEV_TRIFLEX is not set
|
||||
# CONFIG_BLK_DEV_TRM290 is not set
|
||||
# CONFIG_BLK_DEV_VIA82CXXX is not set
|
||||
CONFIG_BLUEZ_BNEP=m
|
||||
CONFIG_BLUEZ_BNEP_MC_FILTER=y
|
||||
CONFIG_BLUEZ_BNEP_PROTO_FILTER=y
|
||||
# CONFIG_BLUEZ_HCIBFUSB is not set
|
||||
# CONFIG_BLUEZ_HCIBLUECARD is not set
|
||||
# CONFIG_BLUEZ_HCIBT3C is not set
|
||||
# CONFIG_BLUEZ_HCIBTUART is not set
|
||||
# CONFIG_BLUEZ_HCIDTL1 is not set
|
||||
CONFIG_BLUEZ_HCIUART_BCSP_TXCRC=y
|
||||
CONFIG_BLUEZ_HCIUART_BCSP=y
|
||||
CONFIG_BLUEZ_HCIUART_H4=y
|
||||
CONFIG_BLUEZ_HCIUART=m
|
||||
CONFIG_BLUEZ_HCIUSB=m
|
||||
CONFIG_BLUEZ_HCIUSB_SCO=y
|
||||
# CONFIG_BLUEZ_HCIVHCI is not set
|
||||
CONFIG_BLUEZ_L2CAP=m
|
||||
CONFIG_BLUEZ=m
|
||||
CONFIG_BLUEZ_RFCOMM=m
|
||||
CONFIG_BLUEZ_RFCOMM_TTY=y
|
||||
CONFIG_BLUEZ_SCO=m
|
||||
# CONFIG_BPQETHER is not set
|
||||
CONFIG_CARDBUS=y
|
||||
# CONFIG_CMDLINE_BOOL is not set
|
||||
CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 init=/etc/preinit noinitrd console=ttyS0,115200"
|
||||
CONFIG_CRC32=y
|
||||
# CONFIG_CS89x0 is not set
|
||||
# CONFIG_DE4X5 is not set
|
||||
# CONFIG_DGRS is not set
|
||||
# CONFIG_DM9102 is not set
|
||||
# CONFIG_DMA_NONPCI is not set
|
||||
# CONFIG_E100 is not set
|
||||
# CONFIG_EEPRO100 is not set
|
||||
# CONFIG_EEPRO100_PIO is not set
|
||||
# CONFIG_EPIC100 is not set
|
||||
# CONFIG_ES3210 is not set
|
||||
# CONFIG_EUROTECH_WDT is not set
|
||||
# CONFIG_FEALNX is not set
|
||||
CONFIG_FILTER=y
|
||||
# CONFIG_FORCEDETH is not set
|
||||
CONFIG_HAMRADIO=y
|
||||
# CONFIG_HAPPYMEAL is not set
|
||||
# CONFIG_HP100 is not set
|
||||
# CONFIG_HPT34X_AUTODMA is not set
|
||||
# CONFIG_I2C_PARPORT is not set
|
||||
# CONFIG_I2O_BLOCK is not set
|
||||
# CONFIG_I2O is not set
|
||||
# CONFIG_I2O_LAN is not set
|
||||
# CONFIG_I2O_PCI is not set
|
||||
# CONFIG_I2O_PROC is not set
|
||||
# CONFIG_I2O_SCSI is not set
|
||||
# CONFIG_I810_TCO is not set
|
||||
# CONFIG_I82092 is not set
|
||||
# CONFIG_I82365 is not set
|
||||
# CONFIG_IB700_WDT is not set
|
||||
# CONFIG_IDE_CHIPSETS is not set
|
||||
# CONFIG_IDEDISK_MULTI_MODE is not set
|
||||
CONFIG_IDEDISK_STROKE=y
|
||||
CONFIG_IDEDMA_AUTO=y
|
||||
CONFIG_IDEDMA_IVB=y
|
||||
# CONFIG_IDEDMA_ONLYDISK is not set
|
||||
CONFIG_IDEDMA_PCI_AUTO=y
|
||||
# CONFIG_IDEDMA_PCI_WIP is not set
|
||||
CONFIG_IDE=m
|
||||
# CONFIG_IDEPCI_SHARE_IRQ is not set
|
||||
# CONFIG_IDE_TASK_IOCTL is not set
|
||||
# CONFIG_IEEE1394 is not set
|
||||
# CONFIG_IP_VS is not set
|
||||
# CONFIG_LAN_SAA9730 is not set
|
||||
# CONFIG_LNE390 is not set
|
||||
CONFIG_LOG_BUF_SHIFT=0
|
||||
# CONFIG_LP_CONSOLE is not set
|
||||
# CONFIG_MACHZ_WDT is not set
|
||||
# CONFIG_MIDI_EMU10K1 is not set
|
||||
# CONFIG_MIDI_VIA82CXXX is not set
|
||||
CONFIG_MINIX_FS=m
|
||||
CONFIG_MIPS_BRCM=y
|
||||
# CONFIG_MIXCOMWD is not set
|
||||
CONFIG_MKISS=m
|
||||
CONFIG_MSDOS_FS=m
|
||||
CONFIG_MTD_BCM947XX=y
|
||||
CONFIG_MTD_CFI_B1=y
|
||||
CONFIG_MTD_CFI_SSTSTD=y
|
||||
CONFIG_MTD_SFLASH=y
|
||||
# CONFIG_NATSEMI is not set
|
||||
# CONFIG_NE2K_PCI is not set
|
||||
# CONFIG_NE3210 is not set
|
||||
CONFIG_NET_PCI=y
|
||||
# CONFIG_NET_PCMCIA is not set
|
||||
# CONFIG_NETROM is not set
|
||||
CONFIG_NET_SCH_ESFQ=m
|
||||
CONFIG_NET_WIRELESS=y
|
||||
CONFIG_NEW_IRQ=y
|
||||
CONFIG_NEW_TIME_C=y
|
||||
# CONFIG_PARPORT_1284 is not set
|
||||
# CONFIG_PARPORT_AMIGA is not set
|
||||
# CONFIG_PARPORT_ATARI is not set
|
||||
# CONFIG_PARPORT_GSC is not set
|
||||
# CONFIG_PARPORT_IP22 is not set
|
||||
CONFIG_PARPORT=m
|
||||
# CONFIG_PARPORT_MFC3 is not set
|
||||
# CONFIG_PARPORT_OTHER is not set
|
||||
# CONFIG_PARPORT_PC is not set
|
||||
CONFIG_PARPORT_SPLINK=m
|
||||
# CONFIG_PARPORT_SUNBPP is not set
|
||||
CONFIG_PCI_AUTO=y
|
||||
# CONFIG_PCI_HERMES is not set
|
||||
# CONFIG_PCI_NAMES is not set
|
||||
# CONFIG_PCI_NEW is not set
|
||||
CONFIG_PCI=y
|
||||
# CONFIG_PCMCIA_ATMEL is not set
|
||||
# CONFIG_PCMCIA_HERMES is not set
|
||||
CONFIG_PCMCIA=m
|
||||
CONFIG_PCMCIA_SERIAL_CS=m
|
||||
# CONFIG_PCNET32 is not set
|
||||
# CONFIG_PCWATCHDOG is not set
|
||||
CONFIG_PDC202XX_BURST=y
|
||||
# CONFIG_PDC202XX_FORCE is not set
|
||||
# CONFIG_PLX_HERMES is not set
|
||||
CONFIG_PPDEV=m
|
||||
CONFIG_PRINTER=m
|
||||
# CONFIG_RADIO_GEMTEK_PCI is not set
|
||||
# CONFIG_RADIO_MAESTRO is not set
|
||||
# CONFIG_RADIO_MAXIRADIO is not set
|
||||
# CONFIG_RADIO_MIROPCM20 is not set
|
||||
# CONFIG_REMOTE_DEBUG is not set
|
||||
# CONFIG_ROSE is not set
|
||||
# CONFIG_SC1200_WDT is not set
|
||||
# CONFIG_SC520_WDT is not set
|
||||
# CONFIG_SCC_DELAY is not set
|
||||
# CONFIG_SCC_TRXECHO is not set
|
||||
# CONFIG_SCSI_CPQFCTS is not set
|
||||
# CONFIG_SCSI_DC390T is not set
|
||||
# CONFIG_SCSI_IMM is not set
|
||||
# CONFIG_SCSI_NCR53C8XX is not set
|
||||
# CONFIG_SCSI_PCMCIA is not set
|
||||
# CONFIG_SCSI_PPA is not set
|
||||
# CONFIG_SCSI_QLOGIC_1280 is not set
|
||||
# CONFIG_SCSI_QLOGIC_FC is not set
|
||||
# CONFIG_SCSI_QLOGIC_ISP is not set
|
||||
# CONFIG_SCSI_SYM53C8XX_2 is not set
|
||||
# CONFIG_SCSI_SYM53C8XX is not set
|
||||
# CONFIG_SCx200_WDT is not set
|
||||
# CONFIG_SIS900 is not set
|
||||
CONFIG_SOFT_WATCHDOG=m
|
||||
# CONFIG_SOUND_AD1980 is not set
|
||||
# CONFIG_SOUND_ALI5455 is not set
|
||||
# CONFIG_SOUND_BT878 is not set
|
||||
# CONFIG_SOUND_CMPCI is not set
|
||||
# CONFIG_SOUND_CS4281 is not set
|
||||
# CONFIG_SOUND_EMU10K1 is not set
|
||||
# CONFIG_SOUND_ES1370 is not set
|
||||
# CONFIG_SOUND_ES1371 is not set
|
||||
# CONFIG_SOUND_ESSSOLO1 is not set
|
||||
# CONFIG_SOUND_FORTE is not set
|
||||
# CONFIG_SOUND_FUSION is not set
|
||||
# CONFIG_SOUND_ICH is not set
|
||||
CONFIG_SOUND=m
|
||||
# CONFIG_SOUND_MAESTRO3 is not set
|
||||
# CONFIG_SOUND_MAESTRO is not set
|
||||
# CONFIG_SOUNDMODEM is not set
|
||||
# CONFIG_SOUND_MSNDCLAS is not set
|
||||
# CONFIG_SOUND_MSNDPIN is not set
|
||||
# CONFIG_SOUND_OSS is not set
|
||||
# CONFIG_SOUND_RME96XX is not set
|
||||
# CONFIG_SOUND_SONICVIBES is not set
|
||||
# CONFIG_SOUND_TRIDENT is not set
|
||||
# CONFIG_SOUND_TVMIXER is not set
|
||||
# CONFIG_SOUND_VIA82CXXX is not set
|
||||
# CONFIG_SOUND_WM97XX is not set
|
||||
# CONFIG_SUNDANCE is not set
|
||||
# CONFIG_SUNDANCE_MMIO is not set
|
||||
# CONFIG_SYNCLINK_CS is not set
|
||||
# CONFIG_TCIC is not set
|
||||
# CONFIG_TIPAR is not set
|
||||
# CONFIG_TLAN is not set
|
||||
# CONFIG_TMD_HERMES is not set
|
||||
# CONFIG_TULIP is not set
|
||||
# CONFIG_TUNER_3036 is not set
|
||||
CONFIG_USB_ACM=m
|
||||
# CONFIG_USB_AIPTEK is not set
|
||||
CONFIG_USB_AUDIO=m
|
||||
# CONFIG_USB_AUERSWALD is not set
|
||||
# CONFIG_USB_BANDWIDTH is not set
|
||||
# CONFIG_USB_BRLVGER is not set
|
||||
# CONFIG_USB_CATC is not set
|
||||
# CONFIG_USB_CDCETHER is not set
|
||||
# CONFIG_USB_DABUSB is not set
|
||||
# CONFIG_USB_DC2XX is not set
|
||||
# CONFIG_USB_DEBUG is not set
|
||||
CONFIG_USB_DEVICEFS=y
|
||||
# CONFIG_USB_DSBR is not set
|
||||
CONFIG_USB_EHCI_HCD=m
|
||||
# CONFIG_USB_EMI26 is not set
|
||||
# CONFIG_USB_HIDDEV is not set
|
||||
# CONFIG_USB_HIDINPUT is not set
|
||||
# CONFIG_USB_HID is not set
|
||||
# CONFIG_USB_HPUSBSCSI is not set
|
||||
# CONFIG_USB_IBMCAM is not set
|
||||
# CONFIG_USB_KAWETH is not set
|
||||
# CONFIG_USB_KBD is not set
|
||||
# CONFIG_USB_KBTAB is not set
|
||||
# CONFIG_USB_KONICAWC is not set
|
||||
# CONFIG_USB_LCD is not set
|
||||
CONFIG_USB=m
|
||||
# CONFIG_USB_MDC800 is not set
|
||||
# CONFIG_USB_MICROTEK is not set
|
||||
# CONFIG_USB_MIDI is not set
|
||||
# CONFIG_USB_MOUSE is not set
|
||||
CONFIG_USB_OHCI=m
|
||||
# CONFIG_USB_OV511 is not set
|
||||
# CONFIG_USB_PEGASUS is not set
|
||||
# CONFIG_USB_POWERMATE is not set
|
||||
CONFIG_USB_PRINTER=m
|
||||
CONFIG_USB_PWC=m
|
||||
# CONFIG_USB_RIO500 is not set
|
||||
# CONFIG_USB_RTL8150 is not set
|
||||
# CONFIG_USB_SCANNER is not set
|
||||
# CONFIG_USB_SE401 is not set
|
||||
CONFIG_USB_SERIAL_BELKIN=m
|
||||
# CONFIG_USB_SERIAL_CYBERJACK is not set
|
||||
# CONFIG_USB_SERIAL_DEBUG is not set
|
||||
# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
|
||||
# CONFIG_USB_SERIAL_EDGEPORT is not set
|
||||
# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
|
||||
# CONFIG_USB_SERIAL_EMPEG is not set
|
||||
CONFIG_USB_SERIAL_FTDI_SIO=m
|
||||
CONFIG_USB_SERIAL_GENERIC=y
|
||||
# CONFIG_USB_SERIAL_IPAQ is not set
|
||||
# CONFIG_USB_SERIAL_IR is not set
|
||||
CONFIG_USB_SERIAL_KEYSPAN=m
|
||||
CONFIG_USB_SERIAL_KEYSPAN_MPR=y
|
||||
# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
|
||||
CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
|
||||
CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
|
||||
CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
|
||||
CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
|
||||
CONFIG_USB_SERIAL_KEYSPAN_USA19=y
|
||||
CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
|
||||
CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
|
||||
CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
|
||||
CONFIG_USB_SERIAL_KEYSPAN_USA28=y
|
||||
CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
|
||||
CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
|
||||
# CONFIG_USB_SERIAL_KLSI is not set
|
||||
# CONFIG_USB_SERIAL_KOBIL_SCT is not set
|
||||
CONFIG_USB_SERIAL=m
|
||||
CONFIG_USB_SERIAL_MCT_U232=m
|
||||
# CONFIG_USB_SERIAL_OMNINET is not set
|
||||
CONFIG_USB_SERIAL_PL2303=m
|
||||
# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
|
||||
CONFIG_USB_SERIAL_VISOR=m
|
||||
# CONFIG_USB_SERIAL_WHITEHEAT is not set
|
||||
# CONFIG_USB_SERIAL_XIRCOM is not set
|
||||
CONFIG_USB_STORAGE_DATAFAB=y
|
||||
# CONFIG_USB_STORAGE_DEBUG is not set
|
||||
CONFIG_USB_STORAGE_DPCM=y
|
||||
CONFIG_USB_STORAGE_FREECOM=y
|
||||
CONFIG_USB_STORAGE_HP8200e=y
|
||||
# CONFIG_USB_STORAGE_ISD200 is not set
|
||||
CONFIG_USB_STORAGE_JUMPSHOT=y
|
||||
CONFIG_USB_STORAGE=m
|
||||
CONFIG_USB_STORAGE_SDDR09=y
|
||||
CONFIG_USB_STORAGE_SDDR55=y
|
||||
# CONFIG_USB_STV680 is not set
|
||||
# CONFIG_USB_TIGL is not set
|
||||
CONFIG_USB_UHCI_ALT=m
|
||||
CONFIG_USB_UHCI=m
|
||||
# CONFIG_USB_USS720 is not set
|
||||
# CONFIG_USB_VICAM is not set
|
||||
# CONFIG_USB_W9968CF is not set
|
||||
# CONFIG_USB_WACOM is not set
|
||||
# CONFIG_VIA_RHINE is not set
|
||||
# CONFIG_VIA_RHINE_MMIO is not set
|
||||
# CONFIG_VIDEO_BT848 is not set
|
||||
# CONFIG_VIDEO_BWQCAM is not set
|
||||
# CONFIG_VIDEO_CPIA is not set
|
||||
# CONFIG_VIDEO_CQCAM is not set
|
||||
CONFIG_VIDEO_DEV=m
|
||||
# CONFIG_VIDEO_MEYE is not set
|
||||
# CONFIG_VIDEO_PMS is not set
|
||||
CONFIG_VIDEO_PROC_FS=y
|
||||
# CONFIG_VIDEO_SAA5249 is not set
|
||||
# CONFIG_VIDEO_STRADIS is not set
|
||||
# CONFIG_VIDEO_ZORAN_BUZ is not set
|
||||
# CONFIG_VIDEO_ZORAN_DC10 is not set
|
||||
# CONFIG_VIDEO_ZORAN is not set
|
||||
# CONFIG_VIDEO_ZORAN_LML33 is not set
|
||||
# CONFIG_VIDEO_ZR36120 is not set
|
||||
# CONFIG_W83877F_WDT is not set
|
||||
# CONFIG_WAFER_WDT is not set
|
||||
# CONFIG_WDC_ALI15X3 is not set
|
||||
# CONFIG_WDT is not set
|
||||
# CONFIG_WDTPCI is not set
|
||||
# CONFIG_WINBOND_840 is not set
|
||||
# CONFIG_YAM is not set
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
#
|
||||
# Makefile for the BCM947xx specific kernel interface routines
|
||||
# under Linux.
|
||||
#
|
||||
|
||||
EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
|
||||
|
||||
O_TARGET := bcm947xx.o
|
||||
|
||||
export-objs := export.o
|
||||
obj-y := prom.o setup.o time.o sbmips.o gpio.o
|
||||
obj-y += nvram.o cfe_env.o hndpmu.o
|
||||
obj-y += sbutils.o utils.o bcmsrom.o hndchipc.o
|
||||
obj-$(CONFIG_PCI) += sbpci.o pcibios.o
|
||||
obj-y += export.o
|
||||
|
||||
include $(TOPDIR)/Rules.make
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,232 +0,0 @@
|
|||
/*
|
||||
* NVRAM variable manipulation (Linux kernel half)
|
||||
*
|
||||
* Copyright 2001-2003, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/string.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <osl.h>
|
||||
#include <bcmendian.h>
|
||||
|
||||
#define NVRAM_SIZE (0x1ff0)
|
||||
static char _nvdata[NVRAM_SIZE] __initdata;
|
||||
static char _valuestr[256] __initdata;
|
||||
|
||||
/*
|
||||
* TLV types. These codes are used in the "type-length-value"
|
||||
* encoding of the items stored in the NVRAM device (flash or EEPROM)
|
||||
*
|
||||
* The layout of the flash/nvram is as follows:
|
||||
*
|
||||
* <type> <length> <data ...> <type> <length> <data ...> <type_end>
|
||||
*
|
||||
* The type code of "ENV_TLV_TYPE_END" marks the end of the list.
|
||||
* The "length" field marks the length of the data section, not
|
||||
* including the type and length fields.
|
||||
*
|
||||
* Environment variables are stored as follows:
|
||||
*
|
||||
* <type_env> <length> <flags> <name> = <value>
|
||||
*
|
||||
* If bit 0 (low bit) is set, the length is an 8-bit value.
|
||||
* If bit 0 (low bit) is clear, the length is a 16-bit value
|
||||
*
|
||||
* Bit 7 set indicates "user" TLVs. In this case, bit 0 still
|
||||
* indicates the size of the length field.
|
||||
*
|
||||
* Flags are from the constants below:
|
||||
*
|
||||
*/
|
||||
#define ENV_LENGTH_16BITS 0x00 /* for low bit */
|
||||
#define ENV_LENGTH_8BITS 0x01
|
||||
|
||||
#define ENV_TYPE_USER 0x80
|
||||
|
||||
#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
|
||||
#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
|
||||
|
||||
/*
|
||||
* The actual TLV types we support
|
||||
*/
|
||||
|
||||
#define ENV_TLV_TYPE_END 0x00
|
||||
#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
|
||||
|
||||
/*
|
||||
* Environment variable flags
|
||||
*/
|
||||
|
||||
#define ENV_FLG_NORMAL 0x00 /* normal read/write */
|
||||
#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
|
||||
#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
|
||||
|
||||
#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
|
||||
#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
|
||||
|
||||
|
||||
/* *********************************************************************
|
||||
* _nvram_read(buffer,offset,length)
|
||||
*
|
||||
* Read data from the NVRAM device
|
||||
*
|
||||
* Input parameters:
|
||||
* buffer - destination buffer
|
||||
* offset - offset of data to read
|
||||
* length - number of bytes to read
|
||||
*
|
||||
* Return value:
|
||||
* number of bytes read, or <0 if error occured
|
||||
********************************************************************* */
|
||||
static int
|
||||
_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
|
||||
{
|
||||
int i;
|
||||
if (offset > NVRAM_SIZE)
|
||||
return -1;
|
||||
|
||||
for ( i = 0; i < length; i++) {
|
||||
buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
|
||||
}
|
||||
return length;
|
||||
}
|
||||
|
||||
|
||||
static char*
|
||||
_strnchr(const char *dest,int c,size_t cnt)
|
||||
{
|
||||
while (*dest && (cnt > 0)) {
|
||||
if (*dest == c) return (char *) dest;
|
||||
dest++;
|
||||
cnt--;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Core support API: Externally visible.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Get the value of an NVRAM variable
|
||||
* @param name name of variable to get
|
||||
* @return value of variable or NULL if undefined
|
||||
*/
|
||||
|
||||
char*
|
||||
cfe_env_get(unsigned char *nv_buf, char* name)
|
||||
{
|
||||
int size;
|
||||
unsigned char *buffer;
|
||||
unsigned char *ptr;
|
||||
unsigned char *envval;
|
||||
unsigned int reclen;
|
||||
unsigned int rectype;
|
||||
int offset;
|
||||
int flg;
|
||||
|
||||
size = NVRAM_SIZE;
|
||||
buffer = &_nvdata[0];
|
||||
|
||||
ptr = buffer;
|
||||
offset = 0;
|
||||
|
||||
/* Read the record type and length */
|
||||
if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
|
||||
goto error;
|
||||
}
|
||||
|
||||
while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
|
||||
|
||||
/* Adjust pointer for TLV type */
|
||||
rectype = *(ptr);
|
||||
offset++;
|
||||
size--;
|
||||
|
||||
/*
|
||||
* Read the length. It can be either 1 or 2 bytes
|
||||
* depending on the code
|
||||
*/
|
||||
if (rectype & ENV_LENGTH_8BITS) {
|
||||
/* Read the record type and length - 8 bits */
|
||||
if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
|
||||
goto error;
|
||||
}
|
||||
reclen = *(ptr);
|
||||
size--;
|
||||
offset++;
|
||||
}
|
||||
else {
|
||||
/* Read the record type and length - 16 bits, MSB first */
|
||||
if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
|
||||
goto error;
|
||||
}
|
||||
reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
|
||||
size -= 2;
|
||||
offset += 2;
|
||||
}
|
||||
|
||||
if (reclen > size)
|
||||
break; /* should not happen, bad NVRAM */
|
||||
|
||||
switch (rectype) {
|
||||
case ENV_TLV_TYPE_ENV:
|
||||
/* Read the TLV data */
|
||||
if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
|
||||
goto error;
|
||||
flg = *ptr++;
|
||||
envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
|
||||
if (envval) {
|
||||
*envval++ = '\0';
|
||||
memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
|
||||
_valuestr[(reclen-1)-(envval-ptr)] = '\0';
|
||||
#if 0
|
||||
printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
|
||||
#endif
|
||||
if(!strcmp(ptr, name)){
|
||||
return _valuestr;
|
||||
}
|
||||
if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
|
||||
return _valuestr;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
/* Unknown TLV type, skip it. */
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Advance to next TLV
|
||||
*/
|
||||
|
||||
size -= (int)reclen;
|
||||
offset += reclen;
|
||||
|
||||
/* Read the next record type */
|
||||
ptr = buffer;
|
||||
if (_nvram_read(nv_buf, ptr,offset,1) != 1)
|
||||
goto error;
|
||||
}
|
||||
|
||||
error:
|
||||
return NULL;
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
#include <linux/module.h>
|
||||
|
||||
#define _export(n) \
|
||||
void n(void); \
|
||||
EXPORT_SYMBOL(n);
|
||||
|
||||
_export(bcm947xx_sbh)
|
||||
|
||||
_export(sb_alp_clock)
|
||||
_export(sb_attach)
|
||||
_export(sb_kattach)
|
||||
_export(sb_backplane64)
|
||||
_export(sb_boardtype)
|
||||
_export(sb_boardvendor)
|
||||
_export(sb_btcgpiowar)
|
||||
_export(sb_bus)
|
||||
_export(sb_chip)
|
||||
_export(sb_chiprev)
|
||||
_export(sb_chipcrev)
|
||||
_export(sb_chippkg)
|
||||
_export(sb_clkctl_clk)
|
||||
_export(sb_clkctl_fast_pwrup_delay)
|
||||
_export(sb_clkctl_init)
|
||||
_export(sb_clkctl_xtal)
|
||||
_export(sb_core_disable)
|
||||
_export(sb_core_reset)
|
||||
_export(sb_core_tofixup)
|
||||
_export(sb_coreflags)
|
||||
_export(sb_coreflags_wo)
|
||||
_export(sb_coreflagshi)
|
||||
_export(sb_coreidx)
|
||||
_export(sb_coreregs)
|
||||
_export(sb_corerev)
|
||||
_export(sb_coreunit)
|
||||
_export(sb_detach)
|
||||
_export(sb_deviceremoved)
|
||||
_export(sb_gpiosetcore)
|
||||
_export(sb_gpiocontrol)
|
||||
_export(sb_gpiointmask)
|
||||
_export(sb_gpiointpolarity)
|
||||
_export(sb_gpioled)
|
||||
_export(sb_gpioin)
|
||||
_export(sb_gpioout)
|
||||
_export(sb_gpioouten)
|
||||
_export(sb_gpiopull)
|
||||
_export(sb_gpiotimerval)
|
||||
_export(sb_irq)
|
||||
_export(sb_iscoreup)
|
||||
_export(sb_pci_setup)
|
||||
_export(sb_pci_sleep)
|
||||
_export(sb_pci_down)
|
||||
_export(sb_pci_up)
|
||||
_export(sb_pcirev)
|
||||
_export(sb_pcmcia_init)
|
||||
_export(sb_pcmciarev)
|
||||
_export(sb_pmu_paref_ldo_enable)
|
||||
_export(sb_pmu_rcal)
|
||||
_export(sb_pmu_set_ldo_voltage)
|
||||
_export(sb_deregister_intr_callback)
|
||||
_export(sb_register_intr_callback)
|
||||
_export(sb_setcore)
|
||||
_export(sb_setcoreidx)
|
||||
_export(sb_war16165)
|
||||
_export(sb_war42780_clkreq)
|
||||
_export(sb_osh)
|
||||
|
||||
_export(getvar)
|
||||
_export(getintvar)
|
||||
|
||||
_export(nvram_get)
|
||||
_export(nvram_getall)
|
||||
|
||||
_export(srom_read)
|
||||
_export(srom_write)
|
||||
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
#
|
||||
# Makefile for the BCM947xx specific kernel interface routines
|
||||
# under Linux.
|
||||
#
|
||||
EXTRA_CFLAGS += -fno-delayed-branch
|
||||
USE_STANDARD_AS_RULE := true
|
||||
|
||||
O_TARGET := brcm.o
|
||||
|
||||
obj-y := int-handler.o irq.o
|
||||
|
||||
include $(TOPDIR)/Rules.make
|
||||
|
|
@ -1,50 +0,0 @@
|
|||
/*
|
||||
* Generic interrupt handler for Broadcom MIPS boards
|
||||
*
|
||||
* Copyright 2004, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
|
||||
#include <asm/asm.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/regdef.h>
|
||||
#include <asm/stackframe.h>
|
||||
|
||||
/*
|
||||
* MIPS IRQ Source
|
||||
* -------- ------
|
||||
* 0 Software (ignored)
|
||||
* 1 Software (ignored)
|
||||
* 2 Combined hardware interrupt (hw0)
|
||||
* 3 Hardware
|
||||
* 4 Hardware
|
||||
* 5 Hardware
|
||||
* 6 Hardware
|
||||
* 7 R4k timer
|
||||
*/
|
||||
|
||||
.text
|
||||
.set noreorder
|
||||
.set noat
|
||||
.align 5
|
||||
NESTED(brcmIRQ, PT_SIZE, sp)
|
||||
SAVE_ALL
|
||||
CLI
|
||||
.set at
|
||||
.set noreorder
|
||||
|
||||
jal brcm_irq_dispatch
|
||||
move a0, sp
|
||||
|
||||
j ret_from_irq
|
||||
nop
|
||||
|
||||
END(brcmIRQ)
|
||||
|
|
@ -1,129 +0,0 @@
|
|||
/*
|
||||
* Generic interrupt control functions for Broadcom MIPS boards
|
||||
*
|
||||
* Copyright 2004, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/gdb-stub.h>
|
||||
|
||||
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
|
||||
|
||||
extern asmlinkage void brcmIRQ(void);
|
||||
extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
|
||||
|
||||
void
|
||||
brcm_irq_dispatch(struct pt_regs *regs)
|
||||
{
|
||||
u32 cause;
|
||||
|
||||
cause = read_c0_cause() &
|
||||
read_c0_status() &
|
||||
CAUSEF_IP;
|
||||
|
||||
#ifdef CONFIG_KERNPROF
|
||||
change_c0_status(cause | 1, 1);
|
||||
#else
|
||||
clear_c0_status(cause);
|
||||
#endif
|
||||
|
||||
if (cause & CAUSEF_IP7)
|
||||
do_IRQ(7, regs);
|
||||
if (cause & CAUSEF_IP2)
|
||||
do_IRQ(2, regs);
|
||||
if (cause & CAUSEF_IP3)
|
||||
do_IRQ(3, regs);
|
||||
if (cause & CAUSEF_IP4)
|
||||
do_IRQ(4, regs);
|
||||
if (cause & CAUSEF_IP5)
|
||||
do_IRQ(5, regs);
|
||||
if (cause & CAUSEF_IP6)
|
||||
do_IRQ(6, regs);
|
||||
}
|
||||
|
||||
static void
|
||||
enable_brcm_irq(unsigned int irq)
|
||||
{
|
||||
if (irq < 8)
|
||||
set_c0_status(1 << (irq + 8));
|
||||
else
|
||||
set_c0_status(IE_IRQ0);
|
||||
}
|
||||
|
||||
static void
|
||||
disable_brcm_irq(unsigned int irq)
|
||||
{
|
||||
if (irq < 8)
|
||||
clear_c0_status(1 << (irq + 8));
|
||||
else
|
||||
clear_c0_status(IE_IRQ0);
|
||||
}
|
||||
|
||||
static void
|
||||
ack_brcm_irq(unsigned int irq)
|
||||
{
|
||||
/* Already done in brcm_irq_dispatch */
|
||||
}
|
||||
|
||||
static unsigned int
|
||||
startup_brcm_irq(unsigned int irq)
|
||||
{
|
||||
enable_brcm_irq(irq);
|
||||
|
||||
return 0; /* never anything pending */
|
||||
}
|
||||
|
||||
static void
|
||||
end_brcm_irq(unsigned int irq)
|
||||
{
|
||||
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
||||
enable_brcm_irq(irq);
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type brcm_irq_type = {
|
||||
typename: "MIPS",
|
||||
startup: startup_brcm_irq,
|
||||
shutdown: disable_brcm_irq,
|
||||
enable: enable_brcm_irq,
|
||||
disable: disable_brcm_irq,
|
||||
ack: ack_brcm_irq,
|
||||
end: end_brcm_irq,
|
||||
NULL
|
||||
};
|
||||
|
||||
void __init
|
||||
init_IRQ(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < NR_IRQS; i++) {
|
||||
irq_desc[i].status = IRQ_DISABLED;
|
||||
irq_desc[i].action = 0;
|
||||
irq_desc[i].depth = 1;
|
||||
irq_desc[i].handler = &brcm_irq_type;
|
||||
}
|
||||
|
||||
set_except_vector(0, brcmIRQ);
|
||||
change_c0_status(ST0_IM, ALLINTS);
|
||||
|
||||
#ifdef CONFIG_REMOTE_DEBUG
|
||||
printk("Breaking into debugger...\n");
|
||||
set_debug_traps();
|
||||
breakpoint();
|
||||
#endif
|
||||
}
|
||||
|
|
@ -1,157 +0,0 @@
|
|||
/*
|
||||
* GPIO char driver
|
||||
*
|
||||
* Copyright 2005, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/miscdevice.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <osl.h>
|
||||
#include <sbutils.h>
|
||||
#include <bcmdevs.h>
|
||||
|
||||
static sb_t *gpio_sbh;
|
||||
static int gpio_major;
|
||||
static devfs_handle_t gpio_dir;
|
||||
static struct {
|
||||
char *name;
|
||||
devfs_handle_t handle;
|
||||
} gpio_file[] = {
|
||||
{ "in", NULL },
|
||||
{ "out", NULL },
|
||||
{ "outen", NULL },
|
||||
{ "control", NULL }
|
||||
};
|
||||
|
||||
static int
|
||||
gpio_open(struct inode *inode, struct file * file)
|
||||
{
|
||||
if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
|
||||
return -ENODEV;
|
||||
|
||||
MOD_INC_USE_COUNT;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
gpio_release(struct inode *inode, struct file * file)
|
||||
{
|
||||
MOD_DEC_USE_COUNT;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static ssize_t
|
||||
gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
|
||||
case 0:
|
||||
val = sb_gpioin(gpio_sbh);
|
||||
break;
|
||||
case 1:
|
||||
val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
|
||||
break;
|
||||
case 2:
|
||||
val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
|
||||
break;
|
||||
case 3:
|
||||
val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
|
||||
break;
|
||||
default:
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (put_user(val, (u32 *) buf))
|
||||
return -EFAULT;
|
||||
|
||||
return sizeof(val);
|
||||
}
|
||||
|
||||
static ssize_t
|
||||
gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (get_user(val, (u32 *) buf))
|
||||
return -EFAULT;
|
||||
|
||||
switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
|
||||
case 0:
|
||||
return -EACCES;
|
||||
case 1:
|
||||
sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
|
||||
break;
|
||||
case 2:
|
||||
sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
|
||||
break;
|
||||
case 3:
|
||||
sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
|
||||
break;
|
||||
default:
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
return sizeof(val);
|
||||
}
|
||||
|
||||
static struct file_operations gpio_fops = {
|
||||
owner: THIS_MODULE,
|
||||
open: gpio_open,
|
||||
release: gpio_release,
|
||||
read: gpio_read,
|
||||
write: gpio_write,
|
||||
};
|
||||
|
||||
static int __init
|
||||
gpio_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (!(gpio_sbh = sb_kattach(SB_OSH)))
|
||||
return -ENODEV;
|
||||
|
||||
sb_gpiosetcore(gpio_sbh);
|
||||
|
||||
if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
|
||||
return gpio_major;
|
||||
|
||||
gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
|
||||
|
||||
for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
|
||||
gpio_file[i].handle = devfs_register(gpio_dir,
|
||||
gpio_file[i].name,
|
||||
DEVFS_FL_DEFAULT, gpio_major, i,
|
||||
S_IFCHR | S_IRUGO | S_IWUGO,
|
||||
&gpio_fops, NULL);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __exit
|
||||
gpio_exit(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAYSIZE(gpio_file); i++)
|
||||
devfs_unregister(gpio_file[i].handle);
|
||||
devfs_unregister(gpio_dir);
|
||||
devfs_unregister_chrdev(gpio_major, "gpio");
|
||||
sb_detach(gpio_sbh);
|
||||
}
|
||||
|
||||
module_init(gpio_init);
|
||||
module_exit(gpio_exit);
|
||||
|
|
@ -1,339 +0,0 @@
|
|||
/*
|
||||
* BCM47XX support code for some chipcommon facilities (uart, jtagm)
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <bcmdefs.h>
|
||||
#include <osl.h>
|
||||
#include <sbutils.h>
|
||||
#include <bcmdevs.h>
|
||||
#include <bcmnvram.h>
|
||||
#include <sbconfig.h>
|
||||
#include <sbchipc.h>
|
||||
#include <sbextif.h>
|
||||
#include <hndchipc.h>
|
||||
#include <hndcpu.h>
|
||||
|
||||
/* debug/trace */
|
||||
#define CC_ERROR(args)
|
||||
|
||||
#ifdef BCMDBG
|
||||
#define CC_MSG(args) printf args
|
||||
#else
|
||||
#define CC_MSG(args)
|
||||
#endif /* BCMDBG */
|
||||
|
||||
/* interested chipcommon interrupt source
|
||||
* - GPIO
|
||||
* - EXTIF
|
||||
* - ECI
|
||||
* - PMU
|
||||
* - UART
|
||||
*/
|
||||
#define MAX_CC_INT_SOURCE 5
|
||||
|
||||
/* chipc secondary isr info */
|
||||
typedef struct {
|
||||
uint intmask; /* int mask */
|
||||
cc_isr_fn isr; /* secondary isr handler */
|
||||
void *cbdata; /* pointer to private data */
|
||||
} cc_isr_info_t;
|
||||
|
||||
static cc_isr_info_t cc_isr_desc[MAX_CC_INT_SOURCE];
|
||||
|
||||
/* chip common intmask */
|
||||
static uint32 cc_intmask = 0;
|
||||
|
||||
static bool BCMINITFN(serial_exists) (osl_t * osh, uint8 * regs) {
|
||||
uint8 save_mcr, status1;
|
||||
|
||||
save_mcr = R_REG(osh, ®s[UART_MCR]);
|
||||
W_REG(osh, ®s[UART_MCR], UART_MCR_LOOP | 0x0a);
|
||||
status1 = R_REG(osh, ®s[UART_MSR]) & 0xf0;
|
||||
W_REG(osh, ®s[UART_MCR], save_mcr);
|
||||
|
||||
return (status1 == 0x90);
|
||||
}
|
||||
|
||||
static void __init sb_extif_serial_init(sb_t * sbh, void *regs,
|
||||
sb_serial_init_fn add)
|
||||
{
|
||||
osl_t *osh = sb_osh(sbh);
|
||||
extifregs_t *eir = (extifregs_t *) regs;
|
||||
sbconfig_t *sb;
|
||||
ulong base;
|
||||
uint irq;
|
||||
int i, n;
|
||||
|
||||
/* Determine external UART register base */
|
||||
sb = (sbconfig_t *) ((ulong) eir + SBCONFIGOFF);
|
||||
base = EXTIF_CFGIF_BASE(sb_base(R_REG(osh, &sb->sbadmatch1)));
|
||||
|
||||
/* Determine IRQ */
|
||||
irq = sb_irq(sbh);
|
||||
|
||||
/* Disable GPIO interrupt initially */
|
||||
W_REG(osh, &eir->gpiointpolarity, 0);
|
||||
W_REG(osh, &eir->gpiointmask, 0);
|
||||
|
||||
/* Search for external UARTs */
|
||||
n = 2;
|
||||
for (i = 0; i < 2; i++) {
|
||||
regs = (void *)REG_MAP(base + (i * 8), 8);
|
||||
if (serial_exists(osh, regs)) {
|
||||
/* Set GPIO 1 to be the external UART IRQ */
|
||||
W_REG(osh, &eir->gpiointmask, 2);
|
||||
/* XXXDetermine external UART clock */
|
||||
if (add)
|
||||
add(regs, irq, 13500000, 0);
|
||||
}
|
||||
}
|
||||
|
||||
/* Add internal UART if enabled */
|
||||
if (R_REG(osh, &eir->corecontrol) & CC_UE)
|
||||
if (add)
|
||||
add((void *)&eir->uartdata, irq, sb_clock(sbh), 2);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initializes UART access. The callback function will be called once
|
||||
* per found UART.
|
||||
*/
|
||||
void BCMINITFN(sb_serial_init) (sb_t * sbh, sb_serial_init_fn add) {
|
||||
osl_t *osh;
|
||||
void *regs;
|
||||
chipcregs_t *cc;
|
||||
uint32 rev, cap, pll, baud_base, div;
|
||||
uint irq;
|
||||
int i, n;
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
|
||||
regs = sb_setcore(sbh, SB_EXTIF, 0);
|
||||
if (regs) {
|
||||
sb_extif_serial_init(sbh, regs, add);
|
||||
return;
|
||||
}
|
||||
|
||||
cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0);
|
||||
ASSERT(cc);
|
||||
|
||||
/* Determine core revision and capabilities */
|
||||
rev = sbh->ccrev;
|
||||
cap = sbh->cccaps;
|
||||
pll = cap & CC_CAP_PLL_MASK;
|
||||
|
||||
/* Determine IRQ */
|
||||
irq = sb_irq(sbh);
|
||||
|
||||
if (pll == PLL_TYPE1) {
|
||||
/* PLL clock */
|
||||
baud_base = sb_clock_rate(pll,
|
||||
R_REG(osh, &cc->clockcontrol_n),
|
||||
R_REG(osh, &cc->clockcontrol_m2));
|
||||
div = 1;
|
||||
} else {
|
||||
/* 5354 chip common uart uses a constant clock
|
||||
* frequency of 25MHz */
|
||||
if (sb_corerev(sbh) == 20) {
|
||||
/* Set the override bit so we don't divide it */
|
||||
W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
|
||||
baud_base = 25000000;
|
||||
} else if (rev >= 11 && rev != 15) {
|
||||
/* Fixed ALP clock */
|
||||
baud_base = sb_alp_clock(sbh);
|
||||
div = 1;
|
||||
/* Turn off UART clock before switching clock source */
|
||||
if (rev >= 21)
|
||||
AND_REG(osh, &cc->corecontrol, ~CC_UARTCLKEN);
|
||||
/* Set the override bit so we don't divide it */
|
||||
OR_REG(osh, &cc->corecontrol, CC_UARTCLKO);
|
||||
if (rev >= 21)
|
||||
OR_REG(osh, &cc->corecontrol, CC_UARTCLKEN);
|
||||
} else if (rev >= 3) {
|
||||
/* Internal backplane clock */
|
||||
baud_base = sb_clock(sbh);
|
||||
div = 2; /* Minimum divisor */
|
||||
W_REG(osh, &cc->clkdiv,
|
||||
((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
|
||||
} else {
|
||||
/* Fixed internal backplane clock */
|
||||
baud_base = 88000000;
|
||||
div = 48;
|
||||
}
|
||||
|
||||
/* Clock source depends on strapping if UartClkOverride is unset */
|
||||
if ((rev > 0)
|
||||
&& ((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) {
|
||||
if ((cap & CC_CAP_UCLKSEL) == CC_CAP_UINTCLK) {
|
||||
/* Internal divided backplane clock */
|
||||
baud_base /= div;
|
||||
} else {
|
||||
/* Assume external clock of 1.8432 MHz */
|
||||
baud_base = 1843200;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Add internal UARTs */
|
||||
n = cap & CC_CAP_UARTS_MASK;
|
||||
for (i = 0; i < n; i++) {
|
||||
/* Register offset changed after revision 0 */
|
||||
if (rev)
|
||||
regs = (void *)((ulong) & cc->uart0data + (i * 256));
|
||||
else
|
||||
regs = (void *)((ulong) & cc->uart0data + (i * 8));
|
||||
|
||||
if (add)
|
||||
add(regs, irq, baud_base, 0);
|
||||
}
|
||||
}
|
||||
|
||||
#if 0
|
||||
/*
|
||||
* Initialize jtag master and return handle for
|
||||
* jtag_rwreg. Returns NULL on failure.
|
||||
*/
|
||||
void *sb_jtagm_init(sb_t * sbh, uint clkd, bool exttap)
|
||||
{
|
||||
void *regs;
|
||||
|
||||
if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
|
||||
chipcregs_t *cc = (chipcregs_t *) regs;
|
||||
uint32 tmp;
|
||||
|
||||
/*
|
||||
* Determine jtagm availability from
|
||||
* core revision and capabilities.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Corerev 10 has jtagm, but the only chip
|
||||
* with it does not have a mips, and
|
||||
* the layout of the jtagcmd register is
|
||||
* different. We'll only accept >= 11.
|
||||
*/
|
||||
if (sbh->ccrev < 11)
|
||||
return (NULL);
|
||||
|
||||
if ((sbh->cccaps & CC_CAP_JTAGP) == 0)
|
||||
return (NULL);
|
||||
|
||||
/* Set clock divider if requested */
|
||||
if (clkd != 0) {
|
||||
tmp = R_REG(osh, &cc->clkdiv);
|
||||
tmp =
|
||||
(tmp & ~CLKD_JTAG) | ((clkd << CLKD_JTAG_SHIFT) &
|
||||
CLKD_JTAG);
|
||||
W_REG(osh, &cc->clkdiv, tmp);
|
||||
}
|
||||
|
||||
/* Enable jtagm */
|
||||
tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
|
||||
W_REG(osh, &cc->jtagctrl, tmp);
|
||||
}
|
||||
|
||||
return (regs);
|
||||
}
|
||||
|
||||
void sb_jtagm_disable(osl_t * osh, void *h)
|
||||
{
|
||||
chipcregs_t *cc = (chipcregs_t *) h;
|
||||
|
||||
W_REG(osh, &cc->jtagctrl, R_REG(osh, &cc->jtagctrl) & ~JCTRL_EN);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read/write a jtag register. Assumes a target with
|
||||
* 8 bit IR and 32 bit DR.
|
||||
*/
|
||||
#define IRWIDTH 8 /* Default Instruction Register width */
|
||||
#define DRWIDTH 32 /* Default Data Register width */
|
||||
|
||||
uint32 jtag_rwreg(osl_t * osh, void *h, uint32 ir, uint32 dr)
|
||||
{
|
||||
chipcregs_t *cc = (chipcregs_t *) h;
|
||||
uint32 tmp;
|
||||
|
||||
W_REG(osh, &cc->jtagir, ir);
|
||||
W_REG(osh, &cc->jtagdr, dr);
|
||||
tmp = JCMD_START | JCMD_ACC_IRDR |
|
||||
((IRWIDTH - 1) << JCMD_IRW_SHIFT) | (DRWIDTH - 1);
|
||||
W_REG(osh, &cc->jtagcmd, tmp);
|
||||
while (((tmp = R_REG(osh, &cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
|
||||
/* OSL_DELAY(1); */
|
||||
}
|
||||
|
||||
tmp = R_REG(osh, &cc->jtagdr);
|
||||
return (tmp);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Interface to register chipc secondary isr
|
||||
*/
|
||||
bool
|
||||
BCMINITFN(sb_cc_register_isr) (sb_t * sbh, cc_isr_fn isr, uint32 ccintmask,
|
||||
void *cbdata) {
|
||||
bool done = FALSE;
|
||||
chipcregs_t *regs;
|
||||
uint origidx;
|
||||
uint i;
|
||||
|
||||
/* Save the current core index */
|
||||
origidx = sb_coreidx(sbh);
|
||||
regs = sb_setcore(sbh, SB_CC, 0);
|
||||
ASSERT(regs);
|
||||
|
||||
for (i = 0; i < MAX_CC_INT_SOURCE; i++) {
|
||||
if (cc_isr_desc[i].isr == NULL) {
|
||||
cc_isr_desc[i].isr = isr;
|
||||
cc_isr_desc[i].cbdata = cbdata;
|
||||
cc_isr_desc[i].intmask = ccintmask;
|
||||
done = TRUE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (done) {
|
||||
cc_intmask = R_REG(sb_osh(sbh), ®s->intmask);
|
||||
cc_intmask |= ccintmask;
|
||||
W_REG(sb_osh(sbh), ®s->intmask, cc_intmask);
|
||||
}
|
||||
|
||||
/* restore original coreidx */
|
||||
sb_setcoreidx(sbh, origidx);
|
||||
return done;
|
||||
}
|
||||
|
||||
/*
|
||||
* chipc primary interrupt handler
|
||||
*/
|
||||
void sb_cc_isr(sb_t * sbh, chipcregs_t * regs)
|
||||
{
|
||||
uint32 ccintstatus;
|
||||
uint32 intstatus;
|
||||
uint32 i;
|
||||
|
||||
/* prior to rev 21 chipc interrupt means uart and gpio */
|
||||
if (sbh->ccrev >= 21)
|
||||
ccintstatus = R_REG(sb_osh(sbh), ®s->intstatus) & cc_intmask;
|
||||
else
|
||||
ccintstatus = (CI_UART | CI_GPIO);
|
||||
|
||||
for (i = 0; i < MAX_CC_INT_SOURCE; i++) {
|
||||
if ((cc_isr_desc[i].isr != NULL) &&
|
||||
(intstatus = (cc_isr_desc[i].intmask & ccintstatus))) {
|
||||
(cc_isr_desc[i].isr) (cc_isr_desc[i].cbdata, intstatus);
|
||||
}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,90 +0,0 @@
|
|||
/*
|
||||
* BCM4710 address space map and definitions
|
||||
* Think twice before adding to this file, this is not the kitchen sink
|
||||
* These definitions are not guaranteed for all 47xx chips, only the 4710
|
||||
*
|
||||
* Copyright 2004, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _bcm4710_h_
|
||||
#define _bcm4710_h_
|
||||
|
||||
/* Address map */
|
||||
#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
|
||||
#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
|
||||
#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
|
||||
#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
|
||||
#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
|
||||
#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
|
||||
|
||||
/* Core register space */
|
||||
#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
|
||||
#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
|
||||
#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
|
||||
#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
|
||||
#define BCM4710_REG_USB 0x18004000 /* USB core registers */
|
||||
#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
|
||||
#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
|
||||
#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
|
||||
#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
|
||||
|
||||
#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
|
||||
#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
|
||||
#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
|
||||
#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
|
||||
#define BCM4710_PROG 0x1f800000 /* Programable interface */
|
||||
#define BCM4710_FLASH 0x1fc00000 /* Flash */
|
||||
|
||||
#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
|
||||
|
||||
#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
|
||||
|
||||
#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
|
||||
#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
|
||||
|
||||
#define SBFLAG_PCI 0
|
||||
#define SBFLAG_ENET0 1
|
||||
#define SBFLAG_ILINE20 2
|
||||
#define SBFLAG_CODEC 3
|
||||
#define SBFLAG_USB 4
|
||||
#define SBFLAG_EXTIF 5
|
||||
#define SBFLAG_ENET1 6
|
||||
|
||||
#ifdef CONFIG_HWSIM
|
||||
#define BCM4710_TRACE(trval) do { *((int *)0xa0000f18) = (trval); } while (0)
|
||||
#else
|
||||
#define BCM4710_TRACE(trval)
|
||||
#endif
|
||||
|
||||
|
||||
/* BCM94702 CPCI -ExtIF used for LocalBus devs */
|
||||
|
||||
#define BCM94702_CPCI_RESET_ADDR BCM4710_EXTIF
|
||||
#define BCM94702_CPCI_BOARDID_ADDR (BCM4710_EXTIF | 0x4000)
|
||||
#define BCM94702_CPCI_DOC_ADDR (BCM4710_EXTIF | 0x6000)
|
||||
#define BCM94702_DOC_ADDR BCM94702_CPCI_DOC_ADDR
|
||||
#define BCM94702_CPCI_LED_ADDR (BCM4710_EXTIF | 0xc000)
|
||||
#define BCM94702_CPCI_NVRAM_ADDR (BCM4710_EXTIF | 0xe000)
|
||||
#define BCM94702_CPCI_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
|
||||
#define BCM94702_CPCI_TOD_REG_BASE (BCM94702_CPCI_NVRAM_ADDR | 0x1ff0)
|
||||
|
||||
#define LED_REG(x) \
|
||||
(*(volatile unsigned char *) (KSEG1ADDR(BCM94702_CPCI_LED_ADDR) + (x)))
|
||||
|
||||
/*
|
||||
* Reset function implemented in PLD. Read or write should trigger hard reset
|
||||
*/
|
||||
#define SYS_HARD_RESET() \
|
||||
{ for (;;) \
|
||||
*( (volatile unsigned char *)\
|
||||
KSEG1ADDR(BCM94702_CPCI_RESET_ADDR) ) = 0x80; \
|
||||
}
|
||||
|
||||
#endif /* _bcm4710_h_ */
|
||||
|
|
@ -1,107 +0,0 @@
|
|||
/*
|
||||
* Misc system wide definitions
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _bcmdefs_h_
|
||||
#define _bcmdefs_h_
|
||||
|
||||
/*
|
||||
* One doesn't need to include this file explicitly, gets included automatically if
|
||||
* typedefs.h is included.
|
||||
*/
|
||||
|
||||
/* Reclaiming text and data :
|
||||
* The following macros specify special linker sections that can be reclaimed
|
||||
* after a system is considered 'up'.
|
||||
*/
|
||||
#if defined(__GNUC__) && defined(BCMRECLAIM)
|
||||
extern bool bcmreclaimed;
|
||||
#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data
|
||||
#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn
|
||||
#else /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
|
||||
#define BCMINITDATA(_data) _data
|
||||
#define BCMINITFN(_fn) _fn
|
||||
#define bcmreclaimed 0
|
||||
#endif /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
|
||||
|
||||
/* Reclaim uninit functions if BCMNODOWN is defined */
|
||||
/* and if they are not already removed by -gc-sections */
|
||||
#ifdef BCMNODOWN
|
||||
#define BCMUNINITFN(_fn) BCMINITFN(_fn)
|
||||
#else
|
||||
#define BCMUNINITFN(_fn) _fn
|
||||
#endif
|
||||
|
||||
#ifdef BCMRECLAIM
|
||||
#define CONST
|
||||
#else
|
||||
#define CONST const
|
||||
#endif /* BCMRECLAIM */
|
||||
|
||||
/* Compatibility with old-style BCMRECLAIM */
|
||||
#define BCMINIT(_id) _id
|
||||
|
||||
|
||||
/* Put some library data/code into ROM to reduce RAM requirements */
|
||||
#if defined(__GNUC__) && defined(BCMROMOFFLOAD)
|
||||
#define BCMROMDATA(_data) __attribute__ ((__section__ (".datarom." #_data))) _data
|
||||
#define BCMROMFN(_fn) __attribute__ ((__section__ (".textrom." #_fn))) _fn
|
||||
#else
|
||||
#define BCMROMDATA(_data) _data
|
||||
#define BCMROMFN(_fn) _fn
|
||||
#endif
|
||||
|
||||
/* Bus types */
|
||||
#define SB_BUS 0 /* Silicon Backplane */
|
||||
#define PCI_BUS 1 /* PCI target */
|
||||
#define PCMCIA_BUS 2 /* PCMCIA target */
|
||||
#define SDIO_BUS 3 /* SDIO target */
|
||||
#define JTAG_BUS 4 /* JTAG */
|
||||
#define NO_BUS 0xFF /* Bus that does not support R/W REG */
|
||||
|
||||
/* Allows optimization for single-bus support */
|
||||
#ifdef BCMBUSTYPE
|
||||
#define BUSTYPE(bus) (BCMBUSTYPE)
|
||||
#else
|
||||
#define BUSTYPE(bus) (bus)
|
||||
#endif
|
||||
|
||||
/* Defines for DMA Address Width - Shared between OSL and HNDDMA */
|
||||
#define DMADDR_MASK_32 0x0 /* Address mask for 32-bits */
|
||||
#define DMADDR_MASK_30 0xc0000000 /* Address mask for 30-bits */
|
||||
#define DMADDR_MASK_0 0xffffffff /* Address mask for 0-bits (hi-part) */
|
||||
|
||||
#define DMADDRWIDTH_30 30 /* 30-bit addressing capability */
|
||||
#define DMADDRWIDTH_32 32 /* 32-bit addressing capability */
|
||||
#define DMADDRWIDTH_63 63 /* 64-bit addressing capability */
|
||||
#define DMADDRWIDTH_64 64 /* 64-bit addressing capability */
|
||||
|
||||
/* packet headroom necessary to accomodate the largest header in the system, (i.e TXOFF).
|
||||
* By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL.
|
||||
* There is a compile time check in wlc.c which ensure that this value is at least as big
|
||||
* as TXOFF. This value is used in dma_rxfill (hnddma.c).
|
||||
*/
|
||||
#define BCMEXTRAHDROOM 160
|
||||
|
||||
/* Headroom required for dongle-to-host communication. Packets allocated
|
||||
* locally in the dongle (e.g. for CDC ioctls or RNDIS messages) should
|
||||
* leave this much room in front for low-level message headers which may
|
||||
* be needed to get across the dongle bus to the host. (These messages
|
||||
* don't go over the network, so room for the full WL header above would
|
||||
* be a waste.)
|
||||
*/
|
||||
#define BCMDONGLEHDRSZ 8
|
||||
|
||||
/* Max. nvram variable table size */
|
||||
#define MAXSZ_NVRAM_VARS 4096
|
||||
|
||||
|
||||
#endif /* _bcmdefs_h_ */
|
||||
|
|
@ -1,393 +0,0 @@
|
|||
/*
|
||||
* Broadcom device-specific manifest constants.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _BCMDEVS_H
|
||||
#define _BCMDEVS_H
|
||||
|
||||
/* PCI vendor IDs */
|
||||
#define VENDOR_EPIGRAM 0xfeda
|
||||
#define VENDOR_BROADCOM 0x14e4
|
||||
#define VENDOR_3COM 0x10b7
|
||||
#define VENDOR_NETGEAR 0x1385
|
||||
#define VENDOR_DIAMOND 0x1092
|
||||
#define VENDOR_DELL 0x1028
|
||||
#define VENDOR_HP 0x0e11
|
||||
#define VENDOR_APPLE 0x106b
|
||||
#define VENDOR_SI_IMAGE 0x1095 /* Silicon Image, used by Arasan SDIO Host */
|
||||
#define VENDOR_BUFFALO 0x1154 /* Buffalo vendor id */
|
||||
#define VENDOR_TI 0x104c /* Texas Instruments */
|
||||
|
||||
/* PCMCIA vendor IDs */
|
||||
#define VENDOR_BROADCOM_PCMCIA 0x02d0
|
||||
|
||||
/* SDIO vendor IDs */
|
||||
#define VENDOR_BROADCOM_SDIO 0x00BF
|
||||
|
||||
/* PCI Device IDs */
|
||||
#define BCM4210_DEVICE_ID 0x1072 /* never used */
|
||||
#define BCM4230_DEVICE_ID 0x1086 /* never used */
|
||||
#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
|
||||
#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
|
||||
#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
|
||||
#define BCM4211_DEVICE_ID 0x4211
|
||||
#define BCM4231_DEVICE_ID 0x4231
|
||||
#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
|
||||
#define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */
|
||||
#define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */
|
||||
#define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */
|
||||
#define BCM4328_D11DUAL_ID 0x4314 /* 4328 802.11a/g id */
|
||||
#define BCM4328_D11G_ID 0x4315 /* 4328 802.11g 2.4Ghz band id */
|
||||
#define BCM4328_D11A_ID 0x4316 /* 4328 802.11a 5Ghz band id */
|
||||
#define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */
|
||||
#define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */
|
||||
#define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */
|
||||
#define BCM4325_D11DUAL_ID 0x431b /* 4325 802.11a/g id */
|
||||
#define BCM4325_D11G_ID 0x431c /* 4325 802.11g 2.4Ghz band id */
|
||||
#define BCM4325_D11A_ID 0x431d /* 4325 802.11a 5Ghz band id */
|
||||
#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
|
||||
#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
|
||||
#define BCM4306_UART_ID 0x4322 /* 4306 uart */
|
||||
#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
|
||||
#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
|
||||
#define BCM4306_D11G_ID2 0x4325
|
||||
#define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */
|
||||
#define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Ghz band id */
|
||||
#define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
|
||||
#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
|
||||
#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
|
||||
#define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */
|
||||
#define BCM_JTAGM_ID 0x43f1 /* BCM jtagm device id */
|
||||
#define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */
|
||||
#define BCM_SDIOH_ID 0x43f3 /* BCM sdio host id */
|
||||
#define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */
|
||||
#define SPIH_FPGA_ID 0x43f5 /* PCI SPI Host Controller FPGA */
|
||||
#define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */
|
||||
#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
|
||||
#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
|
||||
#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
|
||||
#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
|
||||
#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
|
||||
#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
|
||||
#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
|
||||
#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
|
||||
#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
|
||||
#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
|
||||
#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
|
||||
#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
|
||||
#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
|
||||
#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
|
||||
#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
|
||||
#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
|
||||
#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
|
||||
#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
|
||||
#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
|
||||
#define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */
|
||||
#define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */
|
||||
#define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */
|
||||
#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
|
||||
#define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */
|
||||
#define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */
|
||||
#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
|
||||
#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
|
||||
#define JINVANI_SDIOH_ID 0x4743 /* Jinvani SDIO Gold Host */
|
||||
#define BCM27XX_SDIOH_ID 0x2702 /* BCM27xx Standard SDIO Host */
|
||||
#define PCIXX21_FLASHMEDIA_ID 0x803b /* TI PCI xx21 Standard Host Controller */
|
||||
#define PCIXX21_SDIOH_ID 0x803c /* TI PCI xx21 Standard Host Controller */
|
||||
|
||||
/* Chip IDs */
|
||||
#define BCM4710_CHIP_ID 0x4710 /* 4710 chipid returned by sb_chip() */
|
||||
#define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */
|
||||
#define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */
|
||||
#define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */
|
||||
#define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */
|
||||
#define BCM4312_CHIP_ID 0x4312 /* 4312 chip common chipid */
|
||||
#define BCM4318_CHIP_ID 0x4318 /* 4318 chip common chipid */
|
||||
#define BCM4321_CHIP_ID 0x4321 /* 4321 chip common chipid */
|
||||
#define BCM4328_CHIP_ID 0x4328 /* 4328 chip common chipid */
|
||||
#define BCM4325_CHIP_ID 0x4325 /* 4325 chip common chipid */
|
||||
#define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */
|
||||
#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
|
||||
#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */
|
||||
#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */
|
||||
#define BCM5354_CHIP_ID 0x5354 /* bcm5354 chipcommon chipid */
|
||||
#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */
|
||||
#define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */
|
||||
|
||||
/* Package IDs */
|
||||
#define BCM4303_PKG_ID 2 /* 4303 package id */
|
||||
#define BCM4309_PKG_ID 1 /* 4309 package id */
|
||||
#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
|
||||
#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
|
||||
#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
|
||||
#define BCM4328USBD11G_PKG_ID 2 /* 4328 802.11g USB package id */
|
||||
#define BCM4328USBDUAL_PKG_ID 3 /* 4328 802.11a/g USB package id */
|
||||
#define BCM4328SDIOD11G_PKG_ID 4 /* 4328 802.11g SDIO package id */
|
||||
#define BCM4328SDIODUAL_PKG_ID 5 /* 4328 802.11a/g SDIO package id */
|
||||
#define BCM5354E_PKG_ID 1 /* 5354E package id */
|
||||
#define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
|
||||
#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
|
||||
#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
|
||||
|
||||
#define PCIXX21_FLASHMEDIA0_ID 0x8033 /* TI PCI xx21 Standard Host Controller */
|
||||
#define PCIXX21_SDIOH0_ID 0x8034 /* TI PCI xx21 Standard Host Controller */
|
||||
/* boardflags */
|
||||
#define BFL_BTCOEXIST 0x00000001 /* This board implements Bluetooth coexistance */
|
||||
#define BFL_PACTRL 0x00000002 /* This board has gpio 9 controlling the PA */
|
||||
#define BFL_AIRLINEMODE 0x00000004 /* This board implements gpio13 radio disable indication */
|
||||
#define BFL_ADCDIV 0x00000008 /* This board has the rssi ADC divider */
|
||||
#define BFL_ENETROBO 0x00000010 /* This board has robo switch or core */
|
||||
#define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */
|
||||
#define BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */
|
||||
#define BFL_ENETADM 0x00000080 /* This board has ADMtek switch */
|
||||
#define BFL_ENETVLAN 0x00000100 /* This board has vlan capability */
|
||||
#define BFL_AFTERBURNER 0x00000200 /* This board supports Afterburner mode */
|
||||
#define BFL_NOPCI 0x00000400 /* This board leaves PCI floating */
|
||||
#define BFL_FEM 0x00000800 /* This board supports the Front End Module */
|
||||
#define BFL_EXTLNA 0x00001000 /* This board has an external LNA */
|
||||
#define BFL_HGPA 0x00002000 /* This board has a high gain PA */
|
||||
#define BFL_BTCMOD 0x00004000 /* This board' BTCOEXIST is in the alternate gpios */
|
||||
#define BFL_ALTIQ 0x00008000 /* Alternate I/Q settings */
|
||||
#define BFL_NOPA 0x00010000 /* This board has no PA */
|
||||
#define BFL_RSSIINV 0x00020000 /* This board's RSSI uses positive slope */
|
||||
#define BFL_PAREF 0x00040000 /* This board uses the PARef LDO */
|
||||
#define BFL_3TSWITCH 0x00080000 /* This board uses a triple throw switch shared with BT */
|
||||
#define BFL_PHASESHIFTER 0x00100000 /* This board can support phase shifter */
|
||||
#define BFL_BUCKBOOST 0x00200000 /* This board has buck/booster */
|
||||
/* boardflags2 */
|
||||
#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* This board has an external rxbb regulator */
|
||||
#define BFL2_DEPRECIATED_STUB 0x00000002 /* This board flag is depreciated */
|
||||
#define BFL2_TXPWRCTRL_EN 0x00000004 /* This board permits enabling TX Power Control */
|
||||
#define BFL2_2X4_DIV 0x00000008 /* This board supports the 2X4 diversity switch */
|
||||
#define BFL2_5G_PWRGAIN 0x00000010 /* This board supports 5G band power gain */
|
||||
#define BFL2_PCIEWAR_OVR 0x00000020 /* This board overrides ASPM and Clkreq settings */
|
||||
#define BFL2_CAESERS_BRD 0x00000040 /* This board is Dell Caeser's brd (unused by sw) */
|
||||
|
||||
/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
|
||||
#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
|
||||
#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
|
||||
#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
|
||||
#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
|
||||
#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
|
||||
#define BOARD_GPIO_ANT0_SEL 0x100 /* With BFL2_2X4_DIV */
|
||||
#define BOARD_GPIO_ANT1_SEL 0x200 /* With BFL2_2X4_DIV */
|
||||
|
||||
#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
|
||||
#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
|
||||
#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
|
||||
#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
|
||||
|
||||
/* power control defines */
|
||||
#define PLL_DELAY 150 /* us pll on delay */
|
||||
#define FREF_DELAY 200 /* us fref change delay */
|
||||
#define MIN_SLOW_CLK 32 /* us Slow clock period */
|
||||
#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
|
||||
|
||||
/* Reference Board Types */
|
||||
#define BU4710_BOARD 0x0400
|
||||
#define VSIM4710_BOARD 0x0401
|
||||
#define QT4710_BOARD 0x0402
|
||||
|
||||
#define BU4309_BOARD 0x040a
|
||||
#define BCM94309CB_BOARD 0x040b
|
||||
#define BCM94309MP_BOARD 0x040c
|
||||
#define BCM4309AP_BOARD 0x040d
|
||||
|
||||
#define BCM94302MP_BOARD 0x040e
|
||||
|
||||
#define BU4306_BOARD 0x0416
|
||||
#define BCM94306CB_BOARD 0x0417
|
||||
#define BCM94306MP_BOARD 0x0418
|
||||
|
||||
#define BCM94710D_BOARD 0x041a
|
||||
#define BCM94710R1_BOARD 0x041b
|
||||
#define BCM94710R4_BOARD 0x041c
|
||||
#define BCM94710AP_BOARD 0x041d
|
||||
|
||||
#define BU2050_BOARD 0x041f
|
||||
|
||||
|
||||
#define BCM94309G_BOARD 0x0421
|
||||
|
||||
#define BU4704_BOARD 0x0423
|
||||
#define BU4702_BOARD 0x0424
|
||||
|
||||
#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
|
||||
|
||||
|
||||
#define BCM94702MN_BOARD 0x0428
|
||||
|
||||
/* BCM4702 1U CompactPCI Board */
|
||||
#define BCM94702CPCI_BOARD 0x0429
|
||||
|
||||
/* BCM4702 with BCM95380 VLAN Router */
|
||||
#define BCM95380RR_BOARD 0x042a
|
||||
|
||||
/* cb4306 with SiGe PA */
|
||||
#define BCM94306CBSG_BOARD 0x042b
|
||||
|
||||
/* cb4306 with SiGe PA */
|
||||
#define PCSG94306_BOARD 0x042d
|
||||
|
||||
/* bu4704 with sdram */
|
||||
#define BU4704SD_BOARD 0x042e
|
||||
|
||||
/* Dual 11a/11g Router */
|
||||
#define BCM94704AGR_BOARD 0x042f
|
||||
|
||||
/* 11a-only minipci */
|
||||
#define BCM94308MP_BOARD 0x0430
|
||||
|
||||
|
||||
|
||||
#define BU4712_BOARD 0x0444
|
||||
#define BU4712SD_BOARD 0x045d
|
||||
#define BU4712L_BOARD 0x045f
|
||||
|
||||
/* BCM4712 boards */
|
||||
#define BCM94712AP_BOARD 0x0445
|
||||
#define BCM94712P_BOARD 0x0446
|
||||
|
||||
/* BCM4318 boards */
|
||||
#define BU4318_BOARD 0x0447
|
||||
#define CB4318_BOARD 0x0448
|
||||
#define MPG4318_BOARD 0x0449
|
||||
#define MP4318_BOARD 0x044a
|
||||
#define SD4318_BOARD 0x044b
|
||||
|
||||
/* BCM63XX boards */
|
||||
#define BCM96338_BOARD 0x6338
|
||||
#define BCM96348_BOARD 0x6348
|
||||
#define BCM96358_BOARD 0x6358
|
||||
|
||||
/* Another mp4306 with SiGe */
|
||||
#define BCM94306P_BOARD 0x044c
|
||||
|
||||
/* mp4303 */
|
||||
#define BCM94303MP_BOARD 0x044e
|
||||
|
||||
/* mpsgh4306 */
|
||||
#define BCM94306MPSGH_BOARD 0x044f
|
||||
|
||||
/* BRCM 4306 w/ Front End Modules */
|
||||
#define BCM94306MPM 0x0450
|
||||
#define BCM94306MPL 0x0453
|
||||
|
||||
/* 4712agr */
|
||||
#define BCM94712AGR_BOARD 0x0451
|
||||
|
||||
/* pcmcia 4303 */
|
||||
#define PC4303_BOARD 0x0454
|
||||
|
||||
/* 5350K */
|
||||
#define BCM95350K_BOARD 0x0455
|
||||
|
||||
/* 5350R */
|
||||
#define BCM95350R_BOARD 0x0456
|
||||
|
||||
/* 4306mplna */
|
||||
#define BCM94306MPLNA_BOARD 0x0457
|
||||
|
||||
/* 4320 boards */
|
||||
#define BU4320_BOARD 0x0458
|
||||
#define BU4320S_BOARD 0x0459
|
||||
#define BCM94320PH_BOARD 0x045a
|
||||
|
||||
/* 4306mph */
|
||||
#define BCM94306MPH_BOARD 0x045b
|
||||
|
||||
/* 4306pciv */
|
||||
#define BCM94306PCIV_BOARD 0x045c
|
||||
|
||||
#define BU4712SD_BOARD 0x045d
|
||||
|
||||
#define BCM94320PFLSH_BOARD 0x045e
|
||||
|
||||
#define BU4712L_BOARD 0x045f
|
||||
#define BCM94712LGR_BOARD 0x0460
|
||||
#define BCM94320R_BOARD 0x0461
|
||||
|
||||
#define BU5352_BOARD 0x0462
|
||||
|
||||
#define BCM94318MPGH_BOARD 0x0463
|
||||
|
||||
#define BU4311_BOARD 0x0464
|
||||
#define BCM94311MC_BOARD 0x0465
|
||||
#define BCM94311MCAG_BOARD 0x0466
|
||||
|
||||
#define BCM95352GR_BOARD 0x0467
|
||||
|
||||
/* bcm95351agr */
|
||||
#define BCM95351AGR_BOARD 0x0470
|
||||
|
||||
/* bcm94704mpcb */
|
||||
#define BCM94704MPCB_BOARD 0x0472
|
||||
|
||||
/* 4785 boards */
|
||||
#define BU4785_BOARD 0x0478
|
||||
|
||||
/* 4321 boards */
|
||||
#define BU4321_BOARD 0x046b
|
||||
#define BU4321E_BOARD 0x047c
|
||||
#define MP4321_BOARD 0x046c
|
||||
#define CB2_4321_BOARD 0x046d
|
||||
#define MC4321_BOARD 0x046e
|
||||
|
||||
/* 4328 boards */
|
||||
#define BU4328_BOARD 0x0481
|
||||
#define BCM4328SDG_BOARD 0x0482
|
||||
#define BCM4328SDAG_BOARD 0x0483
|
||||
#define BCM4328UG_BOARD 0x0484
|
||||
#define BCM4328UAG_BOARD 0x0485
|
||||
#define BCM4328PC_BOARD 0x0486
|
||||
#define BCM4328CF_BOARD 0x0487
|
||||
|
||||
/* 4325 boards */
|
||||
#define BU4325_BOARD 0x0490
|
||||
|
||||
/* # of GPIO pins */
|
||||
#define GPIO_NUMPINS 16
|
||||
|
||||
/* radio ID codes */
|
||||
#define NORADIO_ID 0xe4f5
|
||||
#define NORADIO_IDCODE 0x4e4f5246
|
||||
|
||||
#define BCM2050_ID 0x2050
|
||||
#define BCM2050_IDCODE 0x02050000
|
||||
#define BCM2050A0_IDCODE 0x1205017f
|
||||
#define BCM2050A1_IDCODE 0x2205017f
|
||||
#define BCM2050R8_IDCODE 0x8205017f
|
||||
|
||||
#define BCM2055_ID 0x2055
|
||||
#define BCM2055_IDCODE 0x02055000
|
||||
#define BCM2055A0_IDCODE 0x1205517f
|
||||
|
||||
#define BCM2060_ID 0x2060
|
||||
#define BCM2060_IDCODE 0x02060000
|
||||
#define BCM2060WW_IDCODE 0x1206017f
|
||||
|
||||
#define BCM2062_ID 0x2062
|
||||
#define BCM2062_IDCODE 0x02062000
|
||||
#define BCM2062A0_IDCODE 0x0206217f
|
||||
|
||||
#define BCM2063_ID 0x2063
|
||||
#define BCM2063_IDCODE 0x02063000
|
||||
#define BCM2063A0_IDCODE 0x0206317f
|
||||
|
||||
/* parts of an idcode: */
|
||||
#define IDCODE_MFG_MASK 0x00000fff
|
||||
#define IDCODE_MFG_SHIFT 0
|
||||
#define IDCODE_ID_MASK 0x0ffff000
|
||||
#define IDCODE_ID_SHIFT 12
|
||||
#define IDCODE_REV_MASK 0xf0000000
|
||||
#define IDCODE_REV_SHIFT 28
|
||||
|
||||
#endif /* _BCMDEVS_H */
|
||||
|
|
@ -1,390 +0,0 @@
|
|||
/*
|
||||
* Broadcom device-specific manifest constants.
|
||||
*
|
||||
* Copyright 2005, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _BCMDEVS_H
|
||||
#define _BCMDEVS_H
|
||||
|
||||
|
||||
/* Known PCI vendor Id's */
|
||||
#define VENDOR_EPIGRAM 0xfeda
|
||||
#define VENDOR_BROADCOM 0x14e4
|
||||
#define VENDOR_3COM 0x10b7
|
||||
#define VENDOR_NETGEAR 0x1385
|
||||
#define VENDOR_DIAMOND 0x1092
|
||||
#define VENDOR_DELL 0x1028
|
||||
#define VENDOR_HP 0x0e11
|
||||
#define VENDOR_APPLE 0x106b
|
||||
|
||||
/* PCI Device Id's */
|
||||
#define BCM4210_DEVICE_ID 0x1072 /* never used */
|
||||
#define BCM4211_DEVICE_ID 0x4211
|
||||
#define BCM4230_DEVICE_ID 0x1086 /* never used */
|
||||
#define BCM4231_DEVICE_ID 0x4231
|
||||
|
||||
#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
|
||||
#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
|
||||
#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
|
||||
#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
|
||||
|
||||
#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
|
||||
#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
|
||||
|
||||
#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
|
||||
#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
|
||||
|
||||
#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
|
||||
#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
|
||||
#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
|
||||
#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
|
||||
#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
|
||||
#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
|
||||
#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
|
||||
#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
|
||||
#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
|
||||
#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
|
||||
#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
|
||||
|
||||
#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
|
||||
|
||||
#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
|
||||
#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
|
||||
#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
|
||||
#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
|
||||
#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
|
||||
#define BCM4610_USB_ID 0x4615 /* 4610 usb */
|
||||
|
||||
#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
|
||||
#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
|
||||
#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
|
||||
#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
|
||||
|
||||
#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
|
||||
#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
|
||||
|
||||
#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
|
||||
#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
|
||||
#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
|
||||
#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
|
||||
|
||||
#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
|
||||
#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
|
||||
#define BCM4306_D11G_ID2 0x4325
|
||||
#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
|
||||
#define BCM4306_UART_ID 0x4322 /* 4306 uart */
|
||||
#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
|
||||
#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
|
||||
|
||||
#define BCM4309_PKG_ID 1 /* 4309 package id */
|
||||
|
||||
#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
|
||||
#define BCM4303_PKG_ID 2 /* 4303 package id */
|
||||
|
||||
#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
|
||||
#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
|
||||
#define BCM4310_UART_ID 0x4312 /* 4310 uart */
|
||||
#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
|
||||
#define BCM4310_USB_ID 0x4315 /* 4310 usb */
|
||||
|
||||
#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
|
||||
#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
|
||||
|
||||
|
||||
#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
|
||||
#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
|
||||
|
||||
#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
|
||||
|
||||
#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
|
||||
#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
|
||||
#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
|
||||
#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
|
||||
|
||||
#define FPGA_JTAGM_ID 0x4330 /* ??? */
|
||||
|
||||
/* Address map */
|
||||
#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
|
||||
#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
|
||||
#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
|
||||
#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
|
||||
#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
|
||||
#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
|
||||
|
||||
/* Core register space */
|
||||
#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
|
||||
#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
|
||||
#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
|
||||
#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
|
||||
#define BCM4710_REG_USB 0x18004000 /* USB core registers */
|
||||
#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
|
||||
#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
|
||||
#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
|
||||
#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
|
||||
|
||||
#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
|
||||
#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
|
||||
#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
|
||||
#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
|
||||
#define BCM4710_PROG 0x1f800000 /* Programable interface */
|
||||
#define BCM4710_FLASH 0x1fc00000 /* Flash */
|
||||
|
||||
#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
|
||||
|
||||
#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
|
||||
|
||||
#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
|
||||
#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
|
||||
|
||||
#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
|
||||
#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
|
||||
#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
|
||||
#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
|
||||
#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
|
||||
|
||||
#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
|
||||
|
||||
#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
|
||||
#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
|
||||
#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
|
||||
|
||||
#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
|
||||
|
||||
/* PCMCIA vendor Id's */
|
||||
|
||||
#define VENDOR_BROADCOM_PCMCIA 0x02d0
|
||||
|
||||
/* SDIO vendor Id's */
|
||||
#define VENDOR_BROADCOM_SDIO 0x00BF
|
||||
|
||||
|
||||
/* boardflags */
|
||||
#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
|
||||
#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
|
||||
#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
|
||||
#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
|
||||
#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
|
||||
#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
|
||||
#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
|
||||
#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
|
||||
#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
|
||||
#define BFL_FEM 0x0800 /* This board supports the Front End Module */
|
||||
#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
|
||||
#define BFL_HGPA 0x2000 /* This board has a high gain PA */
|
||||
#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
|
||||
#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
|
||||
|
||||
/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
|
||||
#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
|
||||
#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
|
||||
#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
|
||||
#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
|
||||
#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
|
||||
#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
|
||||
#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
|
||||
#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
|
||||
#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
|
||||
#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
|
||||
|
||||
/* Bus types */
|
||||
#define SB_BUS 0 /* Silicon Backplane */
|
||||
#define PCI_BUS 1 /* PCI target */
|
||||
#define PCMCIA_BUS 2 /* PCMCIA target */
|
||||
#define SDIO_BUS 3 /* SDIO target */
|
||||
#define JTAG_BUS 4 /* JTAG */
|
||||
|
||||
/* Allows optimization for single-bus support */
|
||||
#ifdef BCMBUSTYPE
|
||||
#define BUSTYPE(bus) (BCMBUSTYPE)
|
||||
#else
|
||||
#define BUSTYPE(bus) (bus)
|
||||
#endif
|
||||
|
||||
/* power control defines */
|
||||
#define PLL_DELAY 150 /* us pll on delay */
|
||||
#define FREF_DELAY 200 /* us fref change delay */
|
||||
#define MIN_SLOW_CLK 32 /* us Slow clock period */
|
||||
#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
|
||||
|
||||
/* Reference Board Types */
|
||||
|
||||
#define BU4710_BOARD 0x0400
|
||||
#define VSIM4710_BOARD 0x0401
|
||||
#define QT4710_BOARD 0x0402
|
||||
|
||||
#define BU4610_BOARD 0x0403
|
||||
#define VSIM4610_BOARD 0x0404
|
||||
|
||||
#define BU4307_BOARD 0x0405
|
||||
#define BCM94301CB_BOARD 0x0406
|
||||
#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
|
||||
#define BCM94301MP_BOARD 0x0407
|
||||
#define BCM94307MP_BOARD 0x0408
|
||||
#define BCMAP4307_BOARD 0x0409
|
||||
|
||||
#define BU4309_BOARD 0x040a
|
||||
#define BCM94309CB_BOARD 0x040b
|
||||
#define BCM94309MP_BOARD 0x040c
|
||||
#define BCM4309AP_BOARD 0x040d
|
||||
|
||||
#define BCM94302MP_BOARD 0x040e
|
||||
|
||||
#define VSIM4310_BOARD 0x040f
|
||||
#define BU4711_BOARD 0x0410
|
||||
#define BCM94310U_BOARD 0x0411
|
||||
#define BCM94310AP_BOARD 0x0412
|
||||
#define BCM94310MP_BOARD 0x0414
|
||||
|
||||
#define BU4306_BOARD 0x0416
|
||||
#define BCM94306CB_BOARD 0x0417
|
||||
#define BCM94306MP_BOARD 0x0418
|
||||
|
||||
#define BCM94710D_BOARD 0x041a
|
||||
#define BCM94710R1_BOARD 0x041b
|
||||
#define BCM94710R4_BOARD 0x041c
|
||||
#define BCM94710AP_BOARD 0x041d
|
||||
|
||||
|
||||
#define BU2050_BOARD 0x041f
|
||||
|
||||
|
||||
#define BCM94309G_BOARD 0x0421
|
||||
|
||||
#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
|
||||
|
||||
#define BU4704_BOARD 0x0423
|
||||
#define BU4702_BOARD 0x0424
|
||||
|
||||
#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
|
||||
|
||||
#define BU4317_BOARD 0x0426
|
||||
|
||||
|
||||
#define BCM94702MN_BOARD 0x0428
|
||||
|
||||
/* BCM4702 1U CompactPCI Board */
|
||||
#define BCM94702CPCI_BOARD 0x0429
|
||||
|
||||
/* BCM4702 with BCM95380 VLAN Router */
|
||||
#define BCM95380RR_BOARD 0x042a
|
||||
|
||||
/* cb4306 with SiGe PA */
|
||||
#define BCM94306CBSG_BOARD 0x042b
|
||||
|
||||
/* mp4301 with 2050 radio */
|
||||
#define BCM94301MPL_BOARD 0x042c
|
||||
|
||||
/* cb4306 with SiGe PA */
|
||||
#define PCSG94306_BOARD 0x042d
|
||||
|
||||
/* bu4704 with sdram */
|
||||
#define BU4704SD_BOARD 0x042e
|
||||
|
||||
/* Dual 11a/11g Router */
|
||||
#define BCM94704AGR_BOARD 0x042f
|
||||
|
||||
/* 11a-only minipci */
|
||||
#define BCM94308MP_BOARD 0x0430
|
||||
|
||||
|
||||
|
||||
/* BCM94317 boards */
|
||||
#define BCM94317CB_BOARD 0x0440
|
||||
#define BCM94317MP_BOARD 0x0441
|
||||
#define BCM94317PCMCIA_BOARD 0x0442
|
||||
#define BCM94317SDIO_BOARD 0x0443
|
||||
|
||||
#define BU4712_BOARD 0x0444
|
||||
#define BU4712SD_BOARD 0x045d
|
||||
#define BU4712L_BOARD 0x045f
|
||||
|
||||
/* BCM4712 boards */
|
||||
#define BCM94712AP_BOARD 0x0445
|
||||
#define BCM94712P_BOARD 0x0446
|
||||
|
||||
/* BCM4318 boards */
|
||||
#define BU4318_BOARD 0x0447
|
||||
#define CB4318_BOARD 0x0448
|
||||
#define MPG4318_BOARD 0x0449
|
||||
#define MP4318_BOARD 0x044a
|
||||
#define SD4318_BOARD 0x044b
|
||||
|
||||
/* BCM63XX boards */
|
||||
#define BCM96338_BOARD 0x6338
|
||||
#define BCM96345_BOARD 0x6345
|
||||
#define BCM96348_BOARD 0x6348
|
||||
|
||||
/* Another mp4306 with SiGe */
|
||||
#define BCM94306P_BOARD 0x044c
|
||||
|
||||
/* CF-like 4317 modules */
|
||||
#define BCM94317CF_BOARD 0x044d
|
||||
|
||||
/* mp4303 */
|
||||
#define BCM94303MP_BOARD 0x044e
|
||||
|
||||
/* mpsgh4306 */
|
||||
#define BCM94306MPSGH_BOARD 0x044f
|
||||
|
||||
/* BRCM 4306 w/ Front End Modules */
|
||||
#define BCM94306MPM 0x0450
|
||||
#define BCM94306MPL 0x0453
|
||||
|
||||
/* 4712agr */
|
||||
#define BCM94712AGR_BOARD 0x0451
|
||||
|
||||
/* The real CF 4317 board */
|
||||
#define CFI4317_BOARD 0x0452
|
||||
|
||||
/* pcmcia 4303 */
|
||||
#define PC4303_BOARD 0x0454
|
||||
|
||||
/* 5350K */
|
||||
#define BCM95350K_BOARD 0x0455
|
||||
|
||||
/* 5350R */
|
||||
#define BCM95350R_BOARD 0x0456
|
||||
|
||||
/* 4306mplna */
|
||||
#define BCM94306MPLNA_BOARD 0x0457
|
||||
|
||||
/* 4320 boards */
|
||||
#define BU4320_BOARD 0x0458
|
||||
#define BU4320S_BOARD 0x0459
|
||||
#define BCM94320PH_BOARD 0x045a
|
||||
|
||||
/* 4306mph */
|
||||
#define BCM94306MPH_BOARD 0x045b
|
||||
|
||||
/* 4306pciv */
|
||||
#define BCM94306PCIV_BOARD 0x045c
|
||||
|
||||
#define BU4712SD_BOARD 0x045d
|
||||
|
||||
#define BCM94320PFLSH_BOARD 0x045e
|
||||
|
||||
#define BU4712L_BOARD 0x045f
|
||||
#define BCM94712LGR_BOARD 0x0460
|
||||
#define BCM94320R_BOARD 0x0461
|
||||
|
||||
#define BU5352_BOARD 0x0462
|
||||
|
||||
#define BCM94318MPGH_BOARD 0x0463
|
||||
|
||||
|
||||
#define BCM95352GR_BOARD 0x0467
|
||||
|
||||
/* bcm95351agr */
|
||||
#define BCM95351AGR_BOARD 0x0470
|
||||
|
||||
/* # of GPIO pins */
|
||||
#define GPIO_NUMPINS 16
|
||||
|
||||
#endif /* _BCMDEVS_H */
|
||||
|
|
@ -1,197 +0,0 @@
|
|||
/*
|
||||
* local version of endian.h - byte order defines
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _BCMENDIAN_H_
|
||||
#define _BCMENDIAN_H_
|
||||
|
||||
#include <typedefs.h>
|
||||
|
||||
/* Byte swap a 16 bit value */
|
||||
#define BCMSWAP16(val) \
|
||||
((uint16)(\
|
||||
(((uint16)(val) & (uint16)0x00ffU) << 8) | \
|
||||
(((uint16)(val) & (uint16)0xff00U) >> 8)))
|
||||
|
||||
/* Byte swap a 32 bit value */
|
||||
#define BCMSWAP32(val) \
|
||||
((uint32)(\
|
||||
(((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
|
||||
(((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
|
||||
(((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
|
||||
(((uint32)(val) & (uint32)0xff000000UL) >> 24)))
|
||||
|
||||
/* 2 Byte swap a 32 bit value */
|
||||
#define BCMSWAP32BY16(val) \
|
||||
((uint32)(\
|
||||
(((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
|
||||
(((uint32)(val) & (uint32)0xffff0000UL) >> 16)))
|
||||
|
||||
|
||||
static INLINE uint16
|
||||
bcmswap16(uint16 val)
|
||||
{
|
||||
return BCMSWAP16(val);
|
||||
}
|
||||
|
||||
static INLINE uint32
|
||||
bcmswap32(uint32 val)
|
||||
{
|
||||
return BCMSWAP32(val);
|
||||
}
|
||||
|
||||
static INLINE uint32
|
||||
bcmswap32by16(uint32 val)
|
||||
{
|
||||
return BCMSWAP32BY16(val);
|
||||
}
|
||||
|
||||
/* buf - start of buffer of shorts to swap */
|
||||
/* len - byte length of buffer */
|
||||
static INLINE void
|
||||
bcmswap16_buf(uint16 *buf, uint len)
|
||||
{
|
||||
len = len/2;
|
||||
|
||||
while (len--) {
|
||||
*buf = bcmswap16(*buf);
|
||||
buf++;
|
||||
}
|
||||
}
|
||||
|
||||
#ifndef hton16
|
||||
#ifndef IL_BIGENDIAN
|
||||
#define HTON16(i) BCMSWAP16(i)
|
||||
#define hton16(i) bcmswap16(i)
|
||||
#define hton32(i) bcmswap32(i)
|
||||
#define ntoh16(i) bcmswap16(i)
|
||||
#define ntoh32(i) bcmswap32(i)
|
||||
#define ltoh16(i) (i)
|
||||
#define ltoh32(i) (i)
|
||||
#define htol16(i) (i)
|
||||
#define htol32(i) (i)
|
||||
#else
|
||||
#define HTON16(i) (i)
|
||||
#define hton16(i) (i)
|
||||
#define hton32(i) (i)
|
||||
#define ntoh16(i) (i)
|
||||
#define ntoh32(i) (i)
|
||||
#define ltoh16(i) bcmswap16(i)
|
||||
#define ltoh32(i) bcmswap32(i)
|
||||
#define htol16(i) bcmswap16(i)
|
||||
#define htol32(i) bcmswap32(i)
|
||||
#endif /* IL_BIGENDIAN */
|
||||
#endif /* hton16 */
|
||||
|
||||
#ifndef IL_BIGENDIAN
|
||||
#define ltoh16_buf(buf, i)
|
||||
#define htol16_buf(buf, i)
|
||||
#else
|
||||
#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
|
||||
#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
|
||||
#endif /* IL_BIGENDIAN */
|
||||
|
||||
/*
|
||||
* store 16-bit value to unaligned little endian byte array.
|
||||
*/
|
||||
static INLINE void
|
||||
htol16_ua_store(uint16 val, uint8 *bytes)
|
||||
{
|
||||
bytes[0] = val&0xff;
|
||||
bytes[1] = val>>8;
|
||||
}
|
||||
|
||||
/*
|
||||
* store 32-bit value to unaligned little endian byte array.
|
||||
*/
|
||||
static INLINE void
|
||||
htol32_ua_store(uint32 val, uint8 *bytes)
|
||||
{
|
||||
bytes[0] = val&0xff;
|
||||
bytes[1] = (val>>8)&0xff;
|
||||
bytes[2] = (val>>16)&0xff;
|
||||
bytes[3] = val>>24;
|
||||
}
|
||||
|
||||
/*
|
||||
* store 16-bit value to unaligned network(big) endian byte array.
|
||||
*/
|
||||
static INLINE void
|
||||
hton16_ua_store(uint16 val, uint8 *bytes)
|
||||
{
|
||||
bytes[1] = val&0xff;
|
||||
bytes[0] = val>>8;
|
||||
}
|
||||
|
||||
/*
|
||||
* store 32-bit value to unaligned network(big) endian byte array.
|
||||
*/
|
||||
static INLINE void
|
||||
hton32_ua_store(uint32 val, uint8 *bytes)
|
||||
{
|
||||
bytes[3] = val&0xff;
|
||||
bytes[2] = (val>>8)&0xff;
|
||||
bytes[1] = (val>>16)&0xff;
|
||||
bytes[0] = val>>24;
|
||||
}
|
||||
|
||||
/*
|
||||
* load 16-bit value from unaligned little endian byte array.
|
||||
*/
|
||||
static INLINE uint16
|
||||
ltoh16_ua(void *bytes)
|
||||
{
|
||||
return (((uint8*)bytes)[1]<<8)+((uint8 *)bytes)[0];
|
||||
}
|
||||
|
||||
/*
|
||||
* load 32-bit value from unaligned little endian byte array.
|
||||
*/
|
||||
static INLINE uint32
|
||||
ltoh32_ua(void *bytes)
|
||||
{
|
||||
return (((uint8*)bytes)[3]<<24)+(((uint8*)bytes)[2]<<16)+
|
||||
(((uint8*)bytes)[1]<<8)+((uint8*)bytes)[0];
|
||||
}
|
||||
|
||||
/*
|
||||
* load 16-bit value from unaligned big(network) endian byte array.
|
||||
*/
|
||||
static INLINE uint16
|
||||
ntoh16_ua(void *bytes)
|
||||
{
|
||||
return (((uint8*)bytes)[0]<<8)+((uint8*)bytes)[1];
|
||||
}
|
||||
|
||||
/*
|
||||
* load 32-bit value from unaligned big(network) endian byte array.
|
||||
*/
|
||||
static INLINE uint32
|
||||
ntoh32_ua(void *bytes)
|
||||
{
|
||||
return (((uint8*)bytes)[0]<<24)+(((uint8*)bytes)[1]<<16)+
|
||||
(((uint8*)bytes)[2]<<8)+((uint8*)bytes)[3];
|
||||
}
|
||||
|
||||
#define ltoh_ua(ptr) (\
|
||||
sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
|
||||
sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
|
||||
(((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
|
||||
)
|
||||
|
||||
#define ntoh_ua(ptr) (\
|
||||
sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
|
||||
sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
|
||||
(((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
|
||||
)
|
||||
|
||||
#endif /* _BCMENDIAN_H_ */
|
||||
|
|
@ -1,167 +0,0 @@
|
|||
/*
|
||||
* NVRAM variable manipulation
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _bcmnvram_h_
|
||||
#define _bcmnvram_h_
|
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <bcmdefs.h>
|
||||
|
||||
struct nvram_header {
|
||||
uint32 magic;
|
||||
uint32 len;
|
||||
uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
|
||||
uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
|
||||
uint32 config_ncdl; /* ncdl values for memc */
|
||||
};
|
||||
|
||||
struct nvram_tuple {
|
||||
char *name;
|
||||
char *value;
|
||||
struct nvram_tuple *next;
|
||||
};
|
||||
|
||||
/*
|
||||
* Get default value for an NVRAM variable
|
||||
*/
|
||||
extern char *nvram_default_get(const char *name);
|
||||
|
||||
/*
|
||||
* Append a chunk of nvram variables to the global list
|
||||
*/
|
||||
extern int nvram_append(void *sb, char *vars, uint varsz);
|
||||
|
||||
/*
|
||||
* Check for reset button press for restoring factory defaults.
|
||||
*/
|
||||
extern bool nvram_reset(void *sbh);
|
||||
|
||||
/*
|
||||
* Disable NVRAM access. May be unnecessary or undefined on certain
|
||||
* platforms.
|
||||
*/
|
||||
extern void nvram_exit(void *sbh);
|
||||
|
||||
/*
|
||||
* Get the value of an NVRAM variable. The pointer returned may be
|
||||
* invalid after a set.
|
||||
* @param name name of variable to get
|
||||
* @return value of variable or NULL if undefined
|
||||
*/
|
||||
extern char * nvram_get(const char *name);
|
||||
|
||||
/*
|
||||
* Read the reset GPIO value from the nvram and set the GPIO
|
||||
* as input
|
||||
*/
|
||||
extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
|
||||
|
||||
/*
|
||||
* Get the value of an NVRAM variable.
|
||||
* @param name name of variable to get
|
||||
* @return value of variable or NUL if undefined
|
||||
*/
|
||||
#define nvram_safe_get(name) (nvram_get(name) ? : "")
|
||||
|
||||
/*
|
||||
* Match an NVRAM variable.
|
||||
* @param name name of variable to match
|
||||
* @param match value to compare against value of variable
|
||||
* @return TRUE if variable is defined and its value is string equal
|
||||
* to match or FALSE otherwise
|
||||
*/
|
||||
static INLINE int
|
||||
nvram_match(char *name, char *match) {
|
||||
const char *value = nvram_get(name);
|
||||
return (value && !strcmp(value, match));
|
||||
}
|
||||
|
||||
/*
|
||||
* Inversely match an NVRAM variable.
|
||||
* @param name name of variable to match
|
||||
* @param match value to compare against value of variable
|
||||
* @return TRUE if variable is defined and its value is not string
|
||||
* equal to invmatch or FALSE otherwise
|
||||
*/
|
||||
static INLINE int
|
||||
nvram_invmatch(char *name, char *invmatch) {
|
||||
const char *value = nvram_get(name);
|
||||
return (value && strcmp(value, invmatch));
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the value of an NVRAM variable. The name and value strings are
|
||||
* copied into private storage. Pointers to previously set values
|
||||
* may become invalid. The new value may be immediately
|
||||
* retrieved but will not be permanently stored until a commit.
|
||||
* @param name name of variable to set
|
||||
* @param value value of variable
|
||||
* @return 0 on success and errno on failure
|
||||
*/
|
||||
extern int nvram_set(const char *name, const char *value);
|
||||
|
||||
/*
|
||||
* Unset an NVRAM variable. Pointers to previously set values
|
||||
* remain valid until a set.
|
||||
* @param name name of variable to unset
|
||||
* @return 0 on success and errno on failure
|
||||
* NOTE: use nvram_commit to commit this change to flash.
|
||||
*/
|
||||
extern int nvram_unset(const char *name);
|
||||
|
||||
/*
|
||||
* Commit NVRAM variables to permanent storage. All pointers to values
|
||||
* may be invalid after a commit.
|
||||
* NVRAM values are undefined after a commit.
|
||||
* @return 0 on success and errno on failure
|
||||
*/
|
||||
extern int nvram_commit(void);
|
||||
|
||||
/*
|
||||
* Get all NVRAM variables (format name=value\0 ... \0\0).
|
||||
* @param buf buffer to store variables
|
||||
* @param count size of buffer in bytes
|
||||
* @return 0 on success and errno on failure
|
||||
*/
|
||||
extern int nvram_getall(char *nvram_buf, int count);
|
||||
|
||||
/*
|
||||
* returns the crc value of the nvram
|
||||
* @param nvh nvram header pointer
|
||||
*/
|
||||
extern uint8 nvram_calc_crc(struct nvram_header * nvh);
|
||||
|
||||
extern char* getvar(char *vars, const char *name);
|
||||
extern int getintvar(char *vars, const char *name);
|
||||
|
||||
#endif /* _LANGUAGE_ASSEMBLY */
|
||||
|
||||
/* The NVRAM version number stored as an NVRAM variable */
|
||||
#define NVRAM_SOFTWARE_VERSION "1"
|
||||
|
||||
#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
|
||||
#define NVRAM_CLEAR_MAGIC 0x0
|
||||
#define NVRAM_INVALID_MAGIC 0xFFFFFFFF
|
||||
#define NVRAM_VERSION 1
|
||||
#define NVRAM_HEADER_SIZE 20
|
||||
#define NVRAM_SPACE 0x8000
|
||||
|
||||
#define NVRAM_MAX_VALUE_LEN 255
|
||||
#define NVRAM_MAX_PARAM_LEN 64
|
||||
|
||||
#define NVRAM_CRC_START_POSITION 9 /* magic, len, crc8 to be skipped */
|
||||
#define NVRAM_CRC_VER_MASK 0xffffff00 /* for crc_ver_init */
|
||||
|
||||
#endif /* _bcmnvram_h_ */
|
||||
|
|
@ -1,309 +0,0 @@
|
|||
/*
|
||||
* Misc useful routines to access NIC local SROM/OTP .
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _bcmsrom_h_
|
||||
#define _bcmsrom_h_
|
||||
|
||||
/* Maximum srom: 4 Kilobits == 512 bytes */
|
||||
#define SROM_MAX 512
|
||||
|
||||
|
||||
#define SROM_WORDS 64
|
||||
|
||||
#define SROM3_SWRGN_OFF 28 /* s/w region offset in words */
|
||||
|
||||
#define SROM_SSID 2
|
||||
|
||||
#define SROM_WL1LHMAXP 29
|
||||
|
||||
#define SROM_WL1LPAB0 30
|
||||
#define SROM_WL1LPAB1 31
|
||||
#define SROM_WL1LPAB2 32
|
||||
|
||||
#define SROM_WL1HPAB0 33
|
||||
#define SROM_WL1HPAB1 34
|
||||
#define SROM_WL1HPAB2 35
|
||||
|
||||
#define SROM_MACHI_IL0 36
|
||||
#define SROM_MACMID_IL0 37
|
||||
#define SROM_MACLO_IL0 38
|
||||
#define SROM_MACHI_ET0 39
|
||||
#define SROM_MACMID_ET0 40
|
||||
#define SROM_MACLO_ET0 41
|
||||
#define SROM_MACHI_ET1 42
|
||||
#define SROM_MACMID_ET1 43
|
||||
#define SROM_MACLO_ET1 44
|
||||
#define SROM3_MACHI 37
|
||||
#define SROM3_MACMID 38
|
||||
#define SROM3_MACLO 39
|
||||
|
||||
#define SROM_BXARSSI2G 40
|
||||
#define SROM_BXARSSI5G 41
|
||||
|
||||
#define SROM_TRI52G 42
|
||||
#define SROM_TRI5GHL 43
|
||||
|
||||
#define SROM_RXPO52G 45
|
||||
|
||||
#define SROM2_ENETPHY 45
|
||||
|
||||
#define SROM_AABREV 46
|
||||
/* Fields in AABREV */
|
||||
#define SROM_BR_MASK 0x00ff
|
||||
#define SROM_CC_MASK 0x0f00
|
||||
#define SROM_CC_SHIFT 8
|
||||
#define SROM_AA0_MASK 0x3000
|
||||
#define SROM_AA0_SHIFT 12
|
||||
#define SROM_AA1_MASK 0xc000
|
||||
#define SROM_AA1_SHIFT 14
|
||||
|
||||
#define SROM_WL0PAB0 47
|
||||
#define SROM_WL0PAB1 48
|
||||
#define SROM_WL0PAB2 49
|
||||
|
||||
#define SROM_LEDBH10 50
|
||||
#define SROM_LEDBH32 51
|
||||
|
||||
#define SROM_WL10MAXP 52
|
||||
|
||||
#define SROM_WL1PAB0 53
|
||||
#define SROM_WL1PAB1 54
|
||||
#define SROM_WL1PAB2 55
|
||||
|
||||
#define SROM_ITT 56
|
||||
|
||||
#define SROM_BFL 57
|
||||
#define SROM_BFL2 28
|
||||
#define SROM3_BFL2 61
|
||||
|
||||
#define SROM_AG10 58
|
||||
|
||||
#define SROM_CCODE 59
|
||||
|
||||
#define SROM_OPO 60
|
||||
|
||||
#define SROM3_LEDDC 62
|
||||
|
||||
#define SROM_CRCREV 63
|
||||
|
||||
/* SROM Rev 4: Reallocate the software part of the srom to accomodate
|
||||
* MIMO features. It assumes up to two PCIE functions and 440 bytes
|
||||
* of useable srom i.e. the useable storage in chips with OTP that
|
||||
* implements hardware redundancy.
|
||||
*/
|
||||
|
||||
#define SROM4_WORDS 220
|
||||
|
||||
#define SROM4_SIGN 32
|
||||
#define SROM4_SIGNATURE 0x5372
|
||||
|
||||
#define SROM4_BREV 33
|
||||
|
||||
#define SROM4_BFL0 34
|
||||
#define SROM4_BFL1 35
|
||||
#define SROM4_BFL2 36
|
||||
#define SROM4_BFL3 37
|
||||
#define SROM5_BFL0 37
|
||||
#define SROM5_BFL1 38
|
||||
#define SROM5_BFL2 39
|
||||
#define SROM5_BFL3 40
|
||||
|
||||
#define SROM4_MACHI 38
|
||||
#define SROM4_MACMID 39
|
||||
#define SROM4_MACLO 40
|
||||
#define SROM5_MACHI 41
|
||||
#define SROM5_MACMID 42
|
||||
#define SROM5_MACLO 43
|
||||
|
||||
#define SROM4_CCODE 41
|
||||
#define SROM4_REGREV 42
|
||||
#define SROM5_CCODE 34
|
||||
#define SROM5_REGREV 35
|
||||
|
||||
#define SROM4_LEDBH10 43
|
||||
#define SROM4_LEDBH32 44
|
||||
#define SROM5_LEDBH10 59
|
||||
#define SROM5_LEDBH32 60
|
||||
|
||||
#define SROM4_LEDDC 45
|
||||
#define SROM5_LEDDC 45
|
||||
|
||||
#define SROM4_AA 46
|
||||
#define SROM4_AA2G_MASK 0x00ff
|
||||
#define SROM4_AA2G_SHIFT 0
|
||||
#define SROM4_AA5G_MASK 0xff00
|
||||
#define SROM4_AA5G_SHIFT 8
|
||||
|
||||
#define SROM4_AG10 47
|
||||
#define SROM4_AG32 48
|
||||
|
||||
#define SROM4_TXPID2G 49
|
||||
#define SROM4_TXPID5G 51
|
||||
#define SROM4_TXPID5GL 53
|
||||
#define SROM4_TXPID5GH 55
|
||||
|
||||
#define SROM4_TXRXC 61
|
||||
#define SROM4_TXCHAIN_MASK 0x000f
|
||||
#define SROM4_TXCHAIN_SHIFT 0
|
||||
#define SROM4_RXCHAIN_MASK 0x00f0
|
||||
#define SROM4_RXCHAIN_SHIFT 4
|
||||
#define SROM4_SWITCH_MASK 0xff00
|
||||
#define SROM4_SWITCH_SHIFT 8
|
||||
|
||||
/* Per-path fields */
|
||||
#define MAX_PATH 4
|
||||
#define SROM4_PATH0 64
|
||||
#define SROM4_PATH1 87
|
||||
#define SROM4_PATH2 110
|
||||
#define SROM4_PATH3 133
|
||||
|
||||
#define SROM4_2G_ITT_MAXP 0
|
||||
#define SROM4_2G_PA 1
|
||||
#define SROM4_5G_ITT_MAXP 5
|
||||
#define SROM4_5GLH_MAXP 6
|
||||
#define SROM4_5G_PA 7
|
||||
#define SROM4_5GL_PA 11
|
||||
#define SROM4_5GH_PA 15
|
||||
|
||||
/* Fields in the ITT_MAXP and 5GLH_MAXP words */
|
||||
#define B2G_MAXP_MASK 0xff
|
||||
#define B2G_ITT_SHIFT 8
|
||||
#define B5G_MAXP_MASK 0xff
|
||||
#define B5G_ITT_SHIFT 8
|
||||
#define B5GH_MAXP_MASK 0xff
|
||||
#define B5GL_MAXP_SHIFT 8
|
||||
|
||||
/* All the miriad power offsets */
|
||||
#define SROM4_2G_CCKPO 156
|
||||
#define SROM4_2G_OFDMPO 157
|
||||
#define SROM4_5G_OFDMPO 159
|
||||
#define SROM4_5GL_OFDMPO 161
|
||||
#define SROM4_5GH_OFDMPO 163
|
||||
#define SROM4_2G_MCSPO 165
|
||||
#define SROM4_5G_MCSPO 173
|
||||
#define SROM4_5GL_MCSPO 181
|
||||
#define SROM4_5GH_MCSPO 189
|
||||
#define SROM4_CDDPO 197
|
||||
#define SROM4_STBCPO 198
|
||||
#define SROM4_BW40PO 199
|
||||
#define SROM4_BWDUPPO 200
|
||||
|
||||
#define SROM4_CRCREV 219
|
||||
|
||||
|
||||
/*SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
|
||||
* This is acombined srom for both MIMO and SISO boards, usable in
|
||||
* the .130 4Kilobit OTP with hardware redundancy.
|
||||
*/
|
||||
|
||||
#define SROM8_SIGN 64
|
||||
|
||||
#define SROM8_BREV 65
|
||||
|
||||
#define SROM8_BFL0 66
|
||||
#define SROM8_BFL1 67
|
||||
#define SROM8_BFL2 68
|
||||
#define SROM8_BFL3 69
|
||||
|
||||
#define SROM8_MACHI 70
|
||||
#define SROM8_MACMID 71
|
||||
#define SROM8_MACLO 72
|
||||
|
||||
#define SROM8_CCODE 73
|
||||
#define SROM8_REGREV 74
|
||||
|
||||
#define SROM8_LEDBH10 75
|
||||
#define SROM8_LEDBH32 76
|
||||
|
||||
#define SROM8_LEDDC 77
|
||||
|
||||
#define SROM8_AA 78
|
||||
|
||||
#define SROM8_AG10 79
|
||||
#define SROM8_AG32 80
|
||||
|
||||
#define SROM8_TXRXC 81
|
||||
|
||||
#define SROM8_BXARSSI2G 82
|
||||
#define SROM8_BXARSSI5G 83
|
||||
#define SROM8_TRI52G 84
|
||||
#define SROM8_TRI5GHL 85
|
||||
#define SROM8_RXPO52G 86
|
||||
|
||||
/* Per-path offsets & fields */
|
||||
#define SROM8_PATH0 96
|
||||
#define SROM8_PATH1 112
|
||||
#define SROM8_PATH2 128
|
||||
#define SROM8_PATH3 144
|
||||
|
||||
#define SROM8_2G_ITT_MAXP 0
|
||||
#define SROM8_2G_PA 1
|
||||
#define SROM8_5G_ITT_MAXP 4
|
||||
#define SROM8_5GLH_MAXP 5
|
||||
#define SROM8_5G_PA 6
|
||||
#define SROM8_5GL_PA 9
|
||||
#define SROM8_5GH_PA 12
|
||||
|
||||
/* All the miriad power offsets */
|
||||
#define SROM8_2G_CCKPO 160
|
||||
|
||||
#define SROM8_2G_OFDMPO 161
|
||||
#define SROM8_5G_OFDMPO 163
|
||||
#define SROM8_5GL_OFDMPO 165
|
||||
#define SROM8_5GH_OFDMPO 167
|
||||
|
||||
#define SROM8_2G_MCSPO 169
|
||||
#define SROM8_5G_MCSPO 177
|
||||
#define SROM8_5GL_MCSPO 185
|
||||
#define SROM8_5GH_MCSPO 193
|
||||
|
||||
#define SROM8_CDDPO 201
|
||||
#define SROM8_STBCPO 202
|
||||
#define SROM8_BW40PO 203
|
||||
#define SROM8_BWDUPPO 204
|
||||
|
||||
/* SISO PA parameters are in the path0 spaces */
|
||||
#define SROM8_SISO 96
|
||||
|
||||
/* Legacy names for SISO PA paramters */
|
||||
#define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP)
|
||||
#define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA)
|
||||
#define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1)
|
||||
#define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2)
|
||||
#define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP)
|
||||
#define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP)
|
||||
#define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA)
|
||||
#define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1)
|
||||
#define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2)
|
||||
#define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA)
|
||||
#define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1)
|
||||
#define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2)
|
||||
#define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA)
|
||||
#define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1)
|
||||
#define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2)
|
||||
|
||||
#define SROM8_CRCREV 219
|
||||
|
||||
/* Prototypes */
|
||||
extern int srom_var_init(sb_t *sbh, uint bus, void *curmap, osl_t *osh,
|
||||
char **vars, uint *count);
|
||||
|
||||
extern int srom_read(sb_t *sbh, uint bus, void *curmap, osl_t *osh,
|
||||
uint byteoff, uint nbytes, uint16 *buf);
|
||||
extern int srom_write(sb_t *sbh, uint bus, void *curmap, osl_t *osh,
|
||||
uint byteoff, uint nbytes, uint16 *buf);
|
||||
|
||||
extern int srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt,
|
||||
char **vars, uint *count);
|
||||
|
||||
#endif /* _bcmsrom_h_ */
|
||||
|
|
@ -1,589 +0,0 @@
|
|||
/*
|
||||
* Misc useful os-independent macros and functions.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _bcmutils_h_
|
||||
#define _bcmutils_h_
|
||||
|
||||
/* ctype replacement */
|
||||
#define _BCM_U 0x01 /* upper */
|
||||
#define _BCM_L 0x02 /* lower */
|
||||
#define _BCM_D 0x04 /* digit */
|
||||
#define _BCM_C 0x08 /* cntrl */
|
||||
#define _BCM_P 0x10 /* punct */
|
||||
#define _BCM_S 0x20 /* white space (space/lf/tab) */
|
||||
#define _BCM_X 0x40 /* hex digit */
|
||||
#define _BCM_SP 0x80 /* hard space (0x20) */
|
||||
|
||||
extern const unsigned char bcm_ctype[];
|
||||
#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
|
||||
|
||||
#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
|
||||
#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
|
||||
#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
|
||||
#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
|
||||
#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
|
||||
#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
|
||||
#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
|
||||
#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
|
||||
#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
|
||||
#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
|
||||
#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
|
||||
#define bcm_tolower(c) (bcm_isupper((c)) ? ((c) + 'a' - 'A') : (c))
|
||||
#define bcm_toupper(c) (bcm_islower((c)) ? ((c) + 'A' - 'a') : (c))
|
||||
|
||||
/* Buffer structure for collecting string-formatted data
|
||||
* using bcm_bprintf() API.
|
||||
* Use bcm_binit() to initialize before use
|
||||
*/
|
||||
|
||||
struct bcmstrbuf {
|
||||
char *buf; /* pointer to current position in origbuf */
|
||||
unsigned int size; /* current (residual) size in bytes */
|
||||
char *origbuf; /* unmodified pointer to orignal buffer */
|
||||
unsigned int origsize; /* unmodified orignal buffer size in bytes */
|
||||
};
|
||||
|
||||
/* ** driver-only section ** */
|
||||
#ifdef BCMDRIVER
|
||||
#include <osl.h>
|
||||
|
||||
#define GPIO_PIN_NOTDEFINED 0x20 /* Pin not defined */
|
||||
|
||||
/*
|
||||
* Spin at most 'us' microseconds while 'exp' is true.
|
||||
* Caller should explicitly test 'exp' when this completes
|
||||
* and take appropriate error action if 'exp' is still true.
|
||||
*/
|
||||
#define SPINWAIT(exp, us) { \
|
||||
uint countdown = (us) + 9; \
|
||||
while ((exp) && (countdown >= 10)) {\
|
||||
OSL_DELAY(10); \
|
||||
countdown -= 10; \
|
||||
} \
|
||||
}
|
||||
|
||||
|
||||
/* osl multi-precedence packet queue */
|
||||
#ifndef PKTQ_LEN_DEFAULT
|
||||
#define PKTQ_LEN_DEFAULT 128 /* Max 128 packets */
|
||||
#endif
|
||||
#ifndef PKTQ_MAX_PREC
|
||||
#define PKTQ_MAX_PREC 16 /* Maximum precedence levels */
|
||||
#endif
|
||||
|
||||
typedef struct pktq_prec {
|
||||
void *head; /* first packet to dequeue */
|
||||
void *tail; /* last packet to dequeue */
|
||||
uint16 len; /* number of queued packets */
|
||||
uint16 max; /* maximum number of queued packets */
|
||||
} pktq_prec_t;
|
||||
|
||||
|
||||
/* multi-priority pkt queue */
|
||||
struct pktq {
|
||||
uint16 num_prec; /* number of precedences in use */
|
||||
uint16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */
|
||||
uint16 max; /* total max packets */
|
||||
uint16 len; /* total number of packets */
|
||||
/* q array must be last since # of elements can be either PKTQ_MAX_PREC or 1 */
|
||||
struct pktq_prec q[PKTQ_MAX_PREC];
|
||||
};
|
||||
|
||||
/* simple, non-priority pkt queue */
|
||||
struct spktq {
|
||||
uint16 num_prec; /* number of precedences in use (always 1) */
|
||||
uint16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */
|
||||
uint16 max; /* total max packets */
|
||||
uint16 len; /* total number of packets */
|
||||
/* q array must be last since # of elements can be either PKTQ_MAX_PREC or 1 */
|
||||
struct pktq_prec q[1];
|
||||
};
|
||||
|
||||
#define PKTQ_PREC_ITER(pq, prec) for (prec = (pq)->num_prec - 1; prec >= 0; prec--)
|
||||
|
||||
/* forward definition of ether_addr structure used by some function prototypes */
|
||||
|
||||
struct ether_addr;
|
||||
|
||||
/* operations on a specific precedence in packet queue */
|
||||
|
||||
#define pktq_psetmax(pq, prec, _max) ((pq)->q[prec].max = (_max))
|
||||
#define pktq_plen(pq, prec) ((pq)->q[prec].len)
|
||||
#define pktq_pavail(pq, prec) ((pq)->q[prec].max - (pq)->q[prec].len)
|
||||
#define pktq_pfull(pq, prec) ((pq)->q[prec].len >= (pq)->q[prec].max)
|
||||
#define pktq_pempty(pq, prec) ((pq)->q[prec].len == 0)
|
||||
|
||||
#define pktq_ppeek(pq, prec) ((pq)->q[prec].head)
|
||||
#define pktq_ppeek_tail(pq, prec) ((pq)->q[prec].tail)
|
||||
|
||||
extern void *pktq_penq(struct pktq *pq, int prec, void *p);
|
||||
extern void *pktq_penq_head(struct pktq *pq, int prec, void *p);
|
||||
extern void *pktq_pdeq(struct pktq *pq, int prec);
|
||||
extern void *pktq_pdeq_tail(struct pktq *pq, int prec);
|
||||
/* Empty the queue at particular precedence level */
|
||||
extern void pktq_pflush(osl_t *osh, struct pktq *pq, int prec, bool dir);
|
||||
/* Remove a specified packet from its queue */
|
||||
extern bool pktq_pdel(struct pktq *pq, void *p, int prec);
|
||||
|
||||
/* operations on a set of precedences in packet queue */
|
||||
|
||||
extern int pktq_mlen(struct pktq *pq, uint prec_bmp);
|
||||
extern void *pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out);
|
||||
|
||||
/* operations on packet queue as a whole */
|
||||
|
||||
#define pktq_len(pq) ((int)(pq)->len)
|
||||
#define pktq_max(pq) ((int)(pq)->max)
|
||||
#define pktq_avail(pq) ((int)((pq)->max - (pq)->len))
|
||||
#define pktq_full(pq) ((pq)->len >= (pq)->max)
|
||||
#define pktq_empty(pq) ((pq)->len == 0)
|
||||
|
||||
/* operations for single precedence queues */
|
||||
#define pktenq(pq, p) pktq_penq(((struct pktq *)pq), 0, (p))
|
||||
#define pktenq_head(pq, p) pktq_penq_head(((struct pktq *)pq), 0, (p))
|
||||
#define pktdeq(pq) pktq_pdeq(((struct pktq *)pq), 0)
|
||||
#define pktdeq_tail(pq) pktq_pdeq_tail(((struct pktq *)pq), 0)
|
||||
#define pktqinit(pq, len) pktq_init(((struct pktq *)pq), 1, len)
|
||||
|
||||
extern void pktq_init(struct pktq *pq, int num_prec, int max_len);
|
||||
/* prec_out may be NULL if caller is not interested in return value */
|
||||
extern void *pktq_deq(struct pktq *pq, int *prec_out);
|
||||
extern void *pktq_deq_tail(struct pktq *pq, int *prec_out);
|
||||
extern void *pktq_peek(struct pktq *pq, int *prec_out);
|
||||
extern void *pktq_peek_tail(struct pktq *pq, int *prec_out);
|
||||
extern void pktq_flush(osl_t *osh, struct pktq *pq, bool dir); /* Empty the entire queue */
|
||||
extern int pktq_setmax(struct pktq *pq, int max_len);
|
||||
|
||||
/* externs */
|
||||
/* packet */
|
||||
extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
|
||||
extern uint pkttotlen(osl_t *osh, void *p);
|
||||
extern void *pktlast(osl_t *osh, void *p);
|
||||
|
||||
/* Get priority from a packet and pass it back in scb (or equiv) */
|
||||
extern uint pktsetprio(void *pkt, bool update_vtag);
|
||||
#define PKTPRIO_VDSCP 0x100 /* DSCP prio found after VLAN tag */
|
||||
#define PKTPRIO_VLAN 0x200 /* VLAN prio found */
|
||||
#define PKTPRIO_UPD 0x400 /* DSCP used to update VLAN prio */
|
||||
#define PKTPRIO_DSCP 0x800 /* DSCP prio found */
|
||||
|
||||
/* string */
|
||||
extern int BCMROMFN(bcm_atoi)(char *s);
|
||||
extern ulong BCMROMFN(bcm_strtoul)(char *cp, char **endp, uint base);
|
||||
extern char *BCMROMFN(bcmstrstr)(char *haystack, char *needle);
|
||||
extern char *BCMROMFN(bcmstrcat)(char *dest, const char *src);
|
||||
extern char *BCMROMFN(bcmstrncat)(char *dest, const char *src, uint size);
|
||||
extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
|
||||
/* ethernet address */
|
||||
extern char *bcm_ether_ntoa(struct ether_addr *ea, char *buf);
|
||||
extern int BCMROMFN(bcm_ether_atoe)(char *p, struct ether_addr *ea);
|
||||
|
||||
/* ip address */
|
||||
struct ipv4_addr;
|
||||
extern char *bcm_ip_ntoa(struct ipv4_addr *ia, char *buf);
|
||||
|
||||
/* delay */
|
||||
extern void bcm_mdelay(uint ms);
|
||||
/* variable access */
|
||||
extern char *getvar(char *vars, const char *name);
|
||||
extern int getintvar(char *vars, const char *name);
|
||||
extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
|
||||
#ifdef BCMPERFSTATS
|
||||
extern void bcm_perf_enable(void);
|
||||
extern void bcmstats(char *fmt);
|
||||
extern void bcmlog(char *fmt, uint a1, uint a2);
|
||||
extern void bcmdumplog(char *buf, int size);
|
||||
extern int bcmdumplogent(char *buf, uint idx);
|
||||
#else
|
||||
#define bcm_perf_enable()
|
||||
#define bcmstats(fmt)
|
||||
#define bcmlog(fmt, a1, a2)
|
||||
#define bcmdumplog(buf, size) *buf = '\0'
|
||||
#define bcmdumplogent(buf, idx) -1
|
||||
#endif /* BCMPERFSTATS */
|
||||
extern char *bcm_nvram_vars(uint *length);
|
||||
extern int bcm_nvram_cache(void *sbh);
|
||||
|
||||
/* Support for sharing code across in-driver iovar implementations.
|
||||
* The intent is that a driver use this structure to map iovar names
|
||||
* to its (private) iovar identifiers, and the lookup function to
|
||||
* find the entry. Macros are provided to map ids and get/set actions
|
||||
* into a single number space for a switch statement.
|
||||
*/
|
||||
|
||||
/* iovar structure */
|
||||
typedef struct bcm_iovar {
|
||||
const char *name; /* name for lookup and display */
|
||||
uint16 varid; /* id for switch */
|
||||
uint16 flags; /* driver-specific flag bits */
|
||||
uint16 type; /* base type of argument */
|
||||
uint16 minlen; /* min length for buffer vars */
|
||||
} bcm_iovar_t;
|
||||
|
||||
/* varid definitions are per-driver, may use these get/set bits */
|
||||
|
||||
/* IOVar action bits for id mapping */
|
||||
#define IOV_GET 0 /* Get an iovar */
|
||||
#define IOV_SET 1 /* Set an iovar */
|
||||
|
||||
/* Varid to actionid mapping */
|
||||
#define IOV_GVAL(id) ((id)*2)
|
||||
#define IOV_SVAL(id) (((id)*2)+IOV_SET)
|
||||
#define IOV_ISSET(actionid) ((actionid & IOV_SET) == IOV_SET)
|
||||
|
||||
/* flags are per-driver based on driver attributes */
|
||||
|
||||
extern const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name);
|
||||
extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool set);
|
||||
|
||||
#endif /* BCMDRIVER */
|
||||
|
||||
/* Base type definitions */
|
||||
#define IOVT_VOID 0 /* no value (implictly set only) */
|
||||
#define IOVT_BOOL 1 /* any value ok (zero/nonzero) */
|
||||
#define IOVT_INT8 2 /* integer values are range-checked */
|
||||
#define IOVT_UINT8 3 /* unsigned int 8 bits */
|
||||
#define IOVT_INT16 4 /* int 16 bits */
|
||||
#define IOVT_UINT16 5 /* unsigned int 16 bits */
|
||||
#define IOVT_INT32 6 /* int 32 bits */
|
||||
#define IOVT_UINT32 7 /* unsigned int 32 bits */
|
||||
#define IOVT_BUFFER 8 /* buffer is size-checked as per minlen */
|
||||
#define BCM_IOVT_VALID(type) (((unsigned int)(type)) <= IOVT_BUFFER)
|
||||
|
||||
/* Initializer for IOV type strings */
|
||||
#define BCM_IOV_TYPE_INIT { \
|
||||
"void", \
|
||||
"bool", \
|
||||
"int8", \
|
||||
"uint8", \
|
||||
"int16", \
|
||||
"uint16", \
|
||||
"int32", \
|
||||
"uint32", \
|
||||
"buffer", \
|
||||
"" }
|
||||
|
||||
#define BCM_IOVT_IS_INT(type) (\
|
||||
(type == IOVT_BOOL) || \
|
||||
(type == IOVT_INT8) || \
|
||||
(type == IOVT_UINT8) || \
|
||||
(type == IOVT_INT16) || \
|
||||
(type == IOVT_UINT16) || \
|
||||
(type == IOVT_INT32) || \
|
||||
(type == IOVT_UINT32))
|
||||
|
||||
/* ** driver/apps-shared section ** */
|
||||
|
||||
#define BCME_STRLEN 64 /* Max string length for BCM errors */
|
||||
#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
|
||||
|
||||
|
||||
/*
|
||||
* error codes could be added but the defined ones shouldn't be changed/deleted
|
||||
* these error codes are exposed to the user code
|
||||
* when ever a new error code is added to this list
|
||||
* please update errorstring table with the related error string and
|
||||
* update osl files with os specific errorcode map
|
||||
*/
|
||||
|
||||
#define BCME_OK 0 /* Success */
|
||||
#define BCME_ERROR -1 /* Error generic */
|
||||
#define BCME_BADARG -2 /* Bad Argument */
|
||||
#define BCME_BADOPTION -3 /* Bad option */
|
||||
#define BCME_NOTUP -4 /* Not up */
|
||||
#define BCME_NOTDOWN -5 /* Not down */
|
||||
#define BCME_NOTAP -6 /* Not AP */
|
||||
#define BCME_NOTSTA -7 /* Not STA */
|
||||
#define BCME_BADKEYIDX -8 /* BAD Key Index */
|
||||
#define BCME_RADIOOFF -9 /* Radio Off */
|
||||
#define BCME_NOTBANDLOCKED -10 /* Not band locked */
|
||||
#define BCME_NOCLK -11 /* No Clock */
|
||||
#define BCME_BADRATESET -12 /* BAD Rate valueset */
|
||||
#define BCME_BADBAND -13 /* BAD Band */
|
||||
#define BCME_BUFTOOSHORT -14 /* Buffer too short */
|
||||
#define BCME_BUFTOOLONG -15 /* Buffer too long */
|
||||
#define BCME_BUSY -16 /* Busy */
|
||||
#define BCME_NOTASSOCIATED -17 /* Not Associated */
|
||||
#define BCME_BADSSIDLEN -18 /* Bad SSID len */
|
||||
#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel */
|
||||
#define BCME_BADCHAN -20 /* Bad Channel */
|
||||
#define BCME_BADADDR -21 /* Bad Address */
|
||||
#define BCME_NORESOURCE -22 /* Not Enough Resources */
|
||||
#define BCME_UNSUPPORTED -23 /* Unsupported */
|
||||
#define BCME_BADLEN -24 /* Bad length */
|
||||
#define BCME_NOTREADY -25 /* Not Ready */
|
||||
#define BCME_EPERM -26 /* Not Permitted */
|
||||
#define BCME_NOMEM -27 /* No Memory */
|
||||
#define BCME_ASSOCIATED -28 /* Associated */
|
||||
#define BCME_RANGE -29 /* Not In Range */
|
||||
#define BCME_NOTFOUND -30 /* Not Found */
|
||||
#define BCME_WME_NOT_ENABLED -31 /* WME Not Enabled */
|
||||
#define BCME_TSPEC_NOTFOUND -32 /* TSPEC Not Found */
|
||||
#define BCME_ACM_NOTSUPPORTED -33 /* ACM Not Supported */
|
||||
#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */
|
||||
#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */
|
||||
#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */
|
||||
#define BCME_VERSION -37 /* Incorrect version */
|
||||
#define BCME_LAST BCME_VERSION
|
||||
|
||||
/* These are collection of BCME Error strings */
|
||||
#define BCMERRSTRINGTABLE { \
|
||||
"OK", \
|
||||
"Undefined error", \
|
||||
"Bad Argument", \
|
||||
"Bad Option", \
|
||||
"Not up", \
|
||||
"Not down", \
|
||||
"Not AP", \
|
||||
"Not STA", \
|
||||
"Bad Key Index", \
|
||||
"Radio Off", \
|
||||
"Not band locked", \
|
||||
"No clock", \
|
||||
"Bad Rate valueset", \
|
||||
"Bad Band", \
|
||||
"Buffer too short", \
|
||||
"Buffer too long", \
|
||||
"Busy", \
|
||||
"Not Associated", \
|
||||
"Bad SSID len", \
|
||||
"Out of Range Channel", \
|
||||
"Bad Channel", \
|
||||
"Bad Address", \
|
||||
"Not Enough Resources", \
|
||||
"Unsupported", \
|
||||
"Bad length", \
|
||||
"Not Ready", \
|
||||
"Not Permitted", \
|
||||
"No Memory", \
|
||||
"Associated", \
|
||||
"Not In Range", \
|
||||
"Not Found", \
|
||||
"WME Not Enabled", \
|
||||
"TSPEC Not Found", \
|
||||
"ACM Not Supported", \
|
||||
"Not WME Association", \
|
||||
"SDIO Bus Error", \
|
||||
"Dongle Not Accessible", \
|
||||
"Incorrect version" \
|
||||
}
|
||||
|
||||
#ifndef ABS
|
||||
#define ABS(a) (((a) < 0)?-(a):(a))
|
||||
#endif /* ABS */
|
||||
|
||||
#ifndef MIN
|
||||
#define MIN(a, b) (((a) < (b))?(a):(b))
|
||||
#endif /* MIN */
|
||||
|
||||
#ifndef MAX
|
||||
#define MAX(a, b) (((a) > (b))?(a):(b))
|
||||
#endif /* MAX */
|
||||
|
||||
#define CEIL(x, y) (((x) + ((y)-1)) / (y))
|
||||
#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
|
||||
#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
|
||||
#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0)
|
||||
#define VALID_MASK(mask) !((mask) & ((mask) + 1))
|
||||
#ifndef OFFSETOF
|
||||
#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
|
||||
#endif /* OFFSETOF */
|
||||
#ifndef ARRAYSIZE
|
||||
#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
|
||||
#endif
|
||||
|
||||
/* bit map related macros */
|
||||
#ifndef setbit
|
||||
#ifndef NBBY /* the BSD family defines NBBY */
|
||||
#define NBBY 8 /* 8 bits per byte */
|
||||
#endif /* #ifndef NBBY */
|
||||
#define setbit(a, i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
|
||||
#define clrbit(a, i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
|
||||
#define isset(a, i) (((const uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
|
||||
#define isclr(a, i) ((((const uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
|
||||
#endif /* setbit */
|
||||
|
||||
#define NBITS(type) (sizeof(type) * 8)
|
||||
#define NBITVAL(nbits) (1 << (nbits))
|
||||
#define MAXBITVAL(nbits) ((1 << (nbits)) - 1)
|
||||
#define NBITMASK(nbits) MAXBITVAL(nbits)
|
||||
#define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8)
|
||||
|
||||
/* basic mux operation - can be optimized on several architectures */
|
||||
#define MUX(pred, true, false) ((pred) ? (true) : (false))
|
||||
|
||||
/* modulo inc/dec - assumes x E [0, bound - 1] */
|
||||
#define MODDEC(x, bound) MUX((x) == 0, (bound) - 1, (x) - 1)
|
||||
#define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
|
||||
|
||||
/* modulo inc/dec, bound = 2^k */
|
||||
#define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
|
||||
#define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
|
||||
|
||||
/* modulo add/sub - assumes x, y E [0, bound - 1] */
|
||||
#define MODADD(x, y, bound) \
|
||||
MUX((x) + (y) >= (bound), (x) + (y) - (bound), (x) + (y))
|
||||
#define MODSUB(x, y, bound) \
|
||||
MUX(((int)(x)) - ((int)(y)) < 0, (x) - (y) + (bound), (x) - (y))
|
||||
|
||||
/* module add/sub, bound = 2^k */
|
||||
#define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
|
||||
#define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
|
||||
|
||||
/* crc defines */
|
||||
#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
|
||||
#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
|
||||
#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
|
||||
#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
|
||||
#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
|
||||
#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
|
||||
|
||||
/* bcm_format_flags() bit description structure */
|
||||
typedef struct bcm_bit_desc {
|
||||
uint32 bit;
|
||||
const char* name;
|
||||
} bcm_bit_desc_t;
|
||||
|
||||
/* tag_ID/length/value_buffer tuple */
|
||||
typedef struct bcm_tlv {
|
||||
uint8 id;
|
||||
uint8 len;
|
||||
uint8 data[1];
|
||||
} bcm_tlv_t;
|
||||
|
||||
/* Check that bcm_tlv_t fits into the given buflen */
|
||||
#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
|
||||
|
||||
/* buffer length for ethernet address from bcm_ether_ntoa() */
|
||||
#define ETHER_ADDR_STR_LEN 18 /* 18-bytes of Ethernet address buffer length */
|
||||
|
||||
/* unaligned load and store macros */
|
||||
#ifdef IL_BIGENDIAN
|
||||
static INLINE uint32
|
||||
load32_ua(uint8 *a)
|
||||
{
|
||||
return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
|
||||
}
|
||||
|
||||
static INLINE void
|
||||
store32_ua(uint8 *a, uint32 v)
|
||||
{
|
||||
a[0] = (v >> 24) & 0xff;
|
||||
a[1] = (v >> 16) & 0xff;
|
||||
a[2] = (v >> 8) & 0xff;
|
||||
a[3] = v & 0xff;
|
||||
}
|
||||
|
||||
static INLINE uint16
|
||||
load16_ua(uint8 *a)
|
||||
{
|
||||
return ((a[0] << 8) | a[1]);
|
||||
}
|
||||
|
||||
static INLINE void
|
||||
store16_ua(uint8 *a, uint16 v)
|
||||
{
|
||||
a[0] = (v >> 8) & 0xff;
|
||||
a[1] = v & 0xff;
|
||||
}
|
||||
|
||||
#else /* IL_BIGENDIAN */
|
||||
|
||||
static INLINE uint32
|
||||
load32_ua(uint8 *a)
|
||||
{
|
||||
return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
|
||||
}
|
||||
|
||||
static INLINE void
|
||||
store32_ua(uint8 *a, uint32 v)
|
||||
{
|
||||
a[3] = (v >> 24) & 0xff;
|
||||
a[2] = (v >> 16) & 0xff;
|
||||
a[1] = (v >> 8) & 0xff;
|
||||
a[0] = v & 0xff;
|
||||
}
|
||||
|
||||
static INLINE uint16
|
||||
load16_ua(uint8 *a)
|
||||
{
|
||||
return ((a[1] << 8) | a[0]);
|
||||
}
|
||||
|
||||
static INLINE void
|
||||
store16_ua(uint8 *a, uint16 v)
|
||||
{
|
||||
a[1] = (v >> 8) & 0xff;
|
||||
a[0] = v & 0xff;
|
||||
}
|
||||
|
||||
#endif /* IL_BIGENDIAN */
|
||||
|
||||
/* externs */
|
||||
/* crc */
|
||||
extern uint8 BCMROMFN(hndcrc8)(uint8 *p, uint nbytes, uint8 crc);
|
||||
extern uint16 BCMROMFN(hndcrc16)(uint8 *p, uint nbytes, uint16 crc);
|
||||
extern uint32 BCMROMFN(hndcrc32)(uint8 *p, uint nbytes, uint32 crc);
|
||||
/* format/print */
|
||||
extern char *bcm_brev_str(uint16 brev, char *buf);
|
||||
extern void printfbig(char *buf);
|
||||
|
||||
/* IE parsing */
|
||||
extern bcm_tlv_t *BCMROMFN(bcm_next_tlv)(bcm_tlv_t *elt, int *buflen);
|
||||
extern bcm_tlv_t *BCMROMFN(bcm_parse_tlvs)(void *buf, int buflen, uint key);
|
||||
extern bcm_tlv_t *BCMROMFN(bcm_parse_ordered_tlvs)(void *buf, int buflen, uint key);
|
||||
|
||||
/* bcmerror */
|
||||
extern const char *bcmerrorstr(int bcmerror);
|
||||
|
||||
/* multi-bool data type: set of bools, mbool is true if any is set */
|
||||
typedef uint32 mbool;
|
||||
#define mboolset(mb, bit) ((mb) |= (bit)) /* set one bool */
|
||||
#define mboolclr(mb, bit) ((mb) &= ~(bit)) /* clear one bool */
|
||||
#define mboolisset(mb, bit) (((mb) & (bit)) != 0) /* TRUE if one bool is set */
|
||||
#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
|
||||
|
||||
/* power conversion */
|
||||
extern uint16 BCMROMFN(bcm_qdbm_to_mw)(uint8 qdbm);
|
||||
extern uint8 BCMROMFN(bcm_mw_to_qdbm)(uint16 mw);
|
||||
|
||||
/* generic datastruct to help dump routines */
|
||||
struct fielddesc {
|
||||
const char *nameandfmt;
|
||||
uint32 offset;
|
||||
uint32 len;
|
||||
};
|
||||
|
||||
extern void bcm_binit(struct bcmstrbuf *b, char *buf, uint size);
|
||||
extern int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...);
|
||||
|
||||
typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
|
||||
extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str,
|
||||
char *buf, uint32 bufsize);
|
||||
|
||||
extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
|
||||
extern uint BCMROMFN(bcm_bitcount)(uint8 *bitmap, uint bytelength);
|
||||
|
||||
#ifdef BCMDBG_PKT /* pkt logging for debugging */
|
||||
#define PKTLIST_SIZE 1000
|
||||
typedef struct {
|
||||
void *list[PKTLIST_SIZE]; /* List of pointers to packets */
|
||||
uint count; /* Total count of the packets */
|
||||
} pktlist_info_t;
|
||||
|
||||
extern void pktlist_add(pktlist_info_t *pktlist, void *p);
|
||||
extern void pktlist_remove(pktlist_info_t *pktlist, void *p);
|
||||
extern char* pktlist_dump(pktlist_info_t *pktlist, char *buf);
|
||||
#endif /* BCMDBG_PKT */
|
||||
|
||||
#endif /* _bcmutils_h_ */
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
/*
|
||||
* HND SiliconBackplane chipcommon support.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _hndchipc_h_
|
||||
#define _hndchipc_h_
|
||||
|
||||
typedef void (*sb_serial_init_fn)(void *regs, uint irq, uint baud_base, uint reg_shift);
|
||||
|
||||
extern void sb_serial_init(sb_t *sbh, sb_serial_init_fn add);
|
||||
|
||||
extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap);
|
||||
extern void sb_jtagm_disable(osl_t *osh, void *h);
|
||||
extern uint32 jtag_rwreg(osl_t *osh, void *h, uint32 ir, uint32 dr);
|
||||
|
||||
typedef void (*cc_isr_fn)(void* cbdata, uint32 ccintst);
|
||||
|
||||
extern bool sb_cc_register_isr(sb_t *sbh, cc_isr_fn isr, uint32 ccintmask, void *cbdata);
|
||||
extern void sb_cc_isr(sb_t *sbh, chipcregs_t *regs);
|
||||
|
||||
#endif /* _hndchipc_h_ */
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
/*
|
||||
* HND SiliconBackplane MIPS/ARM cores software interface.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _hndcpu_h_
|
||||
#define _hndcpu_h_
|
||||
|
||||
#if defined(mips)
|
||||
#include <hndmips.h>
|
||||
#elif defined(__arm__) || defined(__thumb__) || defined(__thumb2__)
|
||||
#include <hndarm.h>
|
||||
#endif
|
||||
|
||||
extern uint sb_irq(sb_t *sbh);
|
||||
extern uint32 sb_cpu_clock(sb_t *sbh);
|
||||
extern void hnd_cpu_wait(sb_t *sbh);
|
||||
extern void hnd_cpu_jumpto(void *addr);
|
||||
extern void hnd_cpu_reset(sb_t *sbh);
|
||||
|
||||
#endif /* _hndcpu_h_ */
|
||||
|
|
@ -1,45 +0,0 @@
|
|||
/*
|
||||
* HND SiliconBackplane MIPS core software interface.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _hndmips_h_
|
||||
#define _hndmips_h_
|
||||
|
||||
extern void sb_mips_init(sb_t *sbh, uint shirq_map_base);
|
||||
extern bool sb_mips_setclock(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
|
||||
extern void enable_pfc(uint32 mode);
|
||||
extern uint32 sb_memc_get_ncdl(sb_t *sbh);
|
||||
|
||||
#if defined(BCMPERFSTATS)
|
||||
/* enable counting - exclusive version. Only one set of counters allowed at a time */
|
||||
extern void hndmips_perf_cyclecount_enable(void);
|
||||
extern void hndmips_perf_instrcount_enable(void);
|
||||
extern void hndmips_perf_icachecount_enable(void);
|
||||
extern void hndmips_perf_dcachecount_enable(void);
|
||||
/* start and stop counting */
|
||||
#define hndmips_perf_start01() \
|
||||
MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) | 0x80008000)
|
||||
#define hndmips_perf_stop01() \
|
||||
MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) & ~0x80008000)
|
||||
/* retrieve coutners - counters *decrement* */
|
||||
#define hndmips_perf_read0() -(long)(MFC0(C0_PERFORMANCE, 0))
|
||||
#define hndmips_perf_read1() -(long)(MFC0(C0_PERFORMANCE, 1))
|
||||
#define hndmips_perf_read2() -(long)(MFC0(C0_PERFORMANCE, 2))
|
||||
/* enable counting - modular version. Each counters can be enabled separately. */
|
||||
extern void hndmips_perf_icache_hit_enable(void);
|
||||
extern void hndmips_perf_icache_miss_enable(void);
|
||||
extern uint32 hndmips_perf_read_instrcount(void);
|
||||
extern uint32 hndmips_perf_read_cache_miss(void);
|
||||
extern uint32 hndmips_perf_read_cache_hit(void);
|
||||
#endif
|
||||
|
||||
#endif /* _hndmips_h_ */
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
/*
|
||||
* HND SiliconBackplane PCI core software interface.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _hndpci_h_
|
||||
#define _hndpci_h_
|
||||
|
||||
extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
|
||||
int len);
|
||||
extern int extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
|
||||
int len);
|
||||
extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
|
||||
int len);
|
||||
extern int extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
|
||||
int len);
|
||||
extern void sbpci_ban(uint16 core);
|
||||
extern int sbpci_init(sb_t *sbh);
|
||||
extern int sbpci_init_pci(sb_t *sbh);
|
||||
extern void sbpci_init_cores(sb_t *sbh);
|
||||
extern void sbpci_arb_park(sb_t *sbh, uint parkid);
|
||||
|
||||
#define PCI_PARK_NVRAM 0xff
|
||||
|
||||
#endif /* _hndpci_h_ */
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
/*
|
||||
* HND SiliconBackplane PMU support.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _hndpmu_h_
|
||||
#define _hndpmu_h_
|
||||
|
||||
#define SET_LDO_VOLTAGE_LDO1 1
|
||||
#define SET_LDO_VOLTAGE_LDO2 2
|
||||
#define SET_LDO_VOLTAGE_LDO3 3
|
||||
#define SET_LDO_VOLTAGE_PAREF 4
|
||||
|
||||
extern void sb_pmu_init(sb_t *sbh, osl_t *osh);
|
||||
extern void sb_pmu_pll_init(sb_t *sbh, osl_t *osh, uint32 xtalfreq);
|
||||
extern void sb_pmu_res_init(sb_t *sbh, osl_t *osh);
|
||||
extern uint32 sb_pmu_force_ilp(sb_t *sbh, osl_t *osh, bool force);
|
||||
extern uint32 sb_pmu_cpu_clock(sb_t *sbh, osl_t *osh);
|
||||
extern uint32 sb_pmu_alp_clock(sb_t *sbh, osl_t *osh);
|
||||
|
||||
extern void sb_pmu_set_switcher_voltage(sb_t *sbh, osl_t *osh, uint8 bb_voltage, uint8 rf_voltage);
|
||||
extern void sb_pmu_set_ldo_voltage(sb_t *sbh, osl_t *osh, uint8 ldo, uint8 voltage);
|
||||
extern void sb_pmu_paref_ldo_enable(sb_t *sbh, osl_t *osh, bool enable);
|
||||
extern uint16 sb_pmu_fast_pwrup_delay(sb_t *sbh, osl_t *osh);
|
||||
extern void sb_pmu_otp_power(sb_t *sbh, osl_t *osh, bool on);
|
||||
extern void sb_pmu_rcal(sb_t *sbh, osl_t *osh);
|
||||
|
||||
#endif /* _hndpmu_h_ */
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
/*
|
||||
* Linux Broadcom BCM47xx GPIO char driver
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _linux_gpio_h_
|
||||
#define _linux_gpio_h_
|
||||
|
||||
struct gpio_ioctl {
|
||||
uint32 mask;
|
||||
uint32 val;
|
||||
};
|
||||
|
||||
#define GPIO_IOC_MAGIC 'G'
|
||||
|
||||
/* reserve/release a gpio to the caller */
|
||||
#define GPIO_IOC_RESERVE _IOWR(GPIO_IOC_MAGIC, 1, struct gpio_ioctl)
|
||||
#define GPIO_IOC_RELEASE _IOWR(GPIO_IOC_MAGIC, 2, struct gpio_ioctl)
|
||||
/* ioctls to read/write the gpio registers */
|
||||
#define GPIO_IOC_OUT _IOWR(GPIO_IOC_MAGIC, 3, struct gpio_ioctl)
|
||||
#define GPIO_IOC_IN _IOWR(GPIO_IOC_MAGIC, 4, struct gpio_ioctl)
|
||||
#define GPIO_IOC_OUTEN _IOWR(GPIO_IOC_MAGIC, 5, struct gpio_ioctl)
|
||||
|
||||
#endif /* _linux_gpio_h_ */
|
||||
|
|
@ -1,432 +0,0 @@
|
|||
/*
|
||||
* Linux-specific abstractions to gain some independence from linux kernel versions.
|
||||
* Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _linuxver_h_
|
||||
#define _linuxver_h_
|
||||
|
||||
#include <linux/version.h>
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
|
||||
#include <linux/config.h>
|
||||
#else
|
||||
#include <linux/autoconf.h>
|
||||
#endif
|
||||
#include <linux/module.h>
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0))
|
||||
/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
|
||||
#ifdef __UNDEF_NO_VERSION__
|
||||
#undef __NO_VERSION__
|
||||
#else
|
||||
#define __NO_VERSION__
|
||||
#endif
|
||||
#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0) */
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)
|
||||
#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
|
||||
#define module_param_string(_name_, _string_, _size_, _perm_) \
|
||||
MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
|
||||
#endif
|
||||
|
||||
/* linux/malloc.h is deprecated, use linux/slab.h instead. */
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 9))
|
||||
#include <linux/malloc.h>
|
||||
#else
|
||||
#include <linux/slab.h>
|
||||
#endif
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
|
||||
#include <linux/workqueue.h>
|
||||
#else
|
||||
#include <linux/tqueue.h>
|
||||
#ifndef work_struct
|
||||
#define work_struct tq_struct
|
||||
#endif
|
||||
#ifndef INIT_WORK
|
||||
#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
|
||||
#endif
|
||||
#ifndef schedule_work
|
||||
#define schedule_work(_work) schedule_task((_work))
|
||||
#endif
|
||||
#ifndef flush_scheduled_work
|
||||
#define flush_scheduled_work() flush_scheduled_tasks()
|
||||
#endif
|
||||
#endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41) */
|
||||
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20)
|
||||
#define MY_INIT_WORK(_work, _func, _data) INIT_WORK(_work, _func)
|
||||
#else
|
||||
#define MY_INIT_WORK(_work, _func, _data) INIT_WORK(_work, _func, _data)
|
||||
typedef void (*work_func_t)(void *work);
|
||||
#endif /* < 2.6.20 */
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
|
||||
/* Some distributions have their own 2.6.x compatibility layers */
|
||||
#ifndef IRQ_NONE
|
||||
typedef void irqreturn_t;
|
||||
#define IRQ_NONE
|
||||
#define IRQ_HANDLED
|
||||
#define IRQ_RETVAL(x)
|
||||
#endif
|
||||
#else
|
||||
typedef irqreturn_t(*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
|
||||
#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0) */
|
||||
|
||||
#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
|
||||
|
||||
#include <pcmcia/version.h>
|
||||
#include <pcmcia/cs_types.h>
|
||||
#include <pcmcia/cs.h>
|
||||
#include <pcmcia/cistpl.h>
|
||||
#include <pcmcia/cisreg.h>
|
||||
#include <pcmcia/ds.h>
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 69))
|
||||
/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
|
||||
* does this, but it's not in 2.4 so we do our own for now.
|
||||
*/
|
||||
static inline void
|
||||
cs_error(client_handle_t handle, int func, int ret)
|
||||
{
|
||||
error_info_t err = { func, ret };
|
||||
CardServices(ReportError, handle, &err);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 15))
|
||||
|
||||
typedef struct pcmcia_device dev_link_t;
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_PCMCIA */
|
||||
|
||||
#ifndef __exit
|
||||
#define __exit
|
||||
#endif
|
||||
#ifndef __devexit
|
||||
#define __devexit
|
||||
#endif
|
||||
#ifndef __devinit
|
||||
#define __devinit __init
|
||||
#endif
|
||||
#ifndef __devinitdata
|
||||
#define __devinitdata
|
||||
#endif
|
||||
#ifndef __devexit_p
|
||||
#define __devexit_p(x) x
|
||||
#endif
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0))
|
||||
|
||||
#define pci_get_drvdata(dev) (dev)->sysdata
|
||||
#define pci_set_drvdata(dev, value) (dev)->sysdata = (value)
|
||||
|
||||
/*
|
||||
* New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
|
||||
*/
|
||||
|
||||
struct pci_device_id {
|
||||
unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
|
||||
unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
|
||||
unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
|
||||
unsigned long driver_data; /* Data private to the driver */
|
||||
};
|
||||
|
||||
struct pci_driver {
|
||||
struct list_head node;
|
||||
char *name;
|
||||
const struct pci_device_id *id_table; /* NULL if wants all devices */
|
||||
int (*probe)(struct pci_dev *dev,
|
||||
const struct pci_device_id *id); /* New device inserted */
|
||||
void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug
|
||||
* capable driver)
|
||||
*/
|
||||
void (*suspend)(struct pci_dev *dev); /* Device suspended */
|
||||
void (*resume)(struct pci_dev *dev); /* Device woken up */
|
||||
};
|
||||
|
||||
#define MODULE_DEVICE_TABLE(type, name)
|
||||
#define PCI_ANY_ID (~0)
|
||||
|
||||
/* compatpci.c */
|
||||
#define pci_module_init pci_register_driver
|
||||
extern int pci_register_driver(struct pci_driver *drv);
|
||||
extern void pci_unregister_driver(struct pci_driver *drv);
|
||||
|
||||
#endif /* PCI registration */
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18))
|
||||
#ifdef MODULE
|
||||
#define module_init(x) int init_module(void) { return x(); }
|
||||
#define module_exit(x) void cleanup_module(void) { x(); }
|
||||
#else
|
||||
#define module_init(x) __initcall(x);
|
||||
#define module_exit(x) __exitcall(x);
|
||||
#endif
|
||||
#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18) */
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 48))
|
||||
#define list_for_each(pos, head) \
|
||||
for (pos = (head)->next; pos != (head); pos = pos->next)
|
||||
#endif
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 13))
|
||||
#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
|
||||
#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 44))
|
||||
#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
|
||||
#endif
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 23))
|
||||
#define pci_enable_device(dev) do { } while (0)
|
||||
#endif
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 14))
|
||||
#define net_device device
|
||||
#endif
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 42))
|
||||
|
||||
/*
|
||||
* DMA mapping
|
||||
*
|
||||
* See linux/Documentation/DMA-mapping.txt
|
||||
*/
|
||||
|
||||
#ifndef PCI_DMA_TODEVICE
|
||||
#define PCI_DMA_TODEVICE 1
|
||||
#define PCI_DMA_FROMDEVICE 2
|
||||
#endif
|
||||
|
||||
typedef u32 dma_addr_t;
|
||||
|
||||
/* Pure 2^n version of get_order */
|
||||
static inline int get_order(unsigned long size)
|
||||
{
|
||||
int order;
|
||||
|
||||
size = (size-1) >> (PAGE_SHIFT-1);
|
||||
order = -1;
|
||||
do {
|
||||
size >>= 1;
|
||||
order++;
|
||||
} while (size);
|
||||
return order;
|
||||
}
|
||||
|
||||
static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
|
||||
dma_addr_t *dma_handle)
|
||||
{
|
||||
void *ret;
|
||||
int gfp = GFP_ATOMIC | GFP_DMA;
|
||||
|
||||
ret = (void *)__get_free_pages(gfp, get_order(size));
|
||||
|
||||
if (ret != NULL) {
|
||||
memset(ret, 0, size);
|
||||
*dma_handle = virt_to_bus(ret);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
|
||||
void *vaddr, dma_addr_t dma_handle)
|
||||
{
|
||||
free_pages((unsigned long)vaddr, get_order(size));
|
||||
}
|
||||
#ifdef ILSIM
|
||||
extern uint pci_map_single(void *dev, void *va, uint size, int direction);
|
||||
extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
|
||||
#else
|
||||
#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
|
||||
#define pci_unmap_single(cookie, address, size, dir)
|
||||
#endif
|
||||
|
||||
#endif /* DMA mapping */
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 43))
|
||||
|
||||
#define dev_kfree_skb_any(a) dev_kfree_skb(a)
|
||||
#define netif_down(dev) do { (dev)->start = 0; } while (0)
|
||||
|
||||
/* pcmcia-cs provides its own netdevice compatibility layer */
|
||||
#ifndef _COMPAT_NETDEVICE_H
|
||||
|
||||
/*
|
||||
* SoftNet
|
||||
*
|
||||
* For pre-softnet kernels we need to tell the upper layer not to
|
||||
* re-enter start_xmit() while we are in there. However softnet
|
||||
* guarantees not to enter while we are in there so there is no need
|
||||
* to do the netif_stop_queue() dance unless the transmit queue really
|
||||
* gets stuck. This should also improve performance according to tests
|
||||
* done by Aman Singla.
|
||||
*/
|
||||
|
||||
#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
|
||||
#define netif_wake_queue(dev) \
|
||||
do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while (0)
|
||||
#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
|
||||
|
||||
static inline void netif_start_queue(struct net_device *dev)
|
||||
{
|
||||
dev->tbusy = 0;
|
||||
dev->interrupt = 0;
|
||||
dev->start = 1;
|
||||
}
|
||||
|
||||
#define netif_queue_stopped(dev) (dev)->tbusy
|
||||
#define netif_running(dev) (dev)->start
|
||||
|
||||
#endif /* _COMPAT_NETDEVICE_H */
|
||||
|
||||
#define netif_device_attach(dev) netif_start_queue(dev)
|
||||
#define netif_device_detach(dev) netif_stop_queue(dev)
|
||||
|
||||
/* 2.4.x renamed bottom halves to tasklets */
|
||||
#define tasklet_struct tq_struct
|
||||
static inline void tasklet_schedule(struct tasklet_struct *tasklet)
|
||||
{
|
||||
queue_task(tasklet, &tq_immediate);
|
||||
mark_bh(IMMEDIATE_BH);
|
||||
}
|
||||
|
||||
static inline void tasklet_init(struct tasklet_struct *tasklet,
|
||||
void (*func)(unsigned long),
|
||||
unsigned long data)
|
||||
{
|
||||
tasklet->next = NULL;
|
||||
tasklet->sync = 0;
|
||||
tasklet->routine = (void (*)(void *))func;
|
||||
tasklet->data = (void *)data;
|
||||
}
|
||||
#define tasklet_kill(tasklet) { do{} while (0); }
|
||||
|
||||
/* 2.4.x introduced del_timer_sync() */
|
||||
#define del_timer_sync(timer) del_timer(timer)
|
||||
|
||||
#else
|
||||
|
||||
#define netif_down(dev)
|
||||
|
||||
#endif /* SoftNet */
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3))
|
||||
|
||||
/*
|
||||
* Emit code to initialise a tq_struct's routine and data pointers
|
||||
*/
|
||||
#define PREPARE_TQUEUE(_tq, _routine, _data) \
|
||||
do { \
|
||||
(_tq)->routine = _routine; \
|
||||
(_tq)->data = _data; \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* Emit code to initialise all of a tq_struct
|
||||
*/
|
||||
#define INIT_TQUEUE(_tq, _routine, _data) \
|
||||
do { \
|
||||
INIT_LIST_HEAD(&(_tq)->list); \
|
||||
(_tq)->sync = 0; \
|
||||
PREPARE_TQUEUE((_tq), (_routine), (_data)); \
|
||||
} while (0)
|
||||
|
||||
#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3) */
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 6))
|
||||
|
||||
/* Power management related routines */
|
||||
|
||||
static inline int
|
||||
pci_save_state(struct pci_dev *dev, u32 *buffer)
|
||||
{
|
||||
int i;
|
||||
if (buffer) {
|
||||
for (i = 0; i < 16; i++)
|
||||
pci_read_config_dword(dev, i * 4, &buffer[i]);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
pci_restore_state(struct pci_dev *dev, u32 *buffer)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (buffer) {
|
||||
for (i = 0; i < 16; i++)
|
||||
pci_write_config_dword(dev, i * 4, buffer[i]);
|
||||
}
|
||||
/*
|
||||
* otherwise, write the context information we know from bootup.
|
||||
* This works around a problem where warm-booting from Windows
|
||||
* combined with a D3(hot)->D0 transition causes PCI config
|
||||
* header data to be forgotten.
|
||||
*/
|
||||
else {
|
||||
for (i = 0; i < 6; i ++)
|
||||
pci_write_config_dword(dev,
|
||||
PCI_BASE_ADDRESS_0 + (i * 4),
|
||||
pci_resource_start(dev, i));
|
||||
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* PCI power management */
|
||||
|
||||
/* Old cp0 access macros deprecated in 2.4.19 */
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 19))
|
||||
#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
|
||||
#endif
|
||||
|
||||
/* Module refcount handled internally in 2.6.x */
|
||||
#ifndef SET_MODULE_OWNER
|
||||
#define SET_MODULE_OWNER(dev) do {} while (0)
|
||||
#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
|
||||
#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
|
||||
#else
|
||||
#define OLD_MOD_INC_USE_COUNT do {} while (0)
|
||||
#define OLD_MOD_DEC_USE_COUNT do {} while (0)
|
||||
#endif
|
||||
|
||||
#ifndef SET_NETDEV_DEV
|
||||
#define SET_NETDEV_DEV(net, pdev) do {} while (0)
|
||||
#endif
|
||||
|
||||
#ifndef HAVE_FREE_NETDEV
|
||||
#define free_netdev(dev) kfree(dev)
|
||||
#endif
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
|
||||
/* struct packet_type redefined in 2.6.x */
|
||||
#define af_packet_priv data
|
||||
#endif
|
||||
|
||||
/* suspend args */
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 11)
|
||||
#define DRV_SUSPEND_STATE_TYPE pm_message_t
|
||||
#else
|
||||
#define DRV_SUSPEND_STATE_TYPE uint32
|
||||
#endif
|
||||
|
||||
#endif /* _linuxver_h_ */
|
||||
|
|
@ -1,542 +0,0 @@
|
|||
/*
|
||||
* HND Run Time Environment for standalone MIPS programs.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _MISPINC_H
|
||||
#define _MISPINC_H
|
||||
|
||||
|
||||
/* MIPS defines */
|
||||
|
||||
#ifdef _LANGUAGE_ASSEMBLY
|
||||
|
||||
/*
|
||||
* Symbolic register names for 32 bit ABI
|
||||
*/
|
||||
#define zero $0 /* wired zero */
|
||||
#define AT $1 /* assembler temp - uppercase because of ".set at" */
|
||||
#define v0 $2 /* return value */
|
||||
#define v1 $3
|
||||
#define a0 $4 /* argument registers */
|
||||
#define a1 $5
|
||||
#define a2 $6
|
||||
#define a3 $7
|
||||
#define t0 $8 /* caller saved */
|
||||
#define t1 $9
|
||||
#define t2 $10
|
||||
#define t3 $11
|
||||
#define t4 $12
|
||||
#define t5 $13
|
||||
#define t6 $14
|
||||
#define t7 $15
|
||||
#define s0 $16 /* callee saved */
|
||||
#define s1 $17
|
||||
#define s2 $18
|
||||
#define s3 $19
|
||||
#define s4 $20
|
||||
#define s5 $21
|
||||
#define s6 $22
|
||||
#define s7 $23
|
||||
#define t8 $24 /* caller saved */
|
||||
#define t9 $25
|
||||
#define jp $25 /* PIC jump register */
|
||||
#define k0 $26 /* kernel scratch */
|
||||
#define k1 $27
|
||||
#define gp $28 /* global pointer */
|
||||
#define sp $29 /* stack pointer */
|
||||
#define fp $30 /* frame pointer */
|
||||
#define s8 $30 /* same like fp! */
|
||||
#define ra $31 /* return address */
|
||||
|
||||
|
||||
/* CP0 Registers */
|
||||
|
||||
#define C0_INX $0
|
||||
#define C0_RAND $1
|
||||
#define C0_TLBLO0 $2
|
||||
#define C0_TLBLO C0_TLBLO0
|
||||
#define C0_TLBLO1 $3
|
||||
#define C0_CTEXT $4
|
||||
#define C0_PGMASK $5
|
||||
#define C0_WIRED $6
|
||||
#define C0_INFO $7
|
||||
#define C0_BADVADDR $8
|
||||
#define C0_COUNT $9
|
||||
#define C0_TLBHI $10
|
||||
#define C0_COMPARE $11
|
||||
#define C0_SR $12
|
||||
#define C0_STATUS C0_SR
|
||||
#define C0_CAUSE $13
|
||||
#define C0_EPC $14
|
||||
#define C0_PRID $15
|
||||
#define C0_CONFIG $16
|
||||
#define C0_LLADDR $17
|
||||
#define C0_WATCHLO $18
|
||||
#define C0_WATCHHI $19
|
||||
#define C0_XCTEXT $20
|
||||
#define C0_DIAGNOSTIC $22
|
||||
#define C0_BROADCOM C0_DIAGNOSTIC
|
||||
#define C0_PERFORMANCE $25
|
||||
#define C0_ECC $26
|
||||
#define C0_CACHEERR $27
|
||||
#define C0_TAGLO $28
|
||||
#define C0_TAGHI $29
|
||||
#define C0_ERREPC $30
|
||||
#define C0_DESAVE $31
|
||||
|
||||
/*
|
||||
* LEAF - declare leaf routine
|
||||
*/
|
||||
#define LEAF(symbol) \
|
||||
.globl symbol; \
|
||||
.align 2; \
|
||||
.type symbol, @function; \
|
||||
.ent symbol, 0; \
|
||||
symbol: .frame sp, 0, ra
|
||||
|
||||
/*
|
||||
* END - mark end of function
|
||||
*/
|
||||
#define END(function) \
|
||||
.end function; \
|
||||
.size function, . - function
|
||||
|
||||
#define _ULCAST_
|
||||
|
||||
#define MFC0_SEL(dst, src, sel) \
|
||||
.word\t(0x40000000 | ((dst) << 16) | ((src) << 11) | (sel))
|
||||
|
||||
|
||||
#define MTC0_SEL(dst, src, sel) \
|
||||
.word\t(0x40800000 | ((dst) << 16) | ((src) << 11) | (sel))
|
||||
|
||||
#else
|
||||
|
||||
/*
|
||||
* The following macros are especially useful for __asm__
|
||||
* inline assembler.
|
||||
*/
|
||||
#ifndef __STR
|
||||
#define __STR(x) #x
|
||||
#endif
|
||||
#ifndef STR
|
||||
#define STR(x) __STR(x)
|
||||
#endif
|
||||
|
||||
#define _ULCAST_ (unsigned long)
|
||||
|
||||
|
||||
/* CP0 Registers */
|
||||
|
||||
#define C0_INX 0 /* CP0: TLB Index */
|
||||
#define C0_RAND 1 /* CP0: TLB Random */
|
||||
#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
|
||||
#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
|
||||
#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
|
||||
#define C0_CTEXT 4 /* CP0: Context */
|
||||
#define C0_PGMASK 5 /* CP0: TLB PageMask */
|
||||
#define C0_WIRED 6 /* CP0: TLB Wired */
|
||||
#define C0_INFO 7 /* CP0: Info */
|
||||
#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
|
||||
#define C0_COUNT 9 /* CP0: Count */
|
||||
#define C0_TLBHI 10 /* CP0: TLB EntryHi */
|
||||
#define C0_COMPARE 11 /* CP0: Compare */
|
||||
#define C0_SR 12 /* CP0: Processor Status */
|
||||
#define C0_STATUS C0_SR /* CP0: Processor Status */
|
||||
#define C0_CAUSE 13 /* CP0: Exception Cause */
|
||||
#define C0_EPC 14 /* CP0: Exception PC */
|
||||
#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
|
||||
#define C0_CONFIG 16 /* CP0: Config */
|
||||
#define C0_LLADDR 17 /* CP0: LLAddr */
|
||||
#define C0_WATCHLO 18 /* CP0: WatchpointLo */
|
||||
#define C0_WATCHHI 19 /* CP0: WatchpointHi */
|
||||
#define C0_XCTEXT 20 /* CP0: XContext */
|
||||
#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
|
||||
#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
|
||||
#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
|
||||
#define C0_ECC 26 /* CP0: ECC */
|
||||
#define C0_CACHEERR 27 /* CP0: CacheErr */
|
||||
#define C0_TAGLO 28 /* CP0: TagLo */
|
||||
#define C0_TAGHI 29 /* CP0: TagHi */
|
||||
#define C0_ERREPC 30 /* CP0: ErrorEPC */
|
||||
#define C0_DESAVE 31 /* CP0: DebugSave */
|
||||
|
||||
#endif /* _LANGUAGE_ASSEMBLY */
|
||||
|
||||
/*
|
||||
* Memory segments (32bit kernel mode addresses)
|
||||
*/
|
||||
#undef KUSEG
|
||||
#undef KSEG0
|
||||
#undef KSEG1
|
||||
#undef KSEG2
|
||||
#undef KSEG3
|
||||
#define KUSEG 0x00000000
|
||||
#define KSEG0 0x80000000
|
||||
#define KSEG1 0xa0000000
|
||||
#define KSEG2 0xc0000000
|
||||
#define KSEG3 0xe0000000
|
||||
#define PHYSADDR_MASK 0x1fffffff
|
||||
|
||||
/*
|
||||
* Map an address to a certain kernel segment
|
||||
*/
|
||||
#undef PHYSADDR
|
||||
#undef KSEG0ADDR
|
||||
#undef KSEG1ADDR
|
||||
#undef KSEG2ADDR
|
||||
#undef KSEG3ADDR
|
||||
|
||||
#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
|
||||
#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
|
||||
#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
|
||||
#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
|
||||
#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
|
||||
|
||||
|
||||
#ifndef Index_Invalidate_I
|
||||
/*
|
||||
* Cache Operations
|
||||
*/
|
||||
#define Index_Invalidate_I 0x00
|
||||
#define Index_Writeback_Inv_D 0x01
|
||||
#define Index_Invalidate_SI 0x02
|
||||
#define Index_Writeback_Inv_SD 0x03
|
||||
#define Index_Load_Tag_I 0x04
|
||||
#define Index_Load_Tag_D 0x05
|
||||
#define Index_Load_Tag_SI 0x06
|
||||
#define Index_Load_Tag_SD 0x07
|
||||
#define Index_Store_Tag_I 0x08
|
||||
#define Index_Store_Tag_D 0x09
|
||||
#define Index_Store_Tag_SI 0x0A
|
||||
#define Index_Store_Tag_SD 0x0B
|
||||
#define Create_Dirty_Excl_D 0x0d
|
||||
#define Create_Dirty_Excl_SD 0x0f
|
||||
#define Hit_Invalidate_I 0x10
|
||||
#define Hit_Invalidate_D 0x11
|
||||
#define Hit_Invalidate_SI 0x12
|
||||
#define Hit_Invalidate_SD 0x13
|
||||
#define Fill_I 0x14
|
||||
#define Hit_Writeback_Inv_D 0x15
|
||||
/* 0x16 is unused */
|
||||
#define Hit_Writeback_Inv_SD 0x17
|
||||
#define R5K_Page_Invalidate_S 0x17
|
||||
#define Hit_Writeback_I 0x18
|
||||
#define Hit_Writeback_D 0x19
|
||||
/* 0x1a is unused */
|
||||
#define Hit_Writeback_SD 0x1b
|
||||
/* 0x1c is unused */
|
||||
/* 0x1e is unused */
|
||||
#define Hit_Set_Virtual_SI 0x1e
|
||||
#define Hit_Set_Virtual_SD 0x1f
|
||||
#endif /* !Index_Invalidate_I */
|
||||
|
||||
|
||||
/*
|
||||
* R4x00 interrupt enable / cause bits
|
||||
*/
|
||||
#define IE_SW0 (_ULCAST_(1) << 8)
|
||||
#define IE_SW1 (_ULCAST_(1) << 9)
|
||||
#define IE_IRQ0 (_ULCAST_(1) << 10)
|
||||
#define IE_IRQ1 (_ULCAST_(1) << 11)
|
||||
#define IE_IRQ2 (_ULCAST_(1) << 12)
|
||||
#define IE_IRQ3 (_ULCAST_(1) << 13)
|
||||
#define IE_IRQ4 (_ULCAST_(1) << 14)
|
||||
#define IE_IRQ5 (_ULCAST_(1) << 15)
|
||||
|
||||
#ifndef ST0_UM
|
||||
/*
|
||||
* Bitfields in the mips32 cp0 status register
|
||||
*/
|
||||
#define ST0_IE 0x00000001
|
||||
#define ST0_EXL 0x00000002
|
||||
#define ST0_ERL 0x00000004
|
||||
#define ST0_UM 0x00000010
|
||||
#define ST0_SWINT0 0x00000100
|
||||
#define ST0_SWINT1 0x00000200
|
||||
#define ST0_HWINT0 0x00000400
|
||||
#define ST0_HWINT1 0x00000800
|
||||
#define ST0_HWINT2 0x00001000
|
||||
#define ST0_HWINT3 0x00002000
|
||||
#define ST0_HWINT4 0x00004000
|
||||
#define ST0_HWINT5 0x00008000
|
||||
#define ST0_IM 0x0000ff00
|
||||
#define ST0_NMI 0x00080000
|
||||
#define ST0_SR 0x00100000
|
||||
#define ST0_TS 0x00200000
|
||||
#define ST0_BEV 0x00400000
|
||||
#define ST0_RE 0x02000000
|
||||
#define ST0_RP 0x08000000
|
||||
#define ST0_CU 0xf0000000
|
||||
#define ST0_CU0 0x10000000
|
||||
#define ST0_CU1 0x20000000
|
||||
#define ST0_CU2 0x40000000
|
||||
#define ST0_CU3 0x80000000
|
||||
#endif /* !ST0_UM */
|
||||
|
||||
|
||||
/*
|
||||
* Bitfields in the mips32 cp0 cause register
|
||||
*/
|
||||
#define C_EXC 0x0000007c
|
||||
#define C_EXC_SHIFT 2
|
||||
#define C_INT 0x0000ff00
|
||||
#define C_INT_SHIFT 8
|
||||
#define C_SW0 (_ULCAST_(1) << 8)
|
||||
#define C_SW1 (_ULCAST_(1) << 9)
|
||||
#define C_IRQ0 (_ULCAST_(1) << 10)
|
||||
#define C_IRQ1 (_ULCAST_(1) << 11)
|
||||
#define C_IRQ2 (_ULCAST_(1) << 12)
|
||||
#define C_IRQ3 (_ULCAST_(1) << 13)
|
||||
#define C_IRQ4 (_ULCAST_(1) << 14)
|
||||
#define C_IRQ5 (_ULCAST_(1) << 15)
|
||||
#define C_WP 0x00400000
|
||||
#define C_IV 0x00800000
|
||||
#define C_CE 0x30000000
|
||||
#define C_CE_SHIFT 28
|
||||
#define C_BD 0x80000000
|
||||
|
||||
/* Values in C_EXC */
|
||||
#define EXC_INT 0
|
||||
#define EXC_TLBM 1
|
||||
#define EXC_TLBL 2
|
||||
#define EXC_TLBS 3
|
||||
#define EXC_AEL 4
|
||||
#define EXC_AES 5
|
||||
#define EXC_IBE 6
|
||||
#define EXC_DBE 7
|
||||
#define EXC_SYS 8
|
||||
#define EXC_BPT 9
|
||||
#define EXC_RI 10
|
||||
#define EXC_CU 11
|
||||
#define EXC_OV 12
|
||||
#define EXC_TR 13
|
||||
#define EXC_WATCH 23
|
||||
#define EXC_MCHK 24
|
||||
|
||||
|
||||
/*
|
||||
* Bits in the cp0 config register.
|
||||
*/
|
||||
#define CONF_CM_CACHABLE_NO_WA 0
|
||||
#define CONF_CM_CACHABLE_WA 1
|
||||
#define CONF_CM_UNCACHED 2
|
||||
#define CONF_CM_CACHABLE_NONCOHERENT 3
|
||||
#define CONF_CM_CACHABLE_CE 4
|
||||
#define CONF_CM_CACHABLE_COW 5
|
||||
#define CONF_CM_CACHABLE_CUW 6
|
||||
#define CONF_CM_CACHABLE_ACCELERATED 7
|
||||
#define CONF_CM_CMASK 7
|
||||
#define CONF_CU (_ULCAST_(1) << 3)
|
||||
#define CONF_DB (_ULCAST_(1) << 4)
|
||||
#define CONF_IB (_ULCAST_(1) << 5)
|
||||
#define CONF_SE (_ULCAST_(1) << 12)
|
||||
#ifndef CONF_BE /* duplicate in mipsregs.h */
|
||||
#define CONF_BE (_ULCAST_(1) << 15)
|
||||
#endif
|
||||
#define CONF_SC (_ULCAST_(1) << 17)
|
||||
#define CONF_AC (_ULCAST_(1) << 23)
|
||||
#define CONF_HALT (_ULCAST_(1) << 25)
|
||||
#ifndef CONF_M /* duplicate in mipsregs.h */
|
||||
#define CONF_M (_ULCAST_(1) << 31)
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Bits in the cp0 config register select 1.
|
||||
*/
|
||||
#define CONF1_FP 0x00000001 /* FPU present */
|
||||
#define CONF1_EP 0x00000002 /* EJTAG present */
|
||||
#define CONF1_CA 0x00000004 /* mips16 implemented */
|
||||
#define CONF1_WR 0x00000008 /* Watch registers present */
|
||||
#define CONF1_PC 0x00000010 /* Performance counters present */
|
||||
#define CONF1_DA_SHIFT 7 /* D$ associativity */
|
||||
#define CONF1_DA_MASK 0x00000380
|
||||
#define CONF1_DA_BASE 1
|
||||
#define CONF1_DL_SHIFT 10 /* D$ line size */
|
||||
#define CONF1_DL_MASK 0x00001c00
|
||||
#define CONF1_DL_BASE 2
|
||||
#define CONF1_DS_SHIFT 13 /* D$ sets/way */
|
||||
#define CONF1_DS_MASK 0x0000e000
|
||||
#define CONF1_DS_BASE 64
|
||||
#define CONF1_IA_SHIFT 16 /* I$ associativity */
|
||||
#define CONF1_IA_MASK 0x00070000
|
||||
#define CONF1_IA_BASE 1
|
||||
#define CONF1_IL_SHIFT 19 /* I$ line size */
|
||||
#define CONF1_IL_MASK 0x00380000
|
||||
#define CONF1_IL_BASE 2
|
||||
#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
|
||||
#define CONF1_IS_MASK 0x01c00000
|
||||
#define CONF1_IS_BASE 64
|
||||
#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
|
||||
#define CONF1_MS_SHIFT 25
|
||||
|
||||
/* PRID register */
|
||||
#define PRID_COPT_MASK 0xff000000
|
||||
#define PRID_COMP_MASK 0x00ff0000
|
||||
#define PRID_IMP_MASK 0x0000ff00
|
||||
#define PRID_REV_MASK 0x000000ff
|
||||
|
||||
#define PRID_COMP_LEGACY 0x000000
|
||||
#define PRID_COMP_MIPS 0x010000
|
||||
#define PRID_COMP_BROADCOM 0x020000
|
||||
#define PRID_COMP_ALCHEMY 0x030000
|
||||
#define PRID_COMP_SIBYTE 0x040000
|
||||
#define PRID_IMP_BCM4710 0x4000
|
||||
#define PRID_IMP_BCM3302 0x9000
|
||||
#define PRID_IMP_BCM3303 0x9100
|
||||
|
||||
#define PRID_IMP_UNKNOWN 0xff00
|
||||
|
||||
#define BCM330X(id) \
|
||||
(((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
|
||||
(PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) || \
|
||||
((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
|
||||
(PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
|
||||
|
||||
/* Bits in C0_BROADCOM */
|
||||
#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
|
||||
#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
|
||||
#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
|
||||
#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
|
||||
#define BRCM_CLF_ENABLE 0x00100000 /* Enable cache line first feature */
|
||||
|
||||
/* PreFetch Cache aka Read Ahead Cache */
|
||||
|
||||
#define PFC_CR0 0xff400000 /* control reg 0 */
|
||||
#define PFC_CR1 0xff400004 /* control reg 1 */
|
||||
|
||||
/* PFC operations */
|
||||
#define PFC_I 0x00000001 /* Enable PFC use for instructions */
|
||||
#define PFC_D 0x00000002 /* Enable PFC use for data */
|
||||
#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
|
||||
#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
|
||||
#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
|
||||
#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
|
||||
#define PFC_DPF 0x00000040 /* Enable directional prefetching */
|
||||
#define PFC_FLUSH 0x00000100 /* Flush the PFC */
|
||||
#define PFC_BRR 0x40000000 /* Bus error indication */
|
||||
#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
|
||||
|
||||
/* Handy defaults */
|
||||
#define PFC_DISABLED 0
|
||||
#define PFC_AUTO 0xffffffff /* auto select the default mode */
|
||||
#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
|
||||
#define PFC_INST_NOPF (PFC_I | PFC_CINV)
|
||||
#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
|
||||
#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
|
||||
#define PFC_I_AND_D (PFC_INST | PFC_DATA)
|
||||
#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
|
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY
|
||||
|
||||
/*
|
||||
* Macros to access the system control coprocessor
|
||||
*/
|
||||
|
||||
#define MFC0(source, sel) \
|
||||
({ \
|
||||
int __res; \
|
||||
__asm__ __volatile__(" \
|
||||
.set\tnoreorder; \
|
||||
.set\tnoat; \
|
||||
.word\t"STR(0x40010000 | ((source) << 11) | (sel))"; \
|
||||
move\t%0, $1; \
|
||||
.set\tat; \
|
||||
.set\treorder" \
|
||||
:"=r" (__res) \
|
||||
: \
|
||||
:"$1"); \
|
||||
__res; \
|
||||
})
|
||||
|
||||
#define MTC0(source, sel, value) \
|
||||
do { \
|
||||
__asm__ __volatile__(" \
|
||||
.set\tnoreorder; \
|
||||
.set\tnoat; \
|
||||
move\t$1, %z0; \
|
||||
.word\t"STR(0x40810000 | ((source) << 11) | (sel))"; \
|
||||
.set\tat; \
|
||||
.set\treorder" \
|
||||
: \
|
||||
:"jr" (value) \
|
||||
:"$1"); \
|
||||
} while (0)
|
||||
|
||||
#define get_c0_count() \
|
||||
({ \
|
||||
int __res; \
|
||||
__asm__ __volatile__(" \
|
||||
.set\tnoreorder; \
|
||||
.set\tnoat; \
|
||||
mfc0\t%0, $9; \
|
||||
.set\tat; \
|
||||
.set\treorder" \
|
||||
:"=r" (__res)); \
|
||||
__res; \
|
||||
})
|
||||
|
||||
static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
|
||||
{
|
||||
uint lsz, sets, ways;
|
||||
|
||||
/* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
|
||||
if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
|
||||
lsz = CONF1_IL_BASE << lsz;
|
||||
sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
|
||||
ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
|
||||
*size = lsz * sets * ways;
|
||||
*lsize = lsz;
|
||||
}
|
||||
|
||||
static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
|
||||
{
|
||||
uint lsz, sets, ways;
|
||||
|
||||
/* Data Cache Size = Associativity * Line Size * Sets Per Way */
|
||||
if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
|
||||
lsz = CONF1_DL_BASE << lsz;
|
||||
sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
|
||||
ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
|
||||
*size = lsz * sets * ways;
|
||||
*lsize = lsz;
|
||||
}
|
||||
|
||||
#define cache_op(base, op) \
|
||||
__asm__ __volatile__(" \
|
||||
.set noreorder; \
|
||||
.set mips3; \
|
||||
cache %1, (%0); \
|
||||
.set mips0; \
|
||||
.set reorder" \
|
||||
: \
|
||||
: "r" (base), \
|
||||
"i" (op));
|
||||
|
||||
#define cache_unroll4(base, delta, op) \
|
||||
__asm__ __volatile__(" \
|
||||
.set noreorder; \
|
||||
.set mips3; \
|
||||
cache %1, 0(%0); \
|
||||
cache %1, delta(%0); \
|
||||
cache %1, (2 * delta)(%0); \
|
||||
cache %1, (3 * delta)(%0); \
|
||||
.set mips0; \
|
||||
.set reorder" \
|
||||
: \
|
||||
: "r" (base), \
|
||||
"i" (op));
|
||||
|
||||
#endif /* !_LANGUAGE_ASSEMBLY */
|
||||
|
||||
#endif /* _MISPINC_H */
|
||||
|
|
@ -1,221 +0,0 @@
|
|||
#ifndef __osl_h
|
||||
#define __osl_h
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <typedefs.h>
|
||||
#include <linuxver.h>
|
||||
#include <pcicfg.h>
|
||||
|
||||
#define ASSERT(n)
|
||||
|
||||
#ifndef ABS
|
||||
#define ABS(a) (((a) < 0)?-(a):(a))
|
||||
#endif /* ABS */
|
||||
|
||||
#ifndef MIN
|
||||
#define MIN(a, b) (((a) < (b))?(a):(b))
|
||||
#endif /* MIN */
|
||||
|
||||
#ifndef MAX
|
||||
#define MAX(a, b) (((a) > (b))?(a):(b))
|
||||
#endif /* MAX */
|
||||
|
||||
#define CEIL(x, y) (((x) + ((y)-1)) / (y))
|
||||
#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
|
||||
#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
|
||||
#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0)
|
||||
#define VALID_MASK(mask) !((mask) & ((mask) + 1))
|
||||
#ifndef OFFSETOF
|
||||
#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
|
||||
#endif /* OFFSETOF */
|
||||
#ifndef ARRAYSIZE
|
||||
#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Spin at most 'us' microseconds while 'exp' is true.
|
||||
* Caller should explicitly test 'exp' when this completes
|
||||
* and take appropriate error action if 'exp' is still true.
|
||||
*/
|
||||
#define SPINWAIT(exp, us) { \
|
||||
uint countdown = (us) + 9; \
|
||||
while ((exp) && (countdown >= 10)) {\
|
||||
OSL_DELAY(10); \
|
||||
countdown -= 10; \
|
||||
} \
|
||||
}
|
||||
|
||||
|
||||
typedef void (*pktfree_cb_fn_t)(void *ctx, void *pkt, unsigned int status);
|
||||
/* Pkttag flag should be part of public information */
|
||||
typedef struct {
|
||||
bool pkttag;
|
||||
uint pktalloced; /* Number of allocated packet buffers */
|
||||
bool mmbus; /* Bus supports memory-mapped register accesses */
|
||||
pktfree_cb_fn_t tx_fn; /* Callback function for PKTFREE */
|
||||
void *tx_ctx; /* Context to the callback function */
|
||||
} osl_pubinfo_t;
|
||||
|
||||
struct osl_info {
|
||||
osl_pubinfo_t pub;
|
||||
uint magic;
|
||||
void *pdev;
|
||||
uint malloced;
|
||||
uint failed;
|
||||
uint bustype;
|
||||
void *dbgmem_list;
|
||||
};
|
||||
|
||||
typedef struct osl_info osl_t;
|
||||
|
||||
#define PCI_CFG_RETRY 10
|
||||
|
||||
/* map/unmap direction */
|
||||
#define DMA_TX 1 /* TX direction for DMA */
|
||||
#define DMA_RX 2 /* RX direction for DMA */
|
||||
|
||||
#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
|
||||
#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
|
||||
#define SET_REG(osh, r, mask, val) W_REG((osh), (r), ((R_REG((osh), r) & ~(mask)) | (val)))
|
||||
|
||||
/* bcopy, bcmp, and bzero */
|
||||
#define bcopy(src, dst, len) memcpy((dst), (src), (len))
|
||||
#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
|
||||
#define bzero(b, len) memset((b), '\0', (len))
|
||||
|
||||
/* uncached virtual address */
|
||||
#ifdef mips
|
||||
#define OSL_UNCACHED(va) KSEG1ADDR((va))
|
||||
#include <asm/addrspace.h>
|
||||
#else
|
||||
#define OSL_UNCACHED(va) (va)
|
||||
#endif /* mips */
|
||||
|
||||
|
||||
#ifndef IL_BIGENDIAN
|
||||
#define R_REG(osh, r) (\
|
||||
sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
|
||||
sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
|
||||
readl((volatile uint32*)(r)) \
|
||||
)
|
||||
#define W_REG(osh, r, v) do { \
|
||||
switch (sizeof(*(r))) { \
|
||||
case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
|
||||
case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
|
||||
case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
|
||||
} \
|
||||
} while (0)
|
||||
#else /* IL_BIGENDIAN */
|
||||
#define R_REG(osh, r) ({ \
|
||||
__typeof(*(r)) __osl_v; \
|
||||
switch (sizeof(*(r))) { \
|
||||
case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
|
||||
case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
|
||||
case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
|
||||
} \
|
||||
__osl_v; \
|
||||
})
|
||||
#define W_REG(osh, r, v) do { \
|
||||
switch (sizeof(*(r))) { \
|
||||
case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
|
||||
case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
|
||||
case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
|
||||
} \
|
||||
} while (0)
|
||||
#endif /* IL_BIGENDIAN */
|
||||
|
||||
/* dereference an address that may cause a bus exception */
|
||||
#define BUSPROBE(val, addr) get_dbe((val), (addr))
|
||||
#include <asm/paccess.h>
|
||||
|
||||
/* map/unmap physical to virtual I/O */
|
||||
#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
|
||||
#define REG_UNMAP(va) iounmap((void *)(va))
|
||||
|
||||
/* shared (dma-able) memory access macros */
|
||||
#define R_SM(r) *(r)
|
||||
#define W_SM(r, v) (*(r) = (v))
|
||||
#define BZERO_SM(r, len) memset((r), '\0', (len))
|
||||
|
||||
#define MALLOC(osh, size) kmalloc((size), GFP_ATOMIC)
|
||||
#define MFREE(osh, addr, size) kfree((addr))
|
||||
#define MALLOCED(osh) (0)
|
||||
|
||||
#define OSL_DELAY _osl_delay
|
||||
static inline void _osl_delay(uint usec)
|
||||
{
|
||||
uint d;
|
||||
|
||||
while (usec > 0) {
|
||||
d = MIN(usec, 1000);
|
||||
udelay(d);
|
||||
usec -= d;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void
|
||||
bcm_mdelay(uint ms)
|
||||
{
|
||||
uint i;
|
||||
|
||||
for (i = 0; i < ms; i++) {
|
||||
OSL_DELAY(1000);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size)
|
||||
#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size)
|
||||
|
||||
#define OSL_PCI_READ_CONFIG(osh, offset, size) \
|
||||
_osl_pci_read_config((osh), (offset), (size))
|
||||
|
||||
static inline uint32
|
||||
_osl_pci_read_config(osl_t *osh, uint offset, uint size)
|
||||
{
|
||||
uint val;
|
||||
uint retry = PCI_CFG_RETRY;
|
||||
|
||||
do {
|
||||
pci_read_config_dword(osh->pdev, offset, &val);
|
||||
if (val != 0xffffffff)
|
||||
break;
|
||||
} while (retry--);
|
||||
|
||||
return (val);
|
||||
}
|
||||
|
||||
#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
|
||||
_osl_pci_write_config((osh), (offset), (size), (val))
|
||||
static inline void
|
||||
_osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
|
||||
{
|
||||
uint retry = PCI_CFG_RETRY;
|
||||
|
||||
do {
|
||||
pci_write_config_dword(osh->pdev, offset, val);
|
||||
if (offset != PCI_BAR0_WIN)
|
||||
break;
|
||||
if (_osl_pci_read_config(osh, offset, size) == val)
|
||||
break;
|
||||
} while (retry--);
|
||||
}
|
||||
|
||||
|
||||
/* return bus # for the pci device pointed by osh->pdev */
|
||||
#define OSL_PCI_BUS(osh) _osl_pci_bus(osh)
|
||||
static inline uint
|
||||
_osl_pci_bus(osl_t *osh)
|
||||
{
|
||||
return ((struct pci_dev *)osh->pdev)->bus->number;
|
||||
}
|
||||
|
||||
/* return slot # for the pci device pointed by osh->pdev */
|
||||
#define OSL_PCI_SLOT(osh) _osl_pci_slot(osh)
|
||||
static inline uint
|
||||
_osl_pci_slot(osl_t *osh)
|
||||
{
|
||||
return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -1,507 +0,0 @@
|
|||
/*
|
||||
* pcicfg.h: PCI configuration constants and structures.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _h_pcicfg_
|
||||
#define _h_pcicfg_
|
||||
|
||||
/* The following inside ifndef's so we don't collide with NTDDK.H */
|
||||
#ifndef PCI_MAX_BUS
|
||||
#define PCI_MAX_BUS 0x100
|
||||
#endif
|
||||
#ifndef PCI_MAX_DEVICES
|
||||
#define PCI_MAX_DEVICES 0x20
|
||||
#endif
|
||||
#ifndef PCI_MAX_FUNCTION
|
||||
#define PCI_MAX_FUNCTION 0x8
|
||||
#endif
|
||||
|
||||
#ifndef PCI_INVALID_VENDORID
|
||||
#define PCI_INVALID_VENDORID 0xffff
|
||||
#endif
|
||||
#ifndef PCI_INVALID_DEVICEID
|
||||
#define PCI_INVALID_DEVICEID 0xffff
|
||||
#endif
|
||||
|
||||
|
||||
/* Convert between bus-slot-function-register and config addresses */
|
||||
|
||||
#define PCICFG_BUS_SHIFT 16 /* Bus shift */
|
||||
#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
|
||||
#define PCICFG_FUN_SHIFT 8 /* Function shift */
|
||||
#define PCICFG_OFF_SHIFT 0 /* Register shift */
|
||||
|
||||
#define PCICFG_BUS_MASK 0xff /* Bus mask */
|
||||
#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
|
||||
#define PCICFG_FUN_MASK 7 /* Function mask */
|
||||
#define PCICFG_OFF_MASK 0xff /* Bus mask */
|
||||
|
||||
#define PCI_CONFIG_ADDR(b, s, f, o) \
|
||||
((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
|
||||
| (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
|
||||
| (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
|
||||
| (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
|
||||
|
||||
#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
|
||||
#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
|
||||
#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
|
||||
#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
|
||||
|
||||
/* PCIE Config space accessing MACROS */
|
||||
|
||||
#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
|
||||
#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
|
||||
#define PCIECFG_FUN_SHIFT 16 /* Function shift */
|
||||
#define PCIECFG_OFF_SHIFT 0 /* Register shift */
|
||||
|
||||
#define PCIECFG_BUS_MASK 0xff /* Bus mask */
|
||||
#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
|
||||
#define PCIECFG_FUN_MASK 7 /* Function mask */
|
||||
#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
|
||||
|
||||
#define PCIE_CONFIG_ADDR(b, s, f, o) \
|
||||
((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
|
||||
| (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
|
||||
| (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
|
||||
| (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
|
||||
|
||||
#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
|
||||
#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
|
||||
#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
|
||||
#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
|
||||
|
||||
/* The actual config space */
|
||||
|
||||
#define PCI_BAR_MAX 6
|
||||
|
||||
#define PCI_ROM_BAR 8
|
||||
|
||||
#define PCR_RSVDA_MAX 2
|
||||
|
||||
/* Bits in PCI bars' flags */
|
||||
|
||||
#define PCIBAR_FLAGS 0xf
|
||||
#define PCIBAR_IO 0x1
|
||||
#define PCIBAR_MEM1M 0x2
|
||||
#define PCIBAR_MEM64 0x4
|
||||
#define PCIBAR_PREFETCH 0x8
|
||||
#define PCIBAR_MEM32_MASK 0xFFFFFF80
|
||||
|
||||
/* pci config status reg has a bit to indicate that capability ptr is present */
|
||||
|
||||
#define PCI_CAPPTR_PRESENT 0x0010
|
||||
|
||||
typedef struct _pci_config_regs {
|
||||
unsigned short vendor;
|
||||
unsigned short device;
|
||||
unsigned short command;
|
||||
unsigned short status;
|
||||
unsigned char rev_id;
|
||||
unsigned char prog_if;
|
||||
unsigned char sub_class;
|
||||
unsigned char base_class;
|
||||
unsigned char cache_line_size;
|
||||
unsigned char latency_timer;
|
||||
unsigned char header_type;
|
||||
unsigned char bist;
|
||||
unsigned long base[PCI_BAR_MAX];
|
||||
unsigned long cardbus_cis;
|
||||
unsigned short subsys_vendor;
|
||||
unsigned short subsys_id;
|
||||
unsigned long baserom;
|
||||
unsigned long rsvd_a[PCR_RSVDA_MAX];
|
||||
unsigned char int_line;
|
||||
unsigned char int_pin;
|
||||
unsigned char min_gnt;
|
||||
unsigned char max_lat;
|
||||
unsigned char dev_dep[192];
|
||||
} pci_config_regs;
|
||||
|
||||
#define SZPCR (sizeof (pci_config_regs))
|
||||
#define MINSZPCR 64 /* offsetof (dev_dep[0] */
|
||||
|
||||
/* A structure for the config registers is nice, but in most
|
||||
* systems the config space is not memory mapped, so we need
|
||||
* filed offsetts. :-(
|
||||
*/
|
||||
#define PCI_CFG_VID 0
|
||||
#define PCI_CFG_DID 2
|
||||
#define PCI_CFG_CMD 4
|
||||
#define PCI_CFG_STAT 6
|
||||
#define PCI_CFG_REV 8
|
||||
#define PCI_CFG_PROGIF 9
|
||||
#define PCI_CFG_SUBCL 0xa
|
||||
#define PCI_CFG_BASECL 0xb
|
||||
#define PCI_CFG_CLSZ 0xc
|
||||
#define PCI_CFG_LATTIM 0xd
|
||||
#define PCI_CFG_HDR 0xe
|
||||
#define PCI_CFG_BIST 0xf
|
||||
#define PCI_CFG_BAR0 0x10
|
||||
#define PCI_CFG_BAR1 0x14
|
||||
#define PCI_CFG_BAR2 0x18
|
||||
#define PCI_CFG_BAR3 0x1c
|
||||
#define PCI_CFG_BAR4 0x20
|
||||
#define PCI_CFG_BAR5 0x24
|
||||
#define PCI_CFG_CIS 0x28
|
||||
#define PCI_CFG_SVID 0x2c
|
||||
#define PCI_CFG_SSID 0x2e
|
||||
#define PCI_CFG_ROMBAR 0x30
|
||||
#define PCI_CFG_CAPPTR 0x34
|
||||
#define PCI_CFG_INT 0x3c
|
||||
#define PCI_CFG_PIN 0x3d
|
||||
#define PCI_CFG_MINGNT 0x3e
|
||||
#define PCI_CFG_MAXLAT 0x3f
|
||||
|
||||
#ifdef __NetBSD__
|
||||
#undef PCI_CLASS_DISPLAY
|
||||
#undef PCI_CLASS_MEMORY
|
||||
#undef PCI_CLASS_BRIDGE
|
||||
#undef PCI_CLASS_INPUT
|
||||
#undef PCI_CLASS_DOCK
|
||||
#endif /* __NetBSD__ */
|
||||
|
||||
#ifdef EFI
|
||||
#undef PCI_CLASS_BRIDGE
|
||||
#undef PCI_CLASS_OLD
|
||||
#undef PCI_CLASS_DISPLAY
|
||||
#undef PCI_CLASS_SERIAL
|
||||
#undef PCI_CLASS_SATELLITE
|
||||
#endif /* EFI */
|
||||
|
||||
/* Classes and subclasses */
|
||||
|
||||
typedef enum {
|
||||
PCI_CLASS_OLD = 0,
|
||||
PCI_CLASS_DASDI,
|
||||
PCI_CLASS_NET,
|
||||
PCI_CLASS_DISPLAY,
|
||||
PCI_CLASS_MMEDIA,
|
||||
PCI_CLASS_MEMORY,
|
||||
PCI_CLASS_BRIDGE,
|
||||
PCI_CLASS_COMM,
|
||||
PCI_CLASS_BASE,
|
||||
PCI_CLASS_INPUT,
|
||||
PCI_CLASS_DOCK,
|
||||
PCI_CLASS_CPU,
|
||||
PCI_CLASS_SERIAL,
|
||||
PCI_CLASS_INTELLIGENT = 0xe,
|
||||
PCI_CLASS_SATELLITE,
|
||||
PCI_CLASS_CRYPT,
|
||||
PCI_CLASS_DSP,
|
||||
PCI_CLASS_XOR = 0xfe
|
||||
} pci_classes;
|
||||
|
||||
typedef enum {
|
||||
PCI_DASDI_SCSI,
|
||||
PCI_DASDI_IDE,
|
||||
PCI_DASDI_FLOPPY,
|
||||
PCI_DASDI_IPI,
|
||||
PCI_DASDI_RAID,
|
||||
PCI_DASDI_OTHER = 0x80
|
||||
} pci_dasdi_subclasses;
|
||||
|
||||
typedef enum {
|
||||
PCI_NET_ETHER,
|
||||
PCI_NET_TOKEN,
|
||||
PCI_NET_FDDI,
|
||||
PCI_NET_ATM,
|
||||
PCI_NET_OTHER = 0x80
|
||||
} pci_net_subclasses;
|
||||
|
||||
typedef enum {
|
||||
PCI_DISPLAY_VGA,
|
||||
PCI_DISPLAY_XGA,
|
||||
PCI_DISPLAY_3D,
|
||||
PCI_DISPLAY_OTHER = 0x80
|
||||
} pci_display_subclasses;
|
||||
|
||||
typedef enum {
|
||||
PCI_MMEDIA_VIDEO,
|
||||
PCI_MMEDIA_AUDIO,
|
||||
PCI_MMEDIA_PHONE,
|
||||
PCI_MEDIA_OTHER = 0x80
|
||||
} pci_mmedia_subclasses;
|
||||
|
||||
typedef enum {
|
||||
PCI_MEMORY_RAM,
|
||||
PCI_MEMORY_FLASH,
|
||||
PCI_MEMORY_OTHER = 0x80
|
||||
} pci_memory_subclasses;
|
||||
|
||||
typedef enum {
|
||||
PCI_BRIDGE_HOST,
|
||||
PCI_BRIDGE_ISA,
|
||||
PCI_BRIDGE_EISA,
|
||||
PCI_BRIDGE_MC,
|
||||
PCI_BRIDGE_PCI,
|
||||
PCI_BRIDGE_PCMCIA,
|
||||
PCI_BRIDGE_NUBUS,
|
||||
PCI_BRIDGE_CARDBUS,
|
||||
PCI_BRIDGE_RACEWAY,
|
||||
PCI_BRIDGE_OTHER = 0x80
|
||||
} pci_bridge_subclasses;
|
||||
|
||||
typedef enum {
|
||||
PCI_COMM_UART,
|
||||
PCI_COMM_PARALLEL,
|
||||
PCI_COMM_MULTIUART,
|
||||
PCI_COMM_MODEM,
|
||||
PCI_COMM_OTHER = 0x80
|
||||
} pci_comm_subclasses;
|
||||
|
||||
typedef enum {
|
||||
PCI_BASE_PIC,
|
||||
PCI_BASE_DMA,
|
||||
PCI_BASE_TIMER,
|
||||
PCI_BASE_RTC,
|
||||
PCI_BASE_PCI_HOTPLUG,
|
||||
PCI_BASE_OTHER = 0x80
|
||||
} pci_base_subclasses;
|
||||
|
||||
typedef enum {
|
||||
PCI_INPUT_KBD,
|
||||
PCI_INPUT_PEN,
|
||||
PCI_INPUT_MOUSE,
|
||||
PCI_INPUT_SCANNER,
|
||||
PCI_INPUT_GAMEPORT,
|
||||
PCI_INPUT_OTHER = 0x80
|
||||
} pci_input_subclasses;
|
||||
|
||||
typedef enum {
|
||||
PCI_DOCK_GENERIC,
|
||||
PCI_DOCK_OTHER = 0x80
|
||||
} pci_dock_subclasses;
|
||||
|
||||
typedef enum {
|
||||
PCI_CPU_386,
|
||||
PCI_CPU_486,
|
||||
PCI_CPU_PENTIUM,
|
||||
PCI_CPU_ALPHA = 0x10,
|
||||
PCI_CPU_POWERPC = 0x20,
|
||||
PCI_CPU_MIPS = 0x30,
|
||||
PCI_CPU_COPROC = 0x40,
|
||||
PCI_CPU_OTHER = 0x80
|
||||
} pci_cpu_subclasses;
|
||||
|
||||
typedef enum {
|
||||
PCI_SERIAL_IEEE1394,
|
||||
PCI_SERIAL_ACCESS,
|
||||
PCI_SERIAL_SSA,
|
||||
PCI_SERIAL_USB,
|
||||
PCI_SERIAL_FIBER,
|
||||
PCI_SERIAL_SMBUS,
|
||||
PCI_SERIAL_OTHER = 0x80
|
||||
} pci_serial_subclasses;
|
||||
|
||||
typedef enum {
|
||||
PCI_INTELLIGENT_I2O
|
||||
} pci_intelligent_subclasses;
|
||||
|
||||
typedef enum {
|
||||
PCI_SATELLITE_TV,
|
||||
PCI_SATELLITE_AUDIO,
|
||||
PCI_SATELLITE_VOICE,
|
||||
PCI_SATELLITE_DATA,
|
||||
PCI_SATELLITE_OTHER = 0x80
|
||||
} pci_satellite_subclasses;
|
||||
|
||||
typedef enum {
|
||||
PCI_CRYPT_NETWORK,
|
||||
PCI_CRYPT_ENTERTAINMENT,
|
||||
PCI_CRYPT_OTHER = 0x80
|
||||
} pci_crypt_subclasses;
|
||||
|
||||
typedef enum {
|
||||
PCI_DSP_DPIO,
|
||||
PCI_DSP_OTHER = 0x80
|
||||
} pci_dsp_subclasses;
|
||||
|
||||
typedef enum {
|
||||
PCI_XOR_QDMA,
|
||||
PCI_XOR_OTHER = 0x80
|
||||
} pci_xor_subclasses;
|
||||
|
||||
/* Header types */
|
||||
typedef enum {
|
||||
PCI_HEADER_NORMAL,
|
||||
PCI_HEADER_BRIDGE,
|
||||
PCI_HEADER_CARDBUS
|
||||
} pci_header_types;
|
||||
|
||||
|
||||
/* Overlay for a PCI-to-PCI bridge */
|
||||
|
||||
#define PPB_RSVDA_MAX 2
|
||||
#define PPB_RSVDD_MAX 8
|
||||
|
||||
typedef struct _ppb_config_regs {
|
||||
unsigned short vendor;
|
||||
unsigned short device;
|
||||
unsigned short command;
|
||||
unsigned short status;
|
||||
unsigned char rev_id;
|
||||
unsigned char prog_if;
|
||||
unsigned char sub_class;
|
||||
unsigned char base_class;
|
||||
unsigned char cache_line_size;
|
||||
unsigned char latency_timer;
|
||||
unsigned char header_type;
|
||||
unsigned char bist;
|
||||
unsigned long rsvd_a[PPB_RSVDA_MAX];
|
||||
unsigned char prim_bus;
|
||||
unsigned char sec_bus;
|
||||
unsigned char sub_bus;
|
||||
unsigned char sec_lat;
|
||||
unsigned char io_base;
|
||||
unsigned char io_lim;
|
||||
unsigned short sec_status;
|
||||
unsigned short mem_base;
|
||||
unsigned short mem_lim;
|
||||
unsigned short pf_mem_base;
|
||||
unsigned short pf_mem_lim;
|
||||
unsigned long pf_mem_base_hi;
|
||||
unsigned long pf_mem_lim_hi;
|
||||
unsigned short io_base_hi;
|
||||
unsigned short io_lim_hi;
|
||||
unsigned short subsys_vendor;
|
||||
unsigned short subsys_id;
|
||||
unsigned long rsvd_b;
|
||||
unsigned char rsvd_c;
|
||||
unsigned char int_pin;
|
||||
unsigned short bridge_ctrl;
|
||||
unsigned char chip_ctrl;
|
||||
unsigned char diag_ctrl;
|
||||
unsigned short arb_ctrl;
|
||||
unsigned long rsvd_d[PPB_RSVDD_MAX];
|
||||
unsigned char dev_dep[192];
|
||||
} ppb_config_regs;
|
||||
|
||||
|
||||
/* PCI CAPABILITY DEFINES */
|
||||
#define PCI_CAP_POWERMGMTCAP_ID 0x01
|
||||
#define PCI_CAP_MSICAP_ID 0x05
|
||||
#define PCI_CAP_PCIECAP_ID 0x10
|
||||
|
||||
/* Data structure to define the Message Signalled Interrupt facility
|
||||
* Valid for PCI and PCIE configurations
|
||||
*/
|
||||
typedef struct _pciconfig_cap_msi {
|
||||
unsigned char capID;
|
||||
unsigned char nextptr;
|
||||
unsigned short msgctrl;
|
||||
unsigned int msgaddr;
|
||||
} pciconfig_cap_msi;
|
||||
|
||||
/* Data structure to define the Power managment facility
|
||||
* Valid for PCI and PCIE configurations
|
||||
*/
|
||||
typedef struct _pciconfig_cap_pwrmgmt {
|
||||
unsigned char capID;
|
||||
unsigned char nextptr;
|
||||
unsigned short pme_cap;
|
||||
unsigned short pme_sts_ctrl;
|
||||
unsigned char pme_bridge_ext;
|
||||
unsigned char data;
|
||||
} pciconfig_cap_pwrmgmt;
|
||||
|
||||
#define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */
|
||||
#define PME_CSR_OFFSET 0x4 /* 4-bytes offset */
|
||||
#define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */
|
||||
#define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */
|
||||
|
||||
/* Data structure to define the PCIE capability */
|
||||
typedef struct _pciconfig_cap_pcie {
|
||||
unsigned char capID;
|
||||
unsigned char nextptr;
|
||||
unsigned short pcie_cap;
|
||||
unsigned int dev_cap;
|
||||
unsigned short dev_ctrl;
|
||||
unsigned short dev_status;
|
||||
unsigned int link_cap;
|
||||
unsigned short link_ctrl;
|
||||
unsigned short link_status;
|
||||
} pciconfig_cap_pcie;
|
||||
|
||||
/* PCIE Enhanced CAPABILITY DEFINES */
|
||||
#define PCIE_EXTCFG_OFFSET 0x100
|
||||
#define PCIE_ADVERRREP_CAPID 0x0001
|
||||
#define PCIE_VC_CAPID 0x0002
|
||||
#define PCIE_DEVSNUM_CAPID 0x0003
|
||||
#define PCIE_PWRBUDGET_CAPID 0x0004
|
||||
|
||||
/* Header to define the PCIE specific capabilities in the extended config space */
|
||||
typedef struct _pcie_enhanced_caphdr {
|
||||
unsigned short capID;
|
||||
unsigned short cap_ver : 4;
|
||||
unsigned short next_ptr : 12;
|
||||
} pcie_enhanced_caphdr;
|
||||
|
||||
|
||||
/* Everything below is BRCM HND proprietary */
|
||||
|
||||
|
||||
/* Brcm PCI configuration registers */
|
||||
#define cap_list rsvd_a[0]
|
||||
#define bar0_window dev_dep[0x80 - 0x40]
|
||||
#define bar1_window dev_dep[0x84 - 0x40]
|
||||
#define sprom_control dev_dep[0x88 - 0x40]
|
||||
|
||||
#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
|
||||
#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
|
||||
#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
|
||||
#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
|
||||
#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
|
||||
#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
|
||||
#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
|
||||
#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
|
||||
#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address */
|
||||
#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
|
||||
#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
|
||||
#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
|
||||
|
||||
#define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */
|
||||
#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
|
||||
#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
|
||||
#define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the
|
||||
* 8KB window, so their address is the "regular"
|
||||
* address plus 4K
|
||||
*/
|
||||
#define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */
|
||||
|
||||
/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
|
||||
#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
|
||||
#define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */
|
||||
#define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */
|
||||
|
||||
/* PCI_INT_STATUS */
|
||||
#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
|
||||
|
||||
/* PCI_INT_MASK */
|
||||
#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
|
||||
#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
|
||||
#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
|
||||
|
||||
/* PCI_SPROM_CONTROL */
|
||||
#define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */
|
||||
#define SPROM_LOCKED 0x08 /* SPROM Locked */
|
||||
#define SPROM_BLANK 0x04 /* indicating a blank SPROM */
|
||||
#define SPROM_WRITEEN 0x10 /* SPROM write enable */
|
||||
#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
|
||||
#define SPROM_OTPIN_USE 0x80 /* device OTP In use */
|
||||
|
||||
#define SPROM_SIZE 256 /* sprom size in 16-bit */
|
||||
#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
|
||||
|
||||
/* PCI_CFG_CMD_STAT */
|
||||
#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
|
||||
|
||||
#endif /* _h_pcicfg_ */
|
||||
|
|
@ -1,856 +0,0 @@
|
|||
/*
|
||||
* SiliconBackplane Chipcommon core hardware definitions.
|
||||
*
|
||||
* The chipcommon core provides chip identification, SB control,
|
||||
* jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
|
||||
* gpio interface, extbus, and support for serial and parallel flashes.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SBCHIPC_H
|
||||
#define _SBCHIPC_H
|
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY
|
||||
|
||||
/* cpp contortions to concatenate w/arg prescan */
|
||||
#ifndef PAD
|
||||
#define _PADLINE(line) pad ## line
|
||||
#define _XSTR(line) _PADLINE(line)
|
||||
#define PAD _XSTR(__LINE__)
|
||||
#endif /* PAD */
|
||||
|
||||
|
||||
typedef volatile struct {
|
||||
uint32 chipid; /* 0x0 */
|
||||
uint32 capabilities;
|
||||
uint32 corecontrol; /* corerev >= 1 */
|
||||
uint32 bist;
|
||||
|
||||
/* OTP */
|
||||
uint32 otpstatus; /* 0x10, corerev >= 10 */
|
||||
uint32 otpcontrol;
|
||||
uint32 otpprog;
|
||||
uint32 PAD;
|
||||
|
||||
/* Interrupt control */
|
||||
uint32 intstatus; /* 0x20 */
|
||||
uint32 intmask;
|
||||
uint32 chipcontrol; /* 0x28, rev >= 11 */
|
||||
uint32 chipstatus; /* 0x2c, rev >= 11 */
|
||||
|
||||
/* Jtag Master */
|
||||
uint32 jtagcmd; /* 0x30, rev >= 10 */
|
||||
uint32 jtagir;
|
||||
uint32 jtagdr;
|
||||
uint32 jtagctrl;
|
||||
|
||||
/* serial flash interface registers */
|
||||
uint32 flashcontrol; /* 0x40 */
|
||||
uint32 flashaddress;
|
||||
uint32 flashdata;
|
||||
uint32 PAD[1];
|
||||
|
||||
/* Silicon backplane configuration broadcast control */
|
||||
uint32 broadcastaddress; /* 0x50 */
|
||||
uint32 broadcastdata;
|
||||
|
||||
/* gpio - cleared only by power-on-reset */
|
||||
uint32 gpiopullup; /* 0x58, corerev >= 20 */
|
||||
uint32 gpiopulldown; /* 0x5c, corerev >= 20 */
|
||||
uint32 gpioin; /* 0x60 */
|
||||
uint32 gpioout;
|
||||
uint32 gpioouten;
|
||||
uint32 gpiocontrol;
|
||||
uint32 gpiointpolarity;
|
||||
uint32 gpiointmask;
|
||||
|
||||
/* GPIO events corerev >= 11 */
|
||||
uint32 gpioevent;
|
||||
uint32 gpioeventintmask;
|
||||
|
||||
/* Watchdog timer */
|
||||
uint32 watchdog; /* 0x80 */
|
||||
|
||||
/* GPIO events corerev >= 11 */
|
||||
uint32 gpioeventintpolarity;
|
||||
|
||||
/* GPIO based LED powersave registers corerev >= 16 */
|
||||
uint32 gpiotimerval; /* 0x88 */
|
||||
uint32 gpiotimeroutmask;
|
||||
|
||||
/* clock control */
|
||||
uint32 clockcontrol_n; /* 0x90 */
|
||||
uint32 clockcontrol_sb; /* aka m0 */
|
||||
uint32 clockcontrol_pci; /* aka m1 */
|
||||
uint32 clockcontrol_m2; /* mii/uart/mipsref */
|
||||
uint32 clockcontrol_m3; /* cpu */
|
||||
uint32 clkdiv; /* corerev >= 3 */
|
||||
uint32 PAD[2];
|
||||
|
||||
/* pll delay registers (corerev >= 4) */
|
||||
uint32 pll_on_delay; /* 0xb0 */
|
||||
uint32 fref_sel_delay;
|
||||
uint32 slow_clk_ctl; /* 5 < corerev < 10 */
|
||||
uint32 PAD[1];
|
||||
|
||||
/* Instaclock registers (corerev >= 10) */
|
||||
uint32 system_clk_ctl; /* 0xc0 */
|
||||
uint32 clkstatestretch;
|
||||
uint32 PAD[14];
|
||||
|
||||
/* ExtBus control registers (corerev >= 3) */
|
||||
uint32 pcmcia_config; /* 0x100 */
|
||||
uint32 pcmcia_memwait;
|
||||
uint32 pcmcia_attrwait;
|
||||
uint32 pcmcia_iowait;
|
||||
uint32 ide_config;
|
||||
uint32 ide_memwait;
|
||||
uint32 ide_attrwait;
|
||||
uint32 ide_iowait;
|
||||
uint32 prog_config;
|
||||
uint32 prog_waitcount;
|
||||
uint32 flash_config;
|
||||
uint32 flash_waitcount;
|
||||
uint32 PAD[4];
|
||||
|
||||
/* Enhanced Coexistance Interface (ECI) registers (corerev >= 21) */
|
||||
uint32 eci_output; /* 0x140 */
|
||||
uint32 eci_control;
|
||||
uint32 eci_inputlo;
|
||||
uint32 eci_inputmi;
|
||||
uint32 eci_inputhi;
|
||||
uint32 eci_inputintpolaritylo;
|
||||
uint32 eci_inputintpolaritymi;
|
||||
uint32 eci_inputintpolarityhi;
|
||||
uint32 eci_intmasklo;
|
||||
uint32 eci_intmaskmi;
|
||||
uint32 eci_intmaskhi;
|
||||
uint32 eci_eventlo;
|
||||
uint32 eci_eventmi;
|
||||
uint32 eci_eventhi;
|
||||
uint32 eci_eventmasklo;
|
||||
uint32 eci_eventmaskmi;
|
||||
uint32 eci_eventmaskhi;
|
||||
uint32 PAD[23];
|
||||
|
||||
|
||||
/* Clock control and hardware workarounds (corerev >= 20) */
|
||||
uint32 clk_ctl_st; /* 0x1e0 */
|
||||
uint32 hw_war;
|
||||
uint32 PAD[70];
|
||||
|
||||
/* uarts */
|
||||
uint8 uart0data; /* 0x300 */
|
||||
uint8 uart0imr;
|
||||
uint8 uart0fcr;
|
||||
uint8 uart0lcr;
|
||||
uint8 uart0mcr;
|
||||
uint8 uart0lsr;
|
||||
uint8 uart0msr;
|
||||
uint8 uart0scratch;
|
||||
uint8 PAD[248]; /* corerev >= 1 */
|
||||
|
||||
uint8 uart1data; /* 0x400 */
|
||||
uint8 uart1imr;
|
||||
uint8 uart1fcr;
|
||||
uint8 uart1lcr;
|
||||
uint8 uart1mcr;
|
||||
uint8 uart1lsr;
|
||||
uint8 uart1msr;
|
||||
uint8 uart1scratch;
|
||||
uint32 PAD[126];
|
||||
|
||||
/* PMU registers (corerev >= 20) */
|
||||
uint32 pmucontrol; /* 0x600 */
|
||||
uint32 pmucapabilities;
|
||||
uint32 pmustatus;
|
||||
uint32 res_state;
|
||||
uint32 res_pending;
|
||||
uint32 pmutimer;
|
||||
uint32 min_res_mask;
|
||||
uint32 max_res_mask;
|
||||
uint32 res_table_sel;
|
||||
uint32 res_dep_mask;
|
||||
uint32 res_updn_timer;
|
||||
uint32 res_timer;
|
||||
uint32 clkstretch;
|
||||
uint32 pmuwatchdog;
|
||||
uint32 PAD[2];
|
||||
uint32 res_req_timer_sel;
|
||||
uint32 res_req_timer;
|
||||
uint32 res_req_mask;
|
||||
uint32 PAD;
|
||||
uint32 chipcontrol_addr;
|
||||
uint32 chipcontrol_data;
|
||||
uint32 regcontrol_addr;
|
||||
uint32 regcontrol_data;
|
||||
uint32 pllcontrol_addr;
|
||||
uint32 pllcontrol_data;
|
||||
uint32 PAD[102];
|
||||
uint16 otp[512];
|
||||
} chipcregs_t;
|
||||
|
||||
#endif /* _LANGUAGE_ASSEMBLY */
|
||||
|
||||
/* corecontrol */
|
||||
#define CC_UE (1 << 0) /* uart enable */
|
||||
|
||||
#define CC_CHIPID 0
|
||||
#define CC_CAPABILITIES 4
|
||||
#define CC_OTPST 0x10
|
||||
#define CC_CHIPST 0x2c
|
||||
#define CC_JTAGCMD 0x30
|
||||
#define CC_JTAGIR 0x34
|
||||
#define CC_JTAGDR 0x38
|
||||
#define CC_JTAGCTRL 0x3c
|
||||
#define CC_WATCHDOG 0x80
|
||||
#define CC_CLKC_N 0x90
|
||||
#define CC_CLKC_M0 0x94
|
||||
#define CC_CLKC_M1 0x98
|
||||
#define CC_CLKC_M2 0x9c
|
||||
#define CC_CLKC_M3 0xa0
|
||||
#define CC_CLKDIV 0xa4
|
||||
#define CC_SYS_CLK_CTL 0xc0
|
||||
#define CC_CLK_CTL_ST SB_CLK_CTL_ST
|
||||
#define PMU_CTL 0x600
|
||||
#define PMU_CAP 0x604
|
||||
#define PMU_ST 0x608
|
||||
#define PMU_TIMER 0x614
|
||||
#define PMU_MIN_RES_MASK 0x618
|
||||
#define PMU_MAX_RES_MASK 0x61c
|
||||
#define PMU_REG_CONTROL_ADDR 0x658
|
||||
#define PMU_REG_CONTROL_DATA 0x65C
|
||||
#define PMU_PLL_CONTROL_ADDR 0x660
|
||||
#define PMU_PLL_CONTROL_DATA 0x664
|
||||
#define CC_OTP 0x800 /* OTP address space */
|
||||
|
||||
/* chipid */
|
||||
#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
|
||||
#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
|
||||
#define CID_REV_SHIFT 16 /* Chip Revision shift */
|
||||
#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
|
||||
#define CID_PKG_SHIFT 20 /* Package Option shift */
|
||||
#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
|
||||
#define CID_CC_SHIFT 24
|
||||
|
||||
/* capabilities */
|
||||
#define CC_CAP_UARTS_MASK 0x00000003 /* Number of uarts */
|
||||
#define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
|
||||
#define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */
|
||||
#define CC_CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
|
||||
#define CC_CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
|
||||
#define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
|
||||
#define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
|
||||
#define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
|
||||
#define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
|
||||
#define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */
|
||||
#define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */
|
||||
#define CC_CAP_PWR_CTL 0x00040000 /* Power control */
|
||||
#define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
|
||||
#define CC_CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
|
||||
#define CC_CAP_OTPSIZE_BASE 5 /* OTP Size base */
|
||||
#define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */
|
||||
#define CC_CAP_ROM 0x00800000 /* Internal boot rom active */
|
||||
#define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */
|
||||
#define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
|
||||
#define CC_CAP_ECI 0x20000000 /* ECI Present, rev >= 21 */
|
||||
|
||||
/* PLL type */
|
||||
#define PLL_NONE 0x00000000
|
||||
#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
|
||||
#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
|
||||
#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
|
||||
#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
|
||||
#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
|
||||
#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
|
||||
#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
|
||||
|
||||
/* ALP clock on pre-PMU chips */
|
||||
#define ALP_CLOCK 20000000
|
||||
|
||||
/* HT clock */
|
||||
#define HT_CLOCK 80000000
|
||||
|
||||
/* watchdog clock */
|
||||
#define WATCHDOG_CLOCK_5354 32000 /* Hz */
|
||||
|
||||
/* corecontrol */
|
||||
#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
|
||||
#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
|
||||
#define CC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */
|
||||
|
||||
/* chipcontrol */
|
||||
#define CHIPCTRL_4321A0_DEFAULT 0x3a4
|
||||
#define CHIPCTRL_4321A1_DEFAULT 0x0a4
|
||||
|
||||
/* Fields in the otpstatus register in rev >= 21 */
|
||||
#define OTPS_OL_MASK 0x000000ff
|
||||
#define OTPS_OL_MFG 0x00000001 /* manuf row is locked */
|
||||
#define OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */
|
||||
#define OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */
|
||||
#define OTPS_OL_GU 0x00000008 /* general use region is locked */
|
||||
#define OTPS_GUP_MASK 0x00000f00
|
||||
#define OTPS_GUP_SHIFT 8
|
||||
#define OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */
|
||||
#define OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */
|
||||
#define OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */
|
||||
#define OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */
|
||||
#define OTPS_READY 0x00001000
|
||||
#define OTPS_RV(x) (1 << (16 + (x)))
|
||||
|
||||
/* Fields in the otpcontrol register in rev >= 21 */
|
||||
#define OTPC_PROGSEL 0x00000001
|
||||
#define OTPC_PCOUNT_MASK 0x0000000e
|
||||
#define OTPC_PCOUNT_SHIFT 1
|
||||
#define OTPC_VSEL_MASK 0x000000f0
|
||||
#define OTPC_VSEL_SHIFT 4
|
||||
#define OTPC_TMM_MASK 0x00000700
|
||||
#define OTPC_TMM_SHIFT 8
|
||||
#define OTPC_ODM 0x00000800
|
||||
#define OTPC_PROGEN 0x80000000
|
||||
|
||||
/* Fields in otpprog in rev >= 21 */
|
||||
#define OTPP_COL_MASK 0x000000ff
|
||||
#define OTPP_COL_SHIFT 0
|
||||
#define OTPP_ROW_MASK 0x0000ff00
|
||||
#define OTPP_ROW_SHIFT 8
|
||||
#define OTPP_OC_MASK 0x0f000000
|
||||
#define OTPP_OC_SHIFT 24
|
||||
#define OTPP_READERR 0x10000000
|
||||
#define OTPP_VALUE_MASK 0x20000000
|
||||
#define OTPP_VALUE_SHIFT 29
|
||||
#define OTPP_START_BUSY 0x80000000
|
||||
|
||||
/* Opcodes for OTPP_OC field */
|
||||
#define OTPPOC_READ 0
|
||||
#define OTPPOC_BIT_PROG 1
|
||||
#define OTPPOC_VERIFY 3
|
||||
#define OTPPOC_INIT 4
|
||||
#define OTPPOC_SET 5
|
||||
#define OTPPOC_RESET 6
|
||||
#define OTPPOC_OCST 7
|
||||
#define OTPPOC_ROW_LOCK 8
|
||||
#define OTPPOC_PRESCN_TEST 9
|
||||
|
||||
/* jtagcmd */
|
||||
#define JCMD_START 0x80000000
|
||||
#define JCMD_BUSY 0x80000000
|
||||
#define JCMD_PAUSE 0x40000000
|
||||
#define JCMD0_ACC_MASK 0x0000f000
|
||||
#define JCMD0_ACC_IRDR 0x00000000
|
||||
#define JCMD0_ACC_DR 0x00001000
|
||||
#define JCMD0_ACC_IR 0x00002000
|
||||
#define JCMD0_ACC_RESET 0x00003000
|
||||
#define JCMD0_ACC_IRPDR 0x00004000
|
||||
#define JCMD0_ACC_PDR 0x00005000
|
||||
#define JCMD0_IRW_MASK 0x00000f00
|
||||
#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
|
||||
#define JCMD_ACC_IRDR 0x00000000
|
||||
#define JCMD_ACC_DR 0x00010000
|
||||
#define JCMD_ACC_IR 0x00020000
|
||||
#define JCMD_ACC_RESET 0x00030000
|
||||
#define JCMD_ACC_IRPDR 0x00040000
|
||||
#define JCMD_ACC_PDR 0x00050000
|
||||
#define JCMD_IRW_MASK 0x00001f00
|
||||
#define JCMD_IRW_SHIFT 8
|
||||
#define JCMD_DRW_MASK 0x0000003f
|
||||
|
||||
/* jtagctrl */
|
||||
#define JCTRL_FORCE_CLK 4 /* Force clock */
|
||||
#define JCTRL_EXT_EN 2 /* Enable external targets */
|
||||
#define JCTRL_EN 1 /* Enable Jtag master */
|
||||
|
||||
/* Fields in clkdiv */
|
||||
#define CLKD_SFLASH 0x0f000000
|
||||
#define CLKD_SFLASH_SHIFT 24
|
||||
#define CLKD_OTP 0x000f0000
|
||||
#define CLKD_OTP_SHIFT 16
|
||||
#define CLKD_JTAG 0x00000f00
|
||||
#define CLKD_JTAG_SHIFT 8
|
||||
#define CLKD_UART 0x000000ff
|
||||
|
||||
/* intstatus/intmask */
|
||||
#define CI_GPIO 0x00000001 /* gpio intr */
|
||||
#define CI_EI 0x00000002 /* extif intr (corerev >= 3) */
|
||||
#define CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */
|
||||
#define CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */
|
||||
#define CI_ECI 0x00000010 /* eci intr (corerev >= 21) */
|
||||
#define CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */
|
||||
#define CI_UART 0x00000040 /* uart intr (corerev >= 21) */
|
||||
#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
|
||||
|
||||
/* slow_clk_ctl */
|
||||
#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
|
||||
#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
|
||||
#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
|
||||
#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
|
||||
#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
|
||||
#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled,
|
||||
* 0: LPO is enabled
|
||||
*/
|
||||
#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,
|
||||
* 0: power logic control
|
||||
*/
|
||||
#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors
|
||||
* PLL clock disable requests from core
|
||||
*/
|
||||
#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't
|
||||
* disable crystal when appropriate
|
||||
*/
|
||||
#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
|
||||
#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
|
||||
#define SCC_CD_SHIFT 16
|
||||
|
||||
/* system_clk_ctl */
|
||||
#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
|
||||
#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
|
||||
#define SYCC_FP 0x00000004 /* ForcePLLOn */
|
||||
#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
|
||||
#define SYCC_HR 0x00000010 /* Force HT */
|
||||
#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
|
||||
#define SYCC_CD_SHIFT 16
|
||||
|
||||
/* pcmcia_iowait */
|
||||
#define PI_W0_MASK 0x0000003f /* waitcount0 */
|
||||
#define PI_W1_MASK 0x00001f00 /* waitcount1 */
|
||||
#define PI_W1_SHIFT 8
|
||||
#define PI_W2_MASK 0x001f0000 /* waitcount2 */
|
||||
#define PI_W2_SHIFT 16
|
||||
#define PI_W3_MASK 0x1f000000 /* waitcount3 */
|
||||
#define PI_W3_SHIFT 24
|
||||
|
||||
/* prog_waitcount */
|
||||
#define PW_W0_MASK 0x0000001f /* waitcount0 */
|
||||
#define PW_W1_MASK 0x00001f00 /* waitcount1 */
|
||||
#define PW_W1_SHIFT 8
|
||||
#define PW_W2_MASK 0x001f0000 /* waitcount2 */
|
||||
#define PW_W2_SHIFT 16
|
||||
#define PW_W3_MASK 0x1f000000 /* waitcount3 */
|
||||
#define PW_W3_SHIFT 24
|
||||
|
||||
#define PW_W0 0x0000000c
|
||||
#define PW_W1 0x00000a00
|
||||
#define PW_W2 0x00020000
|
||||
#define PW_W3 0x01000000
|
||||
|
||||
/* watchdog */
|
||||
#define WATCHDOG_CLOCK 48000000 /* Hz */
|
||||
|
||||
/* Fields in pmucontrol */
|
||||
#define PCTL_ILP_DIV_MASK 0xffff0000
|
||||
#define PCTL_ILP_DIV_SHIFT 16
|
||||
#define PCTL_NOILP_ON_WAIT 0x00000200
|
||||
#define PCTL_HT_REQ_EN 0x00000100
|
||||
#define PCTL_ALP_REQ_EN 0x00000080
|
||||
#define PCTL_XTALFREQ_MASK 0x0000007c
|
||||
#define PCTL_XTALFREQ_SHIFT 2
|
||||
#define PCTL_ILP_DIV_EN 0x00000002
|
||||
#define PCTL_LPO_SEL 0x00000001
|
||||
|
||||
/* gpiotimerval */
|
||||
#define GPIO_ONTIME_SHIFT 16
|
||||
|
||||
/* clockcontrol_n */
|
||||
#define CN_N1_MASK 0x3f /* n1 control */
|
||||
#define CN_N2_MASK 0x3f00 /* n2 control */
|
||||
#define CN_N2_SHIFT 8
|
||||
#define CN_PLLC_MASK 0xf0000 /* pll control */
|
||||
#define CN_PLLC_SHIFT 16
|
||||
|
||||
/* clockcontrol_sb/pci/uart */
|
||||
#define CC_M1_MASK 0x3f /* m1 control */
|
||||
#define CC_M2_MASK 0x3f00 /* m2 control */
|
||||
#define CC_M2_SHIFT 8
|
||||
#define CC_M3_MASK 0x3f0000 /* m3 control */
|
||||
#define CC_M3_SHIFT 16
|
||||
#define CC_MC_MASK 0x1f000000 /* mux control */
|
||||
#define CC_MC_SHIFT 24
|
||||
|
||||
/* N3M Clock control magic field values */
|
||||
#define CC_F6_2 0x02 /* A factor of 2 in */
|
||||
#define CC_F6_3 0x03 /* 6-bit fields like */
|
||||
#define CC_F6_4 0x05 /* N1, M1 or M3 */
|
||||
#define CC_F6_5 0x09
|
||||
#define CC_F6_6 0x11
|
||||
#define CC_F6_7 0x21
|
||||
|
||||
#define CC_F5_BIAS 5 /* 5-bit fields get this added */
|
||||
|
||||
#define CC_MC_BYPASS 0x08
|
||||
#define CC_MC_M1 0x04
|
||||
#define CC_MC_M1M2 0x02
|
||||
#define CC_MC_M1M2M3 0x01
|
||||
#define CC_MC_M1M3 0x11
|
||||
|
||||
/* Type 2 Clock control magic field values */
|
||||
#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
|
||||
#define CC_T2M2_BIAS 3 /* m2 bias */
|
||||
|
||||
#define CC_T2MC_M1BYP 1
|
||||
#define CC_T2MC_M2BYP 2
|
||||
#define CC_T2MC_M3BYP 4
|
||||
|
||||
/* Type 6 Clock control magic field values */
|
||||
#define CC_T6_MMASK 1 /* bits of interest in m */
|
||||
#define CC_T6_M0 120000000 /* sb clock for m = 0 */
|
||||
#define CC_T6_M1 100000000 /* sb clock for m = 1 */
|
||||
#define SB2MIPS_T6(sb) (2 * (sb))
|
||||
|
||||
/* Common clock base */
|
||||
#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
|
||||
#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
|
||||
|
||||
/* Clock control values for 200Mhz in 5350 */
|
||||
#define CLKC_5350_N 0x0311
|
||||
#define CLKC_5350_M 0x04020009
|
||||
|
||||
/* Flash types in the chipcommon capabilities register */
|
||||
#define FLASH_NONE 0x000 /* No flash */
|
||||
#define SFLASH_ST 0x100 /* ST serial flash */
|
||||
#define SFLASH_AT 0x200 /* Atmel serial flash */
|
||||
#define PFLASH 0x700 /* Parallel flash */
|
||||
|
||||
/* Bits in the ExtBus config registers */
|
||||
#define CC_CFG_EN 0x0001 /* Enable */
|
||||
#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
|
||||
#define CC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */
|
||||
#define CC_CFG_EM_SYNC 0x0002 /* Synchronous */
|
||||
#define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */
|
||||
#define CC_CFG_EM_IDE 0x0006 /* IDE */
|
||||
#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
|
||||
#define CC_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */
|
||||
#define CC_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */
|
||||
#define CC_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */
|
||||
#define CC_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */
|
||||
|
||||
/* ExtBus address space */
|
||||
#define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */
|
||||
#define CC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */
|
||||
#define CC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */
|
||||
#define CC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */
|
||||
#define CC_EB_IDE 0x1a800000 /* IDE memory base */
|
||||
#define CC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */
|
||||
#define CC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */
|
||||
#define CC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */
|
||||
#define CC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */
|
||||
|
||||
|
||||
/* Start/busy bit in flashcontrol */
|
||||
#define SFLASH_OPCODE 0x000000ff
|
||||
#define SFLASH_ACTION 0x00000700
|
||||
#define SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
|
||||
#define SFLASH_START 0x80000000
|
||||
#define SFLASH_BUSY SFLASH_START
|
||||
|
||||
/* flashcontrol action codes */
|
||||
#define SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */
|
||||
#define SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */
|
||||
#define SFLASH_ACT_OP3A 0x0200 /* opcode + 3 address bytes */
|
||||
#define SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addres & 1 data bytes */
|
||||
#define SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addres & 4 data bytes */
|
||||
#define SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addres, 4 don't care & 4 data bytes */
|
||||
#define SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addres, 1 don't care & 4 data bytes */
|
||||
|
||||
/* flashcontrol action+opcodes for ST flashes */
|
||||
#define SFLASH_ST_WREN 0x0006 /* Write Enable */
|
||||
#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
|
||||
#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
|
||||
#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
|
||||
#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
|
||||
#define SFLASH_ST_PP 0x0302 /* Page Program */
|
||||
#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
|
||||
#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
|
||||
#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
|
||||
#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
|
||||
#define SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */
|
||||
|
||||
/* Status register bits for ST flashes */
|
||||
#define SFLASH_ST_WIP 0x01 /* Write In Progress */
|
||||
#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
|
||||
#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
|
||||
#define SFLASH_ST_BP_SHIFT 2
|
||||
#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
|
||||
|
||||
/* flashcontrol action+opcodes for Atmel flashes */
|
||||
#define SFLASH_AT_READ 0x07e8
|
||||
#define SFLASH_AT_PAGE_READ 0x07d2
|
||||
#define SFLASH_AT_BUF1_READ
|
||||
#define SFLASH_AT_BUF2_READ
|
||||
#define SFLASH_AT_STATUS 0x01d7
|
||||
#define SFLASH_AT_BUF1_WRITE 0x0384
|
||||
#define SFLASH_AT_BUF2_WRITE 0x0387
|
||||
#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
|
||||
#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
|
||||
#define SFLASH_AT_BUF1_PROGRAM 0x0288
|
||||
#define SFLASH_AT_BUF2_PROGRAM 0x0289
|
||||
#define SFLASH_AT_PAGE_ERASE 0x0281
|
||||
#define SFLASH_AT_BLOCK_ERASE 0x0250
|
||||
#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
|
||||
#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
|
||||
#define SFLASH_AT_BUF1_LOAD 0x0253
|
||||
#define SFLASH_AT_BUF2_LOAD 0x0255
|
||||
#define SFLASH_AT_BUF1_COMPARE 0x0260
|
||||
#define SFLASH_AT_BUF2_COMPARE 0x0261
|
||||
#define SFLASH_AT_BUF1_REPROGRAM 0x0258
|
||||
#define SFLASH_AT_BUF2_REPROGRAM 0x0259
|
||||
|
||||
/* Status register bits for Atmel flashes */
|
||||
#define SFLASH_AT_READY 0x80
|
||||
#define SFLASH_AT_MISMATCH 0x40
|
||||
#define SFLASH_AT_ID_MASK 0x38
|
||||
#define SFLASH_AT_ID_SHIFT 3
|
||||
|
||||
/*
|
||||
* These are the UART port assignments, expressed as offsets from the base
|
||||
* register. These assignments should hold for any serial port based on
|
||||
* a 8250, 16450, or 16550(A).
|
||||
*/
|
||||
|
||||
#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
|
||||
#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
|
||||
#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
|
||||
#define UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */
|
||||
#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
|
||||
#define UART_IIR 2 /* In: Interrupt Identity Register */
|
||||
#define UART_FCR 2 /* Out: FIFO Control Register */
|
||||
#define UART_LCR 3 /* Out: Line Control Register */
|
||||
#define UART_MCR 4 /* Out: Modem Control Register */
|
||||
#define UART_LSR 5 /* In: Line Status Register */
|
||||
#define UART_MSR 6 /* In: Modem Status Register */
|
||||
#define UART_SCR 7 /* I/O: Scratch Register */
|
||||
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
|
||||
#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
|
||||
#define UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */
|
||||
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
|
||||
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
|
||||
#define UART_LSR_RXRDY 0x01 /* Receiver ready */
|
||||
#define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */
|
||||
|
||||
/* Interrupt Identity Register (IIR) bits */
|
||||
#define UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */
|
||||
#define UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */
|
||||
#define UART_IIR_MDM_CHG 0x0 /* Modem status changed */
|
||||
#define UART_IIR_NOINT 0x1 /* No interrupt pending */
|
||||
#define UART_IIR_THRE 0x2 /* THR empty */
|
||||
#define UART_IIR_RCVD_DATA 0x4 /* Received data available */
|
||||
#define UART_IIR_RCVR_STATUS 0x6 /* Receiver status */
|
||||
#define UART_IIR_CHAR_TIME 0xc /* Character time */
|
||||
|
||||
/* Interrupt Enable Register (IER) bits */
|
||||
#define UART_IER_EDSSI 8 /* enable modem status interrupt */
|
||||
#define UART_IER_ELSI 4 /* enable receiver line status interrupt */
|
||||
#define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */
|
||||
#define UART_IER_ERBFI 1 /* enable data available interrupt */
|
||||
|
||||
/* pmustatus */
|
||||
#define PST_INTPEND 0x0040
|
||||
#define PST_SBCLKST 0x0030
|
||||
#define PST_ALPAVAIL 0x0008
|
||||
#define PST_HTAVAIL 0x0004
|
||||
#define PST_RESINIT 0x0003
|
||||
|
||||
/* pmucapabilities */
|
||||
#define PCAP_REV_MASK 0x000000ff
|
||||
|
||||
/* PMU Resource Request Timer registers */
|
||||
/* This is based on PmuRev0 */
|
||||
#define PRRT_TIME_MASK 0x03ff
|
||||
#define PRRT_INTEN 0x0400
|
||||
#define PRRT_REQ_ACTIVE 0x0800
|
||||
#define PRRT_ALP_REQ 0x1000
|
||||
#define PRRT_HT_REQ 0x2000
|
||||
|
||||
/* PMU resource bit position */
|
||||
#define PMURES_BIT(bit) (1 << (bit))
|
||||
|
||||
/* PMU corerev and chip specific PLL controls.
|
||||
* PMU<rev>_PLL<num>_XXXX where <rev> is PMU corerev and <num> is an arbitary number
|
||||
* to differentiate different PLLs controlled by the same PMU rev.
|
||||
*/
|
||||
/* pllcontrol registers */
|
||||
/* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */
|
||||
#define PMU0_PLL0_PLLCTL0 0
|
||||
#define PMU0_PLL0_PC0_PDIV_MASK 1
|
||||
#define PMU0_PLL0_PC0_PDIV_FREQ 25000
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_BASE 8
|
||||
|
||||
/* PC0_DIV_ARM for PLLOUT_ARM */
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7
|
||||
|
||||
/* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */
|
||||
#define PMU0_PLL0_PLLCTL1 1
|
||||
#define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000
|
||||
#define PMU0_PLL0_PC1_WILD_INT_SHIFT 28
|
||||
#define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00
|
||||
#define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8
|
||||
#define PMU0_PLL0_PC1_STOP_MOD 0x00000040
|
||||
|
||||
/* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */
|
||||
#define PMU0_PLL0_PLLCTL2 2
|
||||
#define PMU0_PLL0_PC2_WILD_INT_MASK 0xf
|
||||
#define PMU0_PLL0_PC2_WILD_INT_SHIFT 4
|
||||
|
||||
/* Chip specific PMU resources. */
|
||||
#define RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */
|
||||
#define RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */
|
||||
#define RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */
|
||||
#define RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */
|
||||
#define RES4328_ILP_REQUEST 4 /* 0x00010 */
|
||||
#define RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */
|
||||
#define RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */
|
||||
#define RES4328_ROM_SWITCH 7 /* 0x00080 */
|
||||
#define RES4328_PA_REF_LDO 8 /* 0x00100 */
|
||||
#define RES4328_RADIO_LDO 9 /* 0x00200 */
|
||||
#define RES4328_AFE_LDO 10 /* 0x00400 */
|
||||
#define RES4328_PLL_LDO 11 /* 0x00800 */
|
||||
#define RES4328_BG_FILTBYP 12 /* 0x01000 */
|
||||
#define RES4328_TX_FILTBYP 13 /* 0x02000 */
|
||||
#define RES4328_RX_FILTBYP 14 /* 0x04000 */
|
||||
#define RES4328_XTAL_PU 15 /* 0x08000 */
|
||||
#define RES4328_XTAL_EN 16 /* 0x10000 */
|
||||
#define RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */
|
||||
#define RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */
|
||||
#define RES4328_BB_PLL_PU 19 /* 0x80000 */
|
||||
|
||||
#define RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */
|
||||
#define RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */
|
||||
#define RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */
|
||||
#define RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */
|
||||
#define RES5354_ILP_REQUEST 4 /* 0x00010 */
|
||||
#define RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */
|
||||
#define RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */
|
||||
#define RES5354_ROM_SWITCH 7 /* 0x00080 */
|
||||
#define RES5354_PA_REF_LDO 8 /* 0x00100 */
|
||||
#define RES5354_RADIO_LDO 9 /* 0x00200 */
|
||||
#define RES5354_AFE_LDO 10 /* 0x00400 */
|
||||
#define RES5354_PLL_LDO 11 /* 0x00800 */
|
||||
#define RES5354_BG_FILTBYP 12 /* 0x01000 */
|
||||
#define RES5354_TX_FILTBYP 13 /* 0x02000 */
|
||||
#define RES5354_RX_FILTBYP 14 /* 0x04000 */
|
||||
#define RES5354_XTAL_PU 15 /* 0x08000 */
|
||||
#define RES5354_XTAL_EN 16 /* 0x10000 */
|
||||
#define RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */
|
||||
#define RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */
|
||||
#define RES5354_BB_PLL_PU 19 /* 0x80000 */
|
||||
|
||||
/* pllcontrol registers */
|
||||
/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypsss_sdmod */
|
||||
#define PMU1_PLL0_PLLCTL0 0
|
||||
#define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
|
||||
#define PMU1_PLL0_PC0_P1DIV_SHIFT 20
|
||||
#define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000
|
||||
#define PMU1_PLL0_PC0_P2DIV_SHIFT 24
|
||||
|
||||
/* m<x>div */
|
||||
#define PMU1_PLL0_PLLCTL1 1
|
||||
#define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff
|
||||
#define PMU1_PLL0_PC1_M1DIV_SHIFT 0
|
||||
#define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00
|
||||
#define PMU1_PLL0_PC1_M2DIV_SHIFT 8
|
||||
#define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000
|
||||
#define PMU1_PLL0_PC1_M3DIV_SHIFT 16
|
||||
#define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000
|
||||
#define PMU1_PLL0_PC1_M4DIV_SHIFT 24
|
||||
|
||||
/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
|
||||
#define PMU1_PLL0_PLLCTL2 2
|
||||
#define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff
|
||||
#define PMU1_PLL0_PC2_M5DIV_SHIFT 0
|
||||
#define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00
|
||||
#define PMU1_PLL0_PC2_M6DIV_SHIFT 8
|
||||
#define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000
|
||||
#define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17
|
||||
#define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
|
||||
#define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
|
||||
|
||||
/* ndiv_frac */
|
||||
#define PMU1_PLL0_PLLCTL3 3
|
||||
#define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff
|
||||
#define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0
|
||||
|
||||
/* pll_ctrl */
|
||||
#define PMU1_PLL0_PLLCTL4 4
|
||||
|
||||
/* pll_ctrl, vco_rng, clkdrive_ch<x> */
|
||||
#define PMU1_PLL0_PLLCTL5 5
|
||||
#define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00
|
||||
#define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8
|
||||
|
||||
#define RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */
|
||||
#define RES4325_CBUCK_BURST 1 /* 0x00000002 */
|
||||
#define RES4325_CBUCK_PWM 2 /* 0x00000004 */
|
||||
#define RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */
|
||||
#define RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */
|
||||
#define RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */
|
||||
#define RES4325_ILP_REQUEST 6 /* 0x00000040 */
|
||||
#define RES4325_ABUCK_BURST 7 /* 0x00000080 */
|
||||
#define RES4325_ABUCK_PWM 8 /* 0x00000100 */
|
||||
#define RES4325_LNLDO1_PU 9 /* 0x00000200 */
|
||||
#define RES4325_LNLDO2_PU 10 /* 0x00000400 */
|
||||
#define RES4325_LNLDO3_PU 11 /* 0x00000800 */
|
||||
#define RES4325_LNLDO4_PU 12 /* 0x00001000 */
|
||||
#define RES4325_XTAL_PU 13 /* 0x00002000 */
|
||||
#define RES4325_ALP_AVAIL 14 /* 0x00004000 */
|
||||
#define RES4325_RX_PWRSW_PU 15 /* 0x00008000 */
|
||||
#define RES4325_TX_PWRSW_PU 16 /* 0x00010000 */
|
||||
#define RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */
|
||||
#define RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */
|
||||
#define RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */
|
||||
#define RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */
|
||||
#define RES4325_HT_AVAIL 21 /* 0x00200000 */
|
||||
|
||||
/* Chip specific ChipStatus register bits */
|
||||
#define CST4325_SPROM_OTP_SEL_MASK 0x00000003
|
||||
#define CST4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
|
||||
#define CST4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
|
||||
#define CST4325_OTP_SEL 2 /* OTP is powered up, no SPROM */
|
||||
#define CST4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
|
||||
#define CST4325_SDIO_USB_MODE_MASK 0x00000004
|
||||
#define CST4325_SDIO_USB_MODE_SHIFT 2
|
||||
#define CST4325_RCAL_VALID_MASK 0x00000008
|
||||
#define CST4325_RCAL_VALID_SHIFT 3
|
||||
#define CST4325_RCAL_VALUE_MASK 0x000001f0
|
||||
#define CST4325_RCAL_VALUE_SHIFT 4
|
||||
#define CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */
|
||||
#define CST4325_PMUTOP_2B_SHIFT 9
|
||||
|
||||
#define RES4312_SWITCHER_BURST 0 /* 0x00000001 */
|
||||
#define RES4312_SWITCHER_PWM 1 /* 0x00000002 */
|
||||
#define RES4312_PA_REF_LDO 2 /* 0x00000004 */
|
||||
#define RES4312_CORE_LDO_BURST 3 /* 0x00000008 */
|
||||
#define RES4312_CORE_LDO_PWM 4 /* 0x00000010 */
|
||||
#define RES4312_RADIO_LDO 5 /* 0x00000020 */
|
||||
#define RES4312_ILP_REQUEST 6 /* 0x00000040 */
|
||||
#define RES4312_BG_FILTBYP 7 /* 0x00000080 */
|
||||
#define RES4312_TX_FILTBYP 8 /* 0x00000100 */
|
||||
#define RES4312_RX_FILTBYP 9 /* 0x00000200 */
|
||||
#define RES4312_XTAL_PU 10 /* 0x00000400 */
|
||||
#define RES4312_ALP_AVAIL 11 /* 0x00000800 */
|
||||
#define RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */
|
||||
#define RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */
|
||||
#define RES4312_HT_AVAIL 14 /* 0x00004000 */
|
||||
|
||||
/*
|
||||
* Maximum delay for the PMU state transition.
|
||||
* This is an upper bound intended for spinwaits etc.
|
||||
*/
|
||||
#define PMU_MAX_TRANSITION_DLY 15000
|
||||
|
||||
#endif /* _SBCHIPC_H */
|
||||
|
|
@ -1,389 +0,0 @@
|
|||
/*
|
||||
* Broadcom SiliconBackplane hardware register definitions.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SBCONFIG_H
|
||||
#define _SBCONFIG_H
|
||||
#include "linuxver.h"
|
||||
|
||||
/* cpp contortions to concatenate w/arg prescan */
|
||||
#ifndef PAD
|
||||
#define _PADLINE(line) pad ## line
|
||||
#define _XSTR(line) _PADLINE(line)
|
||||
#define PAD _XSTR(__LINE__)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SiliconBackplane Address Map.
|
||||
* All regions may not exist on all chips.
|
||||
*/
|
||||
#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
|
||||
#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
|
||||
#define SB_PCI_MEM_SZ (64 * 1024 * 1024)
|
||||
#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
|
||||
#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
|
||||
#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
|
||||
#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
|
||||
|
||||
#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
|
||||
#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
|
||||
#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
|
||||
#define SB_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
|
||||
#define SB_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
|
||||
#define SB_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
|
||||
#define SB_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
|
||||
#define SB_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */
|
||||
#define SB_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */
|
||||
#define SB_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
|
||||
#define SB_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
|
||||
|
||||
#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
|
||||
#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
|
||||
#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2
|
||||
* (2 ZettaBytes), low 32 bits
|
||||
*/
|
||||
#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2
|
||||
* (2 ZettaBytes), high 32 bits
|
||||
*/
|
||||
#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
|
||||
#define SB_LED (SB_EXTIF_BASE + 0x00900000)
|
||||
|
||||
|
||||
/* enumeration space related defs */
|
||||
#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
|
||||
#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
|
||||
#define SB_MAXFUNCS 4 /* max. # functions per core */
|
||||
#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
|
||||
#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
|
||||
|
||||
/* mips address */
|
||||
#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
|
||||
|
||||
/*
|
||||
* Sonics Configuration Space Registers.
|
||||
*/
|
||||
#define SBIPSFLAG 0x08
|
||||
#define SBTPSFLAG 0x18
|
||||
#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
|
||||
#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
|
||||
#define SBADMATCH3 0x60
|
||||
#define SBADMATCH2 0x68
|
||||
#define SBADMATCH1 0x70
|
||||
#define SBIMSTATE 0x90
|
||||
#define SBINTVEC 0x94
|
||||
#define SBTMSTATELOW 0x98
|
||||
#define SBTMSTATEHIGH 0x9c
|
||||
#define SBBWA0 0xa0
|
||||
#define SBIMCONFIGLOW 0xa8
|
||||
#define SBIMCONFIGHIGH 0xac
|
||||
#define SBADMATCH0 0xb0
|
||||
#define SBTMCONFIGLOW 0xb8
|
||||
#define SBTMCONFIGHIGH 0xbc
|
||||
#define SBBCONFIG 0xc0
|
||||
#define SBBSTATE 0xc8
|
||||
#define SBACTCNFG 0xd8
|
||||
#define SBFLAGST 0xe8
|
||||
#define SBIDLOW 0xf8
|
||||
#define SBIDHIGH 0xfc
|
||||
|
||||
/* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have
|
||||
* a few registers *below* that line. I think it would be very confusing to try
|
||||
* and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here,
|
||||
*/
|
||||
|
||||
#define SBIMERRLOGA 0xea8
|
||||
#define SBIMERRLOG 0xeb0
|
||||
#define SBTMPORTCONNID0 0xed8
|
||||
#define SBTMPORTLOCK0 0xef8
|
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY
|
||||
|
||||
typedef volatile struct _sbconfig {
|
||||
uint32 PAD[2];
|
||||
uint32 sbipsflag; /* initiator port ocp slave flag */
|
||||
uint32 PAD[3];
|
||||
uint32 sbtpsflag; /* target port ocp slave flag */
|
||||
uint32 PAD[11];
|
||||
uint32 sbtmerrloga; /* (sonics >= 2.3) */
|
||||
uint32 PAD;
|
||||
uint32 sbtmerrlog; /* (sonics >= 2.3) */
|
||||
uint32 PAD[3];
|
||||
uint32 sbadmatch3; /* address match3 */
|
||||
uint32 PAD;
|
||||
uint32 sbadmatch2; /* address match2 */
|
||||
uint32 PAD;
|
||||
uint32 sbadmatch1; /* address match1 */
|
||||
uint32 PAD[7];
|
||||
uint32 sbimstate; /* initiator agent state */
|
||||
uint32 sbintvec; /* interrupt mask */
|
||||
uint32 sbtmstatelow; /* target state */
|
||||
uint32 sbtmstatehigh; /* target state */
|
||||
uint32 sbbwa0; /* bandwidth allocation table0 */
|
||||
uint32 PAD;
|
||||
uint32 sbimconfiglow; /* initiator configuration */
|
||||
uint32 sbimconfighigh; /* initiator configuration */
|
||||
uint32 sbadmatch0; /* address match0 */
|
||||
uint32 PAD;
|
||||
uint32 sbtmconfiglow; /* target configuration */
|
||||
uint32 sbtmconfighigh; /* target configuration */
|
||||
uint32 sbbconfig; /* broadcast configuration */
|
||||
uint32 PAD;
|
||||
uint32 sbbstate; /* broadcast state */
|
||||
uint32 PAD[3];
|
||||
uint32 sbactcnfg; /* activate configuration */
|
||||
uint32 PAD[3];
|
||||
uint32 sbflagst; /* current sbflags */
|
||||
uint32 PAD[3];
|
||||
uint32 sbidlow; /* identification */
|
||||
uint32 sbidhigh; /* identification */
|
||||
} sbconfig_t;
|
||||
|
||||
#endif /* _LANGUAGE_ASSEMBLY */
|
||||
|
||||
/* sbipsflag */
|
||||
#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
|
||||
#define SBIPS_INT1_SHIFT 0
|
||||
#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
|
||||
#define SBIPS_INT2_SHIFT 8
|
||||
#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
|
||||
#define SBIPS_INT3_SHIFT 16
|
||||
#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
|
||||
#define SBIPS_INT4_SHIFT 24
|
||||
|
||||
/* sbtpsflag */
|
||||
#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
|
||||
#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
|
||||
|
||||
/* sbtmerrlog */
|
||||
#define SBTMEL_CM 0x00000007 /* command */
|
||||
#define SBTMEL_CI 0x0000ff00 /* connection id */
|
||||
#define SBTMEL_EC 0x0f000000 /* error code */
|
||||
#define SBTMEL_ME 0x80000000 /* multiple error */
|
||||
|
||||
/* sbimstate */
|
||||
#define SBIM_PC 0xf /* pipecount */
|
||||
#define SBIM_AP_MASK 0x30 /* arbitration policy */
|
||||
#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
|
||||
#define SBIM_AP_TS 0x10 /* use timesliaces only */
|
||||
#define SBIM_AP_TK 0x20 /* use token only */
|
||||
#define SBIM_AP_RSV 0x30 /* reserved */
|
||||
#define SBIM_IBE 0x20000 /* inbanderror */
|
||||
#define SBIM_TO 0x40000 /* timeout */
|
||||
#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
|
||||
#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
|
||||
|
||||
/* sbtmstatelow */
|
||||
#define SBTML_RESET 0x1 /* reset */
|
||||
#define SBTML_REJ_MASK 0x6 /* reject */
|
||||
#define SBTML_REJ_SHIFT 1
|
||||
#define SBTML_CLK 0x10000 /* clock enable */
|
||||
#define SBTML_FGC 0x20000 /* force gated clocks on */
|
||||
#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
|
||||
#define SBTML_PE 0x40000000 /* pme enable */
|
||||
#define SBTML_BE 0x80000000 /* bist enable */
|
||||
|
||||
/* sbtmstatehigh */
|
||||
#define SBTMH_SERR 0x1 /* serror */
|
||||
#define SBTMH_INT 0x2 /* interrupt */
|
||||
#define SBTMH_BUSY 0x4 /* busy */
|
||||
#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
|
||||
#define SBTMH_FL_MASK 0x0fff0000 /* core-specific flags */
|
||||
#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
|
||||
#define SBTMH_GCR 0x20000000 /* gated clock request */
|
||||
#define SBTMH_BISTF 0x40000000 /* bist failed */
|
||||
#define SBTMH_BISTD 0x80000000 /* bist done */
|
||||
|
||||
|
||||
/* sbbwa0 */
|
||||
#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
|
||||
#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
|
||||
#define SBBWA_TAB1_SHIFT 16
|
||||
|
||||
/* sbimconfiglow */
|
||||
#define SBIMCL_STO_MASK 0x7 /* service timeout */
|
||||
#define SBIMCL_RTO_MASK 0x70 /* request timeout */
|
||||
#define SBIMCL_RTO_SHIFT 4
|
||||
#define SBIMCL_CID_MASK 0xff0000 /* connection id */
|
||||
#define SBIMCL_CID_SHIFT 16
|
||||
|
||||
/* sbimconfighigh */
|
||||
#define SBIMCH_IEM_MASK 0xc /* inband error mode */
|
||||
#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
|
||||
#define SBIMCH_TEM_SHIFT 4
|
||||
#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
|
||||
#define SBIMCH_BEM_SHIFT 6
|
||||
|
||||
/* sbadmatch0 */
|
||||
#define SBAM_TYPE_MASK 0x3 /* address type */
|
||||
#define SBAM_AD64 0x4 /* reserved */
|
||||
#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
|
||||
#define SBAM_ADINT0_SHIFT 3
|
||||
#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
|
||||
#define SBAM_ADINT1_SHIFT 3
|
||||
#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
|
||||
#define SBAM_ADINT2_SHIFT 3
|
||||
#define SBAM_ADEN 0x400 /* enable */
|
||||
#define SBAM_ADNEG 0x800 /* negative decode */
|
||||
#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
|
||||
#define SBAM_BASE0_SHIFT 8
|
||||
#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
|
||||
#define SBAM_BASE1_SHIFT 12
|
||||
#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
|
||||
#define SBAM_BASE2_SHIFT 16
|
||||
|
||||
/* sbtmconfiglow */
|
||||
#define SBTMCL_CD_MASK 0xff /* clock divide */
|
||||
#define SBTMCL_CO_MASK 0xf800 /* clock offset */
|
||||
#define SBTMCL_CO_SHIFT 11
|
||||
#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
|
||||
#define SBTMCL_IF_SHIFT 18
|
||||
#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
|
||||
#define SBTMCL_IM_SHIFT 24
|
||||
|
||||
/* sbtmconfighigh */
|
||||
#define SBTMCH_BM_MASK 0x3 /* busy mode */
|
||||
#define SBTMCH_RM_MASK 0x3 /* retry mode */
|
||||
#define SBTMCH_RM_SHIFT 2
|
||||
#define SBTMCH_SM_MASK 0x30 /* stop mode */
|
||||
#define SBTMCH_SM_SHIFT 4
|
||||
#define SBTMCH_EM_MASK 0x300 /* sb error mode */
|
||||
#define SBTMCH_EM_SHIFT 8
|
||||
#define SBTMCH_IM_MASK 0xc00 /* int mode */
|
||||
#define SBTMCH_IM_SHIFT 10
|
||||
|
||||
/* sbbconfig */
|
||||
#define SBBC_LAT_MASK 0x3 /* sb latency */
|
||||
#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
|
||||
#define SBBC_MAX0_SHIFT 16
|
||||
#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
|
||||
#define SBBC_MAX1_SHIFT 20
|
||||
|
||||
/* sbbstate */
|
||||
#define SBBS_SRD 0x1 /* st reg disable */
|
||||
#define SBBS_HRD 0x2 /* hold reg disable */
|
||||
|
||||
/* sbidlow */
|
||||
#define SBIDL_CS_MASK 0x3 /* config space */
|
||||
#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
|
||||
#define SBIDL_AR_SHIFT 3
|
||||
#define SBIDL_SYNCH 0x40 /* sync */
|
||||
#define SBIDL_INIT 0x80 /* initiator */
|
||||
#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
|
||||
#define SBIDL_MINLAT_SHIFT 8
|
||||
#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
|
||||
#define SBIDL_MAXLAT_SHIFT 12
|
||||
#define SBIDL_FIRST 0x10000 /* this initiator is first */
|
||||
#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
|
||||
#define SBIDL_CW_SHIFT 18
|
||||
#define SBIDL_TP_MASK 0xf00000 /* target ports */
|
||||
#define SBIDL_TP_SHIFT 20
|
||||
#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
|
||||
#define SBIDL_IP_SHIFT 24
|
||||
#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
|
||||
#define SBIDL_RV_SHIFT 28
|
||||
#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
|
||||
#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
|
||||
|
||||
/* sbidhigh */
|
||||
#define SBIDH_RC_MASK 0x000f /* revision code */
|
||||
#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
|
||||
#define SBIDH_RCE_SHIFT 8
|
||||
#define SBCOREREV(sbidh) \
|
||||
((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
|
||||
#define SBIDH_CC_MASK 0x8ff0 /* core code */
|
||||
#define SBIDH_CC_SHIFT 4
|
||||
#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
|
||||
#define SBIDH_VC_SHIFT 16
|
||||
|
||||
#define SB_COMMIT 0xfd8 /* update buffered registers value */
|
||||
|
||||
/* vendor codes */
|
||||
#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
|
||||
|
||||
/* core codes */
|
||||
#define SB_NODEV 0x700 /* Invalid coreid */
|
||||
#define SB_CC 0x800 /* chipcommon core */
|
||||
#define SB_ILINE20 0x801 /* iline20 core */
|
||||
#define SB_SDRAM 0x803 /* sdram core */
|
||||
#define SB_PCI 0x804 /* pci core */
|
||||
#define SB_MIPS 0x805 /* mips core */
|
||||
#define SB_ENET 0x806 /* enet mac core */
|
||||
#define SB_CODEC 0x807 /* v90 codec core */
|
||||
#define SB_USB 0x808 /* usb 1.1 host/device core */
|
||||
#define SB_ADSL 0x809 /* ADSL core */
|
||||
#define SB_ILINE100 0x80a /* iline100 core */
|
||||
#define SB_IPSEC 0x80b /* ipsec core */
|
||||
#define SB_PCMCIA 0x80d /* pcmcia core */
|
||||
#define SB_SOCRAM 0x80e /* internal memory core */
|
||||
#define SB_MEMC 0x80f /* memc sdram core */
|
||||
#define SB_EXTIF 0x811 /* external interface core */
|
||||
#define SB_D11 0x812 /* 802.11 MAC core */
|
||||
#define SB_MIPS33 0x816 /* mips3302 core */
|
||||
#define SB_USB11H 0x817 /* usb 1.1 host core */
|
||||
#define SB_USB11D 0x818 /* usb 1.1 device core */
|
||||
#define SB_USB20H 0x819 /* usb 2.0 host core */
|
||||
#define SB_USB20D 0x81a /* usb 2.0 device core */
|
||||
#define SB_SDIOH 0x81b /* sdio host core */
|
||||
#define SB_ROBO 0x81c /* roboswitch core */
|
||||
#define SB_ATA100 0x81d /* parallel ATA core */
|
||||
#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
|
||||
#define SB_GIGETH 0x81f /* gigabit ethernet core */
|
||||
#define SB_PCIE 0x820 /* pci express core */
|
||||
#define SB_MIMO 0x821 /* MIMO phy core */
|
||||
#define SB_SRAMC 0x822 /* SRAM controller core */
|
||||
#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
|
||||
#define SB_ARM7S 0x825 /* ARM7tdmi-s core */
|
||||
#define SB_SDIOD 0x829 /* SDIO device core */
|
||||
#define SB_ARMCM3 0x82a /* ARM Cortex M3 core */
|
||||
#define SB_OCP 0x830 /* OCP2OCP bridge core */
|
||||
#define SB_SC 0x831 /* shared common core */
|
||||
#define SB_AHB 0x832 /* OCP2AHB bridge core */
|
||||
|
||||
#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
|
||||
|
||||
/* Not an enumeration space register, but common to all cores to
|
||||
* communicate w/PMU regarding Silicon Backplane clocking.
|
||||
*/
|
||||
#define SB_CLK_CTL_ST 0x1e0 /* clock control and status */
|
||||
|
||||
/* clk_ctl_st register */
|
||||
#define CCS_FORCEALP 0x00000001 /* force ALP request */
|
||||
#define CCS_FORCEHT 0x00000002 /* force HT request */
|
||||
#define CCS_FORCEILP 0x00000004 /* force ILP request */
|
||||
#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
|
||||
#define CCS_HTAREQ 0x00000010 /* HT Avail Request */
|
||||
#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
|
||||
#define CCS_ALPAVAIL 0x00010000 /* ALP is available */
|
||||
#define CCS_HTAVAIL 0x00020000 /* HT is available */
|
||||
#define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */
|
||||
#define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */
|
||||
|
||||
/* Not really related to Silicon Backplane, but a couple of software
|
||||
* conventions for the use the flash space:
|
||||
*/
|
||||
|
||||
/* Minumum amount of flash we support */
|
||||
#define FLASH_MIN 0x00020000 /* Minimum flash size */
|
||||
|
||||
/* A boot/binary may have an embedded block that describes its size */
|
||||
#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
|
||||
#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
|
||||
#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
|
||||
#define BISZ_TXTST_IDX 1 /* 1: text start */
|
||||
#define BISZ_TXTEND_IDX 2 /* 2: text end */
|
||||
#define BISZ_DATAST_IDX 3 /* 3: data start */
|
||||
#define BISZ_DATAEND_IDX 4 /* 4: data end */
|
||||
#define BISZ_BSSST_IDX 5 /* 5: bss start */
|
||||
#define BISZ_BSSEND_IDX 6 /* 6: bss end */
|
||||
#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
|
||||
|
||||
#endif /* _SBCONFIG_H */
|
||||
|
|
@ -1,233 +0,0 @@
|
|||
/*
|
||||
* Hardware-specific External Interface I/O core definitions
|
||||
* for the BCM47xx family of SiliconBackplane-based chips.
|
||||
*
|
||||
* The External Interface core supports a total of three external chip selects
|
||||
* supporting external interfaces. One of the external chip selects is
|
||||
* used for Flash, one is used for PCMCIA, and the other may be
|
||||
* programmed to support either a synchronous interface or an
|
||||
* asynchronous interface. The asynchronous interface can be used to
|
||||
* support external devices such as UARTs and the BCM2019 Bluetooth
|
||||
* baseband processor.
|
||||
* The external interface core also contains 2 on-chip 16550 UARTs, clock
|
||||
* frequency control, a watchdog interrupt timer, and a GPIO interface.
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SBEXTIF_H
|
||||
#define _SBEXTIF_H
|
||||
|
||||
/* external interface address space */
|
||||
#define EXTIF_PCMCIA_MEMBASE(x) (x)
|
||||
#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
|
||||
#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
|
||||
#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
|
||||
#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
|
||||
|
||||
/* cpp contortions to concatenate w/arg prescan */
|
||||
#ifndef PAD
|
||||
#define _PADLINE(line) pad ## line
|
||||
#define _XSTR(line) _PADLINE(line)
|
||||
#define PAD _XSTR(__LINE__)
|
||||
#endif /* PAD */
|
||||
|
||||
/*
|
||||
* The multiple instances of output and output enable registers
|
||||
* are present to allow driver software for multiple cores to control
|
||||
* gpio outputs without needing to share a single register pair.
|
||||
*/
|
||||
struct gpiouser {
|
||||
uint32 out;
|
||||
uint32 outen;
|
||||
};
|
||||
#define NGPIOUSER 5
|
||||
|
||||
typedef volatile struct {
|
||||
uint32 corecontrol;
|
||||
uint32 extstatus;
|
||||
uint32 PAD[2];
|
||||
|
||||
/* pcmcia control registers */
|
||||
uint32 pcmcia_config;
|
||||
uint32 pcmcia_memwait;
|
||||
uint32 pcmcia_attrwait;
|
||||
uint32 pcmcia_iowait;
|
||||
|
||||
/* programmable interface control registers */
|
||||
uint32 prog_config;
|
||||
uint32 prog_waitcount;
|
||||
|
||||
/* flash control registers */
|
||||
uint32 flash_config;
|
||||
uint32 flash_waitcount;
|
||||
uint32 PAD[4];
|
||||
|
||||
uint32 watchdog;
|
||||
|
||||
/* clock control */
|
||||
uint32 clockcontrol_n;
|
||||
uint32 clockcontrol_sb;
|
||||
uint32 clockcontrol_pci;
|
||||
uint32 clockcontrol_mii;
|
||||
uint32 PAD[3];
|
||||
|
||||
/* gpio */
|
||||
uint32 gpioin;
|
||||
struct gpiouser gpio[NGPIOUSER];
|
||||
uint32 PAD;
|
||||
uint32 ejtagouten;
|
||||
uint32 gpiointpolarity;
|
||||
uint32 gpiointmask;
|
||||
uint32 PAD[153];
|
||||
|
||||
uint8 uartdata;
|
||||
uint8 PAD[3];
|
||||
uint8 uartimer;
|
||||
uint8 PAD[3];
|
||||
uint8 uartfcr;
|
||||
uint8 PAD[3];
|
||||
uint8 uartlcr;
|
||||
uint8 PAD[3];
|
||||
uint8 uartmcr;
|
||||
uint8 PAD[3];
|
||||
uint8 uartlsr;
|
||||
uint8 PAD[3];
|
||||
uint8 uartmsr;
|
||||
uint8 PAD[3];
|
||||
uint8 uartscratch;
|
||||
uint8 PAD[3];
|
||||
} extifregs_t;
|
||||
|
||||
/* corecontrol */
|
||||
#define CC_UE (1 << 0) /* uart enable */
|
||||
|
||||
/* extstatus */
|
||||
#define ES_EM (1 << 0) /* endian mode (ro) */
|
||||
#define ES_EI (1 << 1) /* external interrupt pin (ro) */
|
||||
#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
|
||||
|
||||
/* gpio bit mask */
|
||||
#define GPIO_BIT0 (1 << 0)
|
||||
#define GPIO_BIT1 (1 << 1)
|
||||
#define GPIO_BIT2 (1 << 2)
|
||||
#define GPIO_BIT3 (1 << 3)
|
||||
#define GPIO_BIT4 (1 << 4)
|
||||
#define GPIO_BIT5 (1 << 5)
|
||||
#define GPIO_BIT6 (1 << 6)
|
||||
#define GPIO_BIT7 (1 << 7)
|
||||
|
||||
|
||||
/* pcmcia/prog/flash_config */
|
||||
#define CF_EN (1 << 0) /* enable */
|
||||
#define CF_EM_MASK 0xe /* mode */
|
||||
#define CF_EM_SHIFT 1
|
||||
#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
|
||||
#define CF_EM_SYNC 0x2 /* synchronous mode */
|
||||
#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
|
||||
#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
|
||||
#define CF_BS (1 << 5) /* byteswap */
|
||||
#define CF_CD_MASK 0xc0 /* clock divider */
|
||||
#define CF_CD_SHIFT 6
|
||||
#define CF_CD_DIV2 0x0 /* backplane/2 */
|
||||
#define CF_CD_DIV3 0x40 /* backplane/3 */
|
||||
#define CF_CD_DIV4 0x80 /* backplane/4 */
|
||||
#define CF_CE (1 << 8) /* clock enable */
|
||||
#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
|
||||
|
||||
/* pcmcia_memwait */
|
||||
#define PM_W0_MASK 0x3f /* waitcount0 */
|
||||
#define PM_W1_MASK 0x1f00 /* waitcount1 */
|
||||
#define PM_W1_SHIFT 8
|
||||
#define PM_W2_MASK 0x1f0000 /* waitcount2 */
|
||||
#define PM_W2_SHIFT 16
|
||||
#define PM_W3_MASK 0x1f000000 /* waitcount3 */
|
||||
#define PM_W3_SHIFT 24
|
||||
|
||||
/* pcmcia_attrwait */
|
||||
#define PA_W0_MASK 0x3f /* waitcount0 */
|
||||
#define PA_W1_MASK 0x1f00 /* waitcount1 */
|
||||
#define PA_W1_SHIFT 8
|
||||
#define PA_W2_MASK 0x1f0000 /* waitcount2 */
|
||||
#define PA_W2_SHIFT 16
|
||||
#define PA_W3_MASK 0x1f000000 /* waitcount3 */
|
||||
#define PA_W3_SHIFT 24
|
||||
|
||||
/* prog_waitcount */
|
||||
#define PW_W0_MASK 0x0000001f /* waitcount0 */
|
||||
#define PW_W1_MASK 0x00001f00 /* waitcount1 */
|
||||
#define PW_W1_SHIFT 8
|
||||
#define PW_W2_MASK 0x001f0000 /* waitcount2 */
|
||||
#define PW_W2_SHIFT 16
|
||||
#define PW_W3_MASK 0x1f000000 /* waitcount3 */
|
||||
#define PW_W3_SHIFT 24
|
||||
|
||||
#define PW_W0 0x0000000c
|
||||
#define PW_W1 0x00000a00
|
||||
#define PW_W2 0x00020000
|
||||
#define PW_W3 0x01000000
|
||||
|
||||
/* flash_waitcount */
|
||||
#define FW_W0_MASK 0x1f /* waitcount0 */
|
||||
#define FW_W1_MASK 0x1f00 /* waitcount1 */
|
||||
#define FW_W1_SHIFT 8
|
||||
#define FW_W2_MASK 0x1f0000 /* waitcount2 */
|
||||
#define FW_W2_SHIFT 16
|
||||
#define FW_W3_MASK 0x1f000000 /* waitcount3 */
|
||||
#define FW_W3_SHIFT 24
|
||||
|
||||
/* watchdog */
|
||||
#define WATCHDOG_CLOCK 48000000 /* Hz */
|
||||
|
||||
/* clockcontrol_n */
|
||||
#define CN_N1_MASK 0x3f /* n1 control */
|
||||
#define CN_N2_MASK 0x3f00 /* n2 control */
|
||||
#define CN_N2_SHIFT 8
|
||||
|
||||
/* clockcontrol_sb/pci/mii */
|
||||
#define CC_M1_MASK 0x3f /* m1 control */
|
||||
#define CC_M2_MASK 0x3f00 /* m2 control */
|
||||
#define CC_M2_SHIFT 8
|
||||
#define CC_M3_MASK 0x3f0000 /* m3 control */
|
||||
#define CC_M3_SHIFT 16
|
||||
#define CC_MC_MASK 0x1f000000 /* mux control */
|
||||
#define CC_MC_SHIFT 24
|
||||
|
||||
/* Clock control default values */
|
||||
#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
|
||||
#define CC_DEF_100 0x04020011
|
||||
#define CC_DEF_33 0x11030011
|
||||
#define CC_DEF_25 0x11050011
|
||||
|
||||
/* Clock control values for 125Mhz */
|
||||
#define CC_125_N 0x0802
|
||||
#define CC_125_M 0x04020009
|
||||
#define CC_125_M25 0x11090009
|
||||
#define CC_125_M33 0x11090005
|
||||
|
||||
/* Clock control magic field values */
|
||||
#define CC_F6_2 0x02 /* A factor of 2 in */
|
||||
#define CC_F6_3 0x03 /* 6-bit fields like */
|
||||
#define CC_F6_4 0x05 /* N1, M1 or M3 */
|
||||
#define CC_F6_5 0x09
|
||||
#define CC_F6_6 0x11
|
||||
#define CC_F6_7 0x21
|
||||
|
||||
#define CC_F5_BIAS 5 /* 5-bit fields get this added */
|
||||
|
||||
#define CC_MC_BYPASS 0x08
|
||||
#define CC_MC_M1 0x04
|
||||
#define CC_MC_M1M2 0x02
|
||||
#define CC_MC_M1M2M3 0x01
|
||||
#define CC_MC_M1M3 0x11
|
||||
|
||||
#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
|
||||
|
||||
#endif /* _SBEXTIF_H */
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
/*
|
||||
* Broadcom SiliconBackplane MIPS definitions
|
||||
*
|
||||
* SB MIPS cores are custom MIPS32 processors with SiliconBackplane
|
||||
* OCP interfaces. The CP0 processor ID is 0x00024000, where bits
|
||||
* 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
|
||||
* interface. The core revision is stored in the SB ID register in SB
|
||||
* configuration space.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _sbhndmips_h_
|
||||
#define _sbhndmips_h_
|
||||
|
||||
#include <mipsinc.h>
|
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY
|
||||
|
||||
/* cpp contortions to concatenate w/arg prescan */
|
||||
#ifndef PAD
|
||||
#define _PADLINE(line) pad ## line
|
||||
#define _XSTR(line) _PADLINE(line)
|
||||
#define PAD _XSTR(__LINE__)
|
||||
#endif /* PAD */
|
||||
|
||||
typedef volatile struct {
|
||||
uint32 corecontrol;
|
||||
uint32 PAD[2];
|
||||
uint32 biststatus;
|
||||
uint32 PAD[4];
|
||||
uint32 intstatus;
|
||||
uint32 intmask;
|
||||
uint32 timer;
|
||||
} mipsregs_t;
|
||||
|
||||
#endif /* _LANGUAGE_ASSEMBLY */
|
||||
|
||||
#endif /* _sbhndmips_h_ */
|
||||
|
|
@ -1,146 +0,0 @@
|
|||
/*
|
||||
* BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SBMEMC_H
|
||||
#define _SBMEMC_H
|
||||
|
||||
#ifdef _LANGUAGE_ASSEMBLY
|
||||
|
||||
#define MEMC_CONTROL 0x00
|
||||
#define MEMC_CONFIG 0x04
|
||||
#define MEMC_REFRESH 0x08
|
||||
#define MEMC_BISTSTAT 0x0c
|
||||
#define MEMC_MODEBUF 0x10
|
||||
#define MEMC_BKCLS 0x14
|
||||
#define MEMC_PRIORINV 0x18
|
||||
#define MEMC_DRAMTIM 0x1c
|
||||
#define MEMC_INTSTAT 0x20
|
||||
#define MEMC_INTMASK 0x24
|
||||
#define MEMC_INTINFO 0x28
|
||||
#define MEMC_NCDLCTL 0x30
|
||||
#define MEMC_RDNCDLCOR 0x34
|
||||
#define MEMC_WRNCDLCOR 0x38
|
||||
#define MEMC_MISCDLYCTL 0x3c
|
||||
#define MEMC_DQSGATENCDL 0x40
|
||||
#define MEMC_SPARE 0x44
|
||||
#define MEMC_TPADDR 0x48
|
||||
#define MEMC_TPDATA 0x4c
|
||||
#define MEMC_BARRIER 0x50
|
||||
#define MEMC_CORE 0x54
|
||||
|
||||
#else /* !_LANGUAGE_ASSEMBLY */
|
||||
|
||||
/* Sonics side: MEMC core registers */
|
||||
typedef volatile struct sbmemcregs {
|
||||
uint32 control;
|
||||
uint32 config;
|
||||
uint32 refresh;
|
||||
uint32 biststat;
|
||||
uint32 modebuf;
|
||||
uint32 bkcls;
|
||||
uint32 priorinv;
|
||||
uint32 dramtim;
|
||||
uint32 intstat;
|
||||
uint32 intmask;
|
||||
uint32 intinfo;
|
||||
uint32 reserved1;
|
||||
uint32 ncdlctl;
|
||||
uint32 rdncdlcor;
|
||||
uint32 wrncdlcor;
|
||||
uint32 miscdlyctl;
|
||||
uint32 dqsgatencdl;
|
||||
uint32 spare;
|
||||
uint32 tpaddr;
|
||||
uint32 tpdata;
|
||||
uint32 barrier;
|
||||
uint32 core;
|
||||
} sbmemcregs_t;
|
||||
|
||||
#endif /* _LANGUAGE_ASSEMBLY */
|
||||
|
||||
/* MEMC Core Init values (OCP ID 0x80f) */
|
||||
|
||||
/* For sdr: */
|
||||
#define MEMC_SD_CONFIG_INIT 0x00048000
|
||||
#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
|
||||
#define MEMC_SD_DRAMTIM3_INIT 0x000754da
|
||||
#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
|
||||
#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
|
||||
#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
|
||||
#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
|
||||
#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
|
||||
#define MEMC_SD_CONTROL_INIT0 0x00000002
|
||||
#define MEMC_SD_CONTROL_INIT1 0x00000008
|
||||
#define MEMC_SD_CONTROL_INIT2 0x00000004
|
||||
#define MEMC_SD_CONTROL_INIT3 0x00000010
|
||||
#define MEMC_SD_CONTROL_INIT4 0x00000001
|
||||
#define MEMC_SD_MODEBUF_INIT 0x00000000
|
||||
#define MEMC_SD_REFRESH_INIT 0x0000840f
|
||||
|
||||
|
||||
/* This is for SDRM8X8X4 */
|
||||
#define MEMC_SDR_INIT 0x0008
|
||||
#define MEMC_SDR_MODE 0x32
|
||||
#define MEMC_SDR_NCDL 0x00020032
|
||||
#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
|
||||
|
||||
/* For ddr: */
|
||||
#define MEMC_CONFIG_INIT 0x00048000
|
||||
#define MEMC_DRAMTIM2_INIT 0x000754d8
|
||||
#define MEMC_DRAMTIM25_INIT 0x000754d9
|
||||
#define MEMC_RDNCDLCOR_INIT 0x00000000
|
||||
#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
|
||||
#define MEMC_WRNCDLCOR_INIT 0x49351200
|
||||
#define MEMC_1_WRNCDLCOR_INIT 0x14500200
|
||||
#define MEMC_DQSGATENCDL_INIT 0x00030000
|
||||
#define MEMC_MISCDLYCTL_INIT 0x21061c1b
|
||||
#define MEMC_1_MISCDLYCTL_INIT 0x21021400
|
||||
#define MEMC_NCDLCTL_INIT 0x00002001
|
||||
#define MEMC_CONTROL_INIT0 0x00000002
|
||||
#define MEMC_CONTROL_INIT1 0x00000008
|
||||
#define MEMC_MODEBUF_INIT0 0x00004000
|
||||
#define MEMC_CONTROL_INIT2 0x00000010
|
||||
#define MEMC_MODEBUF_INIT1 0x00000100
|
||||
#define MEMC_CONTROL_INIT3 0x00000010
|
||||
#define MEMC_CONTROL_INIT4 0x00000008
|
||||
#define MEMC_REFRESH_INIT 0x0000840f
|
||||
#define MEMC_CONTROL_INIT5 0x00000004
|
||||
#define MEMC_MODEBUF_INIT2 0x00000000
|
||||
#define MEMC_CONTROL_INIT6 0x00000010
|
||||
#define MEMC_CONTROL_INIT7 0x00000001
|
||||
|
||||
|
||||
/* This is for DDRM16X16X2 */
|
||||
#define MEMC_DDR_INIT 0x0009
|
||||
#define MEMC_DDR_MODE 0x62
|
||||
#define MEMC_DDR_NCDL 0x0005050a
|
||||
#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
|
||||
|
||||
/* mask for sdr/ddr calibration registers */
|
||||
#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
|
||||
#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
|
||||
#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
|
||||
|
||||
/* masks for miscdlyctl registers */
|
||||
#define MEMC_MISC_SM_MASK 0x30000000
|
||||
#define MEMC_MISC_SM_SHIFT 28
|
||||
#define MEMC_MISC_SD_MASK 0x0f000000
|
||||
#define MEMC_MISC_SD_SHIFT 24
|
||||
|
||||
/* hw threshhold for calculating wr/rd for sdr memc */
|
||||
#define MEMC_CD_THRESHOLD 128
|
||||
|
||||
/* Low bit of init register says if memc is ddr or sdr */
|
||||
#define MEMC_CONFIG_DDR 0x00000001
|
||||
|
||||
#endif /* _SBMEMC_H */
|
||||
|
|
@ -1,116 +0,0 @@
|
|||
/*
|
||||
* HND SiliconBackplane PCI core hardware definitions.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _sbpci_h_
|
||||
#define _sbpci_h_
|
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY
|
||||
|
||||
/* cpp contortions to concatenate w/arg prescan */
|
||||
#ifndef PAD
|
||||
#define _PADLINE(line) pad ## line
|
||||
#define _XSTR(line) _PADLINE(line)
|
||||
#define PAD _XSTR(__LINE__)
|
||||
#endif
|
||||
|
||||
/* Sonics side: PCI core and host control registers */
|
||||
typedef struct sbpciregs {
|
||||
uint32 control; /* PCI control */
|
||||
uint32 PAD[3];
|
||||
uint32 arbcontrol; /* PCI arbiter control */
|
||||
uint32 PAD[3];
|
||||
uint32 intstatus; /* Interrupt status */
|
||||
uint32 intmask; /* Interrupt mask */
|
||||
uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
|
||||
uint32 PAD[9];
|
||||
uint32 bcastaddr; /* Sonics broadcast address */
|
||||
uint32 bcastdata; /* Sonics broadcast data */
|
||||
uint32 PAD[2];
|
||||
uint32 gpioin; /* ro: gpio input (>=rev2) */
|
||||
uint32 gpioout; /* rw: gpio output (>=rev2) */
|
||||
uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
|
||||
uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
|
||||
uint32 PAD[36];
|
||||
uint32 sbtopci0; /* Sonics to PCI translation 0 */
|
||||
uint32 sbtopci1; /* Sonics to PCI translation 1 */
|
||||
uint32 sbtopci2; /* Sonics to PCI translation 2 */
|
||||
uint32 PAD[189];
|
||||
uint32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
|
||||
uint16 sprom[36]; /* SPROM shadow Area */
|
||||
uint32 PAD[46];
|
||||
} sbpciregs_t;
|
||||
|
||||
#endif /* _LANGUAGE_ASSEMBLY */
|
||||
|
||||
/* PCI control */
|
||||
#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
|
||||
#define PCI_RST 0x02 /* Value driven out to pin */
|
||||
#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
|
||||
#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
|
||||
|
||||
/* PCI arbiter control */
|
||||
#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
|
||||
#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
|
||||
/* ParkID - for PCI corerev >= 8 */
|
||||
#define PCI_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */
|
||||
#define PCI_PARKID_SHIFT 2
|
||||
#define PCI_PARKID_EXT0 0 /* External master 0 */
|
||||
#define PCI_PARKID_EXT1 1 /* External master 1 */
|
||||
#define PCI_PARKID_EXT2 2 /* External master 2 */
|
||||
#define PCI_PARKID_EXT3 3 /* External master 3 (rev >= 11) */
|
||||
#define PCI_PARKID_INT 3 /* Internal master (rev < 11) */
|
||||
#define PCI11_PARKID_INT 4 /* Internal master (rev >= 11) */
|
||||
#define PCI_PARKID_LAST 4 /* Last active master (rev < 11) */
|
||||
#define PCI11_PARKID_LAST 5 /* Last active master (rev >= 11) */
|
||||
|
||||
/* Interrupt status/mask */
|
||||
#define PCI_INTA 0x01 /* PCI INTA# is asserted */
|
||||
#define PCI_INTB 0x02 /* PCI INTB# is asserted */
|
||||
#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
|
||||
#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
|
||||
#define PCI_PME 0x10 /* PCI PME# is asserted */
|
||||
|
||||
/* (General) PCI/SB mailbox interrupts, two bits per pci function */
|
||||
#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
|
||||
#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
|
||||
#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
|
||||
#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
|
||||
#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
|
||||
#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
|
||||
#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
|
||||
#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
|
||||
|
||||
/* Sonics broadcast address */
|
||||
#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
|
||||
|
||||
/* Sonics to PCI translation types */
|
||||
#define SBTOPCI0_MASK 0xfc000000
|
||||
#define SBTOPCI1_MASK 0xfc000000
|
||||
#define SBTOPCI2_MASK 0xc0000000
|
||||
#define SBTOPCI_MEM 0
|
||||
#define SBTOPCI_IO 1
|
||||
#define SBTOPCI_CFG0 2
|
||||
#define SBTOPCI_CFG1 3
|
||||
#define SBTOPCI_PREF 0x4 /* prefetch enable */
|
||||
#define SBTOPCI_BURST 0x8 /* burst enable */
|
||||
#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
|
||||
#define SBTOPCI_RC_READ 0x00 /* memory read */
|
||||
#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
|
||||
#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
|
||||
|
||||
/* PCI core index in SROM shadow area */
|
||||
#define SRSH_PI_OFFSET 0 /* first word */
|
||||
#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
|
||||
#define SRSH_PI_SHIFT 12 /* bit 15:12 */
|
||||
|
||||
#endif /* _sbpci_h_ */
|
||||
|
|
@ -1,236 +0,0 @@
|
|||
/*
|
||||
* BCM43XX SiliconBackplane PCIE core hardware definitions.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SBPCIE_H
|
||||
#define _SBPCIE_H
|
||||
|
||||
/* cpp contortions to concatenate w/arg prescan */
|
||||
#ifndef PAD
|
||||
#define _PADLINE(line) pad ## line
|
||||
#define _XSTR(line) _PADLINE(line)
|
||||
#define PAD _XSTR(__LINE__)
|
||||
#endif
|
||||
|
||||
/* PCIE Enumeration space offsets */
|
||||
#define PCIE_CORE_CONFIG_OFFSET 0x0
|
||||
#define PCIE_FUNC0_CONFIG_OFFSET 0x400
|
||||
#define PCIE_FUNC1_CONFIG_OFFSET 0x500
|
||||
#define PCIE_FUNC2_CONFIG_OFFSET 0x600
|
||||
#define PCIE_FUNC3_CONFIG_OFFSET 0x700
|
||||
#define PCIE_SPROM_SHADOW_OFFSET 0x800
|
||||
#define PCIE_SBCONFIG_OFFSET 0xE00
|
||||
|
||||
/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
|
||||
#define PCIE_DEV_BAR0_SIZE 0x4000
|
||||
#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0
|
||||
#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000
|
||||
#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
|
||||
#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
|
||||
|
||||
/* different register spaces to access thr'u pcie indirect access */
|
||||
#define PCIE_CONFIGREGS 1 /* Access to config space */
|
||||
#define PCIE_PCIEREGS 2 /* Access to pcie registers */
|
||||
|
||||
/* SB side: PCIE core and host control registers */
|
||||
typedef struct sbpcieregs {
|
||||
uint32 PAD[3];
|
||||
uint32 biststatus; /* bist Status: 0x00C */
|
||||
uint32 gpiosel; /* PCIE gpio sel: 0x010 */
|
||||
uint32 gpioouten; /* PCIE gpio outen: 0x14 */
|
||||
uint32 PAD[4];
|
||||
uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
|
||||
uint32 PAD[54];
|
||||
uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
|
||||
uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
|
||||
uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
|
||||
uint32 PAD[4];
|
||||
|
||||
/* pcie core supports in direct access to config space */
|
||||
uint32 configaddr; /* pcie config space access: Address field: 0x120 */
|
||||
uint32 configdata; /* pcie config space access: Data field: 0x124 */
|
||||
|
||||
/* mdio access to serdes */
|
||||
uint32 mdiocontrol; /* controls the mdio access: 0x128 */
|
||||
uint32 mdiodata; /* Data to the mdio access: 0x12c */
|
||||
|
||||
/* pcie protocol phy/dllp/tlp register indirect access mechanism */
|
||||
uint32 pcieindaddr; /* indirect access to the internal register: 0x130 */
|
||||
uint32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */
|
||||
|
||||
uint32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */
|
||||
uint32 PAD[433];
|
||||
uint16 sprom[36]; /* SPROM shadow Area */
|
||||
} sbpcieregs_t;
|
||||
|
||||
/* SB to PCIE translation masks */
|
||||
#define SBTOPCIE0_MASK 0xfc000000
|
||||
#define SBTOPCIE1_MASK 0xfc000000
|
||||
#define SBTOPCIE2_MASK 0xc0000000
|
||||
|
||||
/* Access type bits (0:1) */
|
||||
#define SBTOPCIE_MEM 0
|
||||
#define SBTOPCIE_IO 1
|
||||
#define SBTOPCIE_CFG0 2
|
||||
#define SBTOPCIE_CFG1 3
|
||||
|
||||
/* Prefetch enable bit 2 */
|
||||
#define SBTOPCIE_PF 4
|
||||
|
||||
/* Write Burst enable for memory write bit 3 */
|
||||
#define SBTOPCIE_WR_BURST 8
|
||||
|
||||
/* config access */
|
||||
#define CONFIGADDR_FUNC_MASK 0x7000
|
||||
#define CONFIGADDR_FUNC_SHF 12
|
||||
#define CONFIGADDR_REG_MASK 0x0FFF
|
||||
#define CONFIGADDR_REG_SHF 0
|
||||
|
||||
/* PCIE protocol regs Indirect Address */
|
||||
#define PCIEADDR_PROT_MASK 0x300
|
||||
#define PCIEADDR_PROT_SHF 8
|
||||
#define PCIEADDR_PL_TLP 0
|
||||
#define PCIEADDR_PL_DLLP 1
|
||||
#define PCIEADDR_PL_PLP 2
|
||||
|
||||
/* PCIE protocol PHY diagnostic registers */
|
||||
#define PCIE_PLP_MODEREG 0x200 /* Mode */
|
||||
#define PCIE_PLP_STATUSREG 0x204 /* Status */
|
||||
#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
|
||||
#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
|
||||
#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
|
||||
#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
|
||||
#define PCIE_PLP_ATTNREG 0x218 /* Attention */
|
||||
#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */
|
||||
#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */
|
||||
#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
|
||||
#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
|
||||
#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg */
|
||||
#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
|
||||
#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
|
||||
#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
|
||||
#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
|
||||
|
||||
/* PCIE protocol DLLP diagnostic registers */
|
||||
#define PCIE_DLLP_LCREG 0x100 /* Link Control */
|
||||
#define PCIE_DLLP_LSREG 0x104 /* Link Status */
|
||||
#define PCIE_DLLP_LAREG 0x108 /* Link Attention */
|
||||
#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
|
||||
#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
|
||||
#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
|
||||
#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
|
||||
#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
|
||||
#define PCIE_DLLP_LRREG 0x120 /* Link Replay */
|
||||
#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
|
||||
#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
|
||||
#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
|
||||
#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
|
||||
#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
|
||||
#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
|
||||
#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
|
||||
#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
|
||||
#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter */
|
||||
#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
|
||||
#define PCIE_DLLP_TESTREG 0x14C /* Test */
|
||||
#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */
|
||||
#define PCIE_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */
|
||||
|
||||
/* PCIE protocol TLP diagnostic registers */
|
||||
#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
|
||||
#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
|
||||
#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address */
|
||||
#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address */
|
||||
#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req */
|
||||
#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address */
|
||||
#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address */
|
||||
#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req */
|
||||
#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address */
|
||||
#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address */
|
||||
#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req */
|
||||
#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len */
|
||||
#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs */
|
||||
#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req */
|
||||
#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len */
|
||||
#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0 */
|
||||
#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1 */
|
||||
#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2 */
|
||||
#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */
|
||||
#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */
|
||||
#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */
|
||||
#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len */
|
||||
#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0 */
|
||||
#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1 */
|
||||
#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func */
|
||||
#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter */
|
||||
#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value */
|
||||
#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1 */
|
||||
#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2 */
|
||||
#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */
|
||||
#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */
|
||||
|
||||
/* MDIO control */
|
||||
#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
|
||||
#define MDIOCTL_DIVISOR_VAL 0x2
|
||||
#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
|
||||
#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
|
||||
|
||||
/* MDIO Data */
|
||||
#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
|
||||
#define MDIODATA_TA 0x00020000 /* Turnaround */
|
||||
#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
|
||||
#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */
|
||||
#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */
|
||||
#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */
|
||||
#define MDIODATA_WRITE 0x10000000 /* write Transaction */
|
||||
#define MDIODATA_READ 0x20000000 /* Read Transaction */
|
||||
#define MDIODATA_START 0x40000000 /* start of Transaction */
|
||||
|
||||
/* MDIO devices (SERDES modules) */
|
||||
#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
|
||||
#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
|
||||
#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
|
||||
|
||||
/* SERDES RX registers */
|
||||
#define SERDES_RX_CTRL 1 /* Rx cntrl */
|
||||
#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
|
||||
#define SERDES_RX_CDR 6 /* CDR */
|
||||
#define SERDES_RX_CDRBW 7 /* CDR BW */
|
||||
|
||||
/* SERDES RX control register */
|
||||
#define SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
|
||||
#define SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
|
||||
|
||||
/* SERDES PLL registers */
|
||||
#define SERDES_PLL_CTRL 1 /* PLL control reg */
|
||||
#define PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
|
||||
|
||||
#define PCIE_L1THRESHOLDTIME_MASK 0xFF00 /* bits 8 - 15 */
|
||||
#define PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */
|
||||
#define PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */
|
||||
|
||||
/* SPROM offsets */
|
||||
#define SRSH_ASPM_OFFSET 4 /* word 4 */
|
||||
#define SRSH_ASPM_ENB 0x18 /* bit 3, 4 */
|
||||
#define SRSH_CLKREQ_OFFSET 20 /* word 20 */
|
||||
#define SRSH_CLKREQ_ENB 0x0800 /* bit 11 */
|
||||
|
||||
/* Linkcontrol reg offset in PCIE Cap */
|
||||
#define PCIE_CAP_LINKCTRL_OFFSET 16 /* linkctrl offset in pcie cap */
|
||||
#define PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */
|
||||
#define PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */
|
||||
#define PCIE_ASPM_ENAB 0x03 /* ASPM L0s & L1 in linkctrl */
|
||||
#define PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */
|
||||
|
||||
/* Status reg PCIE_PLP_STATUSREG */
|
||||
#define PCIE_PLP_POLARITYINV_STAT 0x10
|
||||
|
||||
#endif /* _SBPCIE_H */
|
||||
|
|
@ -1,184 +0,0 @@
|
|||
/*
|
||||
* BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SBPCMCIA_H
|
||||
#define _SBPCMCIA_H
|
||||
|
||||
|
||||
/* All the addresses that are offsets in attribute space are divided
|
||||
* by two to account for the fact that odd bytes are invalid in
|
||||
* attribute space and our read/write routines make the space appear
|
||||
* as if they didn't exist. Still we want to show the original numbers
|
||||
* as documented in the hnd_pcmcia core manual.
|
||||
*/
|
||||
|
||||
/* PCMCIA Function Configuration Registers */
|
||||
#define PCMCIA_FCR (0x700 / 2)
|
||||
|
||||
#define FCR0_OFF 0
|
||||
#define FCR1_OFF (0x40 / 2)
|
||||
#define FCR2_OFF (0x80 / 2)
|
||||
#define FCR3_OFF (0xc0 / 2)
|
||||
|
||||
#define PCMCIA_FCR0 (0x700 / 2)
|
||||
#define PCMCIA_FCR1 (0x740 / 2)
|
||||
#define PCMCIA_FCR2 (0x780 / 2)
|
||||
#define PCMCIA_FCR3 (0x7c0 / 2)
|
||||
|
||||
/* Standard PCMCIA FCR registers */
|
||||
|
||||
#define PCMCIA_COR 0
|
||||
|
||||
#define COR_RST 0x80
|
||||
#define COR_LEV 0x40
|
||||
#define COR_IRQEN 0x04
|
||||
#define COR_BLREN 0x01
|
||||
#define COR_FUNEN 0x01
|
||||
|
||||
|
||||
#define PCICIA_FCSR (2 / 2)
|
||||
#define PCICIA_PRR (4 / 2)
|
||||
#define PCICIA_SCR (6 / 2)
|
||||
#define PCICIA_ESR (8 / 2)
|
||||
|
||||
|
||||
#define PCM_MEMOFF 0x0000
|
||||
#define F0_MEMOFF 0x1000
|
||||
#define F1_MEMOFF 0x2000
|
||||
#define F2_MEMOFF 0x3000
|
||||
#define F3_MEMOFF 0x4000
|
||||
|
||||
/* Memory base in the function fcr's */
|
||||
#define MEM_ADDR0 (0x728 / 2)
|
||||
#define MEM_ADDR1 (0x72a / 2)
|
||||
#define MEM_ADDR2 (0x72c / 2)
|
||||
|
||||
/* PCMCIA base plus Srom access in fcr0: */
|
||||
#define PCMCIA_ADDR0 (0x072e / 2)
|
||||
#define PCMCIA_ADDR1 (0x0730 / 2)
|
||||
#define PCMCIA_ADDR2 (0x0732 / 2)
|
||||
|
||||
#define MEM_SEG (0x0734 / 2)
|
||||
#define SROM_CS (0x0736 / 2)
|
||||
#define SROM_DATAL (0x0738 / 2)
|
||||
#define SROM_DATAH (0x073a / 2)
|
||||
#define SROM_ADDRL (0x073c / 2)
|
||||
#define SROM_ADDRH (0x073e / 2)
|
||||
#define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */
|
||||
#define SROM_INFO (0x07be / 2) /* Corerev >= 6 */
|
||||
|
||||
/* Values for srom_cs: */
|
||||
#define SROM_IDLE 0
|
||||
#define SROM_WRITE 1
|
||||
#define SROM_READ 2
|
||||
#define SROM_WEN 4
|
||||
#define SROM_WDS 7
|
||||
#define SROM_DONE 8
|
||||
|
||||
/* Fields in srom_info: */
|
||||
#define SRI_SZ_MASK 0x03
|
||||
#define SRI_BLANK 0x04
|
||||
#define SRI_OTP 0x80
|
||||
|
||||
/* CIS stuff */
|
||||
|
||||
/* The CIS stops where the FCRs start */
|
||||
#define CIS_SIZE PCMCIA_FCR
|
||||
|
||||
/* CIS tuple length field max */
|
||||
#define CIS_TUPLE_LEN_MAX 0xff
|
||||
|
||||
/* Standard tuples we know about */
|
||||
|
||||
#define CISTPL_VERS_1 0x15 /* CIS ver, manf, dev & ver strings */
|
||||
#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
|
||||
#define CISTPL_FUNCID 0x21 /* Function identification */
|
||||
#define CISTPL_FUNCE 0x22 /* Function extensions */
|
||||
#define CISTPL_CFTABLE 0x1b /* Config table entry */
|
||||
#define CISTPL_END 0xff /* End of the CIS tuple chain */
|
||||
|
||||
/* Function identifier provides context for the function extentions tuple */
|
||||
|
||||
|
||||
/* Function extensions for LANs */
|
||||
|
||||
#define LAN_TECH 1 /* Technology type */
|
||||
#define LAN_SPEED 2 /* Raw bit rate */
|
||||
#define LAN_MEDIA 3 /* Transmission media */
|
||||
#define LAN_NID 4 /* Node identification (aka MAC addr) */
|
||||
#define LAN_CONN 5 /* Connector standard */
|
||||
|
||||
|
||||
/* CFTable */
|
||||
#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
|
||||
#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
|
||||
#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
|
||||
|
||||
/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
|
||||
* take one for HNBU, and use "extensions" (a la FUNCE) within it.
|
||||
*/
|
||||
|
||||
#define CISTPL_BRCM_HNBU 0x80
|
||||
|
||||
/* Subtypes of BRCM_HNBU: */
|
||||
|
||||
#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
|
||||
#define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */
|
||||
#define HNBU_BOARDREV 0x02 /* One byte board revision */
|
||||
#define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1)
|
||||
* or 9 (sromrev > 1) bytes
|
||||
*/
|
||||
#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
|
||||
#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
|
||||
#define HNBU_AA 0x06 /* Antennas available */
|
||||
#define HNBU_AG 0x07 /* Antenna gain */
|
||||
#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
|
||||
#define HNBU_LEDS 0x09 /* LED set */
|
||||
#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
|
||||
* in rev 2
|
||||
*/
|
||||
#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
|
||||
#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
|
||||
#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */
|
||||
#define HNBU_PAPARMS5G 0x0e /* 5G PA params */
|
||||
#define HNBU_ANT5G 0x0f /* 4328 5G antennas available/gain */
|
||||
#define HNBU_RDLID 0x10 /* 2 byte USB remote downloader (RDL) product Id */
|
||||
#define HNBU_RSSISMBXA2G 0x11 /* 4328 2G RSSI mid pt sel & board switch arch,
|
||||
* 2 bytes, rev 3.
|
||||
*/
|
||||
#define HNBU_RSSISMBXA5G 0x12 /* 4328 5G RSSI mid pt sel & board switch arch,
|
||||
* 2 bytes, rev 3.
|
||||
*/
|
||||
#define HNBU_XTALFREQ 0x13 /* 4 byte Crystal frequency in kilohertz */
|
||||
#define HNBU_TRI2G 0x14 /* 4328 2G TR isolation, 1 byte */
|
||||
#define HNBU_TRI5G 0x15 /* 4328 5G TR isolation, 3 bytes */
|
||||
#define HNBU_RXPO2G 0x16 /* 4328 2G RX power offset, 1 byte */
|
||||
#define HNBU_RXPO5G 0x17 /* 4328 5G RX power offset, 1 byte */
|
||||
#define HNBU_BOARDNUM 0x18 /* board serial number, independent of mac addr */
|
||||
#define HNBU_MACADDR 0x19 /* mac addr override for the standard CIS LAN_NID */
|
||||
#define HNBU_RDLSN 0x1a /* 2 bytes; serial # advertised in USB descriptor */
|
||||
#define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */
|
||||
#define HNBU_RDLRNDIS 0x20 /* 1 byte; 1 = RDL advertises RNDIS config */
|
||||
#define HNBU_RDLRWU 0x30 /* 1 byte; 1 = RDL advertises Remote Wake-up */
|
||||
#define HNBU_SROM3SWRGN 0x80 /* 78 bytes; srom rev 3 s/w region without crc8
|
||||
* plus extra info appended.
|
||||
*/
|
||||
|
||||
/* sbtmstatelow */
|
||||
#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
|
||||
#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
|
||||
|
||||
/* sbtmstatehigh */
|
||||
#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
|
||||
|
||||
#endif /* _SBPCMCIA_H */
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
/*
|
||||
* BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SBSDRAM_H
|
||||
#define _SBSDRAM_H
|
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY
|
||||
|
||||
/* Sonics side: SDRAM core registers */
|
||||
typedef volatile struct sbsdramregs {
|
||||
uint32 initcontrol; /* Generates external SDRAM initialization sequence */
|
||||
uint32 config; /* Initializes external SDRAM mode register */
|
||||
uint32 refresh; /* Controls external SDRAM refresh rate */
|
||||
uint32 pad1;
|
||||
uint32 pad2;
|
||||
} sbsdramregs_t;
|
||||
|
||||
#endif /* !_LANGUAGE_ASSEMBLY */
|
||||
|
||||
/* SDRAM initialization control (initcontrol) register bits */
|
||||
#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
|
||||
#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
|
||||
#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
|
||||
#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
|
||||
#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
|
||||
#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
|
||||
#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
|
||||
#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
|
||||
#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
|
||||
#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
|
||||
#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
|
||||
#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
|
||||
#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
|
||||
|
||||
/* SDRAM configuration (config) register bits */
|
||||
#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
|
||||
#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
|
||||
#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
|
||||
#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
|
||||
#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
|
||||
#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
|
||||
|
||||
/* SDRAM refresh control (refresh) register bits */
|
||||
#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
|
||||
#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
|
||||
|
||||
/* SDRAM Core default Init values (OCP ID 0x803) */
|
||||
#define SDRAM_INIT MEM4MX16X2
|
||||
#define SDRAM_CONFIG SDRAM_BURSTFULL
|
||||
#define SDRAM_REFRESH SDRAM_REF(0x40)
|
||||
|
||||
#define MEM1MX16 0x009 /* 2 MB */
|
||||
#define MEM1MX16X2 0x409 /* 4 MB */
|
||||
#define MEM2MX8X2 0x809 /* 4 MB */
|
||||
#define MEM2MX8X4 0xc09 /* 8 MB */
|
||||
#define MEM2MX32 0x439 /* 8 MB */
|
||||
#define MEM4MX16 0x019 /* 8 MB */
|
||||
#define MEM4MX16X2 0x419 /* 16 MB */
|
||||
#define MEM8MX8X2 0x819 /* 16 MB */
|
||||
#define MEM8MX16 0x829 /* 16 MB */
|
||||
#define MEM4MX32 0x429 /* 16 MB */
|
||||
#define MEM8MX8X4 0xc19 /* 32 MB */
|
||||
#define MEM8MX16X2 0xc29 /* 32 MB */
|
||||
|
||||
#endif /* _SBSDRAM_H */
|
||||
|
|
@ -1,85 +0,0 @@
|
|||
/*
|
||||
* BCM47XX Sonics SiliconBackplane embedded ram core
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SBSOCRAM_H
|
||||
#define _SBSOCRAM_H
|
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY
|
||||
|
||||
/* cpp contortions to concatenate w/arg prescan */
|
||||
#ifndef PAD
|
||||
#define _PADLINE(line) pad ## line
|
||||
#define _XSTR(line) _PADLINE(line)
|
||||
#define PAD _XSTR(__LINE__)
|
||||
#endif /* PAD */
|
||||
|
||||
/* Memcsocram core registers */
|
||||
typedef volatile struct sbsocramregs {
|
||||
uint32 coreinfo;
|
||||
uint32 bwalloc;
|
||||
uint32 PAD;
|
||||
uint32 biststat;
|
||||
uint32 bankidx;
|
||||
uint32 standbyctrl;
|
||||
uint32 PAD[116];
|
||||
uint32 pwrctl; /* corerev >= 2 */
|
||||
} sbsocramregs_t;
|
||||
|
||||
#endif /* _LANGUAGE_ASSEMBLY */
|
||||
|
||||
/* Register offsets */
|
||||
#define SR_COREINFO 0x00
|
||||
#define SR_BWALLOC 0x04
|
||||
#define SR_BISTSTAT 0x0c
|
||||
#define SR_BANKINDEX 0x10
|
||||
#define SR_BANKSTBYCTL 0x14
|
||||
#define SR_PWRCTL 0x1e8
|
||||
|
||||
/* Coreinfo register */
|
||||
#define SRCI_PT_MASK 0x00030000
|
||||
#define SRCI_PT_SHIFT 16
|
||||
/* corerev >= 3 */
|
||||
#define SRCI_LSS_MASK 0x00f00000
|
||||
#define SRCI_LSS_SHIFT 20
|
||||
#define SRCI_LRS_MASK 0x0f000000
|
||||
#define SRCI_LRS_SHIFT 24
|
||||
|
||||
/* In corerev 0, the memory size is 2 to the power of the
|
||||
* base plus 16 plus to the contents of the memsize field plus 1.
|
||||
*/
|
||||
#define SRCI_MS0_MASK 0xf
|
||||
#define SR_MS0_BASE 16
|
||||
|
||||
/*
|
||||
* In corerev 1 the bank size is 2 ^ the bank size field plus 14,
|
||||
* the memory size is number of banks times bank size.
|
||||
* The same applies to rom size.
|
||||
*/
|
||||
#define SRCI_ROMNB_MASK 0xf000
|
||||
#define SRCI_ROMNB_SHIFT 12
|
||||
#define SRCI_ROMBSZ_MASK 0xf00
|
||||
#define SRCI_ROMBSZ_SHIFT 8
|
||||
#define SRCI_SRNB_MASK 0xf0
|
||||
#define SRCI_SRNB_SHIFT 4
|
||||
#define SRCI_SRBSZ_MASK 0xf
|
||||
#define SRCI_SRBSZ_SHIFT 0
|
||||
|
||||
#define SR_BSZ_BASE 14
|
||||
|
||||
/* Standby control register */
|
||||
#define SRSC_SBYOVR_MASK 0x80000000
|
||||
#define SRSC_SBYOVR_SHIFT 31
|
||||
#define SRSC_SBYOVRVAL_MASK 0x60000000
|
||||
#define SRSC_SBYOVRVAL_SHIFT 29
|
||||
|
||||
#endif /* _SBSOCRAM_H */
|
||||
|
|
@ -1,276 +0,0 @@
|
|||
/*
|
||||
* SPROM format definitions for the Broadcom 47xx and 43xx chip family.
|
||||
*
|
||||
* Copyright(c) 2002 Broadcom Corporation
|
||||
*/
|
||||
|
||||
#ifndef _SBSPROM_H
|
||||
#define _SBSPROM_H
|
||||
|
||||
#include "typedefs.h"
|
||||
#include "bcmdevs.h"
|
||||
|
||||
/* A word is this many bytes */
|
||||
#define SRW 2
|
||||
|
||||
/* offset into PCI config space for write enable bit */
|
||||
#define CFG_SROM_WRITABLE_OFFSET 0x88
|
||||
#define SROM_WRITEABLE 0x10
|
||||
|
||||
/* enumeration space consists of N contiguous 4Kbyte core register sets */
|
||||
#define SBCORES_BASE 0x18000000
|
||||
#define SBCORES_EACH 0x1000
|
||||
|
||||
/* offset from BAR0 for srom space */
|
||||
#define SROM_BASE 4096
|
||||
|
||||
/* number of 2-byte words in srom */
|
||||
#define SROM_SIZE 64
|
||||
|
||||
#define SROM_BYTES (SROM_SIZE * SRW)
|
||||
|
||||
#define MAX_FN 4
|
||||
|
||||
/* Word 0, Hardware control */
|
||||
#define SROM_HWCTL 0
|
||||
#define HW_FUNMSK 0x000f
|
||||
#define HW_FCLK 0x0200
|
||||
#define HW_CBM 0x0400
|
||||
#define HW_PIMSK 0xf000
|
||||
#define HW_PISHIFT 12
|
||||
#define HW_4301PISHIFT 13
|
||||
#define HW_PI4402 0x2
|
||||
#define HW_FUN4401 0x0001
|
||||
#define HW_FCLK4402 0x0000
|
||||
|
||||
/* Word 1, common-power/boot-rom */
|
||||
#define SROM_COMMPW 1
|
||||
/* boot rom present bit */
|
||||
#define BR_PRESSHIFT 8
|
||||
/* 15:9 for n; boot rom size is 2^(14 + n) bytes */
|
||||
#define BR_SIZESHIFT 9
|
||||
|
||||
/* Word 2, SubsystemId */
|
||||
#define SROM_SSID 2
|
||||
|
||||
/* Word 3, VendorId */
|
||||
#define SROM_VID 3
|
||||
|
||||
/* Function 0 info, function info length */
|
||||
#define SROM_FN0 4
|
||||
#define SROM_FNSZ 8
|
||||
|
||||
/* Within each function: */
|
||||
/* Word 0, deviceID */
|
||||
#define SRFN_DID 0
|
||||
|
||||
/* Words 1-2, ClassCode */
|
||||
#define SRFN_CCL 1
|
||||
/* Word 2, D0 Power */
|
||||
#define SRFN_CCHD0 2
|
||||
|
||||
/* Word 3, PME and D1D2D3 power */
|
||||
#define SRFN_PMED123 3
|
||||
|
||||
#define PME_IL 0
|
||||
#define PME_ENET0 1
|
||||
#define PME_ENET1 2
|
||||
#define PME_CODEC 3
|
||||
|
||||
#define PME_4402_ENET 0
|
||||
#define PME_4402_CODEC 1
|
||||
#define PME_4301_WL 2
|
||||
#define PMEREP_4402_ENET (PMERD3CV | PMERD3CA | PMERD3H | PMERD2 | PMERD1 | PMERD0 | PME)
|
||||
|
||||
/* Word 4, Bar1 enable, pme reports */
|
||||
#define SRFN_B1PMER 4
|
||||
#define B1E 1
|
||||
#define B1SZMSK 0xe
|
||||
#define B1SZSH 1
|
||||
#define PMERMSK 0x0ff0
|
||||
#define PME 0x0010
|
||||
#define PMERD0 0x0020
|
||||
#define PMERD1 0x0040
|
||||
#define PMERD2 0x0080
|
||||
#define PMERD3H 0x0100
|
||||
#define PMERD3CA 0x0200
|
||||
#define PMERD3CV 0x0400
|
||||
#define IGNCLKRR 0x0800
|
||||
#define B0LMSK 0xf000
|
||||
|
||||
/* Words 4-5, Bar0 Sonics value */
|
||||
#define SRFN_B0H 5
|
||||
/* Words 6-7, CIS Pointer */
|
||||
#define SRFN_CISL 6
|
||||
#define SRFN_CISH 7
|
||||
|
||||
/* Words 36-38: iLine MAC address */
|
||||
#define SROM_I_MACHI 36
|
||||
#define SROM_I_MACMID 37
|
||||
#define SROM_I_MACLO 38
|
||||
|
||||
/* Words 36-38: wireless0 MAC address on 43xx */
|
||||
#define SROM_W0_MACHI 36
|
||||
#define SROM_W0_MACMID 37
|
||||
#define SROM_W0_MACLO 38
|
||||
|
||||
/* Words 39-41: enet0 MAC address */
|
||||
#define SROM_E0_MACHI 39
|
||||
#define SROM_E0_MACMID 40
|
||||
#define SROM_E0_MACLO 41
|
||||
|
||||
/* Words 42-44: enet1 MAC address */
|
||||
#define SROM_E1_MACHI 42
|
||||
#define SROM_E1_MACMID 43
|
||||
#define SROM_E1_MACLO 44
|
||||
|
||||
/* Words 42-44: wireless1 MAC address on 4309 */
|
||||
#define SROM_W1_MACHI 42
|
||||
#define SROM_W1_MACMID 43
|
||||
#define SROM_W1_MACLO 44
|
||||
|
||||
#define SROM_EPHY 45
|
||||
|
||||
/* Word 46: BdRev & Antennas0/1 & ccLock for 430x */
|
||||
#define SROM_REV_AA_LOCK 46
|
||||
|
||||
/* Words 47-51 wl0 PA bx */
|
||||
#define SROM_WL0_PAB0 47
|
||||
#define SROM_WL0_PAB1 48
|
||||
#define SROM_WL0_PAB2 49
|
||||
#define SROM_WL0_PAB3 50
|
||||
#define SROM_WL0_PAB4 51
|
||||
|
||||
/* Word 52: wl0/wl1 MaxPower */
|
||||
#define SROM_WL_MAXPWR 52
|
||||
|
||||
/* Words 53-55 wl1 PA bx */
|
||||
#define SROM_WL1_PAB0 53
|
||||
#define SROM_WL1_PAB1 54
|
||||
#define SROM_WL1_PAB2 55
|
||||
|
||||
/* Woprd 56: itt */
|
||||
#define SROM_ITT 56
|
||||
|
||||
/* Words 59-62: OEM Space */
|
||||
#define SROM_WL_OEM 59
|
||||
#define SROM_OEM_SIZE 4
|
||||
|
||||
/* Contents for the srom */
|
||||
|
||||
#define BU4710_SSID 0x0400
|
||||
#define VSIM4710_SSID 0x0401
|
||||
#define QT4710_SSID 0x0402
|
||||
|
||||
#define BU4610_SSID 0x0403
|
||||
#define VSIM4610_SSID 0x0404
|
||||
|
||||
#define BU4307_SSID 0x0405
|
||||
#define BCM94301CB_SSID 0x0406
|
||||
#define BCM94301MP_SSID 0x0407
|
||||
#define BCM94307MP_SSID 0x0408
|
||||
#define AP4307_SSID 0x0409
|
||||
|
||||
#define BU4309_SSID 0x040a
|
||||
#define BCM94309CB_SSID 0x040b
|
||||
#define BCM94309MP_SSID 0x040c
|
||||
#define AP4309_SSID 0x040d
|
||||
|
||||
#define BU4402_SSID 0x4402
|
||||
|
||||
#define CLASS_OTHER 0x8000
|
||||
#define CLASS_ETHER 0x0000
|
||||
#define CLASS_NET 0x0002
|
||||
#define CLASS_COMM 0x0007
|
||||
#define CLASS_MODEM 0x0300
|
||||
#define CLASS_MIPS 0x3000
|
||||
#define CLASS_PROC 0x000b
|
||||
#define CLASS_FLASH 0x0100
|
||||
#define CLASS_MEM 0x0005
|
||||
#define CLASS_SERIALBUS 0x000c
|
||||
#define CLASS_OHCI 0x0310
|
||||
|
||||
/* Broadcom IEEE MAC addresses are 00:90:4c:xx:xx:xx */
|
||||
#define MACHI 0x90
|
||||
|
||||
#define MACMID_BU4710I 0x4c17
|
||||
#define MACMID_BU4710E0 0x4c18
|
||||
#define MACMID_BU4710E1 0x4c19
|
||||
|
||||
#define MACMID_94710R1I 0x4c1a
|
||||
#define MACMID_94710R1E0 0x4c1b
|
||||
#define MACMID_94710R1E1 0x4c1c
|
||||
|
||||
#define MACMID_94710R4I 0x4c1d
|
||||
#define MACMID_94710R4E0 0x4c1e
|
||||
#define MACMID_94710R4E1 0x4c1f
|
||||
|
||||
#define MACMID_94710DEVI 0x4c20
|
||||
#define MACMID_94710DEVE0 0x4c21
|
||||
#define MACMID_94710DEVE1 0x4c22
|
||||
|
||||
#define MACMID_BU4402 0x4c23
|
||||
|
||||
#define MACMID_BU4610I 0x4c24
|
||||
#define MACMID_BU4610E0 0x4c25
|
||||
#define MACMID_BU4610E1 0x4c26
|
||||
|
||||
#define MACMID_BU4307W 0x4c27
|
||||
#define MACMID_BU4307E 0x4c28
|
||||
|
||||
#define MACMID_94301CB 0x4c29
|
||||
|
||||
#define MACMID_94301MP 0x4c2a
|
||||
|
||||
#define MACMID_94307MPW 0x4c2b
|
||||
#define MACMID_94307MPE 0x4c2c
|
||||
|
||||
#define MACMID_AP4307W 0x4c2d
|
||||
#define MACMID_AP4307E 0x4c2e
|
||||
|
||||
#define MACMID_BU4309W0 0x4c2f
|
||||
#define MACMID_BU4309W1 0x4c30
|
||||
#define MACMID_BU4309E 0x4c31
|
||||
|
||||
#define MACMID_94309CBW0 0x4c32
|
||||
#define MACMID_94309CBW1 0x4c33
|
||||
|
||||
#define MACMID_94309MPW0 0x4c34
|
||||
#define MACMID_94309MPW1 0x4c35
|
||||
#define MACMID_94309MPE 0x4c36
|
||||
|
||||
#define MACMID_BU4401 0x4c37
|
||||
|
||||
/* Enet phy settings one or two singles or a dual */
|
||||
/* Bits 4-0 : MII address for enet0 (0x1f for not there */
|
||||
/* Bits 9-5 : MII address for enet1 (0x1f for not there */
|
||||
/* Bit 14 : Mdio for enet0 */
|
||||
/* Bit 15 : Mdio for enet1 */
|
||||
|
||||
/* bu4710 with only one phy on enet1 with address 7: */
|
||||
#define SROM_EPHY_ONE 0x80ff
|
||||
|
||||
/* bu4710 with two individual phys, at 6 and 7, */
|
||||
/* each mdio connected to its own mac: */
|
||||
#define SROM_EPHY_TWO 0x80e6
|
||||
|
||||
/* bu4710 with a dual phy addresses 0 & 1, mdio-connected to enet0 */
|
||||
#define SROM_EPHY_DUAL 0x0001
|
||||
|
||||
/* r1 board with a dual phy at 0, 1 (NOT swapped and mdc0 */
|
||||
#define SROM_EPHY_R1 0x0010
|
||||
|
||||
/* r4 board with a single phy on enet0 at address 5 and a switch */
|
||||
/* chip on enet1 (speciall case: 0x1e */
|
||||
#define SROM_EPHY_R4 0x83e5
|
||||
|
||||
/* 4402 uses an internal phy at phyaddr 1; want mdcport == coreunit == 0 */
|
||||
#define SROM_EPHY_INTERNAL 0x0001
|
||||
|
||||
/* 4307 uses an external phy at phyaddr 0; want mdcport == coreunit == 0 */
|
||||
#define SROM_EPHY_ZERO 0x0000
|
||||
|
||||
#define SROM_VERS 0x0001
|
||||
|
||||
|
||||
#endif /* _SBSPROM_H */
|
||||
|
|
@ -1,211 +0,0 @@
|
|||
/*
|
||||
* Misc utility routines for accessing chip-specific features
|
||||
* of Broadcom HNBU SiliconBackplane-based chips.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _sbutils_h_
|
||||
#define _sbutils_h_
|
||||
|
||||
/*
|
||||
* Data structure to export all chip specific common variables
|
||||
* public (read-only) portion of sbutils handle returned by
|
||||
* sb_attach()/sb_kattach()
|
||||
*/
|
||||
|
||||
struct sb_pub {
|
||||
|
||||
uint bustype; /* SB_BUS, PCI_BUS */
|
||||
uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE */
|
||||
uint buscorerev; /* buscore rev */
|
||||
uint buscoreidx; /* buscore index */
|
||||
int ccrev; /* chip common core rev */
|
||||
uint32 cccaps; /* chip common capabilities */
|
||||
int pmurev; /* pmu core rev */
|
||||
uint32 pmucaps; /* pmu capabilities */
|
||||
uint boardtype; /* board type */
|
||||
uint boardvendor; /* board vendor */
|
||||
uint boardflags; /* board flags */
|
||||
uint chip; /* chip number */
|
||||
uint chiprev; /* chip revision */
|
||||
uint chippkg; /* chip package option */
|
||||
uint32 chipst; /* chip status */
|
||||
uint sonicsrev; /* sonics backplane rev */
|
||||
bool pr42780; /* whether PCIE 42780 WAR applies to this chip */
|
||||
bool pr32414; /* whether 432414 WAR applis to the chip */
|
||||
};
|
||||
|
||||
typedef const struct sb_pub sb_t;
|
||||
|
||||
/*
|
||||
* Many of the routines below take an 'sbh' handle as their first arg.
|
||||
* Allocate this by calling sb_attach(). Free it by calling sb_detach().
|
||||
* At any one time, the sbh is logically focused on one particular sb core
|
||||
* (the "current core").
|
||||
* Use sb_setcore() or sb_setcoreidx() to change the association to another core.
|
||||
*/
|
||||
|
||||
#define SB_OSH NULL /* Use for sb_kattach when no osh is available */
|
||||
|
||||
/* exported externs */
|
||||
extern sb_t *sb_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
|
||||
void *sdh, char **vars, uint *varsz);
|
||||
extern sb_t *sb_kattach(osl_t *osh);
|
||||
extern void sb_detach(sb_t *sbh);
|
||||
extern uint sb_chip(sb_t *sbh);
|
||||
extern uint sb_chiprev(sb_t *sbh);
|
||||
extern uint sb_chipcrev(sb_t *sbh);
|
||||
extern uint sb_chippkg(sb_t *sbh);
|
||||
extern uint sb_pcirev(sb_t *sbh);
|
||||
extern bool sb_war16165(sb_t *sbh);
|
||||
extern uint sb_pcmciarev(sb_t *sbh);
|
||||
extern uint sb_boardvendor(sb_t *sbh);
|
||||
extern uint sb_boardtype(sb_t *sbh);
|
||||
extern uint sb_bus(sb_t *sbh);
|
||||
extern uint sb_buscoretype(sb_t *sbh);
|
||||
extern uint sb_buscorerev(sb_t *sbh);
|
||||
extern uint sb_corelist(sb_t *sbh, uint coreid[]);
|
||||
extern uint sb_coreid(sb_t *sbh);
|
||||
extern uint sb_flag(sb_t *sbh);
|
||||
extern uint sb_coreidx(sb_t *sbh);
|
||||
extern uint sb_coreunit(sb_t *sbh);
|
||||
extern uint sb_corevendor(sb_t *sbh);
|
||||
extern uint sb_corerev(sb_t *sbh);
|
||||
extern void *sb_osh(sb_t *sbh);
|
||||
extern void sb_setosh(sb_t *sbh, osl_t *osh);
|
||||
extern uint sb_corereg(sb_t *sbh, uint coreidx, uint regoff, uint mask, uint val);
|
||||
extern void *sb_coreregs(sb_t *sbh);
|
||||
extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
|
||||
extern void sb_coreflags_wo(sb_t *sbh, uint32 mask, uint32 val);
|
||||
extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
|
||||
extern bool sb_iscoreup(sb_t *sbh);
|
||||
extern uint sb_findcoreidx(sb_t *sbh, uint coreid, uint coreunit);
|
||||
extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
|
||||
extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
|
||||
extern int sb_corebist(sb_t *sbh);
|
||||
extern void sb_commit(sb_t *sbh);
|
||||
extern uint32 sb_base(uint32 admatch);
|
||||
extern uint32 sb_size(uint32 admatch);
|
||||
extern void sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits);
|
||||
extern void sb_core_tofixup(sb_t *sbh);
|
||||
extern void sb_core_disable(sb_t *sbh, uint32 bits);
|
||||
extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
|
||||
extern uint32 sb_clock(sb_t *sbh);
|
||||
extern uint32 sb_alp_clock(sb_t *sbh);
|
||||
extern void sb_pci_setup(sb_t *sbh, uint coremask);
|
||||
extern void sb_pcmcia_init(sb_t *sbh);
|
||||
extern void sb_watchdog(sb_t *sbh, uint ticks);
|
||||
extern void *sb_gpiosetcore(sb_t *sbh);
|
||||
extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
|
||||
extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
|
||||
extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
|
||||
extern uint32 sb_gpioin(sb_t *sbh);
|
||||
extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
|
||||
extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
|
||||
extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
|
||||
extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
|
||||
extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
|
||||
extern uint32 sb_gpiopull(sb_t *sbh, bool updown, uint32 mask, uint32 val);
|
||||
extern uint32 sb_gpioevent(sb_t *sbh, uint regtype, uint32 mask, uint32 val);
|
||||
extern uint32 sb_gpio_int_enable(sb_t *sbh, bool enable);
|
||||
|
||||
/* GPIO event handlers */
|
||||
typedef void (*gpio_handler_t)(uint32 stat, void *arg);
|
||||
|
||||
extern void *sb_gpio_handler_register(sb_t *sbh, uint32 event,
|
||||
bool level, gpio_handler_t cb, void *arg);
|
||||
extern void sb_gpio_handler_unregister(sb_t *sbh, void* gpioh);
|
||||
extern void sb_gpio_handler_process(sb_t *sbh);
|
||||
|
||||
extern void sb_clkctl_init(sb_t *sbh);
|
||||
extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
|
||||
extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
|
||||
extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
|
||||
extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
|
||||
void *intrsenabled_fn, void *intr_arg);
|
||||
extern void sb_deregister_intr_callback(sb_t *sbh);
|
||||
extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to, uint idx);
|
||||
extern uint16 sb_d11_devid(sb_t *sbh);
|
||||
extern int sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
|
||||
uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
|
||||
uint8 *pciheader);
|
||||
extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset);
|
||||
extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val);
|
||||
extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
|
||||
extern bool sb_backplane64(sb_t *sbh);
|
||||
extern void sb_btcgpiowar(sb_t *sbh);
|
||||
|
||||
|
||||
#if defined(BCMDBG_ASSERT)
|
||||
extern bool sb_taclear(sb_t *sbh);
|
||||
#endif
|
||||
|
||||
#ifdef BCMDBG
|
||||
extern void sb_dump(sb_t *sbh, struct bcmstrbuf *b);
|
||||
extern void sb_dumpregs(sb_t *sbh, struct bcmstrbuf *b);
|
||||
extern void sb_view(sb_t *sbh);
|
||||
extern void sb_viewall(sb_t *sbh);
|
||||
extern void sb_clkctl_dump(sb_t *sbh, struct bcmstrbuf *b);
|
||||
extern uint8 sb_pcieL1plldown(sb_t *sbh);
|
||||
extern uint32 sb_pcielcreg(sb_t *sbh, uint32 mask, uint32 val);
|
||||
#endif
|
||||
|
||||
extern bool sb_deviceremoved(sb_t *sbh);
|
||||
extern uint32 sb_socram_size(sb_t *sbh);
|
||||
|
||||
/*
|
||||
* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
|
||||
* The returned path is NULL terminated and has trailing '/'.
|
||||
* Return 0 on success, nonzero otherwise.
|
||||
*/
|
||||
extern int sb_devpath(sb_t *sbh, char *path, int size);
|
||||
/* Read variable with prepending the devpath to the name */
|
||||
extern char *sb_getdevpathvar(sb_t *sbh, const char *name);
|
||||
extern int sb_getdevpathintvar(sb_t *sbh, const char *name);
|
||||
|
||||
extern uint8 sb_pcieclkreq(sb_t *sbh, uint32 mask, uint32 val);
|
||||
extern void sb_war42780_clkreq(sb_t *sbh, bool clkreq);
|
||||
extern void sb_pci_sleep(sb_t *sbh);
|
||||
extern void sb_pci_down(sb_t *sbh);
|
||||
extern void sb_pci_up(sb_t *sbh);
|
||||
|
||||
/* Wake-on-wireless-LAN (WOWL) */
|
||||
extern bool sb_pci_pmecap(sb_t *sbh);
|
||||
extern bool sb_pci_pmeclr(sb_t *sbh);
|
||||
extern void sb_pci_pmeen(sb_t *sbh);
|
||||
|
||||
/* clkctl xtal what flags */
|
||||
#define XTAL 0x1 /* primary crystal oscillator (2050) */
|
||||
#define PLL 0x2 /* main chip pll */
|
||||
|
||||
/* clkctl clk mode */
|
||||
#define CLK_FAST 0 /* force fast (pll) clock */
|
||||
#define CLK_DYNAMIC 2 /* enable dynamic clock control */
|
||||
|
||||
|
||||
/* GPIO usage priorities */
|
||||
#define GPIO_DRV_PRIORITY 0 /* Driver */
|
||||
#define GPIO_APP_PRIORITY 1 /* Application */
|
||||
#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */
|
||||
|
||||
/* GPIO pull up/down */
|
||||
#define GPIO_PULLUP 0
|
||||
#define GPIO_PULLDN 1
|
||||
|
||||
/* GPIO event regtype */
|
||||
#define GPIO_REGEVT 0 /* GPIO register event */
|
||||
#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
|
||||
#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
|
||||
|
||||
/* device path */
|
||||
#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
|
||||
|
||||
#endif /* _sbutils_h_ */
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
/*
|
||||
* Broadcom SiliconBackplane chipcommon serial flash interface
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _sflash_h_
|
||||
#define _sflash_h_
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <sbchipc.h>
|
||||
#include <sbutils.h>
|
||||
|
||||
struct sflash {
|
||||
uint blocksize; /* Block size */
|
||||
uint numblocks; /* Number of blocks */
|
||||
uint32 type; /* Type */
|
||||
uint size; /* Total size in bytes */
|
||||
};
|
||||
|
||||
/* Utility functions */
|
||||
extern int sflash_poll(sb_t *sbh, chipcregs_t *cc, uint offset);
|
||||
extern int sflash_read(sb_t *sbh, chipcregs_t *cc,
|
||||
uint offset, uint len, uchar *buf);
|
||||
extern int sflash_write(sb_t *sbh, chipcregs_t *cc,
|
||||
uint offset, uint len, const uchar *buf);
|
||||
extern int sflash_erase(sb_t *sbh, chipcregs_t *cc, uint offset);
|
||||
extern int sflash_commit(sb_t *sbh, chipcregs_t *cc,
|
||||
uint offset, uint len, const uchar *buf);
|
||||
extern struct sflash *sflash_init(sb_t *sbh, chipcregs_t *cc);
|
||||
|
||||
#endif /* _sflash_h_ */
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
/*
|
||||
* TRX image file header format.
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <typedefs.h>
|
||||
|
||||
#define TRX_MAGIC 0x30524448 /* "HDR0" */
|
||||
#define TRX_VERSION 1 /* Version 1 */
|
||||
#define TRX_MAX_LEN 0x7A0000 /* Max length */
|
||||
#define TRX_NO_HEADER 1 /* Do not write TRX header */
|
||||
#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
|
||||
#define TRX_MAX_OFFSET 3 /* Max number of individual files */
|
||||
|
||||
struct trx_header {
|
||||
uint32 magic; /* "HDR0" */
|
||||
uint32 len; /* Length of file including header */
|
||||
uint32 crc32; /* 32-bit CRC from flag_version to end of file */
|
||||
uint32 flag_version; /* 0:15 flags, 16:31 version */
|
||||
uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
|
||||
};
|
||||
|
||||
/* Compatibility */
|
||||
typedef struct trx_header TRXHDR, *PTRXHDR;
|
||||
|
|
@ -1,373 +0,0 @@
|
|||
/*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _TYPEDEFS_H_
|
||||
#define _TYPEDEFS_H_
|
||||
|
||||
|
||||
/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
|
||||
* typedef file "site_typedefs.h".
|
||||
*
|
||||
* If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
|
||||
* section of this file makes inferences about the compile environment
|
||||
* based on defined symbols and possibly compiler pragmas.
|
||||
*
|
||||
* Following these two sections is the "Default Typedefs"
|
||||
* section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
|
||||
* defined. This section has a default set of typedefs and a few
|
||||
* proprocessor symbols (TRUE, FALSE, NULL, ...).
|
||||
*/
|
||||
|
||||
#ifdef SITE_TYPEDEFS
|
||||
|
||||
/*
|
||||
* Site Specific Typedefs
|
||||
*
|
||||
*/
|
||||
|
||||
#include "site_typedefs.h"
|
||||
|
||||
#else
|
||||
|
||||
/*
|
||||
* Inferred Typedefs
|
||||
*
|
||||
*/
|
||||
|
||||
/* Infer the compile environment based on preprocessor symbols and pramas.
|
||||
* Override type definitions as needed, and include configuration dependent
|
||||
* header files to define types.
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
#define TYPEDEF_BOOL
|
||||
#ifndef FALSE
|
||||
#define FALSE false
|
||||
#endif
|
||||
#ifndef TRUE
|
||||
#define TRUE true
|
||||
#endif
|
||||
|
||||
#else /* ! __cplusplus */
|
||||
|
||||
#if defined(_WIN32)
|
||||
|
||||
#define TYPEDEF_BOOL
|
||||
typedef unsigned char bool; /* consistent w/BOOL */
|
||||
|
||||
#endif /* _WIN32 */
|
||||
|
||||
#endif /* ! __cplusplus */
|
||||
|
||||
/* use the Windows ULONG_PTR type when compiling for 64 bit */
|
||||
#if defined(_WIN64) && !defined(EFI)
|
||||
#include <basetsd.h>
|
||||
#define TYPEDEF_UINTPTR
|
||||
typedef ULONG_PTR uintptr;
|
||||
#elif defined(__x86_64__)
|
||||
#define TYPEDEF_UINTPTR
|
||||
typedef unsigned long long int uintptr;
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(_MINOSL_)
|
||||
#define _NEED_SIZE_T_
|
||||
#endif
|
||||
|
||||
#if defined(EFI) && !defined(_WIN64)
|
||||
#define _NEED_SIZE_T_
|
||||
#endif
|
||||
|
||||
#if defined(_NEED_SIZE_T_)
|
||||
typedef long unsigned int size_t;
|
||||
#endif
|
||||
|
||||
#ifdef __DJGPP__
|
||||
typedef long unsigned int size_t;
|
||||
#endif /* __DJGPP__ */
|
||||
|
||||
#ifdef _MSC_VER /* Microsoft C */
|
||||
#define TYPEDEF_INT64
|
||||
#define TYPEDEF_UINT64
|
||||
typedef signed __int64 int64;
|
||||
typedef unsigned __int64 uint64;
|
||||
#endif
|
||||
|
||||
#if defined(MACOSX)
|
||||
#define TYPEDEF_BOOL
|
||||
#endif
|
||||
|
||||
#if defined(__NetBSD__)
|
||||
#define TYPEDEF_ULONG
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef linux
|
||||
#define TYPEDEF_UINT
|
||||
#define TYPEDEF_USHORT
|
||||
#define TYPEDEF_ULONG
|
||||
#ifdef __KERNEL__
|
||||
#include <linux/version.h>
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19))
|
||||
#define TYPEDEF_BOOL
|
||||
#endif /* >= 2.6.19 */
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* linux */
|
||||
|
||||
#if !defined(linux) && !defined(_WIN32) && !defined(_CFE_) && \
|
||||
!defined(_HNDRTE_) && !defined(_MINOSL_) && !defined(__DJGPP__) && !defined(__IOPOS__)
|
||||
#define TYPEDEF_UINT
|
||||
#define TYPEDEF_USHORT
|
||||
#endif
|
||||
|
||||
|
||||
/* Do not support the (u)int64 types with strict ansi for GNU C */
|
||||
#if defined(__GNUC__) && defined(__STRICT_ANSI__)
|
||||
#define TYPEDEF_INT64
|
||||
#define TYPEDEF_UINT64
|
||||
#endif
|
||||
|
||||
/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
|
||||
* for singned or unsigned
|
||||
*/
|
||||
#if defined(__ICL)
|
||||
|
||||
#define TYPEDEF_INT64
|
||||
|
||||
#if defined(__STDC__)
|
||||
#define TYPEDEF_UINT64
|
||||
#endif
|
||||
|
||||
#endif /* __ICL */
|
||||
|
||||
#if !defined(_WIN32) && !defined(_CFE_) && !defined(_MINOSL_) && \
|
||||
!defined(__DJGPP__) && !defined(__IOPOS__)
|
||||
|
||||
/* pick up ushort & uint from standard types.h */
|
||||
#if defined(linux) && defined(__KERNEL__)
|
||||
|
||||
#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
|
||||
|
||||
#else
|
||||
|
||||
#include <sys/types.h>
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(MACOSX)
|
||||
|
||||
#ifdef __BIG_ENDIAN__
|
||||
#define IL_BIGENDIAN
|
||||
#else
|
||||
#ifdef IL_BIGENDIAN
|
||||
#error "IL_BIGENDIAN was defined for a little-endian compile"
|
||||
#endif
|
||||
#endif /* __BIG_ENDIAN__ */
|
||||
|
||||
#if !defined(__cplusplus)
|
||||
|
||||
#if defined(__i386__)
|
||||
typedef unsigned char bool;
|
||||
#else
|
||||
typedef unsigned int bool;
|
||||
#endif
|
||||
#define TYPE_BOOL 1
|
||||
enum {
|
||||
false = 0,
|
||||
true = 1
|
||||
};
|
||||
|
||||
#if defined(KERNEL)
|
||||
#include <IOKit/IOTypes.h>
|
||||
#endif /* KERNEL */
|
||||
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* MACOSX */
|
||||
|
||||
|
||||
/* use the default typedefs in the next section of this file */
|
||||
#define USE_TYPEDEF_DEFAULTS
|
||||
|
||||
#endif /* SITE_TYPEDEFS */
|
||||
|
||||
|
||||
/*
|
||||
* Default Typedefs
|
||||
*
|
||||
*/
|
||||
|
||||
#ifdef USE_TYPEDEF_DEFAULTS
|
||||
#undef USE_TYPEDEF_DEFAULTS
|
||||
|
||||
#ifndef TYPEDEF_BOOL
|
||||
typedef /* @abstract@ */ unsigned char bool;
|
||||
#endif
|
||||
|
||||
/* define uchar, ushort, uint, ulong */
|
||||
|
||||
#ifndef TYPEDEF_UCHAR
|
||||
typedef unsigned char uchar;
|
||||
#endif
|
||||
|
||||
#ifndef TYPEDEF_USHORT
|
||||
typedef unsigned short ushort;
|
||||
#endif
|
||||
|
||||
#ifndef TYPEDEF_UINT
|
||||
typedef unsigned int uint;
|
||||
#endif
|
||||
|
||||
#ifndef TYPEDEF_ULONG
|
||||
typedef unsigned long ulong;
|
||||
#endif
|
||||
|
||||
/* define [u]int8/16/32/64, uintptr */
|
||||
|
||||
#ifndef TYPEDEF_UINT8
|
||||
typedef unsigned char uint8;
|
||||
#endif
|
||||
|
||||
#ifndef TYPEDEF_UINT16
|
||||
typedef unsigned short uint16;
|
||||
#endif
|
||||
|
||||
#ifndef TYPEDEF_UINT32
|
||||
typedef unsigned int uint32;
|
||||
#endif
|
||||
|
||||
#ifndef TYPEDEF_UINT64
|
||||
typedef unsigned long long uint64;
|
||||
#endif
|
||||
|
||||
#ifndef TYPEDEF_UINTPTR
|
||||
typedef unsigned int uintptr;
|
||||
#endif
|
||||
|
||||
#ifndef TYPEDEF_INT8
|
||||
typedef signed char int8;
|
||||
#endif
|
||||
|
||||
#ifndef TYPEDEF_INT16
|
||||
typedef signed short int16;
|
||||
#endif
|
||||
|
||||
#ifndef TYPEDEF_INT32
|
||||
typedef signed int int32;
|
||||
#endif
|
||||
|
||||
#ifndef TYPEDEF_INT64
|
||||
typedef signed long long int64;
|
||||
#endif
|
||||
|
||||
/* define float32/64, float_t */
|
||||
|
||||
#ifndef TYPEDEF_FLOAT32
|
||||
typedef float float32;
|
||||
#endif
|
||||
|
||||
#ifndef TYPEDEF_FLOAT64
|
||||
typedef double float64;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* abstracted floating point type allows for compile time selection of
|
||||
* single or double precision arithmetic. Compiling with -DFLOAT32
|
||||
* selects single precision; the default is double precision.
|
||||
*/
|
||||
|
||||
#ifndef TYPEDEF_FLOAT_T
|
||||
|
||||
#if defined(FLOAT32)
|
||||
typedef float32 float_t;
|
||||
#else /* default to double precision floating point */
|
||||
typedef float64 float_t;
|
||||
#endif
|
||||
|
||||
#endif /* TYPEDEF_FLOAT_T */
|
||||
|
||||
/* define macro values */
|
||||
|
||||
#ifndef FALSE
|
||||
#define FALSE 0
|
||||
#endif
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE 1 /* TRUE */
|
||||
#endif
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0
|
||||
#endif
|
||||
|
||||
#ifndef OFF
|
||||
#define OFF 0
|
||||
#endif
|
||||
|
||||
#ifndef ON
|
||||
#define ON 1 /* ON = 1 */
|
||||
#endif
|
||||
|
||||
#define AUTO (-1) /* Auto = -1 */
|
||||
|
||||
/* define PTRSZ, INLINE */
|
||||
|
||||
#ifndef PTRSZ
|
||||
#define PTRSZ sizeof(char*)
|
||||
#endif
|
||||
|
||||
#ifndef INLINE
|
||||
|
||||
#ifdef _MSC_VER
|
||||
|
||||
#define INLINE __inline
|
||||
|
||||
#elif defined(__GNUC__)
|
||||
|
||||
#define INLINE __inline__
|
||||
|
||||
#else
|
||||
|
||||
#define INLINE
|
||||
|
||||
#endif /* _MSC_VER */
|
||||
|
||||
#endif /* INLINE */
|
||||
|
||||
#undef TYPEDEF_BOOL
|
||||
#undef TYPEDEF_UCHAR
|
||||
#undef TYPEDEF_USHORT
|
||||
#undef TYPEDEF_UINT
|
||||
#undef TYPEDEF_ULONG
|
||||
#undef TYPEDEF_UINT8
|
||||
#undef TYPEDEF_UINT16
|
||||
#undef TYPEDEF_UINT32
|
||||
#undef TYPEDEF_UINT64
|
||||
#undef TYPEDEF_UINTPTR
|
||||
#undef TYPEDEF_INT8
|
||||
#undef TYPEDEF_INT16
|
||||
#undef TYPEDEF_INT32
|
||||
#undef TYPEDEF_INT64
|
||||
#undef TYPEDEF_FLOAT32
|
||||
#undef TYPEDEF_FLOAT64
|
||||
#undef TYPEDEF_FLOAT_T
|
||||
|
||||
#endif /* USE_TYPEDEF_DEFAULTS */
|
||||
|
||||
/*
|
||||
* Including the bcmdefs.h here, to make sure everyone including typedefs.h
|
||||
* gets this automatically
|
||||
*/
|
||||
#include "bcmdefs.h"
|
||||
|
||||
#endif /* _TYPEDEFS_H_ */
|
||||
|
|
@ -1,252 +0,0 @@
|
|||
/*
|
||||
* NVRAM variable manipulation (Linux kernel half)
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/wrapper.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/miscdevice.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <osl.h>
|
||||
#include <bcmendian.h>
|
||||
#include <bcmnvram.h>
|
||||
#include <sbconfig.h>
|
||||
#include <sbchipc.h>
|
||||
#include <sbutils.h>
|
||||
#include <hndmips.h>
|
||||
#include <sflash.h>
|
||||
|
||||
/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
|
||||
static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
|
||||
|
||||
/* Global SB handle */
|
||||
extern void *bcm947xx_sbh;
|
||||
extern spinlock_t bcm947xx_sbh_lock;
|
||||
|
||||
static int cfe_env;
|
||||
extern char *cfe_env_get(char *nv_buf, const char *name);
|
||||
|
||||
/* Convenience */
|
||||
#define sbh bcm947xx_sbh
|
||||
#define sbh_lock bcm947xx_sbh_lock
|
||||
|
||||
/* Probe for NVRAM header */
|
||||
static void __init
|
||||
early_nvram_init(void)
|
||||
{
|
||||
struct nvram_header *header;
|
||||
chipcregs_t *cc;
|
||||
struct sflash *info = NULL;
|
||||
int i;
|
||||
uint32 base, off, lim;
|
||||
u32 *src, *dst;
|
||||
|
||||
if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
|
||||
base = KSEG1ADDR(SB_FLASH2);
|
||||
switch (readl(&cc->capabilities) & CC_CAP_FLASH_MASK) {
|
||||
case PFLASH:
|
||||
lim = SB_FLASH2_SZ;
|
||||
break;
|
||||
|
||||
case SFLASH_ST:
|
||||
case SFLASH_AT:
|
||||
if ((info = sflash_init(sbh,cc)) == NULL)
|
||||
return;
|
||||
lim = info->size;
|
||||
break;
|
||||
|
||||
case FLASH_NONE:
|
||||
default:
|
||||
return;
|
||||
}
|
||||
} else {
|
||||
/* extif assumed, Stop at 4 MB */
|
||||
base = KSEG1ADDR(SB_FLASH1);
|
||||
lim = SB_FLASH1_SZ;
|
||||
}
|
||||
|
||||
/* XXX: hack for supporting the CFE environment stuff on WGT634U */
|
||||
src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
|
||||
dst = (u32 *) nvram_buf;
|
||||
if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
|
||||
printk("early_nvram_init: WGT634U NVRAM found.\n");
|
||||
|
||||
for (i = 0; i < 0x1ff0; i++) {
|
||||
if (*src == 0xFFFFFFFF)
|
||||
break;
|
||||
*dst++ = *src++;
|
||||
}
|
||||
cfe_env = 1;
|
||||
return;
|
||||
}
|
||||
|
||||
off = FLASH_MIN;
|
||||
while (off <= lim) {
|
||||
/* Windowed flash access */
|
||||
header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
|
||||
if (header->magic == NVRAM_MAGIC)
|
||||
goto found;
|
||||
off <<= 1;
|
||||
}
|
||||
|
||||
/* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
|
||||
header = (struct nvram_header *) KSEG1ADDR(base + 4 * 1024);
|
||||
if (header->magic == NVRAM_MAGIC)
|
||||
goto found;
|
||||
|
||||
header = (struct nvram_header *) KSEG1ADDR(base + 1 * 1024);
|
||||
if (header->magic == NVRAM_MAGIC)
|
||||
goto found;
|
||||
|
||||
printk("early_nvram_init: NVRAM not found\n");
|
||||
return;
|
||||
|
||||
found:
|
||||
src = (u32 *) header;
|
||||
dst = (u32 *) nvram_buf;
|
||||
for (i = 0; i < sizeof(struct nvram_header); i += 4)
|
||||
*dst++ = *src++;
|
||||
for (; i < header->len && i < NVRAM_SPACE; i += 4)
|
||||
*dst++ = ltoh32(*src++);
|
||||
}
|
||||
|
||||
/* Early (before mm or mtd) read-only access to NVRAM */
|
||||
static char * __init
|
||||
early_nvram_get(const char *name)
|
||||
{
|
||||
char *var, *value, *end, *eq;
|
||||
|
||||
if (!name)
|
||||
return NULL;
|
||||
|
||||
/* Too early? */
|
||||
if (sbh == NULL)
|
||||
return NULL;
|
||||
|
||||
if (!nvram_buf[0])
|
||||
early_nvram_init();
|
||||
|
||||
if (cfe_env)
|
||||
return cfe_env_get(nvram_buf, name);
|
||||
|
||||
/* Look for name=value and return value */
|
||||
var = &nvram_buf[sizeof(struct nvram_header)];
|
||||
end = nvram_buf + sizeof(nvram_buf) - 2;
|
||||
end[0] = end[1] = '\0';
|
||||
for (; *var; var = value + strlen(value) + 1) {
|
||||
if (!(eq = strchr(var, '=')))
|
||||
break;
|
||||
value = eq + 1;
|
||||
if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
|
||||
return value;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int __init
|
||||
early_nvram_getall(char *buf, int count)
|
||||
{
|
||||
char *var, *end;
|
||||
int len = 0;
|
||||
|
||||
/* Too early? */
|
||||
if (sbh == NULL)
|
||||
return -1;
|
||||
|
||||
if (!nvram_buf[0])
|
||||
early_nvram_init();
|
||||
|
||||
bzero(buf, count);
|
||||
|
||||
/* Write name=value\0 ... \0\0 */
|
||||
var = &nvram_buf[sizeof(struct nvram_header)];
|
||||
end = nvram_buf + sizeof(nvram_buf) - 2;
|
||||
end[0] = end[1] = '\0';
|
||||
for (; *var; var += strlen(var) + 1) {
|
||||
if ((count - len) <= (strlen(var) + 1))
|
||||
break;
|
||||
len += sprintf(buf + len, "%s", var) + 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
char *
|
||||
nvram_get(const char *name)
|
||||
{
|
||||
return early_nvram_get(name);
|
||||
}
|
||||
|
||||
int
|
||||
nvram_getall(char *buf, int count)
|
||||
{
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
return early_nvram_getall(buf, count);
|
||||
}
|
||||
|
||||
/*
|
||||
* Search the name=value vars for a specific one and return its value.
|
||||
* Returns NULL if not found.
|
||||
*/
|
||||
char*
|
||||
getvar(char *vars, const char *name)
|
||||
{
|
||||
char *s;
|
||||
int len;
|
||||
|
||||
len = strlen(name);
|
||||
|
||||
/* first look in vars[] */
|
||||
for (s = vars; s && *s;) {
|
||||
/* CSTYLED */
|
||||
if ((memcmp(s, name, len) == 0) && (s[len] == '='))
|
||||
return (&s[len+1]);
|
||||
|
||||
while (*s++);
|
||||
}
|
||||
|
||||
/* then query nvram */
|
||||
return (nvram_get(name));
|
||||
}
|
||||
|
||||
/*
|
||||
* Search the vars for a specific one and return its value as
|
||||
* an integer. Returns 0 if not found.
|
||||
*/
|
||||
int
|
||||
getintvar(char *vars, const char *name)
|
||||
{
|
||||
char *val;
|
||||
|
||||
if ((val = getvar(vars, name)) == NULL)
|
||||
return (0);
|
||||
|
||||
return (simple_strtoul(val, NULL, 0));
|
||||
}
|
||||
|
||||
|
|
@ -1,414 +0,0 @@
|
|||
/*
|
||||
* Low-Level PCI and SB support for BCM47xx (Linux support code)
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/paccess.h>
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <osl.h>
|
||||
#include <sbconfig.h>
|
||||
#include <sbutils.h>
|
||||
#include <hndpci.h>
|
||||
#include <pcicfg.h>
|
||||
#include <bcmdevs.h>
|
||||
#include <bcmnvram.h>
|
||||
|
||||
/* Global SB handle */
|
||||
extern sb_t *bcm947xx_sbh;
|
||||
extern spinlock_t bcm947xx_sbh_lock;
|
||||
|
||||
/* Convenience */
|
||||
#define sbh bcm947xx_sbh
|
||||
#define sbh_lock bcm947xx_sbh_lock
|
||||
|
||||
static int
|
||||
sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
|
||||
{
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
spin_lock_irqsave(&sbh_lock, flags);
|
||||
ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
|
||||
PCI_FUNC(dev->devfn), where, value, sizeof(*value));
|
||||
spin_unlock_irqrestore(&sbh_lock, flags);
|
||||
return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static int
|
||||
sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
|
||||
{
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
spin_lock_irqsave(&sbh_lock, flags);
|
||||
ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
|
||||
PCI_FUNC(dev->devfn), where, value, sizeof(*value));
|
||||
spin_unlock_irqrestore(&sbh_lock, flags);
|
||||
return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static int
|
||||
sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
|
||||
{
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
spin_lock_irqsave(&sbh_lock, flags);
|
||||
ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
|
||||
PCI_FUNC(dev->devfn), where, value, sizeof(*value));
|
||||
spin_unlock_irqrestore(&sbh_lock, flags);
|
||||
return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static int
|
||||
sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
|
||||
{
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
spin_lock_irqsave(&sbh_lock, flags);
|
||||
ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
|
||||
PCI_FUNC(dev->devfn), where, &value, sizeof(value));
|
||||
spin_unlock_irqrestore(&sbh_lock, flags);
|
||||
return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static int
|
||||
sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
|
||||
{
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
spin_lock_irqsave(&sbh_lock, flags);
|
||||
ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
|
||||
PCI_FUNC(dev->devfn), where, &value, sizeof(value));
|
||||
spin_unlock_irqrestore(&sbh_lock, flags);
|
||||
return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static int
|
||||
sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
|
||||
{
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
spin_lock_irqsave(&sbh_lock, flags);
|
||||
ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
|
||||
PCI_FUNC(dev->devfn), where, &value, sizeof(value));
|
||||
spin_unlock_irqrestore(&sbh_lock, flags);
|
||||
return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static struct pci_ops pcibios_ops = {
|
||||
sbpci_read_config_byte,
|
||||
sbpci_read_config_word,
|
||||
sbpci_read_config_dword,
|
||||
sbpci_write_config_byte,
|
||||
sbpci_write_config_word,
|
||||
sbpci_write_config_dword
|
||||
};
|
||||
|
||||
|
||||
void __init
|
||||
pcibios_init(void)
|
||||
{
|
||||
ulong flags;
|
||||
|
||||
if (!(sbh = sb_kattach(SB_OSH)))
|
||||
panic("sb_kattach failed");
|
||||
spin_lock_init(&sbh_lock);
|
||||
|
||||
spin_lock_irqsave(&sbh_lock, flags);
|
||||
sbpci_init(sbh);
|
||||
spin_unlock_irqrestore(&sbh_lock, flags);
|
||||
|
||||
set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
|
||||
mdelay(300); /* workaround for atheros cards */
|
||||
|
||||
/* Scan the SB bus */
|
||||
pci_scan_bus(0, &pcibios_ops, NULL);
|
||||
|
||||
}
|
||||
|
||||
char * __init
|
||||
pcibios_setup(char *str)
|
||||
{
|
||||
if (!strncmp(str, "ban=", 4)) {
|
||||
sbpci_ban(simple_strtoul(str + 4, NULL, 0));
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return (str);
|
||||
}
|
||||
|
||||
static u32 pci_iobase = 0x100;
|
||||
static u32 pci_membase = SB_PCI_DMA;
|
||||
static u32 pcmcia_membase = 0x40004000;
|
||||
|
||||
void __init
|
||||
pcibios_fixup_bus(struct pci_bus *b)
|
||||
{
|
||||
struct list_head *ln;
|
||||
struct pci_dev *d;
|
||||
struct resource *res;
|
||||
int pos, size;
|
||||
u32 *base;
|
||||
u8 irq;
|
||||
|
||||
printk("PCI: Fixing up bus %d\n", b->number);
|
||||
|
||||
/* Fix up SB */
|
||||
if (b->number == 0) {
|
||||
for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
|
||||
d = pci_dev_b(ln);
|
||||
/* Fix up interrupt lines */
|
||||
pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
|
||||
d->irq = irq + 2;
|
||||
pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
|
||||
}
|
||||
}
|
||||
|
||||
/* Fix up external PCI */
|
||||
else {
|
||||
for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
|
||||
d = pci_dev_b(ln);
|
||||
/* Fix up resource bases */
|
||||
for (pos = 0; pos < 6; pos++) {
|
||||
res = &d->resource[pos];
|
||||
base = (res->flags & IORESOURCE_IO) ? &pci_iobase : ((b->number == 2) ? &pcmcia_membase : &pci_membase);
|
||||
if (res->end) {
|
||||
size = res->end - res->start + 1;
|
||||
if (*base & (size - 1))
|
||||
*base = (*base + size) & ~(size - 1);
|
||||
res->start = *base;
|
||||
res->end = res->start + size - 1;
|
||||
*base += size;
|
||||
pci_write_config_dword(d,
|
||||
PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
|
||||
}
|
||||
/* Fix up PCI bridge BAR0 only */
|
||||
if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
|
||||
break;
|
||||
}
|
||||
/* Fix up interrupt lines */
|
||||
if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
|
||||
d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
|
||||
pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
unsigned int
|
||||
pcibios_assign_all_busses(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
void
|
||||
pcibios_align_resource(void *data, struct resource *res,
|
||||
unsigned long size, unsigned long align)
|
||||
{
|
||||
}
|
||||
|
||||
int
|
||||
pcibios_enable_resources(struct pci_dev *dev)
|
||||
{
|
||||
u16 cmd, old_cmd;
|
||||
int idx;
|
||||
struct resource *r;
|
||||
|
||||
/* External PCI only */
|
||||
if (dev->bus->number == 0)
|
||||
return 0;
|
||||
|
||||
pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
||||
old_cmd = cmd;
|
||||
for (idx = 0; idx < 6; idx++) {
|
||||
r = &dev->resource[idx];
|
||||
if (r->flags & IORESOURCE_IO)
|
||||
cmd |= PCI_COMMAND_IO;
|
||||
if (r->flags & IORESOURCE_MEM)
|
||||
cmd |= PCI_COMMAND_MEMORY;
|
||||
}
|
||||
if (dev->resource[PCI_ROM_RESOURCE].start)
|
||||
cmd |= PCI_COMMAND_MEMORY;
|
||||
if (cmd != old_cmd) {
|
||||
printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
|
||||
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
pcibios_enable_device(struct pci_dev *dev, int mask)
|
||||
{
|
||||
ulong flags;
|
||||
uint coreidx;
|
||||
void *regs;
|
||||
|
||||
/* External PCI device enable */
|
||||
if (dev->bus->number != 0)
|
||||
return pcibios_enable_resources(dev);
|
||||
|
||||
/* These cores come out of reset enabled */
|
||||
if (dev->device == SB_MIPS ||
|
||||
dev->device == SB_MIPS33 ||
|
||||
dev->device == SB_EXTIF ||
|
||||
dev->device == SB_CC)
|
||||
return 0;
|
||||
|
||||
spin_lock_irqsave(&sbh_lock, flags);
|
||||
coreidx = sb_coreidx(sbh);
|
||||
regs = sb_setcoreidx(sbh, PCI_SLOT(dev->devfn));
|
||||
if (!regs)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
/*
|
||||
* The USB core requires a special bit to be set during core
|
||||
* reset to enable host (OHCI) mode. Resetting the SB core in
|
||||
* pcibios_enable_device() is a hack for compatibility with
|
||||
* vanilla usb-ohci so that it does not have to know about
|
||||
* SB. A driver that wants to use the USB core in device mode
|
||||
* should know about SB and should reset the bit back to 0
|
||||
* after calling pcibios_enable_device().
|
||||
*/
|
||||
if (sb_coreid(sbh) == SB_USB) {
|
||||
printk(KERN_INFO "SB USB 1.1 init\n");
|
||||
sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
|
||||
sb_core_reset(sbh, 1 << 29, 0);
|
||||
}
|
||||
/*
|
||||
* USB 2.0 special considerations:
|
||||
*
|
||||
* 1. Since the core supports both OHCI and EHCI functions, it must
|
||||
* only be reset once.
|
||||
*
|
||||
* 2. In addition to the standard SB reset sequence, the Host Control
|
||||
* Register must be programmed to bring the USB core and various
|
||||
* phy components out of reset.
|
||||
*/
|
||||
else if (sb_coreid(sbh) == SB_USB20H) {
|
||||
|
||||
uint corerev = sb_corerev(sbh);
|
||||
|
||||
printk(KERN_INFO "SB USB20H init\n");
|
||||
printk(KERN_INFO "SB COREREV: %d\n", corerev);
|
||||
|
||||
if (!sb_iscoreup(sbh)) {
|
||||
|
||||
printk(KERN_INFO "SB USB20H resetting\n");
|
||||
|
||||
sb_core_reset(sbh, 0, 0);
|
||||
writel(0x7FF, (ulong)regs + 0x200);
|
||||
udelay(1);
|
||||
}
|
||||
/* PRxxxx: War for 5354 failures. */
|
||||
if (corerev == 1 || corerev == 2) {
|
||||
uint32 tmp;
|
||||
|
||||
/* Change Flush control reg */
|
||||
tmp = readl((uintptr)regs + 0x400);
|
||||
tmp &= ~8;
|
||||
writel(tmp, (uintptr)regs + 0x400);
|
||||
tmp = readl((uintptr)regs + 0x400);
|
||||
printk(KERN_INFO "USB20H fcr: 0x%x\n", tmp);
|
||||
|
||||
/* Change Shim control reg */
|
||||
tmp = readl((uintptr)regs + 0x304);
|
||||
tmp &= ~0x100;
|
||||
writel(tmp, (uintptr)regs + 0x304);
|
||||
tmp = readl((uintptr)regs + 0x304);
|
||||
printk(KERN_INFO "USB20H shim cr: 0x%x\n", tmp);
|
||||
}
|
||||
|
||||
} else
|
||||
sb_core_reset(sbh, 0, 0);
|
||||
|
||||
sb_setcoreidx(sbh, coreidx);
|
||||
spin_unlock_irqrestore(&sbh_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
|
||||
struct resource *res, int resource)
|
||||
{
|
||||
unsigned long where, size;
|
||||
u32 reg;
|
||||
|
||||
/* External PCI only */
|
||||
if (dev->bus->number == 0)
|
||||
return;
|
||||
|
||||
where = PCI_BASE_ADDRESS_0 + (resource * 4);
|
||||
size = res->end - res->start;
|
||||
pci_read_config_dword(dev, where, ®);
|
||||
|
||||
if (dev->bus->number == 1)
|
||||
reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
|
||||
else
|
||||
reg = res->start;
|
||||
|
||||
pci_write_config_dword(dev, where, reg);
|
||||
}
|
||||
|
||||
static void __init
|
||||
quirk_sbpci_bridge(struct pci_dev *dev)
|
||||
{
|
||||
if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
|
||||
return;
|
||||
|
||||
printk("PCI: Fixing up bridge\n");
|
||||
|
||||
/* Enable PCI bridge bus mastering and memory space */
|
||||
pci_set_master(dev);
|
||||
pcibios_enable_resources(dev);
|
||||
|
||||
/* Enable PCI bridge BAR1 prefetch and burst */
|
||||
pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
|
||||
}
|
||||
|
||||
struct pci_fixup pcibios_fixups[] = {
|
||||
{ PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
/*
|
||||
* If we set up a device for bus mastering, we need to check the latency
|
||||
* timer as certain crappy BIOSes forget to set it properly.
|
||||
*/
|
||||
unsigned int pcibios_max_latency = 255;
|
||||
|
||||
void pcibios_set_master(struct pci_dev *dev)
|
||||
{
|
||||
u8 lat;
|
||||
pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
|
||||
if (lat < 16)
|
||||
lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
|
||||
else if (lat > pcibios_max_latency)
|
||||
lat = pcibios_max_latency;
|
||||
else
|
||||
return;
|
||||
printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
|
||||
pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
|
||||
}
|
||||
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
/*
|
||||
* Early initialization code for BCM94710 boards
|
||||
*
|
||||
* Copyright 2004, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/bootinfo.h>
|
||||
|
||||
void __init
|
||||
prom_init(int argc, const char **argv)
|
||||
{
|
||||
unsigned long mem;
|
||||
unsigned long max;
|
||||
|
||||
mips_machgroup = MACH_GROUP_BRCM;
|
||||
mips_machtype = MACH_BCM947XX;
|
||||
|
||||
/* Figure out memory size by finding aliases
|
||||
*
|
||||
* BCM47XX uses 128MB for addressing the ram, if the system contains
|
||||
* less that that amount of ram it remaps the ram more often into the
|
||||
* available space.
|
||||
* Accessing memory after 128MB will cause an exception.
|
||||
* max contains the biggest possible address supported by the platform.
|
||||
* If the method wants to try something above we assume 128MB ram.
|
||||
*/
|
||||
max = ((unsigned long)(prom_init) | ((128 << 20) - 1));
|
||||
for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
|
||||
if (((unsigned long)(prom_init) + mem) > max) {
|
||||
mem = (128 << 20);
|
||||
printk("assume 128MB RAM\n");
|
||||
break;
|
||||
}
|
||||
if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
|
||||
*(unsigned long *)(prom_init))
|
||||
break;
|
||||
}
|
||||
|
||||
add_memory_region(0, mem, BOOT_MEM_RAM);
|
||||
}
|
||||
|
||||
void __init
|
||||
prom_free_prom_memory(void)
|
||||
{
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,780 +0,0 @@
|
|||
/*
|
||||
* Low-Level PCI and SB support for BCM47xx
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <osl.h>
|
||||
#include <pcicfg.h>
|
||||
#include <bcmdevs.h>
|
||||
#include <sbconfig.h>
|
||||
#include <sbutils.h>
|
||||
#include <sbpci.h>
|
||||
#include <bcmendian.h>
|
||||
#include <bcmnvram.h>
|
||||
#include <hndcpu.h>
|
||||
#include <hndmips.h>
|
||||
#include <hndpci.h>
|
||||
|
||||
/* debug/trace */
|
||||
#ifdef BCMDBG_PCI
|
||||
#define PCI_MSG(args) printf args
|
||||
#else
|
||||
#define PCI_MSG(args)
|
||||
#endif /* BCMDBG_PCI */
|
||||
|
||||
/* Can free sbpci_init() memory after boot */
|
||||
#ifndef linux
|
||||
#define __init
|
||||
#endif /* linux */
|
||||
|
||||
/* Emulated configuration space */
|
||||
typedef struct {
|
||||
int n;
|
||||
uint size0;
|
||||
uint size1;
|
||||
uint size2;
|
||||
uint size3;
|
||||
} sb_bar_cfg_t;
|
||||
static pci_config_regs sb_config_regs[SB_MAXCORES];
|
||||
static sb_bar_cfg_t sb_bar_cfg[SB_MAXCORES];
|
||||
|
||||
/* Links to emulated and real PCI configuration spaces */
|
||||
#define MAXFUNCS 2
|
||||
typedef struct {
|
||||
pci_config_regs *emu; /* emulated PCI config */
|
||||
pci_config_regs *pci; /* real PCI config */
|
||||
sb_bar_cfg_t *bar; /* region sizes */
|
||||
} sb_pci_cfg_t;
|
||||
static sb_pci_cfg_t sb_pci_cfg[SB_MAXCORES][MAXFUNCS];
|
||||
|
||||
/* Special emulated config space for non-existing device */
|
||||
static pci_config_regs sb_pci_null = { 0xffff, 0xffff };
|
||||
|
||||
/* Banned cores */
|
||||
static uint16 pci_ban[SB_MAXCORES] = { 0 };
|
||||
static uint pci_banned = 0;
|
||||
|
||||
/* CardBus mode */
|
||||
static bool cardbus = FALSE;
|
||||
|
||||
/* Disable PCI host core */
|
||||
static bool pci_disabled = FALSE;
|
||||
|
||||
/* Host bridge slot #, default to 0 */
|
||||
static uint8 pci_hbslot = 0;
|
||||
|
||||
/* Internal macros */
|
||||
#define PCI_SLOTAD_MAP 16 /* SLOT<n> mapps to AD<n+16> */
|
||||
#define PCI_HBSBCFG_REV 8 /* MIN. core rev. required to
|
||||
* access host bridge PCI cfg space
|
||||
* from SB
|
||||
*/
|
||||
|
||||
/*
|
||||
* Functions for accessing external PCI configuration space
|
||||
*/
|
||||
|
||||
/* Assume one-hot slot wiring */
|
||||
#define PCI_SLOT_MAX 16 /* Max. PCI Slots */
|
||||
|
||||
static uint32 config_cmd(sb_t * sbh, uint bus, uint dev, uint func, uint off)
|
||||
{
|
||||
uint coreidx;
|
||||
sbpciregs_t *regs;
|
||||
uint32 addr = 0;
|
||||
osl_t *osh;
|
||||
|
||||
/* CardBusMode supports only one device */
|
||||
if (cardbus && dev > 1)
|
||||
return 0;
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
|
||||
coreidx = sb_coreidx(sbh);
|
||||
regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
|
||||
|
||||
/* Type 0 transaction */
|
||||
if (bus == 1) {
|
||||
/* Skip unwired slots */
|
||||
if (dev < PCI_SLOT_MAX) {
|
||||
uint32 win;
|
||||
|
||||
/* Slide the PCI window to the appropriate slot */
|
||||
win =
|
||||
(SBTOPCI_CFG0 |
|
||||
((1 << (dev + PCI_SLOTAD_MAP)) & SBTOPCI1_MASK));
|
||||
W_REG(osh, ®s->sbtopci1, win);
|
||||
addr = SB_PCI_CFG |
|
||||
((1 << (dev + PCI_SLOTAD_MAP)) & ~SBTOPCI1_MASK) |
|
||||
(func << PCICFG_FUN_SHIFT) | (off & ~3);
|
||||
}
|
||||
} else {
|
||||
/* Type 1 transaction */
|
||||
W_REG(osh, ®s->sbtopci1, SBTOPCI_CFG1);
|
||||
addr = SB_PCI_CFG |
|
||||
(bus << PCICFG_BUS_SHIFT) |
|
||||
(dev << PCICFG_SLOT_SHIFT) |
|
||||
(func << PCICFG_FUN_SHIFT) | (off & ~3);
|
||||
}
|
||||
|
||||
sb_setcoreidx(sbh, coreidx);
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read host bridge PCI config registers from Silicon Backplane (>=rev8).
|
||||
*
|
||||
* It returns TRUE to indicate that access to the host bridge's pci config
|
||||
* from SB is ok, and values in 'addr' and 'val' are valid.
|
||||
*
|
||||
* It can only read registers at multiple of 4-bytes. Callers must pick up
|
||||
* needed bytes from 'val' based on 'off' value. Value in 'addr' reflects
|
||||
* the register address where value in 'val' is read.
|
||||
*/
|
||||
static bool
|
||||
sb_pcihb_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
|
||||
uint32 ** addr, uint32 * val)
|
||||
{
|
||||
sbpciregs_t *regs;
|
||||
osl_t *osh;
|
||||
uint coreidx;
|
||||
bool ret = FALSE;
|
||||
|
||||
/* sanity check */
|
||||
ASSERT(bus == 1);
|
||||
ASSERT(dev == pci_hbslot);
|
||||
ASSERT(func == 0);
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
|
||||
/* read pci config when core rev >= 8 */
|
||||
coreidx = sb_coreidx(sbh);
|
||||
regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
|
||||
if (regs && sb_corerev(sbh) >= PCI_HBSBCFG_REV) {
|
||||
*addr = (uint32 *) & regs->pcicfg[func][off >> 2];
|
||||
*val = R_REG(osh, *addr);
|
||||
ret = TRUE;
|
||||
}
|
||||
sb_setcoreidx(sbh, coreidx);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int
|
||||
extpci_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
|
||||
void *buf, int len)
|
||||
{
|
||||
uint32 addr = 0, *reg = NULL, val;
|
||||
int ret = 0;
|
||||
|
||||
/*
|
||||
* Set value to -1 when:
|
||||
* flag 'pci_disabled' is true;
|
||||
* value of 'addr' is zero;
|
||||
* REG_MAP() fails;
|
||||
* BUSPROBE() fails;
|
||||
*/
|
||||
if (pci_disabled)
|
||||
val = 0xffffffff;
|
||||
else if (bus == 1 && dev == pci_hbslot && func == 0 &&
|
||||
sb_pcihb_read_config(sbh, bus, dev, func, off, ®, &val)) ;
|
||||
else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
|
||||
((reg = (uint32 *) REG_MAP(addr, len)) == 0) ||
|
||||
(BUSPROBE(val, reg) != 0))
|
||||
val = 0xffffffff;
|
||||
|
||||
PCI_MSG(("%s: 0x%x <= 0x%p(0x%x), len %d, off 0x%x, buf 0x%p\n",
|
||||
__FUNCTION__, val, reg, addr, len, off, buf));
|
||||
|
||||
val >>= 8 * (off & 3);
|
||||
if (len == 4)
|
||||
*((uint32 *) buf) = val;
|
||||
else if (len == 2)
|
||||
*((uint16 *) buf) = (uint16) val;
|
||||
else if (len == 1)
|
||||
*((uint8 *) buf) = (uint8) val;
|
||||
else
|
||||
ret = -1;
|
||||
|
||||
if (reg && addr)
|
||||
REG_UNMAP(reg);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int
|
||||
extpci_write_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
|
||||
void *buf, int len)
|
||||
{
|
||||
osl_t *osh;
|
||||
uint32 addr = 0, *reg = NULL, val;
|
||||
int ret = 0;
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
|
||||
/*
|
||||
* Ignore write attempt when:
|
||||
* flag 'pci_disabled' is true;
|
||||
* value of 'addr' is zero;
|
||||
* REG_MAP() fails;
|
||||
* BUSPROBE() fails;
|
||||
*/
|
||||
if (pci_disabled)
|
||||
return 0;
|
||||
else if (bus == 1 && dev == pci_hbslot && func == 0 &&
|
||||
sb_pcihb_read_config(sbh, bus, dev, func, off, ®, &val)) ;
|
||||
else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
|
||||
((reg = (uint32 *) REG_MAP(addr, len)) == 0) ||
|
||||
(BUSPROBE(val, reg) != 0))
|
||||
goto done;
|
||||
|
||||
if (len == 4)
|
||||
val = *((uint32 *) buf);
|
||||
else if (len == 2) {
|
||||
val &= ~(0xffff << (8 * (off & 3)));
|
||||
val |= *((uint16 *) buf) << (8 * (off & 3));
|
||||
} else if (len == 1) {
|
||||
val &= ~(0xff << (8 * (off & 3)));
|
||||
val |= *((uint8 *) buf) << (8 * (off & 3));
|
||||
} else {
|
||||
ret = -1;
|
||||
goto done;
|
||||
}
|
||||
|
||||
PCI_MSG(("%s: 0x%x => 0x%p\n", __FUNCTION__, val, reg));
|
||||
|
||||
W_REG(osh, reg, val);
|
||||
|
||||
done:
|
||||
if (reg && addr)
|
||||
REG_UNMAP(reg);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Must access emulated PCI configuration at these locations even when
|
||||
* the real PCI config space exists and is accessible.
|
||||
*
|
||||
* PCI_CFG_VID (0x00)
|
||||
* PCI_CFG_DID (0x02)
|
||||
* PCI_CFG_PROGIF (0x09)
|
||||
* PCI_CFG_SUBCL (0x0a)
|
||||
* PCI_CFG_BASECL (0x0b)
|
||||
* PCI_CFG_HDR (0x0e)
|
||||
* PCI_CFG_INT (0x3c)
|
||||
* PCI_CFG_PIN (0x3d)
|
||||
*/
|
||||
#define FORCE_EMUCFG(off, len) \
|
||||
((off == PCI_CFG_VID) || (off == PCI_CFG_DID) || \
|
||||
(off == PCI_CFG_PROGIF) || \
|
||||
(off == PCI_CFG_SUBCL) || (off == PCI_CFG_BASECL) || \
|
||||
(off == PCI_CFG_HDR) || \
|
||||
(off == PCI_CFG_INT) || (off == PCI_CFG_PIN))
|
||||
|
||||
/* Sync the emulation registers and the real PCI config registers. */
|
||||
static void
|
||||
sb_pcid_read_config(sb_t * sbh, uint coreidx, sb_pci_cfg_t * cfg,
|
||||
uint off, uint len)
|
||||
{
|
||||
osl_t *osh;
|
||||
uint oldidx;
|
||||
|
||||
ASSERT(cfg);
|
||||
ASSERT(cfg->emu);
|
||||
ASSERT(cfg->pci);
|
||||
|
||||
/* decide if real PCI config register access is necessary */
|
||||
if (FORCE_EMUCFG(off, len))
|
||||
return;
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
|
||||
/* access to the real pci config space only when the core is up */
|
||||
oldidx = sb_coreidx(sbh);
|
||||
sb_setcoreidx(sbh, coreidx);
|
||||
if (sb_iscoreup(sbh)) {
|
||||
if (len == 4)
|
||||
*(uint32 *) ((ulong) cfg->emu + off) =
|
||||
htol32(R_REG
|
||||
(osh, (uint32 *) ((ulong) cfg->pci + off)));
|
||||
else if (len == 2)
|
||||
*(uint16 *) ((ulong) cfg->emu + off) =
|
||||
htol16(R_REG
|
||||
(osh, (uint16 *) ((ulong) cfg->pci + off)));
|
||||
else if (len == 1)
|
||||
*(uint8 *) ((ulong) cfg->emu + off) =
|
||||
R_REG(osh, (uint8 *) ((ulong) cfg->pci + off));
|
||||
}
|
||||
sb_setcoreidx(sbh, oldidx);
|
||||
}
|
||||
|
||||
static void
|
||||
sb_pcid_write_config(sb_t * sbh, uint coreidx, sb_pci_cfg_t * cfg,
|
||||
uint off, uint len)
|
||||
{
|
||||
osl_t *osh;
|
||||
uint oldidx;
|
||||
|
||||
ASSERT(cfg);
|
||||
ASSERT(cfg->emu);
|
||||
ASSERT(cfg->pci);
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
|
||||
/* decide if real PCI config register access is necessary */
|
||||
if (FORCE_EMUCFG(off, len))
|
||||
return;
|
||||
|
||||
/* access to the real pci config space only when the core is up */
|
||||
oldidx = sb_coreidx(sbh);
|
||||
sb_setcoreidx(sbh, coreidx);
|
||||
if (sb_iscoreup(sbh)) {
|
||||
if (len == 4)
|
||||
W_REG(osh, (uint32 *) ((ulong) cfg->pci + off),
|
||||
ltoh32(*(uint32 *) ((ulong) cfg->emu + off)));
|
||||
else if (len == 2)
|
||||
W_REG(osh, (uint16 *) ((ulong) cfg->pci + off),
|
||||
ltoh16(*(uint16 *) ((ulong) cfg->emu + off)));
|
||||
else if (len == 1)
|
||||
W_REG(osh, (uint8 *) ((ulong) cfg->pci + off),
|
||||
*(uint8 *) ((ulong) cfg->emu + off));
|
||||
}
|
||||
sb_setcoreidx(sbh, oldidx);
|
||||
}
|
||||
|
||||
/*
|
||||
* Functions for accessing translated SB configuration space
|
||||
*/
|
||||
static int
|
||||
sb_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off, void *buf,
|
||||
int len)
|
||||
{
|
||||
pci_config_regs *cfg;
|
||||
|
||||
if (dev >= SB_MAXCORES || func >= MAXFUNCS
|
||||
|| (off + len) > sizeof(pci_config_regs))
|
||||
return -1;
|
||||
cfg = sb_pci_cfg[dev][func].emu;
|
||||
|
||||
ASSERT(ISALIGNED(off, len));
|
||||
ASSERT(ISALIGNED((uintptr) buf, len));
|
||||
|
||||
/* use special config space if the device does not exist */
|
||||
if (!cfg)
|
||||
cfg = &sb_pci_null;
|
||||
/* sync emulation with real PCI config if necessary */
|
||||
else if (sb_pci_cfg[dev][func].pci)
|
||||
sb_pcid_read_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
|
||||
|
||||
if (len == 4)
|
||||
*((uint32 *) buf) = ltoh32(*((uint32 *) ((ulong) cfg + off)));
|
||||
else if (len == 2)
|
||||
*((uint16 *) buf) = ltoh16(*((uint16 *) ((ulong) cfg + off)));
|
||||
else if (len == 1)
|
||||
*((uint8 *) buf) = *((uint8 *) ((ulong) cfg + off));
|
||||
else
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
sb_write_config(sb_t * sbh, uint bus, uint dev, uint func, uint off, void *buf,
|
||||
int len)
|
||||
{
|
||||
uint coreidx;
|
||||
void *regs;
|
||||
pci_config_regs *cfg;
|
||||
osl_t *osh;
|
||||
sb_bar_cfg_t *bar;
|
||||
|
||||
if (dev >= SB_MAXCORES || func >= MAXFUNCS
|
||||
|| (off + len) > sizeof(pci_config_regs))
|
||||
return -1;
|
||||
cfg = sb_pci_cfg[dev][func].emu;
|
||||
if (!cfg)
|
||||
return -1;
|
||||
|
||||
ASSERT(ISALIGNED(off, len));
|
||||
ASSERT(ISALIGNED((uintptr) buf, len));
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
|
||||
/* Emulate BAR sizing */
|
||||
if (off >= OFFSETOF(pci_config_regs, base[0]) &&
|
||||
off <= OFFSETOF(pci_config_regs, base[3]) &&
|
||||
len == 4 && *((uint32 *) buf) == ~0) {
|
||||
coreidx = sb_coreidx(sbh);
|
||||
if ((regs = sb_setcoreidx(sbh, dev))) {
|
||||
bar = sb_pci_cfg[dev][func].bar;
|
||||
/* Highest numbered address match register */
|
||||
if (off == OFFSETOF(pci_config_regs, base[0]))
|
||||
cfg->base[0] = ~(bar->size0 - 1);
|
||||
else if (off == OFFSETOF(pci_config_regs, base[1])
|
||||
&& bar->n >= 1)
|
||||
cfg->base[1] = ~(bar->size1 - 1);
|
||||
else if (off == OFFSETOF(pci_config_regs, base[2])
|
||||
&& bar->n >= 2)
|
||||
cfg->base[2] = ~(bar->size2 - 1);
|
||||
else if (off == OFFSETOF(pci_config_regs, base[3])
|
||||
&& bar->n >= 3)
|
||||
cfg->base[3] = ~(bar->size3 - 1);
|
||||
}
|
||||
sb_setcoreidx(sbh, coreidx);
|
||||
} else if (len == 4)
|
||||
*((uint32 *) ((ulong) cfg + off)) = htol32(*((uint32 *) buf));
|
||||
else if (len == 2)
|
||||
*((uint16 *) ((ulong) cfg + off)) = htol16(*((uint16 *) buf));
|
||||
else if (len == 1)
|
||||
*((uint8 *) ((ulong) cfg + off)) = *((uint8 *) buf);
|
||||
else
|
||||
return -1;
|
||||
|
||||
/* sync emulation with real PCI config if necessary */
|
||||
if (sb_pci_cfg[dev][func].pci)
|
||||
sb_pcid_write_config(sbh, dev, &sb_pci_cfg[dev][func], off,
|
||||
len);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
sbpci_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
|
||||
void *buf, int len)
|
||||
{
|
||||
if (bus == 0)
|
||||
return sb_read_config(sbh, bus, dev, func, off, buf, len);
|
||||
else
|
||||
return extpci_read_config(sbh, bus, dev, func, off, buf, len);
|
||||
}
|
||||
|
||||
int
|
||||
sbpci_write_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
|
||||
void *buf, int len)
|
||||
{
|
||||
if (bus == 0)
|
||||
return sb_write_config(sbh, bus, dev, func, off, buf, len);
|
||||
else
|
||||
return extpci_write_config(sbh, bus, dev, func, off, buf, len);
|
||||
}
|
||||
|
||||
void sbpci_ban(uint16 core)
|
||||
{
|
||||
if (pci_banned < ARRAYSIZE(pci_ban))
|
||||
pci_ban[pci_banned++] = core;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initiliaze PCI core. Return 0 after a successful initialization.
|
||||
* Otherwise return -1 to indicate there is no PCI core and return 1
|
||||
* to indicate PCI core is disabled.
|
||||
*/
|
||||
int __init sbpci_init_pci(sb_t * sbh)
|
||||
{
|
||||
uint chip, chiprev, chippkg, host;
|
||||
uint32 boardflags;
|
||||
sbpciregs_t *pci;
|
||||
sbconfig_t *sb;
|
||||
uint32 val;
|
||||
int ret = 0;
|
||||
char *hbslot;
|
||||
osl_t *osh;
|
||||
|
||||
chip = sb_chip(sbh);
|
||||
chiprev = sb_chiprev(sbh);
|
||||
chippkg = sb_chippkg(sbh);
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
|
||||
if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
|
||||
printk("PCI: no core\n");
|
||||
pci_disabled = TRUE;
|
||||
return -1;
|
||||
}
|
||||
|
||||
if ((chip == 0x4310) && (chiprev == 0))
|
||||
pci_disabled = TRUE;
|
||||
|
||||
sb = (sbconfig_t *) ((ulong) pci + SBCONFIGOFF);
|
||||
|
||||
boardflags = (uint32) getintvar(NULL, "boardflags");
|
||||
|
||||
/*
|
||||
* The 200-pin BCM4712 package does not bond out PCI. Even when
|
||||
* PCI is bonded out, some boards may leave the pins
|
||||
* floating.
|
||||
*/
|
||||
if (((chip == BCM4712_CHIP_ID) &&
|
||||
((chippkg == BCM4712SMALL_PKG_ID) ||
|
||||
(chippkg == BCM4712MID_PKG_ID))) || (boardflags & BFL_NOPCI))
|
||||
pci_disabled = TRUE;
|
||||
|
||||
/* Enable the core */
|
||||
sb_core_reset(sbh, 0, 0);
|
||||
|
||||
/*
|
||||
* If the PCI core should not be touched (disabled, not bonded
|
||||
* out, or pins floating), do not even attempt to access core
|
||||
* registers. Otherwise, try to determine if it is in host
|
||||
* mode.
|
||||
*/
|
||||
if (pci_disabled)
|
||||
host = 0;
|
||||
else
|
||||
host = !BUSPROBE(val, &pci->control);
|
||||
|
||||
if (!host) {
|
||||
ret = 1;
|
||||
|
||||
/* Disable PCI interrupts in client mode */
|
||||
W_REG(osh, &sb->sbintvec, 0);
|
||||
|
||||
/* Disable the PCI bridge in client mode */
|
||||
sbpci_ban(SB_PCI);
|
||||
sb_core_disable(sbh, 0);
|
||||
|
||||
printk("PCI: Disabled\n");
|
||||
} else {
|
||||
printk("PCI: Initializing host\n");
|
||||
|
||||
/* Disable PCI SBReqeustTimeout for BCM4785 */
|
||||
if (chip == BCM4785_CHIP_ID) {
|
||||
AND_REG(osh, &sb->sbimconfiglow, ~0x00000070);
|
||||
sb_commit(sbh);
|
||||
}
|
||||
|
||||
/* Reset the external PCI bus and enable the clock */
|
||||
W_REG(osh, &pci->control, 0x5); /* enable the tristate drivers */
|
||||
W_REG(osh, &pci->control, 0xd); /* enable the PCI clock */
|
||||
OSL_DELAY(150); /* delay > 100 us */
|
||||
W_REG(osh, &pci->control, 0xf); /* deassert PCI reset */
|
||||
/* Use internal arbiter and park REQ/GRNT at external master 0 */
|
||||
W_REG(osh, &pci->arbcontrol, PCI_INT_ARB);
|
||||
OSL_DELAY(1); /* delay 1 us */
|
||||
if (sb_corerev(sbh) >= 8) {
|
||||
val = getintvar(NULL, "parkid");
|
||||
ASSERT(val <= PCI_PARKID_LAST);
|
||||
OR_REG(osh, &pci->arbcontrol, val << PCI_PARKID_SHIFT);
|
||||
OSL_DELAY(1);
|
||||
}
|
||||
|
||||
/* Enable CardBusMode */
|
||||
cardbus = getintvar(NULL, "cardbus") == 1;
|
||||
if (cardbus) {
|
||||
printk("PCI: Enabling CardBus\n");
|
||||
/* GPIO 1 resets the CardBus device on bcm94710ap */
|
||||
sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
|
||||
sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
|
||||
W_REG(osh, &pci->sprom[0],
|
||||
R_REG(osh, &pci->sprom[0]) | 0x400);
|
||||
}
|
||||
|
||||
/* 64 MB I/O access window */
|
||||
W_REG(osh, &pci->sbtopci0, SBTOPCI_IO);
|
||||
/* 64 MB configuration access window */
|
||||
W_REG(osh, &pci->sbtopci1, SBTOPCI_CFG0);
|
||||
/* 1 GB memory access window */
|
||||
W_REG(osh, &pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
|
||||
|
||||
/* Host bridge slot # nvram overwrite */
|
||||
if ((hbslot = nvram_get("pcihbslot"))) {
|
||||
pci_hbslot = simple_strtoul(hbslot, NULL, 0);
|
||||
ASSERT(pci_hbslot < PCI_MAX_DEVICES);
|
||||
}
|
||||
|
||||
/* Enable PCI bridge BAR0 prefetch and burst */
|
||||
val = 6;
|
||||
sbpci_write_config(sbh, 1, pci_hbslot, 0, PCI_CFG_CMD, &val,
|
||||
sizeof(val));
|
||||
|
||||
/* Enable PCI interrupts */
|
||||
W_REG(osh, &pci->intmask, PCI_INTA);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Get the PCI region address and size information.
|
||||
*/
|
||||
static void __init
|
||||
sbpci_init_regions(sb_t * sbh, uint func, pci_config_regs * cfg,
|
||||
sb_bar_cfg_t * bar)
|
||||
{
|
||||
osl_t *osh;
|
||||
uint16 coreid;
|
||||
void *regs;
|
||||
sbconfig_t *sb;
|
||||
uint32 base;
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
coreid = sb_coreid(sbh);
|
||||
regs = sb_coreregs(sbh);
|
||||
sb = (sbconfig_t *) ((ulong) regs + SBCONFIGOFF);
|
||||
|
||||
switch (coreid) {
|
||||
case SB_USB20H:
|
||||
base = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
|
||||
|
||||
cfg->base[0] = func == 0 ? base : base + 0x800; /* OHCI/EHCI */
|
||||
cfg->base[1] = 0;
|
||||
cfg->base[2] = 0;
|
||||
cfg->base[3] = 0;
|
||||
cfg->base[4] = 0;
|
||||
cfg->base[5] = 0;
|
||||
bar->n = 1;
|
||||
bar->size0 = func == 0 ? 0x200 : 0x100; /* OHCI/EHCI */
|
||||
bar->size1 = 0;
|
||||
bar->size2 = 0;
|
||||
bar->size3 = 0;
|
||||
break;
|
||||
default:
|
||||
cfg->base[0] = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
|
||||
cfg->base[1] = htol32(sb_base(R_REG(osh, &sb->sbadmatch1)));
|
||||
cfg->base[2] = htol32(sb_base(R_REG(osh, &sb->sbadmatch2)));
|
||||
cfg->base[3] = htol32(sb_base(R_REG(osh, &sb->sbadmatch3)));
|
||||
cfg->base[4] = 0;
|
||||
cfg->base[5] = 0;
|
||||
bar->n =
|
||||
(R_REG(osh, &sb->sbidlow) & SBIDL_AR_MASK) >>
|
||||
SBIDL_AR_SHIFT;
|
||||
bar->size0 = sb_size(R_REG(osh, &sb->sbadmatch0));
|
||||
bar->size1 = sb_size(R_REG(osh, &sb->sbadmatch1));
|
||||
bar->size2 = sb_size(R_REG(osh, &sb->sbadmatch2));
|
||||
bar->size3 = sb_size(R_REG(osh, &sb->sbadmatch3));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Construct PCI config spaces for SB cores so that they
|
||||
* can be accessed as if they were PCI devices.
|
||||
*/
|
||||
static void __init sbpci_init_cores(sb_t * sbh)
|
||||
{
|
||||
uint chiprev, coreidx, i;
|
||||
sbconfig_t *sb;
|
||||
pci_config_regs *cfg, *pci;
|
||||
sb_bar_cfg_t *bar;
|
||||
void *regs;
|
||||
osl_t *osh;
|
||||
uint16 vendor, device;
|
||||
uint16 coreid;
|
||||
uint8 class, subclass, progif;
|
||||
uint dev;
|
||||
uint8 header;
|
||||
uint func;
|
||||
|
||||
chiprev = sb_chiprev(sbh);
|
||||
coreidx = sb_coreidx(sbh);
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
|
||||
/* Scan the SB bus */
|
||||
bzero(sb_config_regs, sizeof(sb_config_regs));
|
||||
bzero(sb_bar_cfg, sizeof(sb_bar_cfg));
|
||||
bzero(sb_pci_cfg, sizeof(sb_pci_cfg));
|
||||
memset(&sb_pci_null, -1, sizeof(sb_pci_null));
|
||||
cfg = sb_config_regs;
|
||||
bar = sb_bar_cfg;
|
||||
for (dev = 0; dev < SB_MAXCORES; dev++) {
|
||||
/* Check if the core exists */
|
||||
if (!(regs = sb_setcoreidx(sbh, dev)))
|
||||
continue;
|
||||
sb = (sbconfig_t *) ((ulong) regs + SBCONFIGOFF);
|
||||
|
||||
/* Check if this core is banned */
|
||||
coreid = sb_coreid(sbh);
|
||||
for (i = 0; i < pci_banned; i++)
|
||||
if (coreid == pci_ban[i])
|
||||
break;
|
||||
if (i < pci_banned)
|
||||
continue;
|
||||
|
||||
for (func = 0; func < MAXFUNCS; ++func) {
|
||||
/* Make sure we won't go beyond the limit */
|
||||
if (cfg >= &sb_config_regs[SB_MAXCORES]) {
|
||||
printk("PCI: too many emulated devices\n");
|
||||
goto done;
|
||||
}
|
||||
|
||||
/* Convert core id to pci id */
|
||||
if (sb_corepciid
|
||||
(sbh, func, &vendor, &device, &class, &subclass,
|
||||
&progif, &header))
|
||||
continue;
|
||||
|
||||
/*
|
||||
* Differentiate real PCI config from emulated.
|
||||
* non zero 'pci' indicate there is a real PCI config space
|
||||
* for this device.
|
||||
*/
|
||||
switch (device) {
|
||||
case BCM47XX_GIGETH_ID:
|
||||
pci =
|
||||
(pci_config_regs *) ((uint32) regs + 0x800);
|
||||
break;
|
||||
case BCM47XX_SATAXOR_ID:
|
||||
pci =
|
||||
(pci_config_regs *) ((uint32) regs + 0x400);
|
||||
break;
|
||||
case BCM47XX_ATA100_ID:
|
||||
pci =
|
||||
(pci_config_regs *) ((uint32) regs + 0x800);
|
||||
break;
|
||||
default:
|
||||
pci = NULL;
|
||||
break;
|
||||
}
|
||||
/* Supported translations */
|
||||
cfg->vendor = htol16(vendor);
|
||||
cfg->device = htol16(device);
|
||||
cfg->rev_id = chiprev;
|
||||
cfg->prog_if = progif;
|
||||
cfg->sub_class = subclass;
|
||||
cfg->base_class = class;
|
||||
cfg->header_type = header;
|
||||
sbpci_init_regions(sbh, func, cfg, bar);
|
||||
/* Save core interrupt flag */
|
||||
cfg->int_pin =
|
||||
R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
|
||||
/* Save core interrupt assignment */
|
||||
cfg->int_line = sb_irq(sbh);
|
||||
/* Indicate there is no SROM */
|
||||
*((uint32 *) & cfg->sprom_control) = 0xffffffff;
|
||||
|
||||
/* Point to the PCI config spaces */
|
||||
sb_pci_cfg[dev][func].emu = cfg;
|
||||
sb_pci_cfg[dev][func].pci = pci;
|
||||
sb_pci_cfg[dev][func].bar = bar;
|
||||
cfg++;
|
||||
bar++;
|
||||
}
|
||||
}
|
||||
|
||||
done:
|
||||
sb_setcoreidx(sbh, coreidx);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize PCI core and construct PCI config spaces for SB cores.
|
||||
* Must propagate sbpci_init_pci() return value to the caller to let
|
||||
* them know the PCI core initialization status.
|
||||
*/
|
||||
int __init sbpci_init(sb_t * sbh)
|
||||
{
|
||||
int status = sbpci_init_pci(sbh);
|
||||
sbpci_init_cores(sbh);
|
||||
return status;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,253 +0,0 @@
|
|||
/*
|
||||
* Generic setup routines for Broadcom MIPS boards
|
||||
*
|
||||
* Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*
|
||||
* Copyright 2005, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/serialP.h>
|
||||
#include <linux/ide.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/reboot.h>
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <osl.h>
|
||||
#include <sbutils.h>
|
||||
#include <bcmnvram.h>
|
||||
#include <bcmdevs.h>
|
||||
#include <sbhndmips.h>
|
||||
#include <hndmips.h>
|
||||
#include <trxhdr.h>
|
||||
|
||||
/* Virtual IRQ base, after last hw IRQ */
|
||||
#define SBMIPS_VIRTIRQ_BASE 6
|
||||
|
||||
/* # IRQs, hw and sw IRQs */
|
||||
#define SBMIPS_NUMIRQS 8
|
||||
|
||||
/* Global SB handle */
|
||||
sb_t *bcm947xx_sbh = NULL;
|
||||
spinlock_t bcm947xx_sbh_lock = SPIN_LOCK_UNLOCKED;
|
||||
|
||||
/* Convenience */
|
||||
#define sbh bcm947xx_sbh
|
||||
#define sbh_lock bcm947xx_sbh_lock
|
||||
|
||||
extern void bcm947xx_time_init(void);
|
||||
extern void bcm947xx_timer_setup(struct irqaction *irq);
|
||||
|
||||
#ifdef CONFIG_REMOTE_DEBUG
|
||||
extern void set_debug_traps(void);
|
||||
extern void rs_kgdb_hook(struct serial_state *);
|
||||
extern void breakpoint(void);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
|
||||
extern struct ide_ops std_ide_ops;
|
||||
#endif
|
||||
|
||||
/* Kernel command line */
|
||||
char arcs_cmdline[CL_SIZE] __initdata = CONFIG_CMDLINE;
|
||||
extern void sb_serial_init(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
|
||||
|
||||
void
|
||||
bcm947xx_machine_restart(char *command)
|
||||
{
|
||||
printk("Please stand by while rebooting the system...\n");
|
||||
|
||||
if (sb_chip(sbh) == BCM4785_CHIP_ID)
|
||||
MTC0(C0_BROADCOM, 4, (1 << 22));
|
||||
|
||||
/* Set the watchdog timer to reset immediately */
|
||||
__cli();
|
||||
sb_watchdog(sbh, 1);
|
||||
|
||||
if (sb_chip(sbh) == BCM4785_CHIP_ID) {
|
||||
__asm__ __volatile__(
|
||||
".set\tmips3\n\t"
|
||||
"sync\n\t"
|
||||
"wait\n\t"
|
||||
".set\tmips0");
|
||||
}
|
||||
|
||||
while (1);
|
||||
}
|
||||
|
||||
void
|
||||
bcm947xx_machine_halt(void)
|
||||
{
|
||||
printk("System halted\n");
|
||||
|
||||
/* Disable interrupts and watchdog and spin forever */
|
||||
__cli();
|
||||
sb_watchdog(sbh, 0);
|
||||
while (1);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SERIAL
|
||||
|
||||
static int ser_line = 0;
|
||||
|
||||
typedef struct {
|
||||
void *regs;
|
||||
uint irq;
|
||||
uint baud_base;
|
||||
uint reg_shift;
|
||||
} serial_port;
|
||||
|
||||
static serial_port ports[4];
|
||||
static int num_ports = 0;
|
||||
|
||||
static void
|
||||
serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
|
||||
{
|
||||
ports[num_ports].regs = regs;
|
||||
ports[num_ports].irq = irq;
|
||||
ports[num_ports].baud_base = baud_base;
|
||||
ports[num_ports].reg_shift = reg_shift;
|
||||
num_ports++;
|
||||
}
|
||||
|
||||
static void
|
||||
do_serial_add(serial_port *port)
|
||||
{
|
||||
void *regs;
|
||||
uint irq;
|
||||
uint baud_base;
|
||||
uint reg_shift;
|
||||
struct serial_struct s;
|
||||
|
||||
regs = port->regs;
|
||||
irq = port->irq;
|
||||
baud_base = port->baud_base;
|
||||
reg_shift = port->reg_shift;
|
||||
|
||||
memset(&s, 0, sizeof(s));
|
||||
|
||||
s.line = ser_line++;
|
||||
s.iomem_base = regs;
|
||||
s.irq = irq + 2;
|
||||
s.baud_base = baud_base / 16;
|
||||
s.flags = ASYNC_BOOT_AUTOCONF;
|
||||
s.io_type = SERIAL_IO_MEM;
|
||||
s.iomem_reg_shift = reg_shift;
|
||||
|
||||
if (early_serial_setup(&s) != 0) {
|
||||
printk(KERN_ERR "Serial setup failed!\n");
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SERIAL */
|
||||
|
||||
void __init
|
||||
brcm_setup(void)
|
||||
{
|
||||
char *s;
|
||||
int i;
|
||||
char *value;
|
||||
|
||||
/* Get global SB handle */
|
||||
sbh = sb_kattach(SB_OSH);
|
||||
|
||||
/* Initialize clocks and interrupts */
|
||||
sb_mips_init(sbh, SBMIPS_VIRTIRQ_BASE);
|
||||
|
||||
if (BCM330X(current_cpu_data.processor_id) &&
|
||||
(read_c0_diag() & BRCM_PFC_AVAIL)) {
|
||||
/*
|
||||
* Now that the sbh is inited set the proper PFC value
|
||||
*/
|
||||
printk("Setting the PFC to its default value\n");
|
||||
enable_pfc(PFC_AUTO);
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_SERIAL
|
||||
sb_serial_init(sbh, serial_add);
|
||||
|
||||
/* reverse serial ports if nvram variable starts with console=ttyS1 */
|
||||
/* Initialize UARTs */
|
||||
s = nvram_get("kernel_args");
|
||||
if (!s) s = "";
|
||||
if (!strncmp(s, "console=ttyS1", 13)) {
|
||||
for (i = num_ports; i; i--)
|
||||
do_serial_add(&ports[i - 1]);
|
||||
} else {
|
||||
for (i = 0; i < num_ports; i++)
|
||||
do_serial_add(&ports[i]);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
|
||||
ide_ops = &std_ide_ops;
|
||||
#endif
|
||||
|
||||
/* Override default command line arguments */
|
||||
value = nvram_get("kernel_cmdline");
|
||||
if (value && strlen(value) && strncmp(value, "empty", 5))
|
||||
strncpy(arcs_cmdline, value, sizeof(arcs_cmdline));
|
||||
|
||||
|
||||
/* Generic setup */
|
||||
_machine_restart = bcm947xx_machine_restart;
|
||||
_machine_halt = bcm947xx_machine_halt;
|
||||
_machine_power_off = bcm947xx_machine_halt;
|
||||
|
||||
board_time_init = bcm947xx_time_init;
|
||||
board_timer_setup = bcm947xx_timer_setup;
|
||||
}
|
||||
|
||||
const char *
|
||||
get_system_type(void)
|
||||
{
|
||||
static char s[32];
|
||||
|
||||
if (bcm947xx_sbh) {
|
||||
sprintf(s, "Broadcom BCM%X chip rev %d", sb_chip(bcm947xx_sbh),
|
||||
sb_chiprev(bcm947xx_sbh));
|
||||
return s;
|
||||
}
|
||||
else
|
||||
return "Broadcom BCM947XX";
|
||||
}
|
||||
|
||||
void __init
|
||||
bus_error_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
|
@ -1,508 +0,0 @@
|
|||
/*
|
||||
* Broadcom SiliconBackplane chipcommon serial flash interface
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <osl.h>
|
||||
#include "include/bcmutils.h"
|
||||
#include <sbutils.h>
|
||||
#include <sbconfig.h>
|
||||
#include <sbchipc.h>
|
||||
#include <bcmdevs.h>
|
||||
#include <sflash.h>
|
||||
|
||||
/* Private global state */
|
||||
static struct sflash sflash;
|
||||
|
||||
/* Issue a serial flash command */
|
||||
static INLINE void
|
||||
sflash_cmd(osl_t *osh, chipcregs_t *cc, uint opcode)
|
||||
{
|
||||
W_REG(osh, &cc->flashcontrol, SFLASH_START | opcode);
|
||||
while (R_REG(osh, &cc->flashcontrol) & SFLASH_BUSY);
|
||||
}
|
||||
|
||||
/* Initialize serial flash access */
|
||||
struct sflash *
|
||||
sflash_init(sb_t *sbh, chipcregs_t *cc)
|
||||
{
|
||||
uint32 id, id2;
|
||||
osl_t *osh;
|
||||
|
||||
ASSERT(sbh);
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
|
||||
bzero(&sflash, sizeof(sflash));
|
||||
|
||||
sflash.type = sbh->cccaps & CC_CAP_FLASH_MASK;
|
||||
|
||||
switch (sflash.type) {
|
||||
case SFLASH_ST:
|
||||
/* Probe for ST chips */
|
||||
sflash_cmd(osh, cc, SFLASH_ST_DP);
|
||||
sflash_cmd(osh, cc, SFLASH_ST_RES);
|
||||
id = R_REG(osh, &cc->flashdata);
|
||||
switch (id) {
|
||||
case 0x11:
|
||||
/* ST M25P20 2 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 4;
|
||||
break;
|
||||
case 0x12:
|
||||
/* ST M25P40 4 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 8;
|
||||
break;
|
||||
case 0x13:
|
||||
/* ST M25P80 8 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 16;
|
||||
break;
|
||||
case 0x14:
|
||||
/* ST M25P16 16 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 32;
|
||||
break;
|
||||
case 0x15:
|
||||
/* ST M25P32 32 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 64;
|
||||
break;
|
||||
case 0x16:
|
||||
/* ST M25P64 64 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 128;
|
||||
break;
|
||||
case 0xbf:
|
||||
W_REG(osh, &cc->flashaddress, 1);
|
||||
sflash_cmd(osh, cc, SFLASH_ST_RES);
|
||||
id2 = R_REG(osh, &cc->flashdata);
|
||||
if (id2 == 0x44) {
|
||||
/* SST M25VF80 4 Mbit Serial Flash */
|
||||
sflash.blocksize = 64 * 1024;
|
||||
sflash.numblocks = 8;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case SFLASH_AT:
|
||||
/* Probe for Atmel chips */
|
||||
sflash_cmd(osh, cc, SFLASH_AT_STATUS);
|
||||
id = R_REG(osh, &cc->flashdata) & 0x3c;
|
||||
switch (id) {
|
||||
case 0xc:
|
||||
/* Atmel AT45DB011 1Mbit Serial Flash */
|
||||
sflash.blocksize = 256;
|
||||
sflash.numblocks = 512;
|
||||
break;
|
||||
case 0x14:
|
||||
/* Atmel AT45DB021 2Mbit Serial Flash */
|
||||
sflash.blocksize = 256;
|
||||
sflash.numblocks = 1024;
|
||||
break;
|
||||
case 0x1c:
|
||||
/* Atmel AT45DB041 4Mbit Serial Flash */
|
||||
sflash.blocksize = 256;
|
||||
sflash.numblocks = 2048;
|
||||
break;
|
||||
case 0x24:
|
||||
/* Atmel AT45DB081 8Mbit Serial Flash */
|
||||
sflash.blocksize = 256;
|
||||
sflash.numblocks = 4096;
|
||||
break;
|
||||
case 0x2c:
|
||||
/* Atmel AT45DB161 16Mbit Serial Flash */
|
||||
sflash.blocksize = 512;
|
||||
sflash.numblocks = 4096;
|
||||
break;
|
||||
case 0x34:
|
||||
/* Atmel AT45DB321 32Mbit Serial Flash */
|
||||
sflash.blocksize = 512;
|
||||
sflash.numblocks = 8192;
|
||||
break;
|
||||
case 0x3c:
|
||||
/* Atmel AT45DB642 64Mbit Serial Flash */
|
||||
sflash.blocksize = 1024;
|
||||
sflash.numblocks = 8192;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
sflash.size = sflash.blocksize * sflash.numblocks;
|
||||
return sflash.size ? &sflash : NULL;
|
||||
}
|
||||
|
||||
/* Read len bytes starting at offset into buf. Returns number of bytes read. */
|
||||
int
|
||||
sflash_read(sb_t *sbh, chipcregs_t *cc, uint offset, uint len, uchar *buf)
|
||||
{
|
||||
uint8 *from, *to;
|
||||
int cnt, i;
|
||||
osl_t *osh;
|
||||
|
||||
ASSERT(sbh);
|
||||
|
||||
if (!len)
|
||||
return 0;
|
||||
|
||||
if ((offset + len) > sflash.size)
|
||||
return -22;
|
||||
|
||||
if ((len >= 4) && (offset & 3))
|
||||
cnt = 4 - (offset & 3);
|
||||
else if ((len >= 4) && ((uintptr)buf & 3))
|
||||
cnt = 4 - ((uintptr)buf & 3);
|
||||
else
|
||||
cnt = len;
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
|
||||
from = (uint8 *)(uintptr)OSL_UNCACHED(SB_FLASH2 + offset);
|
||||
to = (uint8 *)buf;
|
||||
|
||||
if (cnt < 4) {
|
||||
for (i = 0; i < cnt; i ++) {
|
||||
*to = R_REG(osh, from);
|
||||
from ++;
|
||||
to ++;
|
||||
}
|
||||
return cnt;
|
||||
}
|
||||
|
||||
while (cnt >= 4) {
|
||||
*(uint32 *)to = R_REG(osh, (uint32 *)from);
|
||||
from += 4;
|
||||
to += 4;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
return (len - cnt);
|
||||
}
|
||||
|
||||
/* Poll for command completion. Returns zero when complete. */
|
||||
int
|
||||
sflash_poll(sb_t *sbh, chipcregs_t *cc, uint offset)
|
||||
{
|
||||
osl_t *osh;
|
||||
|
||||
ASSERT(sbh);
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
|
||||
if (offset >= sflash.size)
|
||||
return -22;
|
||||
|
||||
switch (sflash.type) {
|
||||
case SFLASH_ST:
|
||||
/* Check for ST Write In Progress bit */
|
||||
sflash_cmd(osh, cc, SFLASH_ST_RDSR);
|
||||
return R_REG(osh, &cc->flashdata) & SFLASH_ST_WIP;
|
||||
case SFLASH_AT:
|
||||
/* Check for Atmel Ready bit */
|
||||
sflash_cmd(osh, cc, SFLASH_AT_STATUS);
|
||||
return !(R_REG(osh, &cc->flashdata) & SFLASH_AT_READY);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Write len bytes starting at offset into buf. Returns number of bytes
|
||||
* written. Caller should poll for completion.
|
||||
*/
|
||||
int
|
||||
sflash_write(sb_t *sbh, chipcregs_t *cc, uint offset, uint len, const uchar *buf)
|
||||
{
|
||||
struct sflash *sfl;
|
||||
int ret = 0;
|
||||
bool is4712b0;
|
||||
uint32 page, byte, mask;
|
||||
osl_t *osh;
|
||||
|
||||
ASSERT(sbh);
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
|
||||
if (!len)
|
||||
return 0;
|
||||
|
||||
if ((offset + len) > sflash.size)
|
||||
return -22;
|
||||
|
||||
sfl = &sflash;
|
||||
switch (sfl->type) {
|
||||
case SFLASH_ST:
|
||||
is4712b0 = (sbh->chip == BCM4712_CHIP_ID) && (sbh->chiprev == 3);
|
||||
/* Enable writes */
|
||||
sflash_cmd(osh, cc, SFLASH_ST_WREN);
|
||||
if (is4712b0) {
|
||||
mask = 1 << 14;
|
||||
W_REG(osh, &cc->flashaddress, offset);
|
||||
W_REG(osh, &cc->flashdata, *buf++);
|
||||
/* Set chip select */
|
||||
OR_REG(osh, &cc->gpioout, mask);
|
||||
/* Issue a page program with the first byte */
|
||||
sflash_cmd(osh, cc, SFLASH_ST_PP);
|
||||
ret = 1;
|
||||
offset++;
|
||||
len--;
|
||||
while (len > 0) {
|
||||
if ((offset & 255) == 0) {
|
||||
/* Page boundary, drop cs and return */
|
||||
AND_REG(osh, &cc->gpioout, ~mask);
|
||||
if (!sflash_poll(sbh, cc, offset)) {
|
||||
/* Flash rejected command */
|
||||
return -11;
|
||||
}
|
||||
return ret;
|
||||
} else {
|
||||
/* Write single byte */
|
||||
sflash_cmd(osh, cc, *buf++);
|
||||
}
|
||||
ret++;
|
||||
offset++;
|
||||
len--;
|
||||
}
|
||||
/* All done, drop cs if needed */
|
||||
if ((offset & 255) != 1) {
|
||||
/* Drop cs */
|
||||
AND_REG(osh, &cc->gpioout, ~mask);
|
||||
if (!sflash_poll(sbh, cc, offset)) {
|
||||
/* Flash rejected command */
|
||||
return -12;
|
||||
}
|
||||
}
|
||||
} else if ( (sbh->ccrev >= 20) && (len != 1) ) {
|
||||
//} else if ( sbh->ccrev >= 20 ) { /* foxconn modified by EricHuang, 05/24/2007 */
|
||||
W_REG(NULL, &cc->flashaddress, offset);
|
||||
W_REG(NULL, &cc->flashdata, *buf++);
|
||||
/* Issue a page program with CSA bit set */
|
||||
sflash_cmd(osh, cc, SFLASH_ST_CSA | SFLASH_ST_PP);
|
||||
ret = 1;
|
||||
offset++;
|
||||
len--;
|
||||
while (len > 0) {
|
||||
if ((offset & 255) == 0) {
|
||||
/* Page boundary, poll droping cs and return */
|
||||
W_REG(NULL, &cc->flashcontrol, 0);
|
||||
/* wklin added start, 06/08/2007 */
|
||||
W_REG(NULL, &cc->flashcontrol, 0);
|
||||
OSL_DELAY(1);
|
||||
/* wklin added end, 06/08/2007 */
|
||||
/* wklin rmeoved start, 06/08/2007 */
|
||||
#if 0
|
||||
if (!sflash_poll(sbh, cc, offset)) {
|
||||
/* Flash rejected command */
|
||||
return -11;
|
||||
}
|
||||
#endif
|
||||
/* wklin removed end, 06/08/2007 */
|
||||
return ret;
|
||||
} else {
|
||||
/* Write single byte */
|
||||
sflash_cmd(osh, cc, SFLASH_ST_CSA | *buf++);
|
||||
}
|
||||
ret++;
|
||||
offset++;
|
||||
len--;
|
||||
}
|
||||
/* All done, drop cs if needed */
|
||||
if ((offset & 255) != 1) {
|
||||
/* Drop cs, poll */
|
||||
W_REG(NULL, &cc->flashcontrol, 0);
|
||||
/* wklin added start, 06/08/2007 */
|
||||
W_REG(NULL, &cc->flashcontrol, 0);
|
||||
OSL_DELAY(1);
|
||||
/* wklin added end, 06/08/2007 */
|
||||
/* wklin removed start, 06/08/2007 */
|
||||
#if 0
|
||||
if (!sflash_poll(sbh, cc, offset)) {
|
||||
/* Flash rejected command */
|
||||
return -12;
|
||||
}
|
||||
#endif
|
||||
/* wklin removed end, 06/08/2007 */
|
||||
}
|
||||
} else {
|
||||
ret = 1;
|
||||
W_REG(osh, &cc->flashaddress, offset);
|
||||
W_REG(osh, &cc->flashdata, *buf);
|
||||
/* Page program */
|
||||
sflash_cmd(osh, cc, SFLASH_ST_PP);
|
||||
}
|
||||
break;
|
||||
case SFLASH_AT:
|
||||
mask = sfl->blocksize - 1;
|
||||
page = (offset & ~mask) << 1;
|
||||
byte = offset & mask;
|
||||
/* Read main memory page into buffer 1 */
|
||||
if (byte || (len < sfl->blocksize)) {
|
||||
W_REG(osh, &cc->flashaddress, page);
|
||||
sflash_cmd(osh, cc, SFLASH_AT_BUF1_LOAD);
|
||||
/* 250 us for AT45DB321B */
|
||||
SPINWAIT(sflash_poll(sbh, cc, offset), 1000);
|
||||
ASSERT(!sflash_poll(sbh, cc, offset));
|
||||
}
|
||||
/* Write into buffer 1 */
|
||||
for (ret = 0; (ret < (int)len) && (byte < sfl->blocksize); ret++) {
|
||||
W_REG(osh, &cc->flashaddress, byte++);
|
||||
W_REG(osh, &cc->flashdata, *buf++);
|
||||
sflash_cmd(osh, cc, SFLASH_AT_BUF1_WRITE);
|
||||
}
|
||||
/* Write buffer 1 into main memory page */
|
||||
W_REG(osh, &cc->flashaddress, page);
|
||||
sflash_cmd(osh, cc, SFLASH_AT_BUF1_PROGRAM);
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Erase a region. Returns number of bytes scheduled for erasure.
|
||||
* Caller should poll for completion.
|
||||
*/
|
||||
int
|
||||
sflash_erase(sb_t *sbh, chipcregs_t *cc, uint offset)
|
||||
{
|
||||
struct sflash *sfl;
|
||||
osl_t *osh;
|
||||
|
||||
ASSERT(sbh);
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
|
||||
if (offset >= sflash.size)
|
||||
return -22;
|
||||
|
||||
sfl = &sflash;
|
||||
switch (sfl->type) {
|
||||
case SFLASH_ST:
|
||||
sflash_cmd(osh, cc, SFLASH_ST_WREN);
|
||||
W_REG(osh, &cc->flashaddress, offset);
|
||||
sflash_cmd(osh, cc, SFLASH_ST_SE);
|
||||
return sfl->blocksize;
|
||||
case SFLASH_AT:
|
||||
W_REG(osh, &cc->flashaddress, offset << 1);
|
||||
sflash_cmd(osh, cc, SFLASH_AT_PAGE_ERASE);
|
||||
return sfl->blocksize;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* writes the appropriate range of flash, a NULL buf simply erases
|
||||
* the region of flash
|
||||
*/
|
||||
int
|
||||
sflash_commit(sb_t *sbh, chipcregs_t *cc, uint offset, uint len, const uchar *buf)
|
||||
{
|
||||
struct sflash *sfl;
|
||||
uchar *block = NULL, *cur_ptr, *blk_ptr;
|
||||
uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
|
||||
uint blk_offset, blk_len, copied;
|
||||
int bytes, ret = 0;
|
||||
osl_t *osh;
|
||||
|
||||
ASSERT(sbh);
|
||||
|
||||
osh = sb_osh(sbh);
|
||||
|
||||
/* Check address range */
|
||||
if (len <= 0)
|
||||
return 0;
|
||||
|
||||
sfl = &sflash;
|
||||
if ((offset + len) > sfl->size)
|
||||
return -1;
|
||||
|
||||
blocksize = sfl->blocksize;
|
||||
mask = blocksize - 1;
|
||||
|
||||
/* Allocate a block of mem */
|
||||
if (!(block = MALLOC(osh, blocksize)))
|
||||
return -1;
|
||||
|
||||
while (len) {
|
||||
/* Align offset */
|
||||
cur_offset = offset & ~mask;
|
||||
cur_length = blocksize;
|
||||
cur_ptr = block;
|
||||
|
||||
remainder = blocksize - (offset & mask);
|
||||
if (len < remainder)
|
||||
cur_retlen = len;
|
||||
else
|
||||
cur_retlen = remainder;
|
||||
|
||||
/* buf == NULL means erase only */
|
||||
if (buf) {
|
||||
/* Copy existing data into holding block if necessary */
|
||||
if ((offset & mask) || (len < blocksize)) {
|
||||
blk_offset = cur_offset;
|
||||
blk_len = cur_length;
|
||||
blk_ptr = cur_ptr;
|
||||
|
||||
/* Copy entire block */
|
||||
while (blk_len) {
|
||||
copied = sflash_read(sbh, cc, blk_offset, blk_len, blk_ptr);
|
||||
blk_offset += copied;
|
||||
blk_len -= copied;
|
||||
blk_ptr += copied;
|
||||
}
|
||||
}
|
||||
|
||||
/* Copy input data into holding block */
|
||||
memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
|
||||
}
|
||||
|
||||
/* Erase block */
|
||||
if ((ret = sflash_erase(sbh, cc, (uint) cur_offset)) < 0)
|
||||
goto done;
|
||||
while (sflash_poll(sbh, cc, (uint) cur_offset));
|
||||
|
||||
/* buf == NULL means erase only */
|
||||
if (!buf) {
|
||||
offset += cur_retlen;
|
||||
len -= cur_retlen;
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Write holding block */
|
||||
while (cur_length > 0) {
|
||||
if ((bytes = sflash_write(sbh, cc,
|
||||
(uint) cur_offset,
|
||||
(uint) cur_length,
|
||||
(uchar *) cur_ptr)) < 0) {
|
||||
ret = bytes;
|
||||
goto done;
|
||||
}
|
||||
while (sflash_poll(sbh, cc, (uint) cur_offset));
|
||||
cur_offset += bytes;
|
||||
cur_length -= bytes;
|
||||
cur_ptr += bytes;
|
||||
}
|
||||
|
||||
offset += cur_retlen;
|
||||
len -= cur_retlen;
|
||||
buf += cur_retlen;
|
||||
}
|
||||
|
||||
ret = len;
|
||||
done:
|
||||
if (block)
|
||||
MFREE(osh, block, blocksize);
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -1,118 +0,0 @@
|
|||
/*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#include <linux/config.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/serial_reg.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <osl.h>
|
||||
#include <bcmnvram.h>
|
||||
#include <sbconfig.h>
|
||||
#include <sbutils.h>
|
||||
#include <sbchipc.h>
|
||||
#include <hndmips.h>
|
||||
#include <mipsinc.h>
|
||||
#include <hndcpu.h>
|
||||
#include <bcmdevs.h>
|
||||
|
||||
/* Global SB handle */
|
||||
extern void *bcm947xx_sbh;
|
||||
extern spinlock_t bcm947xx_sbh_lock;
|
||||
|
||||
/* Convenience */
|
||||
#define sbh bcm947xx_sbh
|
||||
#define sbh_lock bcm947xx_sbh_lock
|
||||
|
||||
extern int panic_timeout;
|
||||
static int watchdog = 0;
|
||||
|
||||
void __init
|
||||
bcm947xx_time_init(void)
|
||||
{
|
||||
unsigned int hz;
|
||||
|
||||
/*
|
||||
* Use deterministic values for initial counter interrupt
|
||||
* so that calibrate delay avoids encountering a counter wrap.
|
||||
*/
|
||||
write_c0_count(0);
|
||||
write_c0_compare(0xffff);
|
||||
|
||||
if (!(hz = sb_cpu_clock(sbh)))
|
||||
hz = 100000000;
|
||||
|
||||
printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
|
||||
(hz + 500000) / 1000000);
|
||||
|
||||
/* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
|
||||
mips_hpt_frequency = hz / 2;
|
||||
|
||||
/* Set watchdog interval in ms */
|
||||
watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
|
||||
|
||||
/* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
|
||||
if (watchdog > 0) {
|
||||
if (watchdog < 3000)
|
||||
watchdog = 3000;
|
||||
}
|
||||
|
||||
/* Set panic timeout in seconds */
|
||||
panic_timeout = watchdog / 1000;
|
||||
}
|
||||
|
||||
static void
|
||||
bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
||||
{
|
||||
/* Generic MIPS timer code */
|
||||
timer_interrupt(irq, dev_id, regs);
|
||||
|
||||
/* Set the watchdog timer to reset after the specified number of ms */
|
||||
if (watchdog > 0) {
|
||||
if (sb_chip(sbh) == BCM5354_CHIP_ID)
|
||||
sb_watchdog(sbh, WATCHDOG_CLOCK_5354 / 1000 * watchdog);
|
||||
else
|
||||
sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static struct irqaction bcm947xx_timer_irqaction = {
|
||||
bcm947xx_timer_interrupt,
|
||||
SA_INTERRUPT,
|
||||
0,
|
||||
"timer",
|
||||
NULL,
|
||||
NULL
|
||||
};
|
||||
|
||||
void __init
|
||||
bcm947xx_timer_setup(struct irqaction *irq)
|
||||
{
|
||||
int x;
|
||||
|
||||
/* Enable the timer interrupt */
|
||||
setup_irq(7, &bcm947xx_timer_irqaction);
|
||||
|
||||
sti();
|
||||
|
||||
for (x=0; x<5; x++) {
|
||||
unsigned long ticks;
|
||||
ticks = jiffies;
|
||||
while (ticks == jiffies)
|
||||
/* do nothing */;
|
||||
}
|
||||
}
|
||||
|
|
@ -1,104 +0,0 @@
|
|||
/*
|
||||
* Driver O/S-independent utility routines
|
||||
*
|
||||
* Copyright 2007, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <bcmdefs.h>
|
||||
#include <stdarg.h>
|
||||
#include <osl.h>
|
||||
#include <sbutils.h>
|
||||
#include <bcmendian.h>
|
||||
#include "utils.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* crc8
|
||||
*
|
||||
* Computes a crc8 over the input data using the polynomial:
|
||||
*
|
||||
* x^8 + x^7 +x^6 + x^4 + x^2 + 1
|
||||
*
|
||||
* The caller provides the initial value (either CRC8_INIT_VALUE
|
||||
* or the previous returned value) to allow for processing of
|
||||
* discontiguous blocks of data. When generating the CRC the
|
||||
* caller is responsible for complementing the final return value
|
||||
* and inserting it into the byte stream. When checking, a final
|
||||
* return value of CRC8_GOOD_VALUE indicates a valid CRC.
|
||||
*
|
||||
* Reference: Dallas Semiconductor Application Note 27
|
||||
* Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
|
||||
* ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
|
||||
* ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
|
||||
*
|
||||
* ****************************************************************************
|
||||
*/
|
||||
|
||||
static const uint8 crc8_table[256] = {
|
||||
0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
|
||||
0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
|
||||
0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
|
||||
0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
|
||||
0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
|
||||
0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
|
||||
0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
|
||||
0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
|
||||
0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
|
||||
0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
|
||||
0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
|
||||
0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
|
||||
0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
|
||||
0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
|
||||
0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
|
||||
0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
|
||||
0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
|
||||
0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
|
||||
0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
|
||||
0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
|
||||
0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
|
||||
0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
|
||||
0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
|
||||
0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
|
||||
0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
|
||||
0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
|
||||
0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
|
||||
0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
|
||||
0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
|
||||
0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
|
||||
0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
|
||||
0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
|
||||
};
|
||||
|
||||
#define CRC_INNER_LOOP(n, c, x) \
|
||||
(c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
|
||||
|
||||
|
||||
uint8 hndcrc8 (uint8 * pdata, /* pointer to array of data to process */
|
||||
uint nbytes, /* number of input data bytes to process */
|
||||
uint8 crc /* either CRC8_INIT_VALUE or previous return value */
|
||||
)
|
||||
{
|
||||
/* hard code the crc loop instead of using CRC_INNER_LOOP macro
|
||||
* to avoid the undefined and unnecessary (uint8 >> 8) operation.
|
||||
*/
|
||||
while (nbytes-- > 0)
|
||||
crc = crc8_table[(crc ^ *pdata++) & 0xff];
|
||||
|
||||
return crc;
|
||||
}
|
||||
|
||||
char *
|
||||
bcm_ether_ntoa (struct ether_addr *ea, char *buf)
|
||||
{
|
||||
snprintf (buf, 18, "%02x:%02x:%02x:%02x:%02x:%02x",
|
||||
ea->octet[0] & 0xff, ea->octet[1] & 0xff, ea->octet[2] & 0xff,
|
||||
ea->octet[3] & 0xff, ea->octet[4] & 0xff, ea->octet[5] & 0xff);
|
||||
return (buf);
|
||||
}
|
||||
|
||||
|
|
@ -1,65 +0,0 @@
|
|||
#ifndef __bcm_utils_h
|
||||
#define __bcm_utils_h
|
||||
|
||||
#define BCME_STRLEN 64 /* Max string length for BCM errors */
|
||||
#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
|
||||
|
||||
/*
|
||||
* error codes could be added but the defined ones shouldn't be changed/deleted
|
||||
* these error codes are exposed to the user code
|
||||
* when ever a new error code is added to this list
|
||||
* please update errorstring table with the related error string and
|
||||
* update osl files with os specific errorcode map
|
||||
*/
|
||||
|
||||
#define BCME_OK 0 /* Success */
|
||||
#define BCME_ERROR -1 /* Error generic */
|
||||
#define BCME_BADARG -2 /* Bad Argument */
|
||||
#define BCME_BADOPTION -3 /* Bad option */
|
||||
#define BCME_NOTUP -4 /* Not up */
|
||||
#define BCME_NOTDOWN -5 /* Not down */
|
||||
#define BCME_NOTAP -6 /* Not AP */
|
||||
#define BCME_NOTSTA -7 /* Not STA */
|
||||
#define BCME_BADKEYIDX -8 /* BAD Key Index */
|
||||
#define BCME_RADIOOFF -9 /* Radio Off */
|
||||
#define BCME_NOTBANDLOCKED -10 /* Not band locked */
|
||||
#define BCME_NOCLK -11 /* No Clock */
|
||||
#define BCME_BADRATESET -12 /* BAD Rate valueset */
|
||||
#define BCME_BADBAND -13 /* BAD Band */
|
||||
#define BCME_BUFTOOSHORT -14 /* Buffer too short */
|
||||
#define BCME_BUFTOOLONG -15 /* Buffer too long */
|
||||
#define BCME_BUSY -16 /* Busy */
|
||||
#define BCME_NOTASSOCIATED -17 /* Not Associated */
|
||||
#define BCME_BADSSIDLEN -18 /* Bad SSID len */
|
||||
#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel */
|
||||
#define BCME_BADCHAN -20 /* Bad Channel */
|
||||
#define BCME_BADADDR -21 /* Bad Address */
|
||||
#define BCME_NORESOURCE -22 /* Not Enough Resources */
|
||||
#define BCME_UNSUPPORTED -23 /* Unsupported */
|
||||
#define BCME_BADLEN -24 /* Bad length */
|
||||
#define BCME_NOTREADY -25 /* Not Ready */
|
||||
#define BCME_EPERM -26 /* Not Permitted */
|
||||
#define BCME_NOMEM -27 /* No Memory */
|
||||
#define BCME_ASSOCIATED -28 /* Associated */
|
||||
#define BCME_RANGE -29 /* Not In Range */
|
||||
#define BCME_NOTFOUND -30 /* Not Found */
|
||||
#define BCME_WME_NOT_ENABLED -31 /* WME Not Enabled */
|
||||
#define BCME_TSPEC_NOTFOUND -32 /* TSPEC Not Found */
|
||||
#define BCME_ACM_NOTSUPPORTED -33 /* ACM Not Supported */
|
||||
#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */
|
||||
#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */
|
||||
#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */
|
||||
#define BCME_VERSION -37 /* Incorrect version */
|
||||
#define BCME_LAST BCME_VERSION
|
||||
|
||||
/* buffer length for ethernet address from bcm_ether_ntoa() */
|
||||
#define ETHER_ADDR_STR_LEN 18 /* 18-bytes of Ethernet address buffer length */
|
||||
|
||||
struct ether_addr {
|
||||
unsigned char octet[6];
|
||||
};
|
||||
|
||||
extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
|
||||
|
||||
#endif /* __bcm_utils_h */
|
||||
|
||||
|
|
@ -1,303 +0,0 @@
|
|||
/*
|
||||
* Broadcom SiliconBackplane chipcommon serial flash interface
|
||||
*
|
||||
* Copyright 2006, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/mtd/compatmac.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/delay.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <osl.h>
|
||||
// #include <bcmutils.h>
|
||||
#include <bcmdevs.h>
|
||||
#include <bcmnvram.h>
|
||||
#include <sbutils.h>
|
||||
#include <sbconfig.h>
|
||||
#include <sbchipc.h>
|
||||
#include <sflash.h>
|
||||
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
extern struct mtd_partition * init_mtd_partitions(struct mtd_info *mtd, size_t size);
|
||||
#endif
|
||||
|
||||
struct sflash_mtd {
|
||||
sb_t *sbh;
|
||||
chipcregs_t *cc;
|
||||
struct semaphore lock;
|
||||
struct mtd_info mtd;
|
||||
struct mtd_erase_region_info region;
|
||||
};
|
||||
|
||||
/* Private global state */
|
||||
static struct sflash_mtd sflash;
|
||||
|
||||
static int
|
||||
sflash_mtd_poll(struct sflash_mtd *sflash, unsigned int offset, int timeout)
|
||||
{
|
||||
int now = jiffies;
|
||||
int ret = 0;
|
||||
|
||||
for (;;) {
|
||||
if (!sflash_poll(sflash->sbh, sflash->cc, offset)) {
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
if (time_after(jiffies, now + timeout)) {
|
||||
printk(KERN_ERR "sflash: timeout\n");
|
||||
ret = -ETIMEDOUT;
|
||||
break;
|
||||
}
|
||||
if (current->need_resched) {
|
||||
set_current_state(TASK_UNINTERRUPTIBLE);
|
||||
schedule_timeout(timeout / 10);
|
||||
} else
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
sflash_mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
|
||||
{
|
||||
struct sflash_mtd *sflash = (struct sflash_mtd *) mtd->priv;
|
||||
int bytes, ret = 0;
|
||||
|
||||
/* Check address range */
|
||||
if (len == 0){
|
||||
*retlen = 0;
|
||||
return 0;
|
||||
}
|
||||
if (!len)
|
||||
return 0;
|
||||
if ((from + len) > mtd->size)
|
||||
return -EINVAL;
|
||||
|
||||
down(&sflash->lock);
|
||||
|
||||
*retlen = 0;
|
||||
while (len) {
|
||||
if ((bytes = sflash_read(sflash->sbh, sflash->cc, (uint) from, len, buf)) < 0) {
|
||||
ret = bytes;
|
||||
break;
|
||||
}
|
||||
from += (loff_t) bytes;
|
||||
len -= bytes;
|
||||
buf += bytes;
|
||||
*retlen += bytes;
|
||||
}
|
||||
|
||||
up(&sflash->lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
sflash_mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf)
|
||||
{
|
||||
struct sflash_mtd *sflash = (struct sflash_mtd *) mtd->priv;
|
||||
int bytes, ret = 0;
|
||||
|
||||
/* Check address range */
|
||||
if (len == 0){
|
||||
*retlen = 0;
|
||||
return 0;
|
||||
}
|
||||
if (!len)
|
||||
return 0;
|
||||
if ((to + len) > mtd->size)
|
||||
return -EINVAL;
|
||||
|
||||
down(&sflash->lock);
|
||||
|
||||
*retlen = 0;
|
||||
while (len) {
|
||||
if ((bytes = sflash_write(sflash->sbh, sflash->cc, (uint)to, (uint)len, buf)) < 0) {
|
||||
ret = bytes;
|
||||
break;
|
||||
}
|
||||
if ((ret = sflash_mtd_poll(sflash, (unsigned int) to, HZ / 10)))
|
||||
break;
|
||||
to += (loff_t) bytes;
|
||||
len -= bytes;
|
||||
buf += bytes;
|
||||
*retlen += bytes;
|
||||
}
|
||||
|
||||
up(&sflash->lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
sflash_mtd_erase(struct mtd_info *mtd, struct erase_info *erase)
|
||||
{
|
||||
struct sflash_mtd *sflash = (struct sflash_mtd *) mtd->priv;
|
||||
int i, j, ret = 0;
|
||||
unsigned int addr, len;
|
||||
|
||||
/* Check address range */
|
||||
if (!erase->len)
|
||||
return 0;
|
||||
if ((erase->addr + erase->len) > mtd->size)
|
||||
return -EINVAL;
|
||||
|
||||
addr = erase->addr;
|
||||
len = erase->len;
|
||||
|
||||
down(&sflash->lock);
|
||||
|
||||
/* Ensure that requested region is aligned */
|
||||
for (i = 0; i < mtd->numeraseregions; i++) {
|
||||
for (j = 0; j < mtd->eraseregions[i].numblocks; j++) {
|
||||
if (addr == mtd->eraseregions[i].offset + mtd->eraseregions[i].erasesize * j &&
|
||||
len >= mtd->eraseregions[i].erasesize) {
|
||||
if ((ret = sflash_erase(sflash->sbh, sflash->cc, addr)) < 0)
|
||||
break;
|
||||
if ((ret = sflash_mtd_poll(sflash, addr, 10 * HZ)))
|
||||
break;
|
||||
addr += mtd->eraseregions[i].erasesize;
|
||||
len -= mtd->eraseregions[i].erasesize;
|
||||
}
|
||||
}
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
|
||||
up(&sflash->lock);
|
||||
|
||||
/* Set erase status */
|
||||
if (ret)
|
||||
erase->state = MTD_ERASE_FAILED;
|
||||
else
|
||||
erase->state = MTD_ERASE_DONE;
|
||||
|
||||
/* Call erase callback */
|
||||
if (erase->callback)
|
||||
erase->callback(erase);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if LINUX_VERSION_CODE < 0x20212 && defined(MODULE)
|
||||
#define sflash_mtd_init init_module
|
||||
#define sflash_mtd_exit cleanup_module
|
||||
#endif
|
||||
|
||||
mod_init_t
|
||||
sflash_mtd_init(void)
|
||||
{
|
||||
struct pci_dev *pdev;
|
||||
int ret = 0;
|
||||
struct sflash *info;
|
||||
uint i;
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
struct mtd_partition *parts;
|
||||
#endif
|
||||
|
||||
if (!(pdev = pci_find_device(VENDOR_BROADCOM, SB_CC, NULL))) {
|
||||
printk(KERN_ERR "sflash: chipcommon not found\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
memset(&sflash, 0, sizeof(struct sflash_mtd));
|
||||
init_MUTEX(&sflash.lock);
|
||||
|
||||
/* attach to the backplane */
|
||||
if (!(sflash.sbh = sb_kattach(SB_OSH))) {
|
||||
printk(KERN_ERR "sflash: error attaching to backplane\n");
|
||||
ret = -EIO;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* Map registers and flash base */
|
||||
if (!(sflash.cc = ioremap_nocache(pci_resource_start(pdev, 0),
|
||||
pci_resource_len(pdev, 0)))) {
|
||||
printk(KERN_ERR "sflash: error mapping registers\n");
|
||||
ret = -EIO;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* Initialize serial flash access */
|
||||
if (!(info = sflash_init(sflash.sbh, sflash.cc))) {
|
||||
printk(KERN_ERR "sflash: found no supported devices\n");
|
||||
ret = -ENODEV;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
printk(KERN_INFO "sflash: found serial flash; blocksize=%dKB, numblocks=%d, size=%dKB\n",info->blocksize/1024,info->numblocks,info->size/1024);
|
||||
|
||||
/* Setup region info */
|
||||
sflash.region.offset = 0;
|
||||
sflash.region.erasesize = info->blocksize;
|
||||
sflash.region.numblocks = info->numblocks;
|
||||
if (sflash.region.erasesize > sflash.mtd.erasesize)
|
||||
sflash.mtd.erasesize = sflash.region.erasesize;
|
||||
sflash.mtd.size = info->size;
|
||||
sflash.mtd.numeraseregions = 1;
|
||||
|
||||
/* Register with MTD */
|
||||
sflash.mtd.name = "sflash";
|
||||
sflash.mtd.type = MTD_NORFLASH;
|
||||
sflash.mtd.flags = MTD_CAP_NORFLASH;
|
||||
sflash.mtd.eraseregions = &sflash.region;
|
||||
sflash.mtd.module = THIS_MODULE;
|
||||
sflash.mtd.erase = sflash_mtd_erase;
|
||||
sflash.mtd.read = sflash_mtd_read;
|
||||
sflash.mtd.write = sflash_mtd_write;
|
||||
sflash.mtd.priv = &sflash;
|
||||
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
parts = init_mtd_partitions(&sflash.mtd, sflash.mtd.size);
|
||||
for (i = 0; parts[i].name; i++);
|
||||
ret = add_mtd_partitions(&sflash.mtd, parts, i);
|
||||
#else
|
||||
ret = add_mtd_device(&sflash.mtd);
|
||||
#endif
|
||||
if (ret) {
|
||||
printk(KERN_ERR "sflash: add_mtd failed\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
if (sflash.cc)
|
||||
iounmap((void *) sflash.cc);
|
||||
if (sflash.sbh)
|
||||
sb_detach(sflash.sbh);
|
||||
return ret;
|
||||
}
|
||||
|
||||
mod_exit_t
|
||||
sflash_mtd_exit(void)
|
||||
{
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
del_mtd_partitions(&sflash.mtd);
|
||||
#else
|
||||
del_mtd_device(&sflash.mtd);
|
||||
#endif
|
||||
iounmap((void *) sflash.cc);
|
||||
sb_detach(sflash.sbh);
|
||||
}
|
||||
|
||||
module_init(sflash_mtd_init);
|
||||
module_exit(sflash_mtd_exit);
|
||||
|
|
@ -1,547 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
|
||||
* Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
|
||||
* Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
|
||||
*
|
||||
* original functions for finding root filesystem from Mike Baker
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*
|
||||
* Copyright 2004, Broadcom Corporation
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
*
|
||||
* Flash mapping for BCM947XX boards
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/wait.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/map.h>
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
#include <linux/mtd/partitions.h>
|
||||
#endif
|
||||
#include <linux/config.h>
|
||||
#include <linux/squashfs_fs.h>
|
||||
#include <linux/jffs2.h>
|
||||
#include <linux/crc32.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <typedefs.h>
|
||||
#include <osl.h>
|
||||
#include <bcmnvram.h>
|
||||
#include <sbconfig.h>
|
||||
#include <sbchipc.h>
|
||||
#include <sbutils.h>
|
||||
#include <trxhdr.h>
|
||||
|
||||
/* Global SB handle */
|
||||
extern void *bcm947xx_sbh;
|
||||
extern spinlock_t bcm947xx_sbh_lock;
|
||||
|
||||
/* Convenience */
|
||||
#define sbh bcm947xx_sbh
|
||||
#define sbh_lock bcm947xx_sbh_lock
|
||||
|
||||
#define WINDOW_ADDR 0x1fc00000
|
||||
#define WINDOW_SIZE 0x400000
|
||||
#define BUSWIDTH 2
|
||||
|
||||
static struct mtd_info *bcm947xx_mtd;
|
||||
|
||||
__u8 bcm947xx_map_read8(struct map_info *map, unsigned long ofs)
|
||||
{
|
||||
if (map->map_priv_2 == 1)
|
||||
return __raw_readb(map->map_priv_1 + ofs);
|
||||
|
||||
u16 val = __raw_readw(map->map_priv_1 + (ofs & ~1));
|
||||
if (ofs & 1)
|
||||
return ((val >> 8) & 0xff);
|
||||
else
|
||||
return (val & 0xff);
|
||||
}
|
||||
|
||||
__u16 bcm947xx_map_read16(struct map_info *map, unsigned long ofs)
|
||||
{
|
||||
return __raw_readw(map->map_priv_1 + ofs);
|
||||
}
|
||||
|
||||
__u32 bcm947xx_map_read32(struct map_info *map, unsigned long ofs)
|
||||
{
|
||||
return __raw_readl(map->map_priv_1 + ofs);
|
||||
}
|
||||
|
||||
void bcm947xx_map_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
|
||||
{
|
||||
if (len==1) {
|
||||
memcpy_fromio(to, map->map_priv_1 + from, len);
|
||||
} else {
|
||||
int i;
|
||||
u16 *dest = (u16 *) to;
|
||||
u16 *src = (u16 *) (map->map_priv_1 + from);
|
||||
for (i = 0; i < (len / 2); i++) {
|
||||
dest[i] = src[i];
|
||||
}
|
||||
if (len & 1)
|
||||
*((u8 *)dest+len-1) = src[i] & 0xff;
|
||||
}
|
||||
}
|
||||
|
||||
void bcm947xx_map_write8(struct map_info *map, __u8 d, unsigned long adr)
|
||||
{
|
||||
__raw_writeb(d, map->map_priv_1 + adr);
|
||||
mb();
|
||||
}
|
||||
|
||||
void bcm947xx_map_write16(struct map_info *map, __u16 d, unsigned long adr)
|
||||
{
|
||||
__raw_writew(d, map->map_priv_1 + adr);
|
||||
mb();
|
||||
}
|
||||
|
||||
void bcm947xx_map_write32(struct map_info *map, __u32 d, unsigned long adr)
|
||||
{
|
||||
__raw_writel(d, map->map_priv_1 + adr);
|
||||
mb();
|
||||
}
|
||||
|
||||
void bcm947xx_map_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
|
||||
{
|
||||
memcpy_toio(map->map_priv_1 + to, from, len);
|
||||
}
|
||||
|
||||
struct map_info bcm947xx_map = {
|
||||
name: "Physically mapped flash",
|
||||
size: WINDOW_SIZE,
|
||||
buswidth: BUSWIDTH,
|
||||
read8: bcm947xx_map_read8,
|
||||
read16: bcm947xx_map_read16,
|
||||
read32: bcm947xx_map_read32,
|
||||
copy_from: bcm947xx_map_copy_from,
|
||||
write8: bcm947xx_map_write8,
|
||||
write16: bcm947xx_map_write16,
|
||||
write32: bcm947xx_map_write32,
|
||||
copy_to: bcm947xx_map_copy_to
|
||||
};
|
||||
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
|
||||
static struct mtd_partition bcm947xx_parts[] = {
|
||||
{ name: "cfe", offset: 0, size: 0, mask_flags: MTD_WRITEABLE, },
|
||||
{ name: "linux", offset: 0, size: 0, },
|
||||
{ name: "rootfs", offset: 0, size: 0, },
|
||||
{ name: "nvram", offset: 0, size: 0, },
|
||||
{ name: "rootfs_data", offset: 0, size: 0, },
|
||||
{ name: NULL, },
|
||||
};
|
||||
|
||||
static int __init
|
||||
find_cfe_size(struct mtd_info *mtd, size_t size)
|
||||
{
|
||||
struct trx_header *trx;
|
||||
unsigned char buf[512];
|
||||
int off;
|
||||
size_t len;
|
||||
int blocksize;
|
||||
|
||||
trx = (struct trx_header *) buf;
|
||||
|
||||
blocksize = mtd->erasesize;
|
||||
if (blocksize < 0x10000)
|
||||
blocksize = 0x10000;
|
||||
|
||||
for (off = (128*1024); off < size; off += blocksize) {
|
||||
memset(buf, 0xe5, sizeof(buf));
|
||||
|
||||
/*
|
||||
* Read into buffer
|
||||
*/
|
||||
if (MTD_READ(mtd, off, sizeof(buf), &len, buf) ||
|
||||
len != sizeof(buf))
|
||||
continue;
|
||||
|
||||
/* found a TRX header */
|
||||
if (le32_to_cpu(trx->magic) == TRX_MAGIC) {
|
||||
goto found;
|
||||
}
|
||||
}
|
||||
|
||||
printk(KERN_NOTICE
|
||||
"%s: Couldn't find bootloader size\n",
|
||||
mtd->name);
|
||||
return -1;
|
||||
|
||||
found:
|
||||
printk(KERN_NOTICE "bootloader size: %d\n", off);
|
||||
return off;
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* Copied from mtdblock.c
|
||||
*
|
||||
* Cache stuff...
|
||||
*
|
||||
* Since typical flash erasable sectors are much larger than what Linux's
|
||||
* buffer cache can handle, we must implement read-modify-write on flash
|
||||
* sectors for each block write requests. To avoid over-erasing flash sectors
|
||||
* and to speed things up, we locally cache a whole flash sector while it is
|
||||
* being written to until a different sector is required.
|
||||
*/
|
||||
|
||||
static void erase_callback(struct erase_info *done)
|
||||
{
|
||||
wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv;
|
||||
wake_up(wait_q);
|
||||
}
|
||||
|
||||
static int erase_write (struct mtd_info *mtd, unsigned long pos,
|
||||
int len, const char *buf)
|
||||
{
|
||||
struct erase_info erase;
|
||||
DECLARE_WAITQUEUE(wait, current);
|
||||
wait_queue_head_t wait_q;
|
||||
size_t retlen;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* First, let's erase the flash block.
|
||||
*/
|
||||
|
||||
init_waitqueue_head(&wait_q);
|
||||
erase.mtd = mtd;
|
||||
erase.callback = erase_callback;
|
||||
erase.addr = pos;
|
||||
erase.len = len;
|
||||
erase.priv = (u_long)&wait_q;
|
||||
|
||||
set_current_state(TASK_INTERRUPTIBLE);
|
||||
add_wait_queue(&wait_q, &wait);
|
||||
|
||||
ret = MTD_ERASE(mtd, &erase);
|
||||
if (ret) {
|
||||
set_current_state(TASK_RUNNING);
|
||||
remove_wait_queue(&wait_q, &wait);
|
||||
printk (KERN_WARNING "erase of region [0x%lx, 0x%x] "
|
||||
"on \"%s\" failed\n",
|
||||
pos, len, mtd->name);
|
||||
return ret;
|
||||
}
|
||||
|
||||
schedule(); /* Wait for erase to finish. */
|
||||
remove_wait_queue(&wait_q, &wait);
|
||||
|
||||
/*
|
||||
* Next, writhe data to flash.
|
||||
*/
|
||||
|
||||
ret = MTD_WRITE (mtd, pos, len, &retlen, buf);
|
||||
if (ret)
|
||||
return ret;
|
||||
if (retlen != len)
|
||||
return -EIO;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
static int __init
|
||||
find_root(struct mtd_info *mtd, size_t size, struct mtd_partition *part)
|
||||
{
|
||||
struct trx_header trx, *trx2;
|
||||
unsigned char buf[512], *block;
|
||||
int off, blocksize;
|
||||
u32 i, crc = ~0;
|
||||
size_t len;
|
||||
struct squashfs_super_block *sb = (struct squashfs_super_block *) buf;
|
||||
|
||||
blocksize = mtd->erasesize;
|
||||
if (blocksize < 0x10000)
|
||||
blocksize = 0x10000;
|
||||
|
||||
for (off = (128*1024); off < size; off += blocksize) {
|
||||
memset(&trx, 0xe5, sizeof(trx));
|
||||
|
||||
/*
|
||||
* Read into buffer
|
||||
*/
|
||||
if (MTD_READ(mtd, off, sizeof(trx), &len, (char *) &trx) ||
|
||||
len != sizeof(trx))
|
||||
continue;
|
||||
|
||||
/* found a TRX header */
|
||||
if (le32_to_cpu(trx.magic) == TRX_MAGIC) {
|
||||
part->offset = le32_to_cpu(trx.offsets[2]) ? :
|
||||
le32_to_cpu(trx.offsets[1]);
|
||||
part->size = le32_to_cpu(trx.len);
|
||||
|
||||
part->size -= part->offset;
|
||||
part->offset += off;
|
||||
|
||||
goto found;
|
||||
}
|
||||
}
|
||||
|
||||
printk(KERN_NOTICE
|
||||
"%s: Couldn't find root filesystem\n",
|
||||
mtd->name);
|
||||
return -1;
|
||||
|
||||
found:
|
||||
if (part->size == 0)
|
||||
return 0;
|
||||
|
||||
if (MTD_READ(mtd, part->offset, sizeof(buf), &len, buf) || len != sizeof(buf))
|
||||
return 0;
|
||||
|
||||
if (*((__u32 *) buf) == SQUASHFS_MAGIC) {
|
||||
printk(KERN_INFO "%s: Filesystem type: squashfs, size=0x%x\n", mtd->name, (u32) sb->bytes_used);
|
||||
|
||||
/* Update the squashfs partition size based on the superblock info */
|
||||
part->size = sb->bytes_used;
|
||||
len = part->offset + part->size;
|
||||
len += (mtd->erasesize - 1);
|
||||
len &= ~(mtd->erasesize - 1);
|
||||
part->size = len - part->offset;
|
||||
} else if (*((__u16 *) buf) == JFFS2_MAGIC_BITMASK) {
|
||||
printk(KERN_INFO "%s: Filesystem type: jffs2\n", mtd->name);
|
||||
|
||||
/* Move the squashfs outside of the trx */
|
||||
part->size = 0;
|
||||
} else {
|
||||
printk(KERN_INFO "%s: Filesystem type: unknown\n", mtd->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (trx.len != part->offset + part->size - off) {
|
||||
/* Update the trx offsets and length */
|
||||
trx.len = part->offset + part->size - off;
|
||||
|
||||
/* Update the trx crc32 */
|
||||
for (i = (u32) &(((struct trx_header *)NULL)->flag_version); i <= trx.len; i += sizeof(buf)) {
|
||||
if (MTD_READ(mtd, off + i, sizeof(buf), &len, buf) || len != sizeof(buf))
|
||||
return 0;
|
||||
crc = crc32_le(crc, buf, min(sizeof(buf), trx.len - i));
|
||||
}
|
||||
trx.crc32 = crc;
|
||||
|
||||
/* read first eraseblock from the trx */
|
||||
trx2 = block = kmalloc(mtd->erasesize, GFP_KERNEL);
|
||||
if (MTD_READ(mtd, off, mtd->erasesize, &len, block) || len != mtd->erasesize) {
|
||||
printk("Error accessing the first trx eraseblock\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
printk("Updating TRX offsets and length:\n");
|
||||
printk("old trx = [0x%08x, 0x%08x, 0x%08x], len=0x%08x crc32=0x%08x\n", trx2->offsets[0], trx2->offsets[1], trx2->offsets[2], trx2->len, trx2->crc32);
|
||||
printk("new trx = [0x%08x, 0x%08x, 0x%08x], len=0x%08x crc32=0x%08x\n", trx.offsets[0], trx.offsets[1], trx.offsets[2], trx.len, trx.crc32);
|
||||
|
||||
/* Write updated trx header to the flash */
|
||||
memcpy(block, &trx, sizeof(trx));
|
||||
if (mtd->unlock)
|
||||
mtd->unlock(mtd, off, mtd->erasesize);
|
||||
erase_write(mtd, off, mtd->erasesize, block);
|
||||
if (mtd->sync)
|
||||
mtd->sync(mtd);
|
||||
kfree(block);
|
||||
printk("Done\n");
|
||||
}
|
||||
|
||||
return part->size;
|
||||
}
|
||||
|
||||
struct mtd_partition * __init
|
||||
init_mtd_partitions(struct mtd_info *mtd, size_t size)
|
||||
{
|
||||
int cfe_size;
|
||||
|
||||
if ((cfe_size = find_cfe_size(mtd,size)) < 0)
|
||||
return NULL;
|
||||
|
||||
/* boot loader */
|
||||
bcm947xx_parts[0].offset = 0;
|
||||
bcm947xx_parts[0].size = cfe_size;
|
||||
|
||||
/* nvram */
|
||||
if (cfe_size != 384 * 1024) {
|
||||
bcm947xx_parts[3].offset = size - ROUNDUP(NVRAM_SPACE, mtd->erasesize);
|
||||
bcm947xx_parts[3].size = ROUNDUP(NVRAM_SPACE, mtd->erasesize);
|
||||
} else {
|
||||
/* nvram (old 128kb config partition on netgear wgt634u) */
|
||||
bcm947xx_parts[3].offset = bcm947xx_parts[0].size;
|
||||
bcm947xx_parts[3].size = ROUNDUP(NVRAM_SPACE, mtd->erasesize);
|
||||
}
|
||||
|
||||
/* linux (kernel and rootfs) */
|
||||
if (cfe_size != 384 * 1024) {
|
||||
bcm947xx_parts[1].offset = bcm947xx_parts[0].size;
|
||||
bcm947xx_parts[1].size = bcm947xx_parts[3].offset -
|
||||
bcm947xx_parts[1].offset;
|
||||
} else {
|
||||
/* do not count the elf loader, which is on one block */
|
||||
bcm947xx_parts[1].offset = bcm947xx_parts[0].size +
|
||||
bcm947xx_parts[3].size + mtd->erasesize;
|
||||
bcm947xx_parts[1].size = size -
|
||||
bcm947xx_parts[0].size -
|
||||
(2*bcm947xx_parts[3].size) -
|
||||
mtd->erasesize;
|
||||
}
|
||||
|
||||
/* find and size rootfs */
|
||||
if (find_root(mtd,size,&bcm947xx_parts[2])==0) {
|
||||
/* entirely jffs2 */
|
||||
bcm947xx_parts[4].name = NULL;
|
||||
bcm947xx_parts[2].size = size - bcm947xx_parts[2].offset -
|
||||
bcm947xx_parts[3].size;
|
||||
} else {
|
||||
/* legacy setup */
|
||||
/* calculate leftover flash, and assign it to the jffs2 partition */
|
||||
if (cfe_size != 384 * 1024) {
|
||||
bcm947xx_parts[4].offset = bcm947xx_parts[2].offset +
|
||||
bcm947xx_parts[2].size;
|
||||
if ((bcm947xx_parts[4].offset % mtd->erasesize) > 0) {
|
||||
bcm947xx_parts[4].offset += mtd->erasesize -
|
||||
(bcm947xx_parts[4].offset % mtd->erasesize);
|
||||
}
|
||||
bcm947xx_parts[4].size = bcm947xx_parts[3].offset -
|
||||
bcm947xx_parts[4].offset;
|
||||
} else {
|
||||
bcm947xx_parts[4].offset = bcm947xx_parts[2].offset +
|
||||
bcm947xx_parts[2].size;
|
||||
if ((bcm947xx_parts[4].offset % mtd->erasesize) > 0) {
|
||||
bcm947xx_parts[4].offset += mtd->erasesize -
|
||||
(bcm947xx_parts[4].offset % mtd->erasesize);
|
||||
}
|
||||
bcm947xx_parts[4].size = size - bcm947xx_parts[3].size -
|
||||
bcm947xx_parts[4].offset;
|
||||
}
|
||||
}
|
||||
|
||||
return bcm947xx_parts;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
mod_init_t init_bcm947xx_map(void)
|
||||
{
|
||||
ulong flags;
|
||||
uint coreidx;
|
||||
chipcregs_t *cc;
|
||||
uint32 fltype;
|
||||
uint window_addr = 0, window_size = 0;
|
||||
size_t size;
|
||||
int ret = 0;
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
struct mtd_partition *parts;
|
||||
int i;
|
||||
#endif
|
||||
|
||||
spin_lock_irqsave(&sbh_lock, flags);
|
||||
coreidx = sb_coreidx(sbh);
|
||||
|
||||
/* Check strapping option if chipcommon exists */
|
||||
if ((cc = sb_setcore(sbh, SB_CC, 0))) {
|
||||
fltype = readl(&cc->capabilities) & CC_CAP_FLASH_MASK;
|
||||
if (fltype == PFLASH) {
|
||||
bcm947xx_map.map_priv_2 = 1;
|
||||
window_addr = 0x1c000000;
|
||||
bcm947xx_map.size = window_size = 32 * 1024 * 1024;
|
||||
if ((readl(&cc->flash_config) & CC_CFG_DS) == 0)
|
||||
bcm947xx_map.buswidth = 1;
|
||||
}
|
||||
} else {
|
||||
fltype = PFLASH;
|
||||
bcm947xx_map.map_priv_2 = 0;
|
||||
window_addr = WINDOW_ADDR;
|
||||
window_size = WINDOW_SIZE;
|
||||
}
|
||||
|
||||
sb_setcoreidx(sbh, coreidx);
|
||||
spin_unlock_irqrestore(&sbh_lock, flags);
|
||||
|
||||
if (fltype != PFLASH) {
|
||||
printk(KERN_ERR "pflash: found no supported devices\n");
|
||||
ret = -ENODEV;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
bcm947xx_map.map_priv_1 = (unsigned long) ioremap(window_addr, window_size);
|
||||
|
||||
if (!bcm947xx_map.map_priv_1) {
|
||||
printk(KERN_ERR "Failed to ioremap\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
if (!(bcm947xx_mtd = do_map_probe("cfi_probe", &bcm947xx_map))) {
|
||||
printk(KERN_ERR "pflash: cfi_probe failed\n");
|
||||
iounmap((void *)bcm947xx_map.map_priv_1);
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
bcm947xx_mtd->module = THIS_MODULE;
|
||||
|
||||
size = bcm947xx_mtd->size;
|
||||
|
||||
printk(KERN_NOTICE "Flash device: 0x%x at 0x%x\n", size, window_addr);
|
||||
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
parts = init_mtd_partitions(bcm947xx_mtd, size);
|
||||
for (i = 0; parts[i].name; i++);
|
||||
ret = add_mtd_partitions(bcm947xx_mtd, parts, i);
|
||||
if (ret) {
|
||||
printk(KERN_ERR "Flash: add_mtd_partitions failed\n");
|
||||
goto fail;
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
if (bcm947xx_mtd)
|
||||
map_destroy(bcm947xx_mtd);
|
||||
if (bcm947xx_map.map_priv_1)
|
||||
iounmap((void *) bcm947xx_map.map_priv_1);
|
||||
bcm947xx_map.map_priv_1 = 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
mod_exit_t cleanup_bcm947xx_map(void)
|
||||
{
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
del_mtd_partitions(bcm947xx_mtd);
|
||||
#endif
|
||||
map_destroy(bcm947xx_mtd);
|
||||
iounmap((void *) bcm947xx_map.map_priv_1);
|
||||
bcm947xx_map.map_priv_1 = 0;
|
||||
}
|
||||
|
||||
module_init(init_bcm947xx_map);
|
||||
module_exit(cleanup_bcm947xx_map);
|
||||
|
|
@ -1,345 +0,0 @@
|
|||
/* Low-level parallel port routines for the ASUS WL-500g built-in port
|
||||
*
|
||||
* Author: Nuno Grilo <nuno.grilo@netcabo.pt>
|
||||
* Based on parport_pc source
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/parport.h>
|
||||
#include <linux/parport_pc.h>
|
||||
|
||||
#define SPLINK_ADDRESS 0xBF800010
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#ifdef DEBUG
|
||||
#define DPRINTK printk
|
||||
#else
|
||||
#define DPRINTK(stuff...)
|
||||
#endif
|
||||
|
||||
|
||||
/* __parport_splink_frob_control differs from parport_splink_frob_control in that
|
||||
* it doesn't do any extra masking. */
|
||||
static __inline__ unsigned char __parport_splink_frob_control (struct parport *p,
|
||||
unsigned char mask,
|
||||
unsigned char val)
|
||||
{
|
||||
struct parport_pc_private *priv = p->physport->private_data;
|
||||
unsigned char *io = (unsigned char *) p->base;
|
||||
unsigned char ctr = priv->ctr;
|
||||
#ifdef DEBUG_PARPORT
|
||||
printk (KERN_DEBUG
|
||||
"__parport_splink_frob_control(%02x,%02x): %02x -> %02x\n",
|
||||
mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable);
|
||||
#endif
|
||||
ctr = (ctr & ~mask) ^ val;
|
||||
ctr &= priv->ctr_writable; /* only write writable bits. */
|
||||
*(io+2) = ctr;
|
||||
priv->ctr = ctr; /* Update soft copy */
|
||||
return ctr;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void parport_splink_data_forward (struct parport *p)
|
||||
{
|
||||
DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
|
||||
__parport_splink_frob_control (p, 0x20, 0);
|
||||
}
|
||||
|
||||
static void parport_splink_data_reverse (struct parport *p)
|
||||
{
|
||||
DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
|
||||
__parport_splink_frob_control (p, 0x20, 0x20);
|
||||
}
|
||||
|
||||
/*
|
||||
static void parport_splink_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
||||
{
|
||||
DPRINTK(KERN_DEBUG "parport_splink: IRQ handler called\n");
|
||||
parport_generic_irq(irq, (struct parport *) dev_id, regs);
|
||||
}
|
||||
*/
|
||||
|
||||
static void parport_splink_enable_irq(struct parport *p)
|
||||
{
|
||||
DPRINTK(KERN_DEBUG "parport_splink: parport_splink_enable_irq called\n");
|
||||
__parport_splink_frob_control (p, 0x10, 0x10);
|
||||
}
|
||||
|
||||
static void parport_splink_disable_irq(struct parport *p)
|
||||
{
|
||||
DPRINTK(KERN_DEBUG "parport_splink: parport_splink_disable_irq called\n");
|
||||
__parport_splink_frob_control (p, 0x10, 0);
|
||||
}
|
||||
|
||||
static void parport_splink_init_state(struct pardevice *dev, struct parport_state *s)
|
||||
{
|
||||
DPRINTK(KERN_DEBUG "parport_splink: parport_splink_init_state called\n");
|
||||
s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0);
|
||||
if (dev->irq_func &&
|
||||
dev->port->irq != PARPORT_IRQ_NONE)
|
||||
/* Set ackIntEn */
|
||||
s->u.pc.ctr |= 0x10;
|
||||
}
|
||||
|
||||
static void parport_splink_save_state(struct parport *p, struct parport_state *s)
|
||||
{
|
||||
const struct parport_pc_private *priv = p->physport->private_data;
|
||||
DPRINTK(KERN_DEBUG "parport_splink: parport_splink_save_state called\n");
|
||||
s->u.pc.ctr = priv->ctr;
|
||||
}
|
||||
|
||||
static void parport_splink_restore_state(struct parport *p, struct parport_state *s)
|
||||
{
|
||||
struct parport_pc_private *priv = p->physport->private_data;
|
||||
unsigned char *io = (unsigned char *) p->base;
|
||||
unsigned char ctr = s->u.pc.ctr;
|
||||
|
||||
DPRINTK(KERN_DEBUG "parport_splink: parport_splink_restore_state called\n");
|
||||
*(io+2) = ctr;
|
||||
priv->ctr = ctr;
|
||||
}
|
||||
|
||||
static void parport_splink_setup_interrupt(void) {
|
||||
return;
|
||||
}
|
||||
|
||||
static void parport_splink_write_data(struct parport *p, unsigned char d) {
|
||||
DPRINTK(KERN_DEBUG "parport_splink: write data called\n");
|
||||
unsigned char *io = (unsigned char *) p->base;
|
||||
*io = d;
|
||||
}
|
||||
|
||||
static unsigned char parport_splink_read_data(struct parport *p) {
|
||||
DPRINTK(KERN_DEBUG "parport_splink: read data called\n");
|
||||
unsigned char *io = (unsigned char *) p->base;
|
||||
return *io;
|
||||
}
|
||||
|
||||
static void parport_splink_write_control(struct parport *p, unsigned char d)
|
||||
{
|
||||
const unsigned char wm = (PARPORT_CONTROL_STROBE |
|
||||
PARPORT_CONTROL_AUTOFD |
|
||||
PARPORT_CONTROL_INIT |
|
||||
PARPORT_CONTROL_SELECT);
|
||||
|
||||
DPRINTK(KERN_DEBUG "parport_splink: write control called\n");
|
||||
/* Take this out when drivers have adapted to the newer interface. */
|
||||
if (d & 0x20) {
|
||||
printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
|
||||
p->name, p->cad->name);
|
||||
parport_splink_data_reverse (p);
|
||||
}
|
||||
|
||||
__parport_splink_frob_control (p, wm, d & wm);
|
||||
}
|
||||
|
||||
static unsigned char parport_splink_read_control(struct parport *p)
|
||||
{
|
||||
const unsigned char wm = (PARPORT_CONTROL_STROBE |
|
||||
PARPORT_CONTROL_AUTOFD |
|
||||
PARPORT_CONTROL_INIT |
|
||||
PARPORT_CONTROL_SELECT);
|
||||
DPRINTK(KERN_DEBUG "parport_splink: read control called\n");
|
||||
const struct parport_pc_private *priv = p->physport->private_data;
|
||||
return priv->ctr & wm; /* Use soft copy */
|
||||
}
|
||||
|
||||
static unsigned char parport_splink_frob_control (struct parport *p, unsigned char mask,
|
||||
unsigned char val)
|
||||
{
|
||||
const unsigned char wm = (PARPORT_CONTROL_STROBE |
|
||||
PARPORT_CONTROL_AUTOFD |
|
||||
PARPORT_CONTROL_INIT |
|
||||
PARPORT_CONTROL_SELECT);
|
||||
|
||||
DPRINTK(KERN_DEBUG "parport_splink: frob control called\n");
|
||||
/* Take this out when drivers have adapted to the newer interface. */
|
||||
if (mask & 0x20) {
|
||||
printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
|
||||
p->name, p->cad->name,
|
||||
(val & 0x20) ? "reverse" : "forward");
|
||||
if (val & 0x20)
|
||||
parport_splink_data_reverse (p);
|
||||
else
|
||||
parport_splink_data_forward (p);
|
||||
}
|
||||
|
||||
/* Restrict mask and val to control lines. */
|
||||
mask &= wm;
|
||||
val &= wm;
|
||||
|
||||
return __parport_splink_frob_control (p, mask, val);
|
||||
}
|
||||
|
||||
static unsigned char parport_splink_read_status(struct parport *p)
|
||||
{
|
||||
DPRINTK(KERN_DEBUG "parport_splink: read status called\n");
|
||||
unsigned char *io = (unsigned char *) p->base;
|
||||
return *(io+1);
|
||||
}
|
||||
|
||||
static void parport_splink_inc_use_count(void)
|
||||
{
|
||||
#ifdef MODULE
|
||||
MOD_INC_USE_COUNT;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void parport_splink_dec_use_count(void)
|
||||
{
|
||||
#ifdef MODULE
|
||||
MOD_DEC_USE_COUNT;
|
||||
#endif
|
||||
}
|
||||
|
||||
static struct parport_operations parport_splink_ops =
|
||||
{
|
||||
parport_splink_write_data,
|
||||
parport_splink_read_data,
|
||||
|
||||
parport_splink_write_control,
|
||||
parport_splink_read_control,
|
||||
parport_splink_frob_control,
|
||||
|
||||
parport_splink_read_status,
|
||||
|
||||
parport_splink_enable_irq,
|
||||
parport_splink_disable_irq,
|
||||
|
||||
parport_splink_data_forward,
|
||||
parport_splink_data_reverse,
|
||||
|
||||
parport_splink_init_state,
|
||||
parport_splink_save_state,
|
||||
parport_splink_restore_state,
|
||||
|
||||
parport_splink_inc_use_count,
|
||||
parport_splink_dec_use_count,
|
||||
|
||||
parport_ieee1284_epp_write_data,
|
||||
parport_ieee1284_epp_read_data,
|
||||
parport_ieee1284_epp_write_addr,
|
||||
parport_ieee1284_epp_read_addr,
|
||||
|
||||
parport_ieee1284_ecp_write_data,
|
||||
parport_ieee1284_ecp_read_data,
|
||||
parport_ieee1284_ecp_write_addr,
|
||||
|
||||
parport_ieee1284_write_compat,
|
||||
parport_ieee1284_read_nibble,
|
||||
parport_ieee1284_read_byte,
|
||||
};
|
||||
|
||||
/* --- Initialisation code -------------------------------- */
|
||||
|
||||
static struct parport *parport_splink_probe_port (unsigned long int base)
|
||||
{
|
||||
struct parport_pc_private *priv;
|
||||
struct parport_operations *ops;
|
||||
struct parport *p;
|
||||
|
||||
if (check_mem_region(base, 3)) {
|
||||
printk (KERN_DEBUG "parport (0x%lx): iomem region not available\n", base);
|
||||
return NULL;
|
||||
}
|
||||
priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
|
||||
if (!priv) {
|
||||
printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
|
||||
return NULL;
|
||||
}
|
||||
ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
|
||||
if (!ops) {
|
||||
printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
|
||||
base);
|
||||
kfree (priv);
|
||||
return NULL;
|
||||
}
|
||||
memcpy (ops, &parport_splink_ops, sizeof (struct parport_operations));
|
||||
priv->ctr = 0xc;
|
||||
priv->ctr_writable = 0xff;
|
||||
|
||||
if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
|
||||
PARPORT_DMA_NONE, ops))) {
|
||||
printk (KERN_DEBUG "parport (0x%lx): registration failed!\n",
|
||||
base);
|
||||
kfree (priv);
|
||||
kfree (ops);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
|
||||
p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
|
||||
p->private_data = priv;
|
||||
|
||||
parport_proc_register(p);
|
||||
request_mem_region (p->base, 3, p->name);
|
||||
|
||||
/* Done probing. Now put the port into a sensible start-up state. */
|
||||
parport_splink_write_data(p, 0);
|
||||
parport_splink_data_forward (p);
|
||||
|
||||
/* Now that we've told the sharing engine about the port, and
|
||||
found out its characteristics, let the high-level drivers
|
||||
know about it. */
|
||||
parport_announce_port (p);
|
||||
|
||||
DPRINTK(KERN_DEBUG "parport (0x%lx): init ok!\n",
|
||||
base);
|
||||
return p;
|
||||
}
|
||||
|
||||
static void parport_splink_unregister_port(struct parport *p) {
|
||||
struct parport_pc_private *priv = p->private_data;
|
||||
struct parport_operations *ops = p->ops;
|
||||
|
||||
if (p->irq != PARPORT_IRQ_NONE)
|
||||
free_irq(p->irq, p);
|
||||
release_mem_region(p->base, 3);
|
||||
parport_proc_unregister(p);
|
||||
kfree (priv);
|
||||
parport_unregister_port(p);
|
||||
kfree (ops);
|
||||
}
|
||||
|
||||
|
||||
int parport_splink_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
DPRINTK(KERN_DEBUG "parport_splink init called\n");
|
||||
parport_splink_setup_interrupt();
|
||||
ret = !parport_splink_probe_port(SPLINK_ADDRESS);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void parport_splink_cleanup(void) {
|
||||
struct parport *p = parport_enumerate(), *tmp;
|
||||
DPRINTK(KERN_DEBUG "parport_splink cleanup called\n");
|
||||
if (p->size) {
|
||||
if (p->modes & PARPORT_MODE_PCSPP) {
|
||||
while(p) {
|
||||
tmp = p->next;
|
||||
parport_splink_unregister_port(p);
|
||||
p = tmp;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
MODULE_AUTHOR("Nuno Grilo <nuno.grilo@netcabo.pt>");
|
||||
MODULE_DESCRIPTION("Parport Driver for ASUS WL-500g router builtin Port");
|
||||
MODULE_SUPPORTED_DEVICE("ASUS WL-500g builtin Parallel Port");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
module_init(parport_splink_init)
|
||||
module_exit(parport_splink_cleanup)
|
||||
|
||||
|
|
@ -1,110 +0,0 @@
|
|||
#
|
||||
# Copyright (C) 2006-2010 OpenWrt.org
|
||||
#
|
||||
# This is free software, licensed under the GNU General Public License v2.
|
||||
# See /LICENSE for more information.
|
||||
#
|
||||
include $(TOPDIR)/rules.mk
|
||||
include $(INCLUDE_DIR)/image.mk
|
||||
|
||||
define Build/Clean
|
||||
$(MAKE) -C lzma-loader clean
|
||||
endef
|
||||
|
||||
define Image/Prepare
|
||||
cat $(KDIR)/vmlinux | $(STAGING_DIR_HOST)/bin/lzma e -si -so -eos -lc1 -lp2 -pb2 > $(KDIR)/vmlinux.lzma
|
||||
rm -f $(KDIR)/loader.gz
|
||||
$(MAKE) -C lzma-loader \
|
||||
BUILD_DIR="$(KDIR)" \
|
||||
TARGET="$(KDIR)" \
|
||||
clean install
|
||||
echo -ne "\\x00" >> $(KDIR)/loader.gz
|
||||
rm -f $(KDIR)/fs_mark
|
||||
touch $(KDIR)/fs_mark
|
||||
$(call prepare_generic_squashfs,$(KDIR)/fs_mark)
|
||||
endef
|
||||
|
||||
ifneq ($(KERNEL),2.4)
|
||||
define Image/Build/wgt634u
|
||||
dd if=$(KDIR)/loader.elf of=$(BIN_DIR)/openwrt-wgt634u-$(2).bin bs=131072 conv=sync
|
||||
cat $(BIN_DIR)/$(IMG_PREFIX)-$(1).trx >> $(BIN_DIR)/openwrt-wgt634u-$(2).bin
|
||||
endef
|
||||
endif
|
||||
|
||||
define Image/Build/CyberTAN
|
||||
$(STAGING_DIR_HOST)/bin/addpattern -4 -p $(3) -v v$(4) -i $(BIN_DIR)/$(IMG_PREFIX)-$(1).trx -o $(BIN_DIR)/openwrt-$(2)-$(5).bin $(if $(6),-s $(6))
|
||||
endef
|
||||
define Image/Build/CyberTAN2
|
||||
$(STAGING_DIR_HOST)/bin/addpattern -4 -p $(3) -v v$(4) -i $(BIN_DIR)/openwrt-$(2)-$(5)-sysupgrade.bin -o $(BIN_DIR)/openwrt-$(2)-$(5)-factory.bin $(if $(6),-s $(6))
|
||||
endef
|
||||
define Image/Build/CyberTANHead
|
||||
$(STAGING_DIR_HOST)/bin/addpattern -5 -p $(3) -v v$(4) -i /dev/null -o $(KDIR)/openwrt-$(2)-header.bin $(if $(6),-s $(6))
|
||||
endef
|
||||
|
||||
define Image/Build/Motorola
|
||||
$(STAGING_DIR_HOST)/bin/motorola-bin -$(3) $(BIN_DIR)/$(IMG_PREFIX)-$(1).trx $(BIN_DIR)/openwrt-$(2)-$(4).bin
|
||||
endef
|
||||
|
||||
define Image/Build/USR
|
||||
$(STAGING_DIR_HOST)/bin/trx2usr $(BIN_DIR)/$(IMG_PREFIX)-$(1).trx $(BIN_DIR)/openwrt-$(2)-$(3).bin
|
||||
endef
|
||||
|
||||
define trxalign/jffs2-128k
|
||||
-a 0x20000 -f $(KDIR)/root.$(1)
|
||||
endef
|
||||
define trxalign/jffs2-64k
|
||||
-a 0x10000 -f $(KDIR)/root.$(1)
|
||||
endef
|
||||
define trxalign/squashfs
|
||||
-a 1024 -f $(KDIR)/root.$(1) $(if $(2),-f $(2)) -a 0x10000 -A $(KDIR)/fs_mark
|
||||
endef
|
||||
|
||||
define Image/Build/trxV2
|
||||
$(call Image/Build/CyberTANHead,$(1),$(2),$(3),$(4),$(5),$(if $(6),$(6)))
|
||||
$(STAGING_DIR_HOST)/bin/trx -2 -o $(BIN_DIR)/openwrt-$(2)-$(5)-sysupgrade.bin \
|
||||
-f $(KDIR)/loader.gz -f $(KDIR)/vmlinux.lzma \
|
||||
$(call trxalign/$(1),$(1),$(KDIR)/openwrt-$(2)-header.bin)
|
||||
$(call Image/Build/CyberTAN2,$(1),$(2),$(3),$(4),$(5),$(if $(6),$(6)))
|
||||
endef
|
||||
|
||||
define Image/Build/jffs2-128k
|
||||
$(call Image/Build/CyberTAN,$(1),wrt54gs,W54S,4.80.1,$(patsubst jffs2-%,jffs2,$(1)))
|
||||
$(call Image/Build/CyberTAN,$(1),wrtsl54gs,W54U,2.08.1,$(patsubst jffs2-%,jffs2,$(1)))
|
||||
$(call Image/Build/trxV2,$(1),wrt54g3gv2-vf,3G2V,3.00.24,$(patsubst jffs2-%,jffs2,$(1)),6)
|
||||
ifeq ($(KERNEL),2.6)
|
||||
$(call Image/Build/wgt634u,$(1),$(patsubst jffs2-%,jffs2,$(1)))
|
||||
endif
|
||||
endef
|
||||
|
||||
define Image/Build/jffs2-64k
|
||||
$(call Image/Build/CyberTAN,$(1),wrt54g3g,W54F,2.20.1,$(patsubst jffs2-%,jffs2,$(1)))
|
||||
$(call Image/Build/CyberTAN,$(1),wrt54g3g-em,W3GN,2.20.1,$(patsubst jffs2-%,jffs2,$(1)))
|
||||
$(call Image/Build/CyberTAN,$(1),wrt54g,W54G,4.71.1,$(patsubst jffs2-%,jffs2,$(1)))
|
||||
$(call Image/Build/CyberTAN,$(1),wrt54gs_v4,W54s,1.09.1,$(patsubst jffs2-%,jffs2,$(1)))
|
||||
$(call Image/Build/CyberTAN,$(1),wrt150n,N150,1.51.3,$(patsubst jffs2-%,jffs2,$(1)))
|
||||
$(call Image/Build/CyberTAN,$(1),wrt300n_v1,EWCB,1.03.6,$(patsubst jffs2-%,jffs2,$(1)))
|
||||
$(call Image/Build/CyberTAN,$(1),wrt300n_v11,EWC2,1.51.2,$(patsubst jffs2-%,jffs2,$(1)))
|
||||
$(call Image/Build/CyberTAN,$(1),wrt350n_v1,EWCG,1.04.1,$(patsubst jffs2-%,jffs2,$(1)))
|
||||
$(call Image/Build/Motorola,$(1),wa840g,2,$(patsubst jffs2-%,jffs2,$(1)))
|
||||
$(call Image/Build/Motorola,$(1),we800g,3,$(patsubst jffs2-%,jffs2,$(1)))
|
||||
endef
|
||||
|
||||
define Image/Build/squashfs
|
||||
$(call Image/Build/jffs2-64k,$(1))
|
||||
$(call Image/Build/jffs2-128k,$(1))
|
||||
endef
|
||||
|
||||
define Image/Build/Initramfs
|
||||
$(STAGING_DIR_HOST)/bin/trx -o $(BIN_DIR)/$(IMG_PREFIX)-initramfs.trx -f $(KDIR)/loader.gz -f $(KDIR)/vmlinux.lzma
|
||||
endef
|
||||
|
||||
define Image/Build
|
||||
$(STAGING_DIR_HOST)/bin/trx -o $(BIN_DIR)/$(IMG_PREFIX)-$(1).trx \
|
||||
-f $(KDIR)/loader.gz -f $(KDIR)/vmlinux.lzma \
|
||||
$(call trxalign/$(1),$(1))
|
||||
$(call Image/Build/$(1),$(1))
|
||||
$(call Image/Build/Motorola,$(1),wr850g,1,$(1))
|
||||
$(call Image/Build/USR,$(1),usr5461,$(1))
|
||||
endef
|
||||
|
||||
$(eval $(call BuildImage))
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
#
|
||||
# Copyright (C) 2006 OpenWrt.org
|
||||
#
|
||||
# This is free software, licensed under the GNU General Public License v2.
|
||||
# See /LICENSE for more information.
|
||||
#
|
||||
|
||||
include $(TOPDIR)/rules.mk
|
||||
|
||||
PKG_NAME := lzma-loader
|
||||
PKG_BUILD_DIR := $(BUILD_DIR)/$(PKG_NAME)
|
||||
|
||||
$(PKG_BUILD_DIR)/.prepared:
|
||||
mkdir $(PKG_BUILD_DIR)
|
||||
$(CP) ./src/* $(PKG_BUILD_DIR)/
|
||||
touch $@
|
||||
|
||||
$(PKG_BUILD_DIR)/loader.gz: $(PKG_BUILD_DIR)/.prepared
|
||||
$(MAKE) -C $(PKG_BUILD_DIR) CC="$(TARGET_CC)" \
|
||||
LD="$(TARGET_CROSS)ld" CROSS_COMPILE="$(TARGET_CROSS)"
|
||||
|
||||
download:
|
||||
prepare: $(PKG_BUILD_DIR)/.prepared
|
||||
compile: $(PKG_BUILD_DIR)/loader.gz
|
||||
install:
|
||||
|
||||
ifneq ($(TARGET),)
|
||||
install: compile
|
||||
$(CP) $(PKG_BUILD_DIR)/loader.gz $(PKG_BUILD_DIR)/loader.elf $(TARGET)/
|
||||
endif
|
||||
|
||||
clean:
|
||||
rm -rf $(PKG_BUILD_DIR)
|
||||
|
|
@ -1,663 +0,0 @@
|
|||
/*
|
||||
LzmaDecode.c
|
||||
LZMA Decoder
|
||||
|
||||
LZMA SDK 4.05 Copyright (c) 1999-2004 Igor Pavlov (2004-08-25)
|
||||
http://www.7-zip.org/
|
||||
|
||||
LZMA SDK is licensed under two licenses:
|
||||
1) GNU Lesser General Public License (GNU LGPL)
|
||||
2) Common Public License (CPL)
|
||||
It means that you can select one of these two licenses and
|
||||
follow rules of that license.
|
||||
|
||||
SPECIAL EXCEPTION:
|
||||
Igor Pavlov, as the author of this code, expressly permits you to
|
||||
statically or dynamically link your code (or bind by name) to the
|
||||
interfaces of this file without subjecting your linked code to the
|
||||
terms of the CPL or GNU LGPL. Any modifications or additions
|
||||
to this file, however, are subject to the LGPL or CPL terms.
|
||||
*/
|
||||
|
||||
#include "LzmaDecode.h"
|
||||
|
||||
#ifndef Byte
|
||||
#define Byte unsigned char
|
||||
#endif
|
||||
|
||||
#define kNumTopBits 24
|
||||
#define kTopValue ((UInt32)1 << kNumTopBits)
|
||||
|
||||
#define kNumBitModelTotalBits 11
|
||||
#define kBitModelTotal (1 << kNumBitModelTotalBits)
|
||||
#define kNumMoveBits 5
|
||||
|
||||
typedef struct _CRangeDecoder
|
||||
{
|
||||
Byte *Buffer;
|
||||
Byte *BufferLim;
|
||||
UInt32 Range;
|
||||
UInt32 Code;
|
||||
#ifdef _LZMA_IN_CB
|
||||
ILzmaInCallback *InCallback;
|
||||
int Result;
|
||||
#endif
|
||||
int ExtraBytes;
|
||||
} CRangeDecoder;
|
||||
|
||||
Byte RangeDecoderReadByte(CRangeDecoder *rd)
|
||||
{
|
||||
if (rd->Buffer == rd->BufferLim)
|
||||
{
|
||||
#ifdef _LZMA_IN_CB
|
||||
UInt32 size;
|
||||
rd->Result = rd->InCallback->Read(rd->InCallback, &rd->Buffer, &size);
|
||||
rd->BufferLim = rd->Buffer + size;
|
||||
if (size == 0)
|
||||
#endif
|
||||
{
|
||||
rd->ExtraBytes = 1;
|
||||
return 0xFF;
|
||||
}
|
||||
}
|
||||
return (*rd->Buffer++);
|
||||
}
|
||||
|
||||
/* #define ReadByte (*rd->Buffer++) */
|
||||
#define ReadByte (RangeDecoderReadByte(rd))
|
||||
|
||||
void RangeDecoderInit(CRangeDecoder *rd,
|
||||
#ifdef _LZMA_IN_CB
|
||||
ILzmaInCallback *inCallback
|
||||
#else
|
||||
Byte *stream, UInt32 bufferSize
|
||||
#endif
|
||||
)
|
||||
{
|
||||
int i;
|
||||
#ifdef _LZMA_IN_CB
|
||||
rd->InCallback = inCallback;
|
||||
rd->Buffer = rd->BufferLim = 0;
|
||||
#else
|
||||
rd->Buffer = stream;
|
||||
rd->BufferLim = stream + bufferSize;
|
||||
#endif
|
||||
rd->ExtraBytes = 0;
|
||||
rd->Code = 0;
|
||||
rd->Range = (0xFFFFFFFF);
|
||||
for(i = 0; i < 5; i++)
|
||||
rd->Code = (rd->Code << 8) | ReadByte;
|
||||
}
|
||||
|
||||
#define RC_INIT_VAR UInt32 range = rd->Range; UInt32 code = rd->Code;
|
||||
#define RC_FLUSH_VAR rd->Range = range; rd->Code = code;
|
||||
#define RC_NORMALIZE if (range < kTopValue) { range <<= 8; code = (code << 8) | ReadByte; }
|
||||
|
||||
UInt32 RangeDecoderDecodeDirectBits(CRangeDecoder *rd, int numTotalBits)
|
||||
{
|
||||
RC_INIT_VAR
|
||||
UInt32 result = 0;
|
||||
int i;
|
||||
for (i = numTotalBits; i > 0; i--)
|
||||
{
|
||||
/* UInt32 t; */
|
||||
range >>= 1;
|
||||
|
||||
result <<= 1;
|
||||
if (code >= range)
|
||||
{
|
||||
code -= range;
|
||||
result |= 1;
|
||||
}
|
||||
/*
|
||||
t = (code - range) >> 31;
|
||||
t &= 1;
|
||||
code -= range & (t - 1);
|
||||
result = (result + result) | (1 - t);
|
||||
*/
|
||||
RC_NORMALIZE
|
||||
}
|
||||
RC_FLUSH_VAR
|
||||
return result;
|
||||
}
|
||||
|
||||
int RangeDecoderBitDecode(CProb *prob, CRangeDecoder *rd)
|
||||
{
|
||||
UInt32 bound = (rd->Range >> kNumBitModelTotalBits) * *prob;
|
||||
if (rd->Code < bound)
|
||||
{
|
||||
rd->Range = bound;
|
||||
*prob += (kBitModelTotal - *prob) >> kNumMoveBits;
|
||||
if (rd->Range < kTopValue)
|
||||
{
|
||||
rd->Code = (rd->Code << 8) | ReadByte;
|
||||
rd->Range <<= 8;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
rd->Range -= bound;
|
||||
rd->Code -= bound;
|
||||
*prob -= (*prob) >> kNumMoveBits;
|
||||
if (rd->Range < kTopValue)
|
||||
{
|
||||
rd->Code = (rd->Code << 8) | ReadByte;
|
||||
rd->Range <<= 8;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
#define RC_GET_BIT2(prob, mi, A0, A1) \
|
||||
UInt32 bound = (range >> kNumBitModelTotalBits) * *prob; \
|
||||
if (code < bound) \
|
||||
{ A0; range = bound; *prob += (kBitModelTotal - *prob) >> kNumMoveBits; mi <<= 1; } \
|
||||
else \
|
||||
{ A1; range -= bound; code -= bound; *prob -= (*prob) >> kNumMoveBits; mi = (mi + mi) + 1; } \
|
||||
RC_NORMALIZE
|
||||
|
||||
#define RC_GET_BIT(prob, mi) RC_GET_BIT2(prob, mi, ; , ;)
|
||||
|
||||
int RangeDecoderBitTreeDecode(CProb *probs, int numLevels, CRangeDecoder *rd)
|
||||
{
|
||||
int mi = 1;
|
||||
int i;
|
||||
#ifdef _LZMA_LOC_OPT
|
||||
RC_INIT_VAR
|
||||
#endif
|
||||
for(i = numLevels; i > 0; i--)
|
||||
{
|
||||
#ifdef _LZMA_LOC_OPT
|
||||
CProb *prob = probs + mi;
|
||||
RC_GET_BIT(prob, mi)
|
||||
#else
|
||||
mi = (mi + mi) + RangeDecoderBitDecode(probs + mi, rd);
|
||||
#endif
|
||||
}
|
||||
#ifdef _LZMA_LOC_OPT
|
||||
RC_FLUSH_VAR
|
||||
#endif
|
||||
return mi - (1 << numLevels);
|
||||
}
|
||||
|
||||
int RangeDecoderReverseBitTreeDecode(CProb *probs, int numLevels, CRangeDecoder *rd)
|
||||
{
|
||||
int mi = 1;
|
||||
int i;
|
||||
int symbol = 0;
|
||||
#ifdef _LZMA_LOC_OPT
|
||||
RC_INIT_VAR
|
||||
#endif
|
||||
for(i = 0; i < numLevels; i++)
|
||||
{
|
||||
#ifdef _LZMA_LOC_OPT
|
||||
CProb *prob = probs + mi;
|
||||
RC_GET_BIT2(prob, mi, ; , symbol |= (1 << i))
|
||||
#else
|
||||
int bit = RangeDecoderBitDecode(probs + mi, rd);
|
||||
mi = mi + mi + bit;
|
||||
symbol |= (bit << i);
|
||||
#endif
|
||||
}
|
||||
#ifdef _LZMA_LOC_OPT
|
||||
RC_FLUSH_VAR
|
||||
#endif
|
||||
return symbol;
|
||||
}
|
||||
|
||||
Byte LzmaLiteralDecode(CProb *probs, CRangeDecoder *rd)
|
||||
{
|
||||
int symbol = 1;
|
||||
#ifdef _LZMA_LOC_OPT
|
||||
RC_INIT_VAR
|
||||
#endif
|
||||
do
|
||||
{
|
||||
#ifdef _LZMA_LOC_OPT
|
||||
CProb *prob = probs + symbol;
|
||||
RC_GET_BIT(prob, symbol)
|
||||
#else
|
||||
symbol = (symbol + symbol) | RangeDecoderBitDecode(probs + symbol, rd);
|
||||
#endif
|
||||
}
|
||||
while (symbol < 0x100);
|
||||
#ifdef _LZMA_LOC_OPT
|
||||
RC_FLUSH_VAR
|
||||
#endif
|
||||
return symbol;
|
||||
}
|
||||
|
||||
Byte LzmaLiteralDecodeMatch(CProb *probs, CRangeDecoder *rd, Byte matchByte)
|
||||
{
|
||||
int symbol = 1;
|
||||
#ifdef _LZMA_LOC_OPT
|
||||
RC_INIT_VAR
|
||||
#endif
|
||||
do
|
||||
{
|
||||
int bit;
|
||||
int matchBit = (matchByte >> 7) & 1;
|
||||
matchByte <<= 1;
|
||||
#ifdef _LZMA_LOC_OPT
|
||||
{
|
||||
CProb *prob = probs + ((1 + matchBit) << 8) + symbol;
|
||||
RC_GET_BIT2(prob, symbol, bit = 0, bit = 1)
|
||||
}
|
||||
#else
|
||||
bit = RangeDecoderBitDecode(probs + ((1 + matchBit) << 8) + symbol, rd);
|
||||
symbol = (symbol << 1) | bit;
|
||||
#endif
|
||||
if (matchBit != bit)
|
||||
{
|
||||
while (symbol < 0x100)
|
||||
{
|
||||
#ifdef _LZMA_LOC_OPT
|
||||
CProb *prob = probs + symbol;
|
||||
RC_GET_BIT(prob, symbol)
|
||||
#else
|
||||
symbol = (symbol + symbol) | RangeDecoderBitDecode(probs + symbol, rd);
|
||||
#endif
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
while (symbol < 0x100);
|
||||
#ifdef _LZMA_LOC_OPT
|
||||
RC_FLUSH_VAR
|
||||
#endif
|
||||
return symbol;
|
||||
}
|
||||
|
||||
#define kNumPosBitsMax 4
|
||||
#define kNumPosStatesMax (1 << kNumPosBitsMax)
|
||||
|
||||
#define kLenNumLowBits 3
|
||||
#define kLenNumLowSymbols (1 << kLenNumLowBits)
|
||||
#define kLenNumMidBits 3
|
||||
#define kLenNumMidSymbols (1 << kLenNumMidBits)
|
||||
#define kLenNumHighBits 8
|
||||
#define kLenNumHighSymbols (1 << kLenNumHighBits)
|
||||
|
||||
#define LenChoice 0
|
||||
#define LenChoice2 (LenChoice + 1)
|
||||
#define LenLow (LenChoice2 + 1)
|
||||
#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))
|
||||
#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))
|
||||
#define kNumLenProbs (LenHigh + kLenNumHighSymbols)
|
||||
|
||||
int LzmaLenDecode(CProb *p, CRangeDecoder *rd, int posState)
|
||||
{
|
||||
if(RangeDecoderBitDecode(p + LenChoice, rd) == 0)
|
||||
return RangeDecoderBitTreeDecode(p + LenLow +
|
||||
(posState << kLenNumLowBits), kLenNumLowBits, rd);
|
||||
if(RangeDecoderBitDecode(p + LenChoice2, rd) == 0)
|
||||
return kLenNumLowSymbols + RangeDecoderBitTreeDecode(p + LenMid +
|
||||
(posState << kLenNumMidBits), kLenNumMidBits, rd);
|
||||
return kLenNumLowSymbols + kLenNumMidSymbols +
|
||||
RangeDecoderBitTreeDecode(p + LenHigh, kLenNumHighBits, rd);
|
||||
}
|
||||
|
||||
#define kNumStates 12
|
||||
|
||||
#define kStartPosModelIndex 4
|
||||
#define kEndPosModelIndex 14
|
||||
#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))
|
||||
|
||||
#define kNumPosSlotBits 6
|
||||
#define kNumLenToPosStates 4
|
||||
|
||||
#define kNumAlignBits 4
|
||||
#define kAlignTableSize (1 << kNumAlignBits)
|
||||
|
||||
#define kMatchMinLen 2
|
||||
|
||||
#define IsMatch 0
|
||||
#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))
|
||||
#define IsRepG0 (IsRep + kNumStates)
|
||||
#define IsRepG1 (IsRepG0 + kNumStates)
|
||||
#define IsRepG2 (IsRepG1 + kNumStates)
|
||||
#define IsRep0Long (IsRepG2 + kNumStates)
|
||||
#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))
|
||||
#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))
|
||||
#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)
|
||||
#define LenCoder (Align + kAlignTableSize)
|
||||
#define RepLenCoder (LenCoder + kNumLenProbs)
|
||||
#define Literal (RepLenCoder + kNumLenProbs)
|
||||
|
||||
#if Literal != LZMA_BASE_SIZE
|
||||
StopCompilingDueBUG
|
||||
#endif
|
||||
|
||||
#ifdef _LZMA_OUT_READ
|
||||
|
||||
typedef struct _LzmaVarState
|
||||
{
|
||||
CRangeDecoder RangeDecoder;
|
||||
Byte *Dictionary;
|
||||
UInt32 DictionarySize;
|
||||
UInt32 DictionaryPos;
|
||||
UInt32 GlobalPos;
|
||||
UInt32 Reps[4];
|
||||
int lc;
|
||||
int lp;
|
||||
int pb;
|
||||
int State;
|
||||
int PreviousIsMatch;
|
||||
int RemainLen;
|
||||
} LzmaVarState;
|
||||
|
||||
int LzmaDecoderInit(
|
||||
unsigned char *buffer, UInt32 bufferSize,
|
||||
int lc, int lp, int pb,
|
||||
unsigned char *dictionary, UInt32 dictionarySize,
|
||||
#ifdef _LZMA_IN_CB
|
||||
ILzmaInCallback *inCallback
|
||||
#else
|
||||
unsigned char *inStream, UInt32 inSize
|
||||
#endif
|
||||
)
|
||||
{
|
||||
LzmaVarState *vs = (LzmaVarState *)buffer;
|
||||
CProb *p = (CProb *)(buffer + sizeof(LzmaVarState));
|
||||
UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + lp));
|
||||
UInt32 i;
|
||||
if (bufferSize < numProbs * sizeof(CProb) + sizeof(LzmaVarState))
|
||||
return LZMA_RESULT_NOT_ENOUGH_MEM;
|
||||
vs->Dictionary = dictionary;
|
||||
vs->DictionarySize = dictionarySize;
|
||||
vs->DictionaryPos = 0;
|
||||
vs->GlobalPos = 0;
|
||||
vs->Reps[0] = vs->Reps[1] = vs->Reps[2] = vs->Reps[3] = 1;
|
||||
vs->lc = lc;
|
||||
vs->lp = lp;
|
||||
vs->pb = pb;
|
||||
vs->State = 0;
|
||||
vs->PreviousIsMatch = 0;
|
||||
vs->RemainLen = 0;
|
||||
dictionary[dictionarySize - 1] = 0;
|
||||
for (i = 0; i < numProbs; i++)
|
||||
p[i] = kBitModelTotal >> 1;
|
||||
RangeDecoderInit(&vs->RangeDecoder,
|
||||
#ifdef _LZMA_IN_CB
|
||||
inCallback
|
||||
#else
|
||||
inStream, inSize
|
||||
#endif
|
||||
);
|
||||
return LZMA_RESULT_OK;
|
||||
}
|
||||
|
||||
int LzmaDecode(unsigned char *buffer,
|
||||
unsigned char *outStream, UInt32 outSize,
|
||||
UInt32 *outSizeProcessed)
|
||||
{
|
||||
LzmaVarState *vs = (LzmaVarState *)buffer;
|
||||
CProb *p = (CProb *)(buffer + sizeof(LzmaVarState));
|
||||
CRangeDecoder rd = vs->RangeDecoder;
|
||||
int state = vs->State;
|
||||
int previousIsMatch = vs->PreviousIsMatch;
|
||||
Byte previousByte;
|
||||
UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3];
|
||||
UInt32 nowPos = 0;
|
||||
UInt32 posStateMask = (1 << (vs->pb)) - 1;
|
||||
UInt32 literalPosMask = (1 << (vs->lp)) - 1;
|
||||
int lc = vs->lc;
|
||||
int len = vs->RemainLen;
|
||||
UInt32 globalPos = vs->GlobalPos;
|
||||
|
||||
Byte *dictionary = vs->Dictionary;
|
||||
UInt32 dictionarySize = vs->DictionarySize;
|
||||
UInt32 dictionaryPos = vs->DictionaryPos;
|
||||
|
||||
if (len == -1)
|
||||
{
|
||||
*outSizeProcessed = 0;
|
||||
return LZMA_RESULT_OK;
|
||||
}
|
||||
|
||||
while(len > 0 && nowPos < outSize)
|
||||
{
|
||||
UInt32 pos = dictionaryPos - rep0;
|
||||
if (pos >= dictionarySize)
|
||||
pos += dictionarySize;
|
||||
outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos];
|
||||
if (++dictionaryPos == dictionarySize)
|
||||
dictionaryPos = 0;
|
||||
len--;
|
||||
}
|
||||
if (dictionaryPos == 0)
|
||||
previousByte = dictionary[dictionarySize - 1];
|
||||
else
|
||||
previousByte = dictionary[dictionaryPos - 1];
|
||||
#else
|
||||
|
||||
int LzmaDecode(
|
||||
Byte *buffer, UInt32 bufferSize,
|
||||
int lc, int lp, int pb,
|
||||
#ifdef _LZMA_IN_CB
|
||||
ILzmaInCallback *inCallback,
|
||||
#else
|
||||
unsigned char *inStream, UInt32 inSize,
|
||||
#endif
|
||||
unsigned char *outStream, UInt32 outSize,
|
||||
UInt32 *outSizeProcessed)
|
||||
{
|
||||
UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + lp));
|
||||
CProb *p = (CProb *)buffer;
|
||||
CRangeDecoder rd;
|
||||
UInt32 i;
|
||||
int state = 0;
|
||||
int previousIsMatch = 0;
|
||||
Byte previousByte = 0;
|
||||
UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;
|
||||
UInt32 nowPos = 0;
|
||||
UInt32 posStateMask = (1 << pb) - 1;
|
||||
UInt32 literalPosMask = (1 << lp) - 1;
|
||||
int len = 0;
|
||||
if (bufferSize < numProbs * sizeof(CProb))
|
||||
return LZMA_RESULT_NOT_ENOUGH_MEM;
|
||||
for (i = 0; i < numProbs; i++)
|
||||
p[i] = kBitModelTotal >> 1;
|
||||
RangeDecoderInit(&rd,
|
||||
#ifdef _LZMA_IN_CB
|
||||
inCallback
|
||||
#else
|
||||
inStream, inSize
|
||||
#endif
|
||||
);
|
||||
#endif
|
||||
|
||||
*outSizeProcessed = 0;
|
||||
while(nowPos < outSize)
|
||||
{
|
||||
int posState = (int)(
|
||||
(nowPos
|
||||
#ifdef _LZMA_OUT_READ
|
||||
+ globalPos
|
||||
#endif
|
||||
)
|
||||
& posStateMask);
|
||||
#ifdef _LZMA_IN_CB
|
||||
if (rd.Result != LZMA_RESULT_OK)
|
||||
return rd.Result;
|
||||
#endif
|
||||
if (rd.ExtraBytes != 0)
|
||||
return LZMA_RESULT_DATA_ERROR;
|
||||
if (RangeDecoderBitDecode(p + IsMatch + (state << kNumPosBitsMax) + posState, &rd) == 0)
|
||||
{
|
||||
CProb *probs = p + Literal + (LZMA_LIT_SIZE *
|
||||
(((
|
||||
(nowPos
|
||||
#ifdef _LZMA_OUT_READ
|
||||
+ globalPos
|
||||
#endif
|
||||
)
|
||||
& literalPosMask) << lc) + (previousByte >> (8 - lc))));
|
||||
|
||||
if (state < 4) state = 0;
|
||||
else if (state < 10) state -= 3;
|
||||
else state -= 6;
|
||||
if (previousIsMatch)
|
||||
{
|
||||
Byte matchByte;
|
||||
#ifdef _LZMA_OUT_READ
|
||||
UInt32 pos = dictionaryPos - rep0;
|
||||
if (pos >= dictionarySize)
|
||||
pos += dictionarySize;
|
||||
matchByte = dictionary[pos];
|
||||
#else
|
||||
matchByte = outStream[nowPos - rep0];
|
||||
#endif
|
||||
previousByte = LzmaLiteralDecodeMatch(probs, &rd, matchByte);
|
||||
previousIsMatch = 0;
|
||||
}
|
||||
else
|
||||
previousByte = LzmaLiteralDecode(probs, &rd);
|
||||
outStream[nowPos++] = previousByte;
|
||||
#ifdef _LZMA_OUT_READ
|
||||
dictionary[dictionaryPos] = previousByte;
|
||||
if (++dictionaryPos == dictionarySize)
|
||||
dictionaryPos = 0;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
previousIsMatch = 1;
|
||||
if (RangeDecoderBitDecode(p + IsRep + state, &rd) == 1)
|
||||
{
|
||||
if (RangeDecoderBitDecode(p + IsRepG0 + state, &rd) == 0)
|
||||
{
|
||||
if (RangeDecoderBitDecode(p + IsRep0Long + (state << kNumPosBitsMax) + posState, &rd) == 0)
|
||||
{
|
||||
#ifdef _LZMA_OUT_READ
|
||||
UInt32 pos;
|
||||
#endif
|
||||
if (
|
||||
(nowPos
|
||||
#ifdef _LZMA_OUT_READ
|
||||
+ globalPos
|
||||
#endif
|
||||
)
|
||||
== 0)
|
||||
return LZMA_RESULT_DATA_ERROR;
|
||||
state = state < 7 ? 9 : 11;
|
||||
#ifdef _LZMA_OUT_READ
|
||||
pos = dictionaryPos - rep0;
|
||||
if (pos >= dictionarySize)
|
||||
pos += dictionarySize;
|
||||
previousByte = dictionary[pos];
|
||||
dictionary[dictionaryPos] = previousByte;
|
||||
if (++dictionaryPos == dictionarySize)
|
||||
dictionaryPos = 0;
|
||||
#else
|
||||
previousByte = outStream[nowPos - rep0];
|
||||
#endif
|
||||
outStream[nowPos++] = previousByte;
|
||||
continue;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
UInt32 distance;
|
||||
if(RangeDecoderBitDecode(p + IsRepG1 + state, &rd) == 0)
|
||||
distance = rep1;
|
||||
else
|
||||
{
|
||||
if(RangeDecoderBitDecode(p + IsRepG2 + state, &rd) == 0)
|
||||
distance = rep2;
|
||||
else
|
||||
{
|
||||
distance = rep3;
|
||||
rep3 = rep2;
|
||||
}
|
||||
rep2 = rep1;
|
||||
}
|
||||
rep1 = rep0;
|
||||
rep0 = distance;
|
||||
}
|
||||
len = LzmaLenDecode(p + RepLenCoder, &rd, posState);
|
||||
state = state < 7 ? 8 : 11;
|
||||
}
|
||||
else
|
||||
{
|
||||
int posSlot;
|
||||
rep3 = rep2;
|
||||
rep2 = rep1;
|
||||
rep1 = rep0;
|
||||
state = state < 7 ? 7 : 10;
|
||||
len = LzmaLenDecode(p + LenCoder, &rd, posState);
|
||||
posSlot = RangeDecoderBitTreeDecode(p + PosSlot +
|
||||
((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) <<
|
||||
kNumPosSlotBits), kNumPosSlotBits, &rd);
|
||||
if (posSlot >= kStartPosModelIndex)
|
||||
{
|
||||
int numDirectBits = ((posSlot >> 1) - 1);
|
||||
rep0 = ((2 | ((UInt32)posSlot & 1)) << numDirectBits);
|
||||
if (posSlot < kEndPosModelIndex)
|
||||
{
|
||||
rep0 += RangeDecoderReverseBitTreeDecode(
|
||||
p + SpecPos + rep0 - posSlot - 1, numDirectBits, &rd);
|
||||
}
|
||||
else
|
||||
{
|
||||
rep0 += RangeDecoderDecodeDirectBits(&rd,
|
||||
numDirectBits - kNumAlignBits) << kNumAlignBits;
|
||||
rep0 += RangeDecoderReverseBitTreeDecode(p + Align, kNumAlignBits, &rd);
|
||||
}
|
||||
}
|
||||
else
|
||||
rep0 = posSlot;
|
||||
rep0++;
|
||||
}
|
||||
if (rep0 == (UInt32)(0))
|
||||
{
|
||||
/* it's for stream version */
|
||||
len = -1;
|
||||
break;
|
||||
}
|
||||
if (rep0 > nowPos
|
||||
#ifdef _LZMA_OUT_READ
|
||||
+ globalPos
|
||||
#endif
|
||||
)
|
||||
{
|
||||
return LZMA_RESULT_DATA_ERROR;
|
||||
}
|
||||
len += kMatchMinLen;
|
||||
do
|
||||
{
|
||||
#ifdef _LZMA_OUT_READ
|
||||
UInt32 pos = dictionaryPos - rep0;
|
||||
if (pos >= dictionarySize)
|
||||
pos += dictionarySize;
|
||||
previousByte = dictionary[pos];
|
||||
dictionary[dictionaryPos] = previousByte;
|
||||
if (++dictionaryPos == dictionarySize)
|
||||
dictionaryPos = 0;
|
||||
#else
|
||||
previousByte = outStream[nowPos - rep0];
|
||||
#endif
|
||||
outStream[nowPos++] = previousByte;
|
||||
len--;
|
||||
}
|
||||
while(len > 0 && nowPos < outSize);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef _LZMA_OUT_READ
|
||||
vs->RangeDecoder = rd;
|
||||
vs->DictionaryPos = dictionaryPos;
|
||||
vs->GlobalPos = globalPos + nowPos;
|
||||
vs->Reps[0] = rep0;
|
||||
vs->Reps[1] = rep1;
|
||||
vs->Reps[2] = rep2;
|
||||
vs->Reps[3] = rep3;
|
||||
vs->State = state;
|
||||
vs->PreviousIsMatch = previousIsMatch;
|
||||
vs->RemainLen = len;
|
||||
#endif
|
||||
|
||||
*outSizeProcessed = nowPos;
|
||||
return LZMA_RESULT_OK;
|
||||
}
|
||||
|
|
@ -1,100 +0,0 @@
|
|||
/*
|
||||
LzmaDecode.h
|
||||
LZMA Decoder interface
|
||||
|
||||
LZMA SDK 4.05 Copyright (c) 1999-2004 Igor Pavlov (2004-08-25)
|
||||
http://www.7-zip.org/
|
||||
|
||||
LZMA SDK is licensed under two licenses:
|
||||
1) GNU Lesser General Public License (GNU LGPL)
|
||||
2) Common Public License (CPL)
|
||||
It means that you can select one of these two licenses and
|
||||
follow rules of that license.
|
||||
|
||||
SPECIAL EXCEPTION:
|
||||
Igor Pavlov, as the author of this code, expressly permits you to
|
||||
statically or dynamically link your code (or bind by name) to the
|
||||
interfaces of this file without subjecting your linked code to the
|
||||
terms of the CPL or GNU LGPL. Any modifications or additions
|
||||
to this file, however, are subject to the LGPL or CPL terms.
|
||||
*/
|
||||
|
||||
#ifndef __LZMADECODE_H
|
||||
#define __LZMADECODE_H
|
||||
|
||||
/* #define _LZMA_IN_CB */
|
||||
/* Use callback for input data */
|
||||
|
||||
/* #define _LZMA_OUT_READ */
|
||||
/* Use read function for output data */
|
||||
|
||||
/* #define _LZMA_PROB32 */
|
||||
/* It can increase speed on some 32-bit CPUs,
|
||||
but memory usage will be doubled in that case */
|
||||
|
||||
/* #define _LZMA_LOC_OPT */
|
||||
/* Enable local speed optimizations inside code */
|
||||
|
||||
#ifndef UInt32
|
||||
#ifdef _LZMA_UINT32_IS_ULONG
|
||||
#define UInt32 unsigned long
|
||||
#else
|
||||
#define UInt32 unsigned int
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef _LZMA_PROB32
|
||||
#define CProb UInt32
|
||||
#else
|
||||
#define CProb unsigned short
|
||||
#endif
|
||||
|
||||
#define LZMA_RESULT_OK 0
|
||||
#define LZMA_RESULT_DATA_ERROR 1
|
||||
#define LZMA_RESULT_NOT_ENOUGH_MEM 2
|
||||
|
||||
#ifdef _LZMA_IN_CB
|
||||
typedef struct _ILzmaInCallback
|
||||
{
|
||||
int (*Read)(void *object, unsigned char **buffer, UInt32 *bufferSize);
|
||||
} ILzmaInCallback;
|
||||
#endif
|
||||
|
||||
#define LZMA_BASE_SIZE 1846
|
||||
#define LZMA_LIT_SIZE 768
|
||||
|
||||
/*
|
||||
bufferSize = (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << (lc + lp)))* sizeof(CProb)
|
||||
bufferSize += 100 in case of _LZMA_OUT_READ
|
||||
by default CProb is unsigned short,
|
||||
but if specify _LZMA_PROB_32, CProb will be UInt32(unsigned int)
|
||||
*/
|
||||
|
||||
#ifdef _LZMA_OUT_READ
|
||||
int LzmaDecoderInit(
|
||||
unsigned char *buffer, UInt32 bufferSize,
|
||||
int lc, int lp, int pb,
|
||||
unsigned char *dictionary, UInt32 dictionarySize,
|
||||
#ifdef _LZMA_IN_CB
|
||||
ILzmaInCallback *inCallback
|
||||
#else
|
||||
unsigned char *inStream, UInt32 inSize
|
||||
#endif
|
||||
);
|
||||
#endif
|
||||
|
||||
int LzmaDecode(
|
||||
unsigned char *buffer,
|
||||
#ifndef _LZMA_OUT_READ
|
||||
UInt32 bufferSize,
|
||||
int lc, int lp, int pb,
|
||||
#ifdef _LZMA_IN_CB
|
||||
ILzmaInCallback *inCallback,
|
||||
#else
|
||||
unsigned char *inStream, UInt32 inSize,
|
||||
#endif
|
||||
#endif
|
||||
unsigned char *outStream, UInt32 outSize,
|
||||
UInt32 *outSizeProcessed);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,77 +0,0 @@
|
|||
#
|
||||
# Makefile for Broadcom BCM947XX boards
|
||||
#
|
||||
# Copyright 2001-2003, Broadcom Corporation
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
||||
# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
||||
# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
||||
#
|
||||
# Copyright 2004 Manuel Novoa III <mjn3@codepoet.org>
|
||||
# Modified to support bzip'd kernels.
|
||||
# Of course, it would be better to integrate bunzip capability into CFE.
|
||||
#
|
||||
# Copyright 2005 Oleg I. Vdovikin <oleg@cs.msu.su>
|
||||
# Cleaned up, modified for lzma support, removed from kernel
|
||||
#
|
||||
|
||||
TEXT_START := 0x80001000
|
||||
BZ_TEXT_START := 0x80400000
|
||||
|
||||
OBJCOPY := $(CROSS_COMPILE)objcopy -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
|
||||
|
||||
CFLAGS = -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
|
||||
-fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 -mno-abicalls -fno-pic \
|
||||
-ffunction-sections -pipe -mlong-calls -fno-common \
|
||||
-mabi=32 -march=mips32 -Wa,-32 -Wa,-march=mips32 -Wa,-mips32 -Wa,--trap
|
||||
CFLAGS += -DLOADADDR=$(TEXT_START) -D_LZMA_IN_CB
|
||||
|
||||
ASFLAGS = $(CFLAGS) -D__ASSEMBLY__ -DBZ_TEXT_START=$(BZ_TEXT_START)
|
||||
|
||||
SEDFLAGS := s/BZ_TEXT_START/$(BZ_TEXT_START)/;s/TEXT_START/$(TEXT_START)/
|
||||
|
||||
OBJECTS := head.o data.o
|
||||
|
||||
all: loader.gz loader.elf
|
||||
|
||||
# Don't build dependencies, this may die if $(CC) isn't gcc
|
||||
dep:
|
||||
|
||||
install:
|
||||
|
||||
loader.gz: loader
|
||||
gzip -nc9 $< > $@
|
||||
|
||||
loader.elf: loader.o
|
||||
cp $< $@
|
||||
|
||||
loader: loader.o
|
||||
$(OBJCOPY) $< $@
|
||||
|
||||
loader.o: loader.lds $(OBJECTS)
|
||||
$(LD) -static --gc-sections -no-warn-mismatch -T loader.lds -o $@ $(OBJECTS)
|
||||
|
||||
loader.lds: loader.lds.in Makefile
|
||||
@sed "$(SEDFLAGS)" < $< > $@
|
||||
|
||||
data.o: data.lds decompress.image
|
||||
$(LD) -no-warn-mismatch -T data.lds -r -o $@ -b binary decompress.image -b elf32-tradlittlemips
|
||||
|
||||
data.lds:
|
||||
@echo "SECTIONS { .data : { code_start = .; *(.data) code_stop = .; }}" > $@
|
||||
|
||||
decompress.image: decompress
|
||||
$(OBJCOPY) $< $@
|
||||
|
||||
decompress: decompress.lds decompress.o LzmaDecode.o
|
||||
$(LD) -static --gc-sections -no-warn-mismatch -T decompress.lds -o $@ decompress.o LzmaDecode.o
|
||||
|
||||
decompress.lds: decompress.lds.in Makefile
|
||||
@sed "$(SEDFLAGS)" < $< > $@
|
||||
|
||||
mrproper: clean
|
||||
|
||||
clean:
|
||||
rm -f loader.gz loader decompress *.lds *.o *.image
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
/*
|
||||
* LZMA compressed kernel decompressor for bcm947xx boards
|
||||
*
|
||||
* Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
The code is intended to decompress kernel, being compressed using lzma utility
|
||||
build using 7zip LZMA SDK. This utility is located in the LZMA_Alone directory
|
||||
|
||||
decompressor code expects that your .trx file consist of three partitions:
|
||||
|
||||
1) decompressor itself (this is gziped code which pmon/cfe will extract and run
|
||||
on boot-up instead of real kernel)
|
||||
2) LZMA compressed kernel (both streamed and regular modes are supported now)
|
||||
3) Root filesystem
|
||||
|
||||
Please be sure to apply the following patch for use this new trx layout (it will
|
||||
allow using both new and old trx files for root filesystem lookup code)
|
||||
|
||||
--- linuz/arch/mips/brcm-boards/bcm947xx/setup.c 2005-01-23 19:24:27.503322896 +0300
|
||||
+++ linux/arch/mips/brcm-boards/bcm947xx/setup.c 2005-01-23 19:29:05.237100944 +0300
|
||||
@@ -221,7 +221,9 @@
|
||||
/* Try looking at TRX header for rootfs offset */
|
||||
if (le32_to_cpu(trx->magic) == TRX_MAGIC) {
|
||||
bcm947xx_parts[1].offset = off;
|
||||
- if (le32_to_cpu(trx->offsets[1]) > off)
|
||||
+ if (le32_to_cpu(trx->offsets[2]) > off)
|
||||
+ off = le32_to_cpu(trx->offsets[2]);
|
||||
+ else if (le32_to_cpu(trx->offsets[1]) > off)
|
||||
off = le32_to_cpu(trx->offsets[1]);
|
||||
continue;
|
||||
}
|
||||
|
||||
|
||||
Revision history:
|
||||
0.02 Initial release
|
||||
0.03 Added Mineharu Takahara <mtakahar@yahoo.com> patch to pass actual
|
||||
output size to decoder (stream mode compressed input is not
|
||||
a requirement anymore)
|
||||
0.04 Reordered functions using lds script
|
||||
|
|
@ -1,179 +0,0 @@
|
|||
/*
|
||||
* LZMA compressed kernel decompressor for bcm947xx boards
|
||||
*
|
||||
* Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*
|
||||
* Please note, this was code based on the bunzip2 decompressor code
|
||||
* by Manuel Novoa III (mjn3@codepoet.org), although the only thing left
|
||||
* is an idea and part of original vendor code
|
||||
*
|
||||
*
|
||||
* 12-Mar-2005 Mineharu Takahara <mtakahar@yahoo.com>
|
||||
* pass actual output size to decoder (stream mode
|
||||
* compressed input is not a requirement anymore)
|
||||
*
|
||||
* 24-Apr-2005 Oleg I. Vdovikin
|
||||
* reordered functions using lds script, removed forward decl
|
||||
*
|
||||
*/
|
||||
|
||||
#include "LzmaDecode.h"
|
||||
|
||||
#define BCM4710_FLASH 0x1fc00000 /* Flash */
|
||||
|
||||
#define KSEG0 0x80000000
|
||||
#define KSEG1 0xa0000000
|
||||
|
||||
#define KSEG1ADDR(a) ((((unsigned)(a)) & 0x1fffffffU) | KSEG1)
|
||||
|
||||
#define Index_Invalidate_I 0x00
|
||||
#define Index_Writeback_Inv_D 0x01
|
||||
|
||||
#define cache_unroll(base,op) \
|
||||
__asm__ __volatile__( \
|
||||
".set noreorder;\n" \
|
||||
".set mips3;\n" \
|
||||
"cache %1, (%0);\n" \
|
||||
".set mips0;\n" \
|
||||
".set reorder\n" \
|
||||
: \
|
||||
: "r" (base), \
|
||||
"i" (op));
|
||||
|
||||
static __inline__ void blast_icache(unsigned long size, unsigned long lsize)
|
||||
{
|
||||
unsigned long start = KSEG0;
|
||||
unsigned long end = (start + size);
|
||||
|
||||
while(start < end) {
|
||||
cache_unroll(start,Index_Invalidate_I);
|
||||
start += lsize;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ void blast_dcache(unsigned long size, unsigned long lsize)
|
||||
{
|
||||
unsigned long start = KSEG0;
|
||||
unsigned long end = (start + size);
|
||||
|
||||
while(start < end) {
|
||||
cache_unroll(start,Index_Writeback_Inv_D);
|
||||
start += lsize;
|
||||
}
|
||||
}
|
||||
|
||||
#define TRX_MAGIC 0x30524448 /* "HDR0" */
|
||||
|
||||
struct trx_header {
|
||||
unsigned int magic; /* "HDR0" */
|
||||
unsigned int len; /* Length of file including header */
|
||||
unsigned int crc32; /* 32-bit CRC from flag_version to end of file */
|
||||
unsigned int flag_version; /* 0:15 flags, 16:31 version */
|
||||
unsigned int offsets[3]; /* Offsets of partitions from start of header */
|
||||
};
|
||||
|
||||
/* beyound the image end, size not known in advance */
|
||||
extern unsigned char workspace[];
|
||||
|
||||
unsigned int offset;
|
||||
unsigned char *data;
|
||||
|
||||
/* flash access should be aligned, so wrapper is used */
|
||||
/* read byte from the flash, all accesses are 32-bit aligned */
|
||||
static int read_byte(void *object, unsigned char **buffer, UInt32 *bufferSize)
|
||||
{
|
||||
static unsigned int val;
|
||||
|
||||
if (((unsigned int)offset % 4) == 0) {
|
||||
val = *(unsigned int *)data;
|
||||
data += 4;
|
||||
}
|
||||
|
||||
*bufferSize = 1;
|
||||
*buffer = ((unsigned char *)&val) + (offset++ & 3);
|
||||
|
||||
return LZMA_RESULT_OK;
|
||||
}
|
||||
|
||||
static __inline__ unsigned char get_byte(void)
|
||||
{
|
||||
unsigned char *buffer;
|
||||
UInt32 fake;
|
||||
|
||||
return read_byte(0, &buffer, &fake), *buffer;
|
||||
}
|
||||
|
||||
/* should be the first function */
|
||||
void entry(unsigned long icache_size, unsigned long icache_lsize,
|
||||
unsigned long dcache_size, unsigned long dcache_lsize,
|
||||
unsigned long fw_arg0, unsigned long fw_arg1,
|
||||
unsigned long fw_arg2, unsigned long fw_arg3)
|
||||
{
|
||||
unsigned int i; /* temp value */
|
||||
unsigned int lc; /* literal context bits */
|
||||
unsigned int lp; /* literal pos state bits */
|
||||
unsigned int pb; /* pos state bits */
|
||||
unsigned int osize; /* uncompressed size */
|
||||
|
||||
ILzmaInCallback callback;
|
||||
callback.Read = read_byte;
|
||||
|
||||
/* look for trx header, 32-bit data access */
|
||||
for (data = ((unsigned char *) KSEG1ADDR(BCM4710_FLASH));
|
||||
((struct trx_header *)data)->magic != TRX_MAGIC; data += 65536);
|
||||
|
||||
/* compressed kernel is in the partition 0 or 1 */
|
||||
if (((struct trx_header *)data)->offsets[1] > 65536)
|
||||
data += ((struct trx_header *)data)->offsets[0];
|
||||
else
|
||||
data += ((struct trx_header *)data)->offsets[1];
|
||||
|
||||
offset = 0;
|
||||
|
||||
/* lzma args */
|
||||
i = get_byte();
|
||||
lc = i % 9, i = i / 9;
|
||||
lp = i % 5, pb = i / 5;
|
||||
|
||||
/* skip rest of the LZMA coder property */
|
||||
for (i = 0; i < 4; i++)
|
||||
get_byte();
|
||||
|
||||
/* read the lower half of uncompressed size in the header */
|
||||
osize = ((unsigned int)get_byte()) +
|
||||
((unsigned int)get_byte() << 8) +
|
||||
((unsigned int)get_byte() << 16) +
|
||||
((unsigned int)get_byte() << 24);
|
||||
|
||||
/* skip rest of the header (upper half of uncompressed size) */
|
||||
for (i = 0; i < 4; i++)
|
||||
get_byte();
|
||||
|
||||
/* decompress kernel */
|
||||
if (LzmaDecode(workspace, ~0, lc, lp, pb, &callback,
|
||||
(unsigned char*)LOADADDR, osize, &i) == LZMA_RESULT_OK)
|
||||
{
|
||||
blast_dcache(dcache_size, dcache_lsize);
|
||||
blast_icache(icache_size, icache_lsize);
|
||||
|
||||
/* Jump to load address */
|
||||
((void (*)(unsigned long, unsigned long, unsigned long,
|
||||
unsigned long)) LOADADDR)(fw_arg0, fw_arg1, fw_arg2,
|
||||
fw_arg3);
|
||||
}
|
||||
}
|
||||
|
|
@ -1,20 +0,0 @@
|
|||
OUTPUT_ARCH(mips)
|
||||
ENTRY(entry)
|
||||
SECTIONS {
|
||||
. = BZ_TEXT_START;
|
||||
.text : {
|
||||
*(.text.entry)
|
||||
*(.text)
|
||||
*(.rodata)
|
||||
}
|
||||
|
||||
.data : {
|
||||
*(.data)
|
||||
}
|
||||
|
||||
.bss : {
|
||||
*(.bss)
|
||||
}
|
||||
|
||||
workspace = .;
|
||||
}
|
||||
|
|
@ -1,160 +0,0 @@
|
|||
/* Copyright 2005 Oleg I. Vdovikin (oleg@cs.msu.su) */
|
||||
/* cache manipulation adapted from Broadcom code */
|
||||
/* idea taken from original bunzip2 decompressor code */
|
||||
/* Copyright 2004 Manuel Novoa III (mjn3@codepoet.org) */
|
||||
/* Licensed under the linux kernel's version of the GPL.*/
|
||||
|
||||
#include <asm/asm.h>
|
||||
#include <asm/regdef.h>
|
||||
|
||||
#define KSEG0 0x80000000
|
||||
|
||||
#define C0_CONFIG $16
|
||||
#define C0_TAGLO $28
|
||||
#define C0_TAGHI $29
|
||||
|
||||
#define CONF1_DA_SHIFT 7 /* D$ associativity */
|
||||
#define CONF1_DA_MASK 0x00000380
|
||||
#define CONF1_DA_BASE 1
|
||||
#define CONF1_DL_SHIFT 10 /* D$ line size */
|
||||
#define CONF1_DL_MASK 0x00001c00
|
||||
#define CONF1_DL_BASE 2
|
||||
#define CONF1_DS_SHIFT 13 /* D$ sets/way */
|
||||
#define CONF1_DS_MASK 0x0000e000
|
||||
#define CONF1_DS_BASE 64
|
||||
#define CONF1_IA_SHIFT 16 /* I$ associativity */
|
||||
#define CONF1_IA_MASK 0x00070000
|
||||
#define CONF1_IA_BASE 1
|
||||
#define CONF1_IL_SHIFT 19 /* I$ line size */
|
||||
#define CONF1_IL_MASK 0x00380000
|
||||
#define CONF1_IL_BASE 2
|
||||
#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
|
||||
#define CONF1_IS_MASK 0x01c00000
|
||||
#define CONF1_IS_BASE 64
|
||||
|
||||
#define Index_Invalidate_I 0x00
|
||||
#define Index_Writeback_Inv_D 0x01
|
||||
|
||||
.text
|
||||
LEAF(startup)
|
||||
.set noreorder
|
||||
addi sp, -48
|
||||
sw a0, 16(sp)
|
||||
sw a1, 20(sp)
|
||||
sw a2, 24(sp)
|
||||
sw a3, 28(sp)
|
||||
|
||||
/* Copy decompressor code to the right place */
|
||||
li t2, BZ_TEXT_START
|
||||
add a0, t2, 0
|
||||
la a1, code_start
|
||||
la a2, code_stop
|
||||
$L1:
|
||||
lw t0, 0(a1)
|
||||
sw t0, 0(a0)
|
||||
add a1, 4
|
||||
add a0, 4
|
||||
blt a1, a2, $L1
|
||||
nop
|
||||
|
||||
/* At this point we need to invalidate dcache and */
|
||||
/* icache before jumping to new code */
|
||||
|
||||
1: /* Get cache sizes */
|
||||
.set mips32
|
||||
mfc0 s0,C0_CONFIG,1
|
||||
.set mips0
|
||||
|
||||
li s1,CONF1_DL_MASK
|
||||
and s1,s0
|
||||
beq s1,zero,nodc
|
||||
nop
|
||||
|
||||
srl s1,CONF1_DL_SHIFT
|
||||
li t0,CONF1_DL_BASE
|
||||
sll s1,t0,s1 /* s1 has D$ cache line size */
|
||||
|
||||
li s2,CONF1_DA_MASK
|
||||
and s2,s0
|
||||
srl s2,CONF1_DA_SHIFT
|
||||
addiu s2,CONF1_DA_BASE /* s2 now has D$ associativity */
|
||||
|
||||
li t0,CONF1_DS_MASK
|
||||
and t0,s0
|
||||
srl t0,CONF1_DS_SHIFT
|
||||
li s3,CONF1_DS_BASE
|
||||
sll s3,s3,t0 /* s3 has D$ sets per way */
|
||||
|
||||
multu s2,s3 /* sets/way * associativity */
|
||||
mflo t0 /* total cache lines */
|
||||
|
||||
multu s1,t0 /* D$ linesize * lines */
|
||||
mflo s2 /* s2 is now D$ size in bytes */
|
||||
|
||||
/* Initilize the D$: */
|
||||
mtc0 zero,C0_TAGLO
|
||||
mtc0 zero,C0_TAGHI
|
||||
|
||||
li t0,KSEG0 /* Just an address for the first $ line */
|
||||
addu t1,t0,s2 /* + size of cache == end */
|
||||
|
||||
.set mips3
|
||||
1: cache Index_Writeback_Inv_D,0(t0)
|
||||
.set mips0
|
||||
bne t0,t1,1b
|
||||
addu t0,s1
|
||||
|
||||
nodc:
|
||||
/* Now we get to do it all again for the I$ */
|
||||
|
||||
move s3,zero /* just in case there is no icache */
|
||||
move s4,zero
|
||||
|
||||
li t0,CONF1_IL_MASK
|
||||
and t0,s0
|
||||
beq t0,zero,noic
|
||||
nop
|
||||
|
||||
srl t0,CONF1_IL_SHIFT
|
||||
li s3,CONF1_IL_BASE
|
||||
sll s3,t0 /* s3 has I$ cache line size */
|
||||
|
||||
li t0,CONF1_IA_MASK
|
||||
and t0,s0
|
||||
srl t0,CONF1_IA_SHIFT
|
||||
addiu s4,t0,CONF1_IA_BASE /* s4 now has I$ associativity */
|
||||
|
||||
li t0,CONF1_IS_MASK
|
||||
and t0,s0
|
||||
srl t0,CONF1_IS_SHIFT
|
||||
li s5,CONF1_IS_BASE
|
||||
sll s5,t0 /* s5 has I$ sets per way */
|
||||
|
||||
multu s4,s5 /* sets/way * associativity */
|
||||
mflo t0 /* s4 is now total cache lines */
|
||||
|
||||
multu s3,t0 /* I$ linesize * lines */
|
||||
mflo s4 /* s4 is cache size in bytes */
|
||||
|
||||
/* Initilize the I$: */
|
||||
mtc0 zero,C0_TAGLO
|
||||
mtc0 zero,C0_TAGHI
|
||||
|
||||
li t0,KSEG0 /* Just an address for the first $ line */
|
||||
addu t1,t0,s4 /* + size of cache == end */
|
||||
|
||||
.set mips3
|
||||
1: cache Index_Invalidate_I,0(t0)
|
||||
.set mips0
|
||||
bne t0,t1,1b
|
||||
addu t0,s3
|
||||
|
||||
noic:
|
||||
move a0,s3 /* icache line size */
|
||||
move a1,s4 /* icache size */
|
||||
move a2,s1 /* dcache line size */
|
||||
jal t2
|
||||
move a3,s2 /* dcache size */
|
||||
|
||||
.set reorder
|
||||
END(startup)
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
OUTPUT_ARCH(mips)
|
||||
ENTRY(startup)
|
||||
SECTIONS {
|
||||
. = TEXT_START;
|
||||
.text : {
|
||||
*(.text)
|
||||
*(.rodata)
|
||||
}
|
||||
|
||||
.data : {
|
||||
*(.data)
|
||||
}
|
||||
|
||||
.bss : {
|
||||
*(.bss)
|
||||
}
|
||||
}
|
||||
|
|
@ -1,596 +0,0 @@
|
|||
--- a/arch/mips/config-shared.in
|
||||
+++ b/arch/mips/config-shared.in
|
||||
@@ -208,6 +208,14 @@ if [ "$CONFIG_SIBYTE_SB1xxx_SOC" = "y" ]
|
||||
fi
|
||||
define_bool CONFIG_MIPS_RTC y
|
||||
fi
|
||||
+dep_bool 'Support for Broadcom MIPS-based boards' CONFIG_MIPS_BRCM $CONFIG_EXPERIMENTAL
|
||||
+dep_bool 'Support for Broadcom BCM947XX' CONFIG_BCM947XX $CONFIG_MIPS_BRCM
|
||||
+if [ "$CONFIG_BCM947XX" = "y" ] ; then
|
||||
+ bool ' Support for Broadcom BCM4710' CONFIG_BCM4710
|
||||
+ bool ' Support for Broadcom BCM4310' CONFIG_BCM4310
|
||||
+ bool ' Support for Broadcom BCM4704' CONFIG_BCM4704
|
||||
+ bool ' Support for Broadcom BCM5365' CONFIG_BCM5365
|
||||
+fi
|
||||
bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
|
||||
bool 'Support for TANBAC TB0226 (Mbase)' CONFIG_TANBAC_TB0226
|
||||
bool 'Support for TANBAC TB0229 (VR4131DIMM)' CONFIG_TANBAC_TB0229
|
||||
@@ -229,6 +237,11 @@ define_bool CONFIG_RWSEM_GENERIC_SPINLOC
|
||||
define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
|
||||
|
||||
#
|
||||
+# Provide an option for a default kernel command line
|
||||
+#
|
||||
+string 'Default kernel command string' CONFIG_CMDLINE ""
|
||||
+
|
||||
+#
|
||||
# Select some configuration options automatically based on user selections.
|
||||
#
|
||||
if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
|
||||
@@ -554,6 +567,12 @@ if [ "$CONFIG_SIBYTE_SB1xxx_SOC" = "y" ]
|
||||
define_bool CONFIG_SWAP_IO_SPACE_L y
|
||||
define_bool CONFIG_BOOT_ELF32 y
|
||||
fi
|
||||
+if [ "$CONFIG_BCM947XX" = "y" ] ; then
|
||||
+ define_bool CONFIG_PCI y
|
||||
+ define_bool CONFIG_NONCOHERENT_IO y
|
||||
+ define_bool CONFIG_NEW_TIME_C y
|
||||
+ define_bool CONFIG_NEW_IRQ y
|
||||
+fi
|
||||
if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
|
||||
define_bool CONFIG_ARC32 y
|
||||
define_bool CONFIG_ARC_MEMORY y
|
||||
@@ -1042,7 +1061,11 @@ comment 'Kernel hacking'
|
||||
|
||||
bool 'Are you using a crosscompiler' CONFIG_CROSSCOMPILE
|
||||
bool 'Enable run-time debugging' CONFIG_RUNTIME_DEBUG
|
||||
-bool 'Remote GDB kernel debugging' CONFIG_KGDB
|
||||
+if [ "$CONFIG_BCM947XX" = "y" ] ; then
|
||||
+ bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
|
||||
+else
|
||||
+ bool 'Remote GDB kernel debugging' CONFIG_KGDB
|
||||
+fi
|
||||
dep_bool ' Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_KGDB
|
||||
if [ "$CONFIG_KGDB" = "y" ]; then
|
||||
define_bool CONFIG_DEBUG_INFO y
|
||||
--- a/arch/mips/kernel/cpu-probe.c
|
||||
+++ b/arch/mips/kernel/cpu-probe.c
|
||||
@@ -162,7 +162,7 @@ static inline int __cpu_has_fpu(void)
|
||||
|
||||
static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
|
||||
{
|
||||
- switch (c->processor_id & 0xff00) {
|
||||
+ switch (c->processor_id & PRID_IMP_MASK) {
|
||||
case PRID_IMP_R2000:
|
||||
c->cputype = CPU_R2000;
|
||||
c->isa_level = MIPS_CPU_ISA_I;
|
||||
@@ -172,7 +172,7 @@ static inline void cpu_probe_legacy(stru
|
||||
c->tlbsize = 64;
|
||||
break;
|
||||
case PRID_IMP_R3000:
|
||||
- if ((c->processor_id & 0xff) == PRID_REV_R3000A)
|
||||
+ if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A)
|
||||
if (cpu_has_confreg())
|
||||
c->cputype = CPU_R3081E;
|
||||
else
|
||||
@@ -187,12 +187,12 @@ static inline void cpu_probe_legacy(stru
|
||||
break;
|
||||
case PRID_IMP_R4000:
|
||||
if (read_c0_config() & CONF_SC) {
|
||||
- if ((c->processor_id & 0xff) >= PRID_REV_R4400)
|
||||
+ if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
|
||||
c->cputype = CPU_R4400PC;
|
||||
else
|
||||
c->cputype = CPU_R4000PC;
|
||||
} else {
|
||||
- if ((c->processor_id & 0xff) >= PRID_REV_R4400)
|
||||
+ if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
|
||||
c->cputype = CPU_R4400SC;
|
||||
else
|
||||
c->cputype = CPU_R4000SC;
|
||||
@@ -438,7 +438,7 @@ static inline void decode_config1(struct
|
||||
static inline void cpu_probe_mips(struct cpuinfo_mips *c)
|
||||
{
|
||||
decode_config1(c);
|
||||
- switch (c->processor_id & 0xff00) {
|
||||
+ switch (c->processor_id & PRID_IMP_MASK) {
|
||||
case PRID_IMP_4KC:
|
||||
c->cputype = CPU_4KC;
|
||||
c->isa_level = MIPS_CPU_ISA_M32;
|
||||
@@ -479,10 +479,10 @@ static inline void cpu_probe_alchemy(str
|
||||
{
|
||||
decode_config1(c);
|
||||
c->options |= MIPS_CPU_PREFETCH;
|
||||
- switch (c->processor_id & 0xff00) {
|
||||
+ switch (c->processor_id & PRID_IMP_MASK) {
|
||||
case PRID_IMP_AU1_REV1:
|
||||
case PRID_IMP_AU1_REV2:
|
||||
- switch ((c->processor_id >> 24) & 0xff) {
|
||||
+ switch ((c->processor_id >> 24) & PRID_REV_MASK) {
|
||||
case 0:
|
||||
c->cputype = CPU_AU1000;
|
||||
break;
|
||||
@@ -510,10 +510,34 @@ static inline void cpu_probe_alchemy(str
|
||||
}
|
||||
}
|
||||
|
||||
+static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
|
||||
+{
|
||||
+ decode_config1(c);
|
||||
+ c->options |= MIPS_CPU_PREFETCH;
|
||||
+ switch (c->processor_id & PRID_IMP_MASK) {
|
||||
+ case PRID_IMP_BCM4710:
|
||||
+ c->cputype = CPU_BCM4710;
|
||||
+ c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
|
||||
+ MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
|
||||
+ c->scache.flags = MIPS_CACHE_NOT_PRESENT;
|
||||
+ break;
|
||||
+ case PRID_IMP_4KC:
|
||||
+ case PRID_IMP_BCM3302:
|
||||
+ c->cputype = CPU_BCM3302;
|
||||
+ c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
|
||||
+ MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
|
||||
+ c->scache.flags = MIPS_CACHE_NOT_PRESENT;
|
||||
+ break;
|
||||
+ default:
|
||||
+ c->cputype = CPU_UNKNOWN;
|
||||
+ break;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
|
||||
{
|
||||
decode_config1(c);
|
||||
- switch (c->processor_id & 0xff00) {
|
||||
+ switch (c->processor_id & PRID_IMP_MASK) {
|
||||
case PRID_IMP_SB1:
|
||||
c->cputype = CPU_SB1;
|
||||
c->isa_level = MIPS_CPU_ISA_M64;
|
||||
@@ -535,7 +559,7 @@ static inline void cpu_probe_sibyte(stru
|
||||
static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
|
||||
{
|
||||
decode_config1(c);
|
||||
- switch (c->processor_id & 0xff00) {
|
||||
+ switch (c->processor_id & PRID_IMP_MASK) {
|
||||
case PRID_IMP_SR71000:
|
||||
c->cputype = CPU_SR71000;
|
||||
c->isa_level = MIPS_CPU_ISA_M64;
|
||||
@@ -560,7 +584,7 @@ __init void cpu_probe(void)
|
||||
c->cputype = CPU_UNKNOWN;
|
||||
|
||||
c->processor_id = read_c0_prid();
|
||||
- switch (c->processor_id & 0xff0000) {
|
||||
+ switch (c->processor_id & PRID_COMP_MASK) {
|
||||
|
||||
case PRID_COMP_LEGACY:
|
||||
cpu_probe_legacy(c);
|
||||
@@ -571,6 +595,9 @@ __init void cpu_probe(void)
|
||||
case PRID_COMP_ALCHEMY:
|
||||
cpu_probe_alchemy(c);
|
||||
break;
|
||||
+ case PRID_COMP_BROADCOM:
|
||||
+ cpu_probe_broadcom(c);
|
||||
+ break;
|
||||
case PRID_COMP_SIBYTE:
|
||||
cpu_probe_sibyte(c);
|
||||
break;
|
||||
--- a/arch/mips/kernel/head.S
|
||||
+++ b/arch/mips/kernel/head.S
|
||||
@@ -28,12 +28,20 @@
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/stackframe.h>
|
||||
|
||||
+#ifdef CONFIG_BCM4710
|
||||
+#undef eret
|
||||
+#define eret nop; nop; eret
|
||||
+#endif
|
||||
+
|
||||
.text
|
||||
+ j kernel_entry
|
||||
+ nop
|
||||
+
|
||||
/*
|
||||
* Reserved space for exception handlers.
|
||||
* Necessary for machines which link their kernels at KSEG0.
|
||||
*/
|
||||
- .fill 0x400
|
||||
+ .fill 0x3f4
|
||||
|
||||
/* The following two symbols are used for kernel profiling. */
|
||||
EXPORT(stext)
|
||||
--- a/arch/mips/kernel/proc.c
|
||||
+++ b/arch/mips/kernel/proc.c
|
||||
@@ -78,9 +78,10 @@ static const char *cpu_name[] = {
|
||||
[CPU_AU1550] "Au1550",
|
||||
[CPU_24K] "MIPS 24K",
|
||||
[CPU_AU1200] "Au1200",
|
||||
+ [CPU_BCM4710] "BCM4710",
|
||||
+ [CPU_BCM3302] "BCM3302",
|
||||
};
|
||||
|
||||
-
|
||||
static int show_cpuinfo(struct seq_file *m, void *v)
|
||||
{
|
||||
unsigned int version = current_cpu_data.processor_id;
|
||||
--- a/arch/mips/kernel/setup.c
|
||||
+++ b/arch/mips/kernel/setup.c
|
||||
@@ -493,6 +493,7 @@ void __init setup_arch(char **cmdline_p)
|
||||
void swarm_setup(void);
|
||||
void hp_setup(void);
|
||||
void au1x00_setup(void);
|
||||
+ void brcm_setup(void);
|
||||
void frame_info_init(void);
|
||||
|
||||
frame_info_init();
|
||||
@@ -691,6 +692,11 @@ void __init setup_arch(char **cmdline_p)
|
||||
pmc_yosemite_setup();
|
||||
break;
|
||||
#endif
|
||||
+#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4310)
|
||||
+ case MACH_GROUP_BRCM:
|
||||
+ brcm_setup();
|
||||
+ break;
|
||||
+#endif
|
||||
default:
|
||||
panic("Unsupported architecture");
|
||||
}
|
||||
--- a/arch/mips/kernel/traps.c
|
||||
+++ b/arch/mips/kernel/traps.c
|
||||
@@ -920,6 +920,7 @@ void __init per_cpu_trap_init(void)
|
||||
void __init trap_init(void)
|
||||
{
|
||||
extern char except_vec1_generic;
|
||||
+ extern char except_vec2_generic;
|
||||
extern char except_vec3_generic, except_vec3_r4000;
|
||||
extern char except_vec_ejtag_debug;
|
||||
extern char except_vec4;
|
||||
@@ -927,6 +928,7 @@ void __init trap_init(void)
|
||||
|
||||
/* Copy the generic exception handler code to it's final destination. */
|
||||
memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
|
||||
+ memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
|
||||
|
||||
/*
|
||||
* Setup default vectors
|
||||
@@ -985,6 +987,12 @@ void __init trap_init(void)
|
||||
set_except_vector(13, handle_tr);
|
||||
set_except_vector(22, handle_mdmx);
|
||||
|
||||
+ if (current_cpu_data.cputype == CPU_SB1) {
|
||||
+ /* Enable timer interrupt and scd mapped interrupt */
|
||||
+ clear_c0_status(0xf000);
|
||||
+ set_c0_status(0xc00);
|
||||
+ }
|
||||
+
|
||||
if (cpu_has_fpu && !cpu_has_nofpuex)
|
||||
set_except_vector(15, handle_fpe);
|
||||
|
||||
--- a/arch/mips/Makefile
|
||||
+++ b/arch/mips/Makefile
|
||||
@@ -726,6 +726,19 @@ LOADADDR += 0x80020000
|
||||
endif
|
||||
|
||||
#
|
||||
+# Broadcom BCM947XX variants
|
||||
+#
|
||||
+ifdef CONFIG_BCM947XX
|
||||
+LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
|
||||
+SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
|
||||
+LOADADDR := 0x80001000
|
||||
+
|
||||
+zImage: vmlinux
|
||||
+ $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
|
||||
+export LOADADDR
|
||||
+endif
|
||||
+
|
||||
+#
|
||||
# Choosing incompatible machines durings configuration will result in
|
||||
# error messages during linking. Select a default linkscript if
|
||||
# none has been choosen above.
|
||||
@@ -779,6 +792,7 @@ archclean:
|
||||
$(MAKE) -C arch/$(ARCH)/tools clean
|
||||
$(MAKE) -C arch/mips/baget clean
|
||||
$(MAKE) -C arch/mips/lasat clean
|
||||
+ $(MAKE) -C arch/mips/bcm947xx/compressed clean
|
||||
|
||||
archmrproper:
|
||||
@$(MAKEBOOT) mrproper
|
||||
--- a/arch/mips/mm/c-r4k.c
|
||||
+++ b/arch/mips/mm/c-r4k.c
|
||||
@@ -1118,3 +1118,47 @@ void __init ld_mmu_r4xx0(void)
|
||||
build_clear_page();
|
||||
build_copy_page();
|
||||
}
|
||||
+
|
||||
+#ifdef CONFIG_BCM4704
|
||||
+static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
|
||||
+{
|
||||
+ unsigned long ic_lsize = current_cpu_data.icache.linesz;
|
||||
+ int i;
|
||||
+ for (i = 0; i < nbytes; i += ic_lsize)
|
||||
+ fill_icache_line((addr + i));
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
+ * This must be run from the cache on 4704A0
|
||||
+ * so there are no mips core BIU ops in progress
|
||||
+ * when the PFC is enabled.
|
||||
+ */
|
||||
+#define PFC_CR0 0xff400000 /* control reg 0 */
|
||||
+#define PFC_CR1 0xff400004 /* control reg 1 */
|
||||
+static void __init enable_pfc(u32 mode)
|
||||
+{
|
||||
+ /* write range */
|
||||
+ *(volatile u32 *)PFC_CR1 = 0xffff0000;
|
||||
+
|
||||
+ /* enable */
|
||||
+ *(volatile u32 *)PFC_CR0 = mode;
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
+
|
||||
+void check_enable_mips_pfc(int val)
|
||||
+{
|
||||
+
|
||||
+#ifdef CONFIG_BCM4704
|
||||
+ struct cpuinfo_mips *c = ¤t_cpu_data;
|
||||
+
|
||||
+ /* enable prefetch cache */
|
||||
+ if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
|
||||
+ && (read_c0_diag() & (1 << 29))) {
|
||||
+ mips32_icache_fill((unsigned long) &enable_pfc, 64);
|
||||
+ enable_pfc(val);
|
||||
+ }
|
||||
+#endif
|
||||
+}
|
||||
+
|
||||
+
|
||||
--- a/arch/mips/pci/Makefile
|
||||
+++ b/arch/mips/pci/Makefile
|
||||
@@ -13,7 +13,9 @@ obj-$(CONFIG_MIPS_GT64120) += ops-gt6412
|
||||
obj-$(CONFIG_MIPS_MSC) += ops-msc.o
|
||||
obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
|
||||
obj-$(CONFIG_SNI_RM200_PCI) += ops-sni.o
|
||||
+ifndef CONFIG_BCM947XX
|
||||
obj-y += pci.o
|
||||
+endif
|
||||
obj-$(CONFIG_PCI_AUTO) += pci_auto.o
|
||||
|
||||
include $(TOPDIR)/Rules.make
|
||||
--- a/drivers/char/serial.c
|
||||
+++ b/drivers/char/serial.c
|
||||
@@ -444,6 +444,10 @@ static _INLINE_ unsigned int serial_in(s
|
||||
return inb(info->port+1);
|
||||
#endif
|
||||
case SERIAL_IO_MEM:
|
||||
+#ifdef CONFIG_BCM4310
|
||||
+ readb((unsigned long) info->iomem_base +
|
||||
+ (UART_SCR<<info->iomem_reg_shift));
|
||||
+#endif
|
||||
return readb((unsigned long) info->iomem_base +
|
||||
(offset<<info->iomem_reg_shift));
|
||||
default:
|
||||
@@ -464,6 +468,9 @@ static _INLINE_ void serial_out(struct a
|
||||
case SERIAL_IO_MEM:
|
||||
writeb(value, (unsigned long) info->iomem_base +
|
||||
(offset<<info->iomem_reg_shift));
|
||||
+#ifdef CONFIG_BCM4704
|
||||
+ *((volatile unsigned int *) KSEG1ADDR(0x18000000));
|
||||
+#endif
|
||||
break;
|
||||
default:
|
||||
outb(value, info->port+offset);
|
||||
@@ -1728,7 +1735,7 @@ static void change_speed(struct async_st
|
||||
/* Special case since 134 is really 134.5 */
|
||||
quot = (2*baud_base / 269);
|
||||
else if (baud)
|
||||
- quot = baud_base / baud;
|
||||
+ quot = (baud_base + (baud / 2)) / baud;
|
||||
}
|
||||
/* If the quotient is zero refuse the change */
|
||||
if (!quot && old_termios) {
|
||||
@@ -1745,12 +1752,12 @@ static void change_speed(struct async_st
|
||||
/* Special case since 134 is really 134.5 */
|
||||
quot = (2*baud_base / 269);
|
||||
else if (baud)
|
||||
- quot = baud_base / baud;
|
||||
+ quot = (baud_base + (baud / 2)) / baud;
|
||||
}
|
||||
}
|
||||
/* As a last resort, if the quotient is zero, default to 9600 bps */
|
||||
if (!quot)
|
||||
- quot = baud_base / 9600;
|
||||
+ quot = (baud_base + 4800) / 9600;
|
||||
/*
|
||||
* Work around a bug in the Oxford Semiconductor 952 rev B
|
||||
* chip which causes it to seriously miscalculate baud rates
|
||||
@@ -5994,6 +6001,13 @@ static int __init serial_console_setup(s
|
||||
* Divisor, bytesize and parity
|
||||
*/
|
||||
state = rs_table + co->index;
|
||||
+ /*
|
||||
+ * Safe guard: state structure must have been initialized
|
||||
+ */
|
||||
+ if (state->iomem_base == NULL) {
|
||||
+ printk("!unable to setup serial console!\n");
|
||||
+ return -1;
|
||||
+ }
|
||||
if (doflow)
|
||||
state->flags |= ASYNC_CONS_FLOW;
|
||||
info = &async_sercons;
|
||||
@@ -6007,7 +6021,7 @@ static int __init serial_console_setup(s
|
||||
info->io_type = state->io_type;
|
||||
info->iomem_base = state->iomem_base;
|
||||
info->iomem_reg_shift = state->iomem_reg_shift;
|
||||
- quot = state->baud_base / baud;
|
||||
+ quot = (state->baud_base + (baud / 2)) / baud;
|
||||
cval = cflag & (CSIZE | CSTOPB);
|
||||
#if defined(__powerpc__) || defined(__alpha__)
|
||||
cval >>= 8;
|
||||
--- a/drivers/net/Makefile
|
||||
+++ b/drivers/net/Makefile
|
||||
@@ -3,6 +3,8 @@
|
||||
# Makefile for the Linux network (ethercard) device drivers.
|
||||
#
|
||||
|
||||
+EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
|
||||
+
|
||||
obj-y :=
|
||||
obj-m :=
|
||||
obj-n :=
|
||||
--- a/drivers/parport/Config.in
|
||||
+++ b/drivers/parport/Config.in
|
||||
@@ -11,6 +11,7 @@ comment 'Parallel port support'
|
||||
tristate 'Parallel port support' CONFIG_PARPORT
|
||||
if [ "$CONFIG_PARPORT" != "n" ]; then
|
||||
dep_tristate ' PC-style hardware' CONFIG_PARPORT_PC $CONFIG_PARPORT
|
||||
+ dep_tristate ' Asus WL500g parallel port' CONFIG_PARPORT_SPLINK $CONFIG_PARPORT
|
||||
if [ "$CONFIG_PARPORT_PC" != "n" -a "$CONFIG_SERIAL" != "n" ]; then
|
||||
if [ "$CONFIG_SERIAL" = "m" ]; then
|
||||
define_tristate CONFIG_PARPORT_PC_CML1 m
|
||||
--- a/drivers/parport/Makefile
|
||||
+++ b/drivers/parport/Makefile
|
||||
@@ -22,6 +22,7 @@ endif
|
||||
|
||||
obj-$(CONFIG_PARPORT) += parport.o
|
||||
obj-$(CONFIG_PARPORT_PC) += parport_pc.o
|
||||
+obj-$(CONFIG_PARPORT_SPLINK) += parport_splink.o
|
||||
obj-$(CONFIG_PARPORT_PC_PCMCIA) += parport_cs.o
|
||||
obj-$(CONFIG_PARPORT_AMIGA) += parport_amiga.o
|
||||
obj-$(CONFIG_PARPORT_MFC3) += parport_mfc3.o
|
||||
--- a/include/asm-mips/bootinfo.h
|
||||
+++ b/include/asm-mips/bootinfo.h
|
||||
@@ -37,6 +37,7 @@
|
||||
#define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
|
||||
#define MACH_GROUP_LASAT 21
|
||||
#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
|
||||
+#define MACH_GROUP_BRCM 23 /* Broadcom */
|
||||
|
||||
/*
|
||||
* Valid machtype values for group unknown (low order halfword of mips_machtype)
|
||||
@@ -197,6 +198,15 @@
|
||||
#define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
|
||||
|
||||
/*
|
||||
+ * Valid machtypes for group Broadcom
|
||||
+ */
|
||||
+#define MACH_BCM93725 0
|
||||
+#define MACH_BCM93725_VJ 1
|
||||
+#define MACH_BCM93730 2
|
||||
+#define MACH_BCM947XX 3
|
||||
+#define MACH_BCM933XX 4
|
||||
+
|
||||
+/*
|
||||
* Valid machtype for group TITAN
|
||||
*/
|
||||
#define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
|
||||
--- a/include/asm-mips/cpu.h
|
||||
+++ b/include/asm-mips/cpu.h
|
||||
@@ -22,6 +22,11 @@
|
||||
spec.
|
||||
*/
|
||||
|
||||
+#define PRID_COPT_MASK 0xff000000
|
||||
+#define PRID_COMP_MASK 0x00ff0000
|
||||
+#define PRID_IMP_MASK 0x0000ff00
|
||||
+#define PRID_REV_MASK 0x000000ff
|
||||
+
|
||||
#define PRID_COMP_LEGACY 0x000000
|
||||
#define PRID_COMP_MIPS 0x010000
|
||||
#define PRID_COMP_BROADCOM 0x020000
|
||||
@@ -58,6 +63,7 @@
|
||||
#define PRID_IMP_RM7000 0x2700
|
||||
#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
|
||||
#define PRID_IMP_RM9000 0x3400
|
||||
+#define PRID_IMP_BCM4710 0x4000
|
||||
#define PRID_IMP_R5432 0x5400
|
||||
#define PRID_IMP_R5500 0x5500
|
||||
#define PRID_IMP_4KC 0x8000
|
||||
@@ -66,10 +72,16 @@
|
||||
#define PRID_IMP_4KEC 0x8400
|
||||
#define PRID_IMP_4KSC 0x8600
|
||||
#define PRID_IMP_25KF 0x8800
|
||||
+#define PRID_IMP_BCM3302 0x9000
|
||||
+#define PRID_IMP_BCM3303 0x9100
|
||||
#define PRID_IMP_24K 0x9300
|
||||
|
||||
#define PRID_IMP_UNKNOWN 0xff00
|
||||
|
||||
+#define BCM330X(id) \
|
||||
+ (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
|
||||
+ || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
|
||||
+
|
||||
/*
|
||||
* These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
|
||||
*/
|
||||
@@ -174,7 +186,9 @@
|
||||
#define CPU_AU1550 57
|
||||
#define CPU_24K 58
|
||||
#define CPU_AU1200 59
|
||||
-#define CPU_LAST 59
|
||||
+#define CPU_BCM4710 60
|
||||
+#define CPU_BCM3302 61
|
||||
+#define CPU_LAST 61
|
||||
|
||||
/*
|
||||
* ISA Level encodings
|
||||
--- a/include/asm-mips/r4kcache.h
|
||||
+++ b/include/asm-mips/r4kcache.h
|
||||
@@ -567,4 +567,17 @@ static inline void blast_scache128_page_
|
||||
cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
|
||||
}
|
||||
|
||||
+extern inline void fill_icache_line(unsigned long addr)
|
||||
+{
|
||||
+ __asm__ __volatile__(
|
||||
+ ".set noreorder\n\t"
|
||||
+ ".set mips3\n\t"
|
||||
+ "cache %1, (%0)\n\t"
|
||||
+ ".set mips0\n\t"
|
||||
+ ".set reorder"
|
||||
+ :
|
||||
+ : "r" (addr),
|
||||
+ "i" (Fill));
|
||||
+}
|
||||
+
|
||||
#endif /* __ASM_R4KCACHE_H */
|
||||
--- a/include/asm-mips/serial.h
|
||||
+++ b/include/asm-mips/serial.h
|
||||
@@ -223,6 +223,13 @@
|
||||
#define TXX927_SERIAL_PORT_DEFNS
|
||||
#endif
|
||||
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+/* reserve 4 ports to be configured at runtime */
|
||||
+#define BCM947XX_SERIAL_PORT_DEFNS { 0, }, { 0, }, { 0, }, { 0, },
|
||||
+#else
|
||||
+#define BCM947XX_SERIAL_PORT_DEFNS
|
||||
+#endif
|
||||
+
|
||||
#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
|
||||
#define STD_SERIAL_PORT_DEFNS \
|
||||
/* UART CLK PORT IRQ FLAGS */ \
|
||||
@@ -470,6 +477,7 @@
|
||||
#define SERIAL_PORT_DFNS \
|
||||
ATLAS_SERIAL_PORT_DEFNS \
|
||||
AU1000_SERIAL_PORT_DEFNS \
|
||||
+ BCM947XX_SERIAL_PORT_DEFNS \
|
||||
COBALT_SERIAL_PORT_DEFNS \
|
||||
DDB5477_SERIAL_PORT_DEFNS \
|
||||
EV96100_SERIAL_PORT_DEFNS \
|
||||
--- a/init/do_mounts.c
|
||||
+++ b/init/do_mounts.c
|
||||
@@ -255,7 +255,13 @@ static struct dev_name_struct {
|
||||
{ "ftlb", 0x2c08 },
|
||||
{ "ftlc", 0x2c10 },
|
||||
{ "ftld", 0x2c18 },
|
||||
+#if defined(CONFIG_MTD_BLOCK) || defined(CONFIG_MTD_BLOCK_RO)
|
||||
{ "mtdblock", 0x1f00 },
|
||||
+ { "mtdblock0",0x1f00 },
|
||||
+ { "mtdblock1",0x1f01 },
|
||||
+ { "mtdblock2",0x1f02 },
|
||||
+ { "mtdblock3",0x1f03 },
|
||||
+#endif
|
||||
{ "nb", 0x2b00 },
|
||||
{ NULL, 0 }
|
||||
};
|
||||
|
|
@ -1,491 +0,0 @@
|
|||
--- a/arch/mips/kernel/entry.S
|
||||
+++ b/arch/mips/kernel/entry.S
|
||||
@@ -100,6 +100,10 @@ END(except_vec1_generic)
|
||||
* and R4400 SC and MC versions.
|
||||
*/
|
||||
NESTED(except_vec3_generic, 0, sp)
|
||||
+#ifdef CONFIG_BCM4710
|
||||
+ nop
|
||||
+ nop
|
||||
+#endif
|
||||
#if R5432_CP0_INTERRUPT_WAR
|
||||
mfc0 k0, CP0_INDEX
|
||||
#endif
|
||||
--- a/arch/mips/mm/c-r4k.c
|
||||
+++ b/arch/mips/mm/c-r4k.c
|
||||
@@ -14,6 +14,12 @@
|
||||
#include <linux/mm.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
+#ifdef CONFIG_BCM4710
|
||||
+#include "../bcm947xx/include/typedefs.h"
|
||||
+#include "../bcm947xx/include/sbconfig.h"
|
||||
+#include <asm/paccess.h>
|
||||
+#endif
|
||||
+
|
||||
#include <asm/bcache.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/cacheops.h>
|
||||
@@ -40,6 +46,7 @@ static struct bcache_ops no_sc_ops = {
|
||||
.bc_inv = (void *)no_sc_noop
|
||||
};
|
||||
|
||||
+int bcm4710 = 0;
|
||||
struct bcache_ops *bcops = &no_sc_ops;
|
||||
|
||||
#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010)
|
||||
@@ -64,8 +71,10 @@ static inline void r4k_blast_dcache_page
|
||||
static inline void r4k_blast_dcache_page_setup(void)
|
||||
{
|
||||
unsigned long dc_lsize = current_cpu_data.dcache.linesz;
|
||||
-
|
||||
- if (dc_lsize == 16)
|
||||
+
|
||||
+ if (bcm4710)
|
||||
+ r4k_blast_dcache_page = blast_dcache_page;
|
||||
+ else if (dc_lsize == 16)
|
||||
r4k_blast_dcache_page = blast_dcache16_page;
|
||||
else if (dc_lsize == 32)
|
||||
r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
|
||||
@@ -77,7 +86,9 @@ static void r4k_blast_dcache_page_indexe
|
||||
{
|
||||
unsigned long dc_lsize = current_cpu_data.dcache.linesz;
|
||||
|
||||
- if (dc_lsize == 16)
|
||||
+ if (bcm4710)
|
||||
+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
|
||||
+ else if (dc_lsize == 16)
|
||||
r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
|
||||
else if (dc_lsize == 32)
|
||||
r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
|
||||
@@ -89,7 +100,9 @@ static inline void r4k_blast_dcache_setu
|
||||
{
|
||||
unsigned long dc_lsize = current_cpu_data.dcache.linesz;
|
||||
|
||||
- if (dc_lsize == 16)
|
||||
+ if (bcm4710)
|
||||
+ r4k_blast_dcache = blast_dcache;
|
||||
+ else if (dc_lsize == 16)
|
||||
r4k_blast_dcache = blast_dcache16;
|
||||
else if (dc_lsize == 32)
|
||||
r4k_blast_dcache = blast_dcache32;
|
||||
@@ -266,6 +279,7 @@ static void r4k___flush_cache_all(void)
|
||||
r4k_blast_dcache();
|
||||
r4k_blast_icache();
|
||||
|
||||
+ if (!bcm4710)
|
||||
switch (current_cpu_data.cputype) {
|
||||
case CPU_R4000SC:
|
||||
case CPU_R4000MC:
|
||||
@@ -304,10 +318,10 @@ static void r4k_flush_cache_mm(struct mm
|
||||
* Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
|
||||
* only flush the primary caches but R10000 and R12000 behave sane ...
|
||||
*/
|
||||
- if (current_cpu_data.cputype == CPU_R4000SC ||
|
||||
+ if (!bcm4710 && (current_cpu_data.cputype == CPU_R4000SC ||
|
||||
current_cpu_data.cputype == CPU_R4000MC ||
|
||||
current_cpu_data.cputype == CPU_R4400SC ||
|
||||
- current_cpu_data.cputype == CPU_R4400MC)
|
||||
+ current_cpu_data.cputype == CPU_R4400MC))
|
||||
r4k_blast_scache();
|
||||
}
|
||||
|
||||
@@ -383,12 +397,15 @@ static void r4k_flush_icache_range(unsig
|
||||
unsigned long ic_lsize = current_cpu_data.icache.linesz;
|
||||
unsigned long addr, aend;
|
||||
|
||||
+ addr = start & ~(dc_lsize - 1);
|
||||
+ aend = (end - 1) & ~(dc_lsize - 1);
|
||||
+
|
||||
if (!cpu_has_ic_fills_f_dc) {
|
||||
if (end - start > dcache_size)
|
||||
r4k_blast_dcache();
|
||||
else {
|
||||
- addr = start & ~(dc_lsize - 1);
|
||||
- aend = (end - 1) & ~(dc_lsize - 1);
|
||||
+ BCM4710_PROTECTED_FILL_TLB(addr);
|
||||
+ BCM4710_PROTECTED_FILL_TLB(aend);
|
||||
|
||||
while (1) {
|
||||
/* Hit_Writeback_Inv_D */
|
||||
@@ -403,8 +420,6 @@ static void r4k_flush_icache_range(unsig
|
||||
if (end - start > icache_size)
|
||||
r4k_blast_icache();
|
||||
else {
|
||||
- addr = start & ~(ic_lsize - 1);
|
||||
- aend = (end - 1) & ~(ic_lsize - 1);
|
||||
while (1) {
|
||||
/* Hit_Invalidate_I */
|
||||
protected_flush_icache_line(addr);
|
||||
@@ -413,6 +428,9 @@ static void r4k_flush_icache_range(unsig
|
||||
addr += ic_lsize;
|
||||
}
|
||||
}
|
||||
+
|
||||
+ if (bcm4710)
|
||||
+ flush_cache_all();
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -443,7 +461,8 @@ static void r4k_flush_icache_page(struct
|
||||
if (cpu_has_subset_pcaches) {
|
||||
unsigned long addr = (unsigned long) page_address(page);
|
||||
|
||||
- r4k_blast_scache_page(addr);
|
||||
+ if (!bcm4710)
|
||||
+ r4k_blast_scache_page(addr);
|
||||
ClearPageDcacheDirty(page);
|
||||
|
||||
return;
|
||||
@@ -451,6 +470,7 @@ static void r4k_flush_icache_page(struct
|
||||
|
||||
if (!cpu_has_ic_fills_f_dc) {
|
||||
unsigned long addr = (unsigned long) page_address(page);
|
||||
+
|
||||
r4k_blast_dcache_page(addr);
|
||||
ClearPageDcacheDirty(page);
|
||||
}
|
||||
@@ -477,7 +497,7 @@ static void r4k_dma_cache_wback_inv(unsi
|
||||
/* Catch bad driver code */
|
||||
BUG_ON(size == 0);
|
||||
|
||||
- if (cpu_has_subset_pcaches) {
|
||||
+ if (!bcm4710 && cpu_has_subset_pcaches) {
|
||||
unsigned long sc_lsize = current_cpu_data.scache.linesz;
|
||||
|
||||
if (size >= scache_size) {
|
||||
@@ -509,6 +529,8 @@ static void r4k_dma_cache_wback_inv(unsi
|
||||
R4600_HIT_CACHEOP_WAR_IMPL;
|
||||
a = addr & ~(dc_lsize - 1);
|
||||
end = (addr + size - 1) & ~(dc_lsize - 1);
|
||||
+ BCM4710_FILL_TLB(a);
|
||||
+ BCM4710_FILL_TLB(end);
|
||||
while (1) {
|
||||
flush_dcache_line(a); /* Hit_Writeback_Inv_D */
|
||||
if (a == end)
|
||||
@@ -527,7 +549,7 @@ static void r4k_dma_cache_inv(unsigned l
|
||||
/* Catch bad driver code */
|
||||
BUG_ON(size == 0);
|
||||
|
||||
- if (cpu_has_subset_pcaches) {
|
||||
+ if (!bcm4710 && (cpu_has_subset_pcaches)) {
|
||||
unsigned long sc_lsize = current_cpu_data.scache.linesz;
|
||||
|
||||
if (size >= scache_size) {
|
||||
@@ -554,6 +576,8 @@ static void r4k_dma_cache_inv(unsigned l
|
||||
R4600_HIT_CACHEOP_WAR_IMPL;
|
||||
a = addr & ~(dc_lsize - 1);
|
||||
end = (addr + size - 1) & ~(dc_lsize - 1);
|
||||
+ BCM4710_FILL_TLB(a);
|
||||
+ BCM4710_FILL_TLB(end);
|
||||
while (1) {
|
||||
flush_dcache_line(a); /* Hit_Writeback_Inv_D */
|
||||
if (a == end)
|
||||
@@ -577,6 +601,8 @@ static void r4k_flush_cache_sigtramp(uns
|
||||
unsigned long dc_lsize = current_cpu_data.dcache.linesz;
|
||||
|
||||
R4600_HIT_CACHEOP_WAR_IMPL;
|
||||
+ BCM4710_PROTECTED_FILL_TLB(addr);
|
||||
+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
|
||||
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
|
||||
protected_flush_icache_line(addr & ~(ic_lsize - 1));
|
||||
if (MIPS4K_ICACHE_REFILL_WAR) {
|
||||
@@ -986,10 +1012,12 @@ static void __init setup_scache(void)
|
||||
case CPU_R4000MC:
|
||||
case CPU_R4400SC:
|
||||
case CPU_R4400MC:
|
||||
- probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
|
||||
- sc_present = probe_scache_kseg1(config);
|
||||
- if (sc_present)
|
||||
- c->options |= MIPS_CPU_CACHE_CDEX_S;
|
||||
+ if (!bcm4710) {
|
||||
+ probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
|
||||
+ sc_present = probe_scache_kseg1(config);
|
||||
+ if (sc_present)
|
||||
+ c->options |= MIPS_CPU_CACHE_CDEX_S;
|
||||
+ }
|
||||
break;
|
||||
|
||||
case CPU_R10000:
|
||||
@@ -1041,6 +1069,19 @@ static void __init setup_scache(void)
|
||||
static inline void coherency_setup(void)
|
||||
{
|
||||
change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
|
||||
+
|
||||
+#if defined(CONFIG_BCM4310) || defined(CONFIG_BCM4704) || defined(CONFIG_BCM5365)
|
||||
+ if (BCM330X(current_cpu_data.processor_id)) {
|
||||
+ uint32 cm;
|
||||
+
|
||||
+ cm = read_c0_diag();
|
||||
+ /* Enable icache */
|
||||
+ cm |= (1 << 31);
|
||||
+ /* Enable dcache */
|
||||
+ cm |= (1 << 30);
|
||||
+ write_c0_diag(cm);
|
||||
+ }
|
||||
+#endif
|
||||
|
||||
/*
|
||||
* c0_status.cu=0 specifies that updates by the sc instruction use
|
||||
@@ -1073,6 +1114,12 @@ void __init ld_mmu_r4xx0(void)
|
||||
memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
|
||||
memcpy((void *)(KSEG1 + 0x100), &except_vec2_generic, 0x80);
|
||||
|
||||
+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & PRID_REV_MASK) == 0) {
|
||||
+ printk("Enabling BCM4710A0 cache workarounds.\n");
|
||||
+ bcm4710 = 1;
|
||||
+ } else
|
||||
+ bcm4710 = 0;
|
||||
+
|
||||
probe_pcache();
|
||||
setup_scache();
|
||||
|
||||
--- a/arch/mips/mm/tlbex-mips32.S
|
||||
+++ b/arch/mips/mm/tlbex-mips32.S
|
||||
@@ -90,6 +90,9 @@
|
||||
.set noat
|
||||
LEAF(except_vec0_r4000)
|
||||
.set mips3
|
||||
+#ifdef CONFIG_BCM4704
|
||||
+ nop
|
||||
+#endif
|
||||
#ifdef CONFIG_SMP
|
||||
mfc0 k1, CP0_CONTEXT
|
||||
la k0, pgd_current
|
||||
--- a/include/asm-mips/r4kcache.h
|
||||
+++ b/include/asm-mips/r4kcache.h
|
||||
@@ -15,6 +15,18 @@
|
||||
#include <asm/asm.h>
|
||||
#include <asm/cacheops.h>
|
||||
|
||||
+#ifdef CONFIG_BCM4710
|
||||
+#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
|
||||
+
|
||||
+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
|
||||
+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
|
||||
+#else
|
||||
+#define BCM4710_DUMMY_RREG()
|
||||
+
|
||||
+#define BCM4710_FILL_TLB(addr)
|
||||
+#define BCM4710_PROTECTED_FILL_TLB(addr)
|
||||
+#endif
|
||||
+
|
||||
#define cache_op(op,addr) \
|
||||
__asm__ __volatile__( \
|
||||
" .set noreorder \n" \
|
||||
@@ -27,12 +39,25 @@
|
||||
|
||||
static inline void flush_icache_line_indexed(unsigned long addr)
|
||||
{
|
||||
- cache_op(Index_Invalidate_I, addr);
|
||||
+ unsigned int way;
|
||||
+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
|
||||
+
|
||||
+ for (way = 0; way < current_cpu_data.dcache.ways; way++) {
|
||||
+ cache_op(Index_Invalidate_I, addr);
|
||||
+ addr += ws_inc;
|
||||
+ }
|
||||
}
|
||||
|
||||
static inline void flush_dcache_line_indexed(unsigned long addr)
|
||||
{
|
||||
- cache_op(Index_Writeback_Inv_D, addr);
|
||||
+ unsigned int way;
|
||||
+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
|
||||
+
|
||||
+ for (way = 0; way < current_cpu_data.dcache.ways; way++) {
|
||||
+ BCM4710_DUMMY_RREG();
|
||||
+ cache_op(Index_Writeback_Inv_D, addr);
|
||||
+ addr += ws_inc;
|
||||
+ }
|
||||
}
|
||||
|
||||
static inline void flush_scache_line_indexed(unsigned long addr)
|
||||
@@ -47,6 +72,7 @@ static inline void flush_icache_line(uns
|
||||
|
||||
static inline void flush_dcache_line(unsigned long addr)
|
||||
{
|
||||
+ BCM4710_DUMMY_RREG();
|
||||
cache_op(Hit_Writeback_Inv_D, addr);
|
||||
}
|
||||
|
||||
@@ -91,6 +117,7 @@ static inline void protected_flush_icach
|
||||
*/
|
||||
static inline void protected_writeback_dcache_line(unsigned long addr)
|
||||
{
|
||||
+ BCM4710_DUMMY_RREG();
|
||||
__asm__ __volatile__(
|
||||
".set noreorder\n\t"
|
||||
".set mips3\n"
|
||||
@@ -138,6 +165,62 @@ static inline void invalidate_tcache_pag
|
||||
: "r" (base), \
|
||||
"i" (op));
|
||||
|
||||
+#define cache_unroll(base,op) \
|
||||
+ __asm__ __volatile__(" \
|
||||
+ .set noreorder; \
|
||||
+ .set mips3; \
|
||||
+ cache %1, (%0); \
|
||||
+ .set mips0; \
|
||||
+ .set reorder" \
|
||||
+ : \
|
||||
+ : "r" (base), \
|
||||
+ "i" (op));
|
||||
+
|
||||
+
|
||||
+static inline void blast_dcache(void)
|
||||
+{
|
||||
+ unsigned long start = KSEG0;
|
||||
+ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
|
||||
+ unsigned long end = (start + dcache_size);
|
||||
+
|
||||
+ while(start < end) {
|
||||
+ BCM4710_DUMMY_RREG();
|
||||
+ cache_unroll(start,Index_Writeback_Inv_D);
|
||||
+ start += current_cpu_data.dcache.linesz;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static inline void blast_dcache_page(unsigned long page)
|
||||
+{
|
||||
+ unsigned long start = page;
|
||||
+ unsigned long end = start + PAGE_SIZE;
|
||||
+
|
||||
+ BCM4710_FILL_TLB(start);
|
||||
+ do {
|
||||
+ BCM4710_DUMMY_RREG();
|
||||
+ cache_unroll(start,Hit_Writeback_Inv_D);
|
||||
+ start += current_cpu_data.dcache.linesz;
|
||||
+ } while (start < end);
|
||||
+}
|
||||
+
|
||||
+static inline void blast_dcache_page_indexed(unsigned long page)
|
||||
+{
|
||||
+ unsigned long start = page;
|
||||
+ unsigned long end = start + PAGE_SIZE;
|
||||
+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
|
||||
+ unsigned long ws_end = current_cpu_data.dcache.ways <<
|
||||
+ current_cpu_data.dcache.waybit;
|
||||
+ unsigned long ws, addr;
|
||||
+
|
||||
+ for (ws = 0; ws < ws_end; ws += ws_inc) {
|
||||
+ start = page + ws;
|
||||
+ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
|
||||
+ BCM4710_DUMMY_RREG();
|
||||
+ cache_unroll(addr,Index_Writeback_Inv_D);
|
||||
+ }
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
static inline void blast_dcache16(void)
|
||||
{
|
||||
unsigned long start = KSEG0;
|
||||
@@ -148,8 +231,9 @@ static inline void blast_dcache16(void)
|
||||
unsigned long ws, addr;
|
||||
|
||||
for (ws = 0; ws < ws_end; ws += ws_inc)
|
||||
- for (addr = start; addr < end; addr += 0x200)
|
||||
+ for (addr = start; addr < end; addr += 0x200) {
|
||||
cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
|
||||
+ }
|
||||
}
|
||||
|
||||
static inline void blast_dcache16_page(unsigned long page)
|
||||
@@ -173,8 +257,9 @@ static inline void blast_dcache16_page_i
|
||||
unsigned long ws, addr;
|
||||
|
||||
for (ws = 0; ws < ws_end; ws += ws_inc)
|
||||
- for (addr = start; addr < end; addr += 0x200)
|
||||
+ for (addr = start; addr < end; addr += 0x200) {
|
||||
cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
|
||||
+ }
|
||||
}
|
||||
|
||||
static inline void blast_icache16(void)
|
||||
@@ -196,6 +281,7 @@ static inline void blast_icache16_page(u
|
||||
unsigned long start = page;
|
||||
unsigned long end = start + PAGE_SIZE;
|
||||
|
||||
+ BCM4710_FILL_TLB(start);
|
||||
do {
|
||||
cache16_unroll32(start,Hit_Invalidate_I);
|
||||
start += 0x200;
|
||||
@@ -281,6 +367,7 @@ static inline void blast_scache16_page_i
|
||||
: "r" (base), \
|
||||
"i" (op));
|
||||
|
||||
+
|
||||
static inline void blast_dcache32(void)
|
||||
{
|
||||
unsigned long start = KSEG0;
|
||||
@@ -291,8 +378,9 @@ static inline void blast_dcache32(void)
|
||||
unsigned long ws, addr;
|
||||
|
||||
for (ws = 0; ws < ws_end; ws += ws_inc)
|
||||
- for (addr = start; addr < end; addr += 0x400)
|
||||
+ for (addr = start; addr < end; addr += 0x400) {
|
||||
cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
|
||||
+ }
|
||||
}
|
||||
|
||||
static inline void blast_dcache32_page(unsigned long page)
|
||||
@@ -316,8 +404,9 @@ static inline void blast_dcache32_page_i
|
||||
unsigned long ws, addr;
|
||||
|
||||
for (ws = 0; ws < ws_end; ws += ws_inc)
|
||||
- for (addr = start; addr < end; addr += 0x400)
|
||||
+ for (addr = start; addr < end; addr += 0x400) {
|
||||
cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
|
||||
+ }
|
||||
}
|
||||
|
||||
static inline void blast_icache32(void)
|
||||
@@ -339,6 +428,7 @@ static inline void blast_icache32_page(u
|
||||
unsigned long start = page;
|
||||
unsigned long end = start + PAGE_SIZE;
|
||||
|
||||
+ BCM4710_FILL_TLB(start);
|
||||
do {
|
||||
cache32_unroll32(start,Hit_Invalidate_I);
|
||||
start += 0x400;
|
||||
@@ -443,6 +533,7 @@ static inline void blast_icache64_page(u
|
||||
unsigned long start = page;
|
||||
unsigned long end = start + PAGE_SIZE;
|
||||
|
||||
+ BCM4710_FILL_TLB(start);
|
||||
do {
|
||||
cache64_unroll32(start,Hit_Invalidate_I);
|
||||
start += 0x800;
|
||||
--- a/include/asm-mips/stackframe.h
|
||||
+++ b/include/asm-mips/stackframe.h
|
||||
@@ -209,6 +209,20 @@
|
||||
|
||||
#endif
|
||||
|
||||
+#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4704)
|
||||
+
|
||||
+#undef RESTORE_SP_AND_RET
|
||||
+#define RESTORE_SP_AND_RET \
|
||||
+ lw sp, PT_R29(sp); \
|
||||
+ .set mips3; \
|
||||
+ nop; \
|
||||
+ nop; \
|
||||
+ eret; \
|
||||
+ .set mips0
|
||||
+
|
||||
+#endif
|
||||
+
|
||||
+
|
||||
#define RESTORE_SP \
|
||||
lw sp, PT_R29(sp); \
|
||||
|
||||
--- a/mm/memory.c
|
||||
+++ b/mm/memory.c
|
||||
@@ -927,6 +927,7 @@ static inline void break_cow(struct vm_a
|
||||
flush_page_to_ram(new_page);
|
||||
flush_cache_page(vma, address);
|
||||
establish_pte(vma, address, page_table, pte_mkwrite(pte_mkdirty(mk_pte(new_page, vma->vm_page_prot))));
|
||||
+ flush_icache_page(vma, new_page);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1,68 +0,0 @@
|
|||
--- a/arch/mips/bcm947xx/Makefile
|
||||
+++ b/arch/mips/bcm947xx/Makefile
|
||||
@@ -11,6 +11,7 @@ export-objs := export.o
|
||||
obj-y := prom.o setup.o time.o sbmips.o gpio.o
|
||||
obj-y += nvram.o cfe_env.o hndpmu.o
|
||||
obj-y += sbutils.o utils.o bcmsrom.o hndchipc.o
|
||||
+obj-y += sflash.o
|
||||
obj-$(CONFIG_PCI) += sbpci.o pcibios.o
|
||||
obj-y += export.o
|
||||
|
||||
--- a/drivers/mtd/devices/Config.in
|
||||
+++ b/drivers/mtd/devices/Config.in
|
||||
@@ -5,6 +5,7 @@
|
||||
mainmenu_option next_comment
|
||||
|
||||
comment 'Self-contained MTD device drivers'
|
||||
+bool ' Broadcom Chipcommon Serial Flash support' CONFIG_MTD_SFLASH
|
||||
dep_tristate ' Ramix PMC551 PCI Mezzanine RAM card support' CONFIG_MTD_PMC551 $CONFIG_MTD $CONFIG_PCI
|
||||
if [ "$CONFIG_MTD_PMC551" = "y" -o "$CONFIG_MTD_PMC551" = "m" ]; then
|
||||
bool ' PMC551 256M DRAM Bugfix' CONFIG_MTD_PMC551_BUGFIX
|
||||
--- a/drivers/mtd/devices/Makefile
|
||||
+++ b/drivers/mtd/devices/Makefile
|
||||
@@ -3,6 +3,8 @@
|
||||
#
|
||||
# $Id: Makefile,v 1.4 2001/06/26 21:10:05 spse Exp $
|
||||
|
||||
+EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
|
||||
+
|
||||
O_TARGET := devlink.o
|
||||
|
||||
# *** BIG UGLY NOTE ***
|
||||
@@ -12,6 +14,7 @@ O_TARGET := devlink.o
|
||||
# here where previously there was none. We now have to ensure that
|
||||
# doc200[01].o are linked before docprobe.o
|
||||
|
||||
+obj-$(CONFIG_MTD_SFLASH) += sflash.o
|
||||
obj-$(CONFIG_MTD_DOC1000) += doc1000.o
|
||||
obj-$(CONFIG_MTD_DOC2000) += doc2000.o
|
||||
obj-$(CONFIG_MTD_DOC2001) += doc2001.o
|
||||
--- a/drivers/mtd/maps/Config.in
|
||||
+++ b/drivers/mtd/maps/Config.in
|
||||
@@ -48,6 +48,7 @@ if [ "$CONFIG_PPC" = "y" ]; then
|
||||
fi
|
||||
|
||||
if [ "$CONFIG_MIPS" = "y" ]; then
|
||||
+ dep_tristate ' CFI Flash device mapped on Broadcom BCM947XX boards' CONFIG_MTD_BCM947XX $CONFIG_MTD_CFI
|
||||
dep_tristate ' Pb1000 MTD support' CONFIG_MTD_PB1000 $CONFIG_MIPS_PB1000
|
||||
dep_tristate ' Pb1500 MTD support' CONFIG_MTD_PB1500 $CONFIG_MIPS_PB1500
|
||||
dep_tristate ' Pb1100 MTD support' CONFIG_MTD_PB1100 $CONFIG_MIPS_PB1100
|
||||
--- a/drivers/mtd/maps/Makefile
|
||||
+++ b/drivers/mtd/maps/Makefile
|
||||
@@ -3,6 +3,8 @@
|
||||
#
|
||||
# $Id: Makefile,v 1.37 2003/01/24 14:26:38 dwmw2 Exp $
|
||||
|
||||
+EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
|
||||
+
|
||||
BELOW25 := $(shell echo $(PATCHLEVEL) | sed s/[1234]/y/)
|
||||
|
||||
ifeq ($(BELOW25),y)
|
||||
@@ -10,6 +12,7 @@ O_TARGET := mapslink.o
|
||||
endif
|
||||
|
||||
# Chip mappings
|
||||
+obj-$(CONFIG_MTD_BCM947XX) += bcm947xx-flash.o
|
||||
obj-$(CONFIG_MTD_CDB89712) += cdb89712.o
|
||||
obj-$(CONFIG_MTD_ARM_INTEGRATOR)+= integrator-flash.o
|
||||
obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
--- a/drivers/bluetooth/hci_usb.c
|
||||
+++ b/drivers/bluetooth/hci_usb.c
|
||||
@@ -259,6 +259,9 @@ static int hci_usb_isoc_rx_submit(struct
|
||||
void *buf;
|
||||
|
||||
mtu = husb->isoc_in_ep->wMaxPacketSize;
|
||||
+#ifdef CONFIG_BCM4710
|
||||
+ mtu = (mtu + 1) & ~1; /* brcm: isoc buffers must be aligned on word boundary */
|
||||
+#endif
|
||||
size = mtu * HCI_MAX_ISOC_FRAMES;
|
||||
|
||||
buf = kmalloc(size, GFP_ATOMIC);
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
--- a/arch/mips/lib/ide-std.c
|
||||
+++ b/arch/mips/lib/ide-std.c
|
||||
@@ -31,12 +31,14 @@ static int std_ide_default_irq(ide_ioreg
|
||||
static ide_ioreg_t std_ide_default_io_base(int index)
|
||||
{
|
||||
switch (index) {
|
||||
+#if 0
|
||||
case 0: return 0x1f0;
|
||||
case 1: return 0x170;
|
||||
case 2: return 0x1e8;
|
||||
case 3: return 0x168;
|
||||
case 4: return 0x1e0;
|
||||
case 5: return 0x160;
|
||||
+#endif
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,580 +0,0 @@
|
|||
--- a/drivers/net/b44.c
|
||||
+++ b/drivers/net/b44.c
|
||||
@@ -1,7 +1,9 @@
|
||||
/* b44.c: Broadcom 4400 device driver.
|
||||
*
|
||||
* Copyright (C) 2002 David S. Miller (davem@redhat.com)
|
||||
- * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
|
||||
+ * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
|
||||
+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
|
||||
+ * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
|
||||
*
|
||||
* Distribute under GPL.
|
||||
*/
|
||||
@@ -25,6 +27,39 @@
|
||||
|
||||
#include "b44.h"
|
||||
|
||||
+#include <typedefs.h>
|
||||
+#include <bcmdevs.h>
|
||||
+#include <osl.h>
|
||||
+#include <bcmnvram.h>
|
||||
+#include <sbconfig.h>
|
||||
+#include <sbchipc.h>
|
||||
+#include <sflash.h>
|
||||
+
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
|
||||
+
|
||||
+static inline void e_aton(char *str, char *dest)
|
||||
+{
|
||||
+ int i = 0;
|
||||
+ u16 *d = (u16 *) dest;
|
||||
+
|
||||
+ if (str == NULL) {
|
||||
+ memset(dest, 0, 6);
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ for (;;) {
|
||||
+ dest[i++] = (char) simple_strtoul(str, NULL, 16);
|
||||
+ str += 2;
|
||||
+ if (!*str++ || i == 6)
|
||||
+ break;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static int instance = 0;
|
||||
+#endif
|
||||
+
|
||||
+
|
||||
#define DRV_MODULE_NAME "b44"
|
||||
#define PFX DRV_MODULE_NAME ": "
|
||||
#define DRV_MODULE_VERSION "0.93"
|
||||
@@ -75,7 +110,7 @@ static char version[] __devinitdata =
|
||||
DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
|
||||
|
||||
MODULE_AUTHOR("David S. Miller (davem@redhat.com)");
|
||||
-MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
|
||||
+MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_PARM(b44_debug, "i");
|
||||
MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
|
||||
@@ -89,6 +124,8 @@ static struct pci_device_id b44_pci_tbl[
|
||||
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
|
||||
{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
|
||||
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
|
||||
+ { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4713,
|
||||
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
|
||||
{ } /* terminate list with empty entry */
|
||||
};
|
||||
|
||||
@@ -113,11 +150,13 @@ static int b44_wait_bit(struct b44 *bp,
|
||||
udelay(10);
|
||||
}
|
||||
if (i == timeout) {
|
||||
+#ifdef DEBUG
|
||||
printk(KERN_ERR PFX "%s: BUG! Timeout waiting for bit %08x of register "
|
||||
"%lx to %s.\n",
|
||||
bp->dev->name,
|
||||
bit, reg,
|
||||
(clear ? "clear" : "set"));
|
||||
+#endif
|
||||
return -ENODEV;
|
||||
}
|
||||
return 0;
|
||||
@@ -236,6 +275,8 @@ static void ssb_core_reset(struct b44 *b
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
+static int b44_4713_instance;
|
||||
+
|
||||
static int ssb_core_unit(struct b44 *bp)
|
||||
{
|
||||
#if 0
|
||||
@@ -258,6 +299,9 @@ static int ssb_core_unit(struct b44 *bp)
|
||||
break;
|
||||
};
|
||||
#endif
|
||||
+ if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
|
||||
+ return b44_4713_instance++;
|
||||
+ else
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -267,6 +311,28 @@ static int ssb_is_core_up(struct b44 *bp
|
||||
== SBTMSLOW_CLOCK);
|
||||
}
|
||||
|
||||
+static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ bw32(B44_CAM_CTRL, (CAM_CTRL_READ |
|
||||
+ (index << CAM_CTRL_INDEX_SHIFT)));
|
||||
+
|
||||
+ b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
|
||||
+
|
||||
+ val = br32(B44_CAM_DATA_LO);
|
||||
+
|
||||
+ data[2] = (val >> 24) & 0xFF;
|
||||
+ data[3] = (val >> 16) & 0xFF;
|
||||
+ data[4] = (val >> 8) & 0xFF;
|
||||
+ data[5] = (val >> 0) & 0xFF;
|
||||
+
|
||||
+ val = br32(B44_CAM_DATA_HI);
|
||||
+
|
||||
+ data[0] = (val >> 8) & 0xFF;
|
||||
+ data[1] = (val >> 0) & 0xFF;
|
||||
+}
|
||||
+
|
||||
static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
|
||||
{
|
||||
u32 val;
|
||||
@@ -287,7 +353,7 @@ static void __b44_cam_write(struct b44 *
|
||||
|
||||
static inline void __b44_disable_ints(struct b44 *bp)
|
||||
{
|
||||
- bw32(B44_IMASK, 0);
|
||||
+ bw32(B44_IMASK, ISTAT_TO); /* leave the timeout interrupt active */
|
||||
}
|
||||
|
||||
static void b44_disable_ints(struct b44 *bp)
|
||||
@@ -303,14 +369,14 @@ static void b44_enable_ints(struct b44 *
|
||||
bw32(B44_IMASK, bp->imask);
|
||||
}
|
||||
|
||||
-static int b44_readphy(struct b44 *bp, int reg, u32 *val)
|
||||
+static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
|
||||
{
|
||||
int err;
|
||||
|
||||
bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
|
||||
bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
|
||||
(MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
|
||||
- (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
|
||||
+ (phy_addr << MDIO_DATA_PMD_SHIFT) |
|
||||
(reg << MDIO_DATA_RA_SHIFT) |
|
||||
(MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
|
||||
err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
|
||||
@@ -319,23 +385,42 @@ static int b44_readphy(struct b44 *bp, i
|
||||
return err;
|
||||
}
|
||||
|
||||
-static int b44_writephy(struct b44 *bp, int reg, u32 val)
|
||||
+static int b44_readphy(struct b44 *bp, int reg, u32 *val)
|
||||
+{
|
||||
+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
|
||||
+ return 0;
|
||||
+
|
||||
+ return __b44_readphy(bp, bp->phy_addr, reg, val);
|
||||
+}
|
||||
+
|
||||
+static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
|
||||
{
|
||||
bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
|
||||
bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
|
||||
(MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
|
||||
- (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
|
||||
+ (phy_addr << MDIO_DATA_PMD_SHIFT) |
|
||||
(reg << MDIO_DATA_RA_SHIFT) |
|
||||
(MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
|
||||
(val & MDIO_DATA_DATA)));
|
||||
return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
|
||||
}
|
||||
|
||||
+static int b44_writephy(struct b44 *bp, int reg, u32 val)
|
||||
+{
|
||||
+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
|
||||
+ return 0;
|
||||
+
|
||||
+ return __b44_writephy(bp, bp->phy_addr, reg, val);
|
||||
+}
|
||||
+
|
||||
static int b44_phy_reset(struct b44 *bp)
|
||||
{
|
||||
u32 val;
|
||||
int err;
|
||||
|
||||
+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
|
||||
+ return 0;
|
||||
+
|
||||
err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
|
||||
if (err)
|
||||
return err;
|
||||
@@ -406,6 +491,23 @@ static int b44_setup_phy(struct b44 *bp)
|
||||
u32 val;
|
||||
int err;
|
||||
|
||||
+
|
||||
+ /*
|
||||
+ * workaround for bad hardware design in Linksys WAP54G v1.0
|
||||
+ * see https://dev.openwrt.org/ticket/146
|
||||
+ * check and reset bit "isolate"
|
||||
+ */
|
||||
+ if ((bp->pdev->device == PCI_DEVICE_ID_BCM4713) &&
|
||||
+ (atoi(nvram_get("boardnum")) == 2) &&
|
||||
+ (__b44_readphy(bp, 0, MII_BMCR, &val) == 0) &&
|
||||
+ (val & BMCR_ISOLATE) &&
|
||||
+ (__b44_writephy(bp, 0, MII_BMCR, val & ~BMCR_ISOLATE) != 0)) {
|
||||
+ printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
|
||||
+ }
|
||||
+
|
||||
+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
|
||||
+ return 0;
|
||||
+
|
||||
if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
|
||||
goto out;
|
||||
if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
|
||||
@@ -498,6 +600,19 @@ static void b44_check_phy(struct b44 *bp
|
||||
{
|
||||
u32 bmsr, aux;
|
||||
|
||||
+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
|
||||
+ bp->flags |= B44_FLAG_100_BASE_T;
|
||||
+ bp->flags |= B44_FLAG_FULL_DUPLEX;
|
||||
+ if (!netif_carrier_ok(bp->dev)) {
|
||||
+ u32 val = br32(B44_TX_CTRL);
|
||||
+ val |= TX_CTRL_DUPLEX;
|
||||
+ bw32(B44_TX_CTRL, val);
|
||||
+ netif_carrier_on(bp->dev);
|
||||
+ b44_link_report(bp);
|
||||
+ }
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
|
||||
!b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
|
||||
(bmsr != 0xffff)) {
|
||||
@@ -765,6 +880,25 @@ static int b44_rx(struct b44 *bp, int bu
|
||||
return received;
|
||||
}
|
||||
|
||||
+
|
||||
+static inline void __b44_reset(struct b44 *bp)
|
||||
+{
|
||||
+ spin_lock_irq(&bp->lock);
|
||||
+ b44_halt(bp);
|
||||
+ b44_init_rings(bp);
|
||||
+ b44_init_hw(bp);
|
||||
+ spin_unlock_irq(&bp->lock);
|
||||
+
|
||||
+ b44_enable_ints(bp);
|
||||
+ netif_wake_queue(bp->dev);
|
||||
+}
|
||||
+
|
||||
+static inline void __b44_set_timeout(struct b44 *bp, int timeout)
|
||||
+{
|
||||
+ /* Set timeout for Rx to two seconds after the last Tx */
|
||||
+ bw32(B44_GPTIMER, timeout ? 2 * 125000000 : 0);
|
||||
+}
|
||||
+
|
||||
static int b44_poll(struct net_device *netdev, int *budget)
|
||||
{
|
||||
struct b44 *bp = netdev->priv;
|
||||
@@ -772,13 +906,13 @@ static int b44_poll(struct net_device *n
|
||||
|
||||
spin_lock_irq(&bp->lock);
|
||||
|
||||
- if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
|
||||
+ if (bp->istat & ISTAT_TX) {
|
||||
/* spin_lock(&bp->tx_lock); */
|
||||
b44_tx(bp);
|
||||
/* spin_unlock(&bp->tx_lock); */
|
||||
}
|
||||
spin_unlock_irq(&bp->lock);
|
||||
-
|
||||
+
|
||||
done = 1;
|
||||
if (bp->istat & ISTAT_RX) {
|
||||
int orig_budget = *budget;
|
||||
@@ -796,24 +930,18 @@ static int b44_poll(struct net_device *n
|
||||
done = 0;
|
||||
}
|
||||
|
||||
- if (bp->istat & ISTAT_ERRORS) {
|
||||
- spin_lock_irq(&bp->lock);
|
||||
- b44_halt(bp);
|
||||
- b44_init_rings(bp);
|
||||
- b44_init_hw(bp);
|
||||
- netif_wake_queue(bp->dev);
|
||||
- spin_unlock_irq(&bp->lock);
|
||||
- done = 1;
|
||||
- }
|
||||
-
|
||||
if (done) {
|
||||
netif_rx_complete(netdev);
|
||||
b44_enable_ints(bp);
|
||||
}
|
||||
|
||||
+ if ((bp->core_unit == 1) && (bp->istat & (ISTAT_TX | ISTAT_RX)))
|
||||
+ __b44_set_timeout(bp, (bp->istat & ISTAT_TX) ? 1 : 0);
|
||||
+
|
||||
return (done ? 0 : 1);
|
||||
}
|
||||
|
||||
+
|
||||
static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
||||
{
|
||||
struct net_device *dev = dev_id;
|
||||
@@ -832,6 +960,18 @@ static irqreturn_t b44_interrupt(int irq
|
||||
*/
|
||||
istat &= imask;
|
||||
if (istat) {
|
||||
+ /* Workaround for the WL-500g WAN port hang */
|
||||
+ if (istat & (ISTAT_TO | ISTAT_ERRORS)) {
|
||||
+ /*
|
||||
+ * no rx before the watchdog timeout
|
||||
+ * reset the interface
|
||||
+ */
|
||||
+ __b44_reset(bp);
|
||||
+ }
|
||||
+
|
||||
+ if ((bp->core_unit == 1) && (bp->istat & (ISTAT_TX | ISTAT_RX)))
|
||||
+ __b44_set_timeout(bp, (bp->istat & ISTAT_TX) ? 1 : 0);
|
||||
+
|
||||
handled = 1;
|
||||
if (netif_rx_schedule_prep(dev)) {
|
||||
/* NOTE: These writes are posted by the readback of
|
||||
@@ -848,6 +988,7 @@ static irqreturn_t b44_interrupt(int irq
|
||||
bw32(B44_ISTAT, istat);
|
||||
br32(B44_ISTAT);
|
||||
}
|
||||
+
|
||||
spin_unlock_irqrestore(&bp->lock, flags);
|
||||
return IRQ_RETVAL(handled);
|
||||
}
|
||||
@@ -859,16 +1000,7 @@ static void b44_tx_timeout(struct net_de
|
||||
printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
|
||||
dev->name);
|
||||
|
||||
- spin_lock_irq(&bp->lock);
|
||||
-
|
||||
- b44_halt(bp);
|
||||
- b44_init_rings(bp);
|
||||
- b44_init_hw(bp);
|
||||
-
|
||||
- spin_unlock_irq(&bp->lock);
|
||||
-
|
||||
- b44_enable_ints(bp);
|
||||
-
|
||||
+ __b44_reset(bp);
|
||||
netif_wake_queue(dev);
|
||||
}
|
||||
|
||||
@@ -1092,6 +1224,8 @@ static void b44_clear_stats(struct b44 *
|
||||
/* bp->lock is held. */
|
||||
static void b44_chip_reset(struct b44 *bp)
|
||||
{
|
||||
+ unsigned int sb_clock;
|
||||
+
|
||||
if (ssb_is_core_up(bp)) {
|
||||
bw32(B44_RCV_LAZY, 0);
|
||||
bw32(B44_ENET_CTRL, ENET_CTRL_DISABLE);
|
||||
@@ -1105,9 +1239,10 @@ static void b44_chip_reset(struct b44 *b
|
||||
bw32(B44_DMARX_CTRL, 0);
|
||||
bp->rx_prod = bp->rx_cons = 0;
|
||||
} else {
|
||||
- ssb_pci_setup(bp, (bp->core_unit == 0 ?
|
||||
- SBINTVEC_ENET0 :
|
||||
- SBINTVEC_ENET1));
|
||||
+ /*if (bp->pdev->device != PCI_DEVICE_ID_BCM4713)*/
|
||||
+ ssb_pci_setup(bp, (bp->core_unit == 0 ?
|
||||
+ SBINTVEC_ENET0 :
|
||||
+ SBINTVEC_ENET1));
|
||||
}
|
||||
|
||||
ssb_core_reset(bp);
|
||||
@@ -1115,6 +1250,11 @@ static void b44_chip_reset(struct b44 *b
|
||||
b44_clear_stats(bp);
|
||||
|
||||
/* Make PHY accessible. */
|
||||
+ if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
|
||||
+ sb_clock = 100000000; /* 100 MHz */
|
||||
+ else
|
||||
+ sb_clock = 62500000; /* 62.5 MHz */
|
||||
+
|
||||
bw32(B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
|
||||
(0x0d & MDIO_CTRL_MAXF_MASK)));
|
||||
br32(B44_MDIO_CTRL);
|
||||
@@ -1216,6 +1356,8 @@ static int b44_open(struct net_device *d
|
||||
struct b44 *bp = dev->priv;
|
||||
int err;
|
||||
|
||||
+ netif_carrier_off(dev);
|
||||
+
|
||||
err = b44_alloc_consistent(bp);
|
||||
if (err)
|
||||
return err;
|
||||
@@ -1236,9 +1378,10 @@ static int b44_open(struct net_device *d
|
||||
bp->timer.expires = jiffies + HZ;
|
||||
bp->timer.data = (unsigned long) bp;
|
||||
bp->timer.function = b44_timer;
|
||||
- add_timer(&bp->timer);
|
||||
+ b44_timer((unsigned long) bp);
|
||||
|
||||
b44_enable_ints(bp);
|
||||
+ netif_start_queue(dev);
|
||||
|
||||
return 0;
|
||||
|
||||
@@ -1638,7 +1781,7 @@ static int b44_ioctl(struct net_device *
|
||||
u32 mii_regval;
|
||||
|
||||
spin_lock_irq(&bp->lock);
|
||||
- err = b44_readphy(bp, data->reg_num & 0x1f, &mii_regval);
|
||||
+ err = __b44_readphy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
|
||||
spin_unlock_irq(&bp->lock);
|
||||
|
||||
data->val_out = mii_regval;
|
||||
@@ -1651,7 +1794,7 @@ static int b44_ioctl(struct net_device *
|
||||
return -EPERM;
|
||||
|
||||
spin_lock_irq(&bp->lock);
|
||||
- err = b44_writephy(bp, data->reg_num & 0x1f, data->val_in);
|
||||
+ err = __b44_writephy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
|
||||
spin_unlock_irq(&bp->lock);
|
||||
|
||||
return err;
|
||||
@@ -1678,21 +1821,52 @@ static int b44_read_eeprom(struct b44 *b
|
||||
static int __devinit b44_get_invariants(struct b44 *bp)
|
||||
{
|
||||
u8 eeprom[128];
|
||||
+ u8 buf[32];
|
||||
int err;
|
||||
+ unsigned long flags;
|
||||
|
||||
- err = b44_read_eeprom(bp, &eeprom[0]);
|
||||
- if (err)
|
||||
- goto out;
|
||||
-
|
||||
- bp->dev->dev_addr[0] = eeprom[79];
|
||||
- bp->dev->dev_addr[1] = eeprom[78];
|
||||
- bp->dev->dev_addr[2] = eeprom[81];
|
||||
- bp->dev->dev_addr[3] = eeprom[80];
|
||||
- bp->dev->dev_addr[4] = eeprom[83];
|
||||
- bp->dev->dev_addr[5] = eeprom[82];
|
||||
-
|
||||
- bp->phy_addr = eeprom[90] & 0x1f;
|
||||
- bp->mdc_port = (eeprom[90] >> 14) & 0x1;
|
||||
+ if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) {
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+ sprintf(buf, "et%dmacaddr", instance - 1);
|
||||
+ e_aton(nvram_get(buf), bp->dev->dev_addr);
|
||||
+
|
||||
+ sprintf(buf, "et%dphyaddr", instance - 1);
|
||||
+ bp->phy_addr = B44_PHY_ADDR_NO_PHY;
|
||||
+#else
|
||||
+ /*
|
||||
+ * BCM47xx boards don't have a EEPROM. The MAC is stored in
|
||||
+ * a NVRAM area somewhere in the flash memory. As we don't
|
||||
+ * know the location and/or the format of the NVRAM area
|
||||
+ * here, we simply rely on the bootloader to write the
|
||||
+ * MAC into the CAM.
|
||||
+ */
|
||||
+ spin_lock_irqsave(&bp->lock, flags);
|
||||
+ __b44_cam_read(bp, bp->dev->dev_addr, 0);
|
||||
+ spin_unlock_irqrestore(&bp->lock, flags);
|
||||
+
|
||||
+ /*
|
||||
+ * BCM47xx boards don't have a PHY. Usually there is a switch
|
||||
+ * chip with multiple PHYs connected to the PHY port.
|
||||
+ */
|
||||
+ bp->phy_addr = B44_PHY_ADDR_NO_PHY;
|
||||
+#endif
|
||||
+ bp->dma_offset = 0;
|
||||
+ } else {
|
||||
+ err = b44_read_eeprom(bp, &eeprom[0]);
|
||||
+ if (err)
|
||||
+ return err;
|
||||
+
|
||||
+ bp->dev->dev_addr[0] = eeprom[79];
|
||||
+ bp->dev->dev_addr[1] = eeprom[78];
|
||||
+ bp->dev->dev_addr[2] = eeprom[81];
|
||||
+ bp->dev->dev_addr[3] = eeprom[80];
|
||||
+ bp->dev->dev_addr[4] = eeprom[83];
|
||||
+ bp->dev->dev_addr[5] = eeprom[82];
|
||||
+
|
||||
+ bp->phy_addr = eeprom[90] & 0x1f;
|
||||
+ bp->dma_offset = SB_PCI_DMA;
|
||||
+ bp->mdc_port = (eeprom[90] >> 14) & 0x1;
|
||||
+ }
|
||||
|
||||
/* With this, plus the rx_header prepended to the data by the
|
||||
* hardware, we'll land the ethernet header on a 2-byte boundary.
|
||||
@@ -1702,13 +1876,12 @@ static int __devinit b44_get_invariants(
|
||||
bp->imask = IMASK_DEF;
|
||||
|
||||
bp->core_unit = ssb_core_unit(bp);
|
||||
- bp->dma_offset = ssb_get_addr(bp, SBID_PCI_DMA, 0);
|
||||
|
||||
/* XXX - really required?
|
||||
bp->flags |= B44_FLAG_BUGGY_TXPTR;
|
||||
*/
|
||||
-out:
|
||||
- return err;
|
||||
+
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
static int __devinit b44_init_one(struct pci_dev *pdev,
|
||||
@@ -1720,6 +1893,10 @@ static int __devinit b44_init_one(struct
|
||||
struct b44 *bp;
|
||||
int err, i;
|
||||
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+ instance++;
|
||||
+#endif
|
||||
+
|
||||
if (b44_version_printed++ == 0)
|
||||
printk(KERN_INFO "%s", version);
|
||||
|
||||
@@ -1834,11 +2011,17 @@ static int __devinit b44_init_one(struct
|
||||
*/
|
||||
b44_chip_reset(bp);
|
||||
|
||||
- printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
|
||||
+ printk(KERN_INFO "%s: Broadcom %s 10/100BaseT Ethernet ", dev->name,
|
||||
+ (pdev->device == PCI_DEVICE_ID_BCM4713) ? "47xx" : "4400");
|
||||
for (i = 0; i < 6; i++)
|
||||
printk("%2.2x%c", dev->dev_addr[i],
|
||||
i == 5 ? '\n' : ':');
|
||||
|
||||
+ /* Initialize phy */
|
||||
+ spin_lock_irq(&bp->lock);
|
||||
+ b44_chip_reset(bp);
|
||||
+ spin_unlock_irq(&bp->lock);
|
||||
+
|
||||
return 0;
|
||||
|
||||
err_out_iounmap:
|
||||
--- a/drivers/net/b44.h
|
||||
+++ b/drivers/net/b44.h
|
||||
@@ -229,8 +229,6 @@
|
||||
#define SBIPSFLAG_IMASK4 0x3f000000 /* Which sbflags --> mips interrupt 4 */
|
||||
#define SBIPSFLAG_ISHIFT4 24
|
||||
#define B44_SBTPSFLAG 0x0F18UL /* SB Target Port OCP Slave Flag */
|
||||
-#define SBTPS_NUM0_MASK 0x0000003f
|
||||
-#define SBTPS_F0EN0 0x00000040
|
||||
#define B44_SBADMATCH3 0x0F60UL /* SB Address Match 3 */
|
||||
#define B44_SBADMATCH2 0x0F68UL /* SB Address Match 2 */
|
||||
#define B44_SBADMATCH1 0x0F70UL /* SB Address Match 1 */
|
||||
@@ -461,6 +459,8 @@ struct ring_info {
|
||||
};
|
||||
|
||||
#define B44_MCAST_TABLE_SIZE 32
|
||||
+#define B44_PHY_ADDR_NO_PHY 30
|
||||
+#define B44_MDC_RATIO 5000000
|
||||
|
||||
/* SW copy of device statistics, kept up to date by periodic timer
|
||||
* which probes HW values. Must have same relative layout as HW
|
||||
--- a/include/linux/pci_ids.h
|
||||
+++ b/include/linux/pci_ids.h
|
||||
@@ -1765,6 +1765,7 @@
|
||||
#define PCI_DEVICE_ID_TIGON3_5901_2 0x170e
|
||||
#define PCI_DEVICE_ID_BCM4401 0x4401
|
||||
#define PCI_DEVICE_ID_BCM4401B0 0x4402
|
||||
+#define PCI_DEVICE_ID_BCM4713 0x4713
|
||||
|
||||
#define PCI_VENDOR_ID_ENE 0x1524
|
||||
#define PCI_DEVICE_ID_ENE_1211 0x1211
|
||||
|
|
@ -1,84 +0,0 @@
|
|||
--- a/drivers/pcmcia/yenta.c
|
||||
+++ b/drivers/pcmcia/yenta.c
|
||||
@@ -543,6 +543,9 @@ static unsigned int yenta_probe_irq(pci_
|
||||
* Probe for usable interrupts using the force
|
||||
* register to generate bogus card status events.
|
||||
*/
|
||||
+
|
||||
+#ifndef CONFIG_BCM947XX
|
||||
+ /* WRT54G3G does not like this */
|
||||
cb_writel(socket, CB_SOCKET_EVENT, -1);
|
||||
cb_writel(socket, CB_SOCKET_MASK, CB_CSTSMASK);
|
||||
exca_writeb(socket, I365_CSCINT, 0);
|
||||
@@ -557,7 +560,8 @@ static unsigned int yenta_probe_irq(pci_
|
||||
}
|
||||
cb_writel(socket, CB_SOCKET_MASK, 0);
|
||||
exca_writeb(socket, I365_CSCINT, 0);
|
||||
-
|
||||
+#endif
|
||||
+
|
||||
mask = probe_irq_mask(val) & 0xffff;
|
||||
|
||||
bridge_ctrl &= ~CB_BRIDGE_INTR;
|
||||
@@ -578,6 +582,12 @@ static void yenta_get_socket_capabilitie
|
||||
socket->cap.cb_dev = socket->dev;
|
||||
socket->cap.bus = NULL;
|
||||
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+ /* irq mask probing is broken for the WRT54G3G */
|
||||
+ if (socket->cap.irq_mask == 0)
|
||||
+ socket->cap.irq_mask = 0x6f8;
|
||||
+#endif
|
||||
+
|
||||
printk(KERN_INFO "Yenta ISA IRQ mask 0x%04x, PCI irq %d\n",
|
||||
socket->cap.irq_mask, socket->cb_irq);
|
||||
}
|
||||
@@ -609,6 +619,15 @@ static void yenta_open_bh(void * data)
|
||||
printk(KERN_INFO "Socket status: %08x\n",
|
||||
cb_readl(socket, CB_SOCKET_STATE));
|
||||
|
||||
+ /* Generate an interrupt on card insert/remove */
|
||||
+ config_writew(socket, CB_SOCKET_MASK, CB_CSTSMASK | CB_CDMASK);
|
||||
+
|
||||
+ /* Set up Multifunction Routing Status Register */
|
||||
+ config_writew(socket, 0x8C, 0x1000 /* MFUNC3 to GPIO3 */ | 0x2 /* MFUNC0 to INTA */);
|
||||
+
|
||||
+ /* Switch interrupts to parallelized */
|
||||
+ config_writeb(socket, 0x92, 0x64);
|
||||
+
|
||||
/* Register it with the pcmcia layer.. */
|
||||
cardbus_register(socket);
|
||||
|
||||
@@ -731,7 +750,7 @@ static void yenta_allocate_res(pci_socke
|
||||
{
|
||||
struct pci_bus *bus;
|
||||
struct resource *root, *res;
|
||||
- u32 start, end;
|
||||
+ u32 start = 0, end = 0;
|
||||
u32 align, size, min, max;
|
||||
unsigned offset;
|
||||
unsigned mask;
|
||||
@@ -750,6 +769,15 @@ static void yenta_allocate_res(pci_socke
|
||||
res->end = 0;
|
||||
root = pci_find_parent_resource(socket->dev, res);
|
||||
|
||||
+#ifdef CONFIG_BCM947XX
|
||||
+ /* default mem resources are completely fscked up on the wrt54g3g */
|
||||
+ /* bypass the entire resource allocation stuff below and just set it statically */
|
||||
+ if (type & IORESOURCE_MEM) {
|
||||
+ res->start = 0x40004000;
|
||||
+ res->end = res->start + 0x3fff;
|
||||
+ }
|
||||
+
|
||||
+#else
|
||||
if (!root)
|
||||
return;
|
||||
|
||||
@@ -794,6 +822,7 @@ static void yenta_allocate_res(pci_socke
|
||||
res->start = res->end = 0;
|
||||
return;
|
||||
}
|
||||
+#endif
|
||||
|
||||
config_writel(socket, offset, res->start);
|
||||
config_writel(socket, offset+4, res->end);
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
--- a/drivers/net/b44.h
|
||||
+++ b/drivers/net/b44.h
|
||||
@@ -122,6 +122,7 @@
|
||||
#define RXCONFIG_FLOW 0x00000020 /* Flow Control Enable */
|
||||
#define RXCONFIG_FLOW_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */
|
||||
#define RXCONFIG_RFILT 0x00000080 /* Reject Filter */
|
||||
+#define RXCONFIG_CAM_ABSENT 0x00000100 /* CAM Absent */
|
||||
#define B44_RXMAXLEN 0x0404UL /* EMAC RX Max Packet Length */
|
||||
#define B44_TXMAXLEN 0x0408UL /* EMAC TX Max Packet Length */
|
||||
#define B44_MDIO_CTRL 0x0410UL /* EMAC MDIO Control */
|
||||
--- a/drivers/net/b44.c
|
||||
+++ b/drivers/net/b44.c
|
||||
@@ -1299,6 +1299,7 @@ static int b44_set_mac_addr(struct net_d
|
||||
{
|
||||
struct b44 *bp = dev->priv;
|
||||
struct sockaddr *addr = p;
|
||||
+ u32 val;
|
||||
|
||||
if (netif_running(dev))
|
||||
return -EBUSY;
|
||||
@@ -1306,7 +1307,11 @@ static int b44_set_mac_addr(struct net_d
|
||||
memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
|
||||
|
||||
spin_lock_irq(&bp->lock);
|
||||
- __b44_set_mac_addr(bp);
|
||||
+
|
||||
+ val = br32(B44_RXCONFIG);
|
||||
+ if (!(val & RXCONFIG_CAM_ABSENT))
|
||||
+ __b44_set_mac_addr(bp);
|
||||
+
|
||||
spin_unlock_irq(&bp->lock);
|
||||
|
||||
return 0;
|
||||
@@ -1493,7 +1498,7 @@ static void __b44_set_rx_mode(struct net
|
||||
|
||||
val = br32(B44_RXCONFIG);
|
||||
val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
|
||||
- if (dev->flags & IFF_PROMISC) {
|
||||
+ if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
|
||||
val |= RXCONFIG_PROMISC;
|
||||
bw32(B44_RXCONFIG, val);
|
||||
} else {
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
--- a/net/sched/sch_generic.c
|
||||
+++ b/net/sched/sch_generic.c
|
||||
@@ -84,6 +84,11 @@ int qdisc_restart(struct net_device *dev
|
||||
struct sk_buff *skb;
|
||||
|
||||
/* Dequeue packet */
|
||||
+ if (!q) {
|
||||
+ if (net_ratelimit())
|
||||
+ printk(KERN_DEBUG "HELP ME! qdisc_restart called, but no Qdisc!\n");
|
||||
+ return 0;
|
||||
+ }
|
||||
if ((skb = q->dequeue(q)) != NULL) {
|
||||
if (spin_trylock(&dev->xmit_lock)) {
|
||||
/* Remember that the driver is grabbed by us. */
|
||||
|
|
@ -1,100 +0,0 @@
|
|||
--- a/drivers/ide/pci/aec62xx.c
|
||||
+++ b/drivers/ide/pci/aec62xx.c
|
||||
@@ -3,6 +3,8 @@
|
||||
*
|
||||
* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
|
||||
*
|
||||
+ * With Broadcom 4780 patches
|
||||
+ *
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
@@ -329,7 +331,11 @@ static int aec62xx_config_drive_xfer_rat
|
||||
ide_hwif_t *hwif = HWIF(drive);
|
||||
struct hd_driveid *id = drive->id;
|
||||
|
||||
+#ifndef CONFIG_BCM947XX
|
||||
if ((id->capability & 1) && drive->autodma) {
|
||||
+#else
|
||||
+ if (1) {
|
||||
+#endif
|
||||
/* Consult the list of known "bad" drives */
|
||||
if (hwif->ide_dma_bad_drive(drive))
|
||||
goto fast_ata_pio;
|
||||
@@ -414,10 +420,60 @@ static unsigned int __init init_chipset_
|
||||
{
|
||||
int bus_speed = system_bus_clock();
|
||||
|
||||
+#ifndef CONFIG_BCM947XX
|
||||
if (dev->resource[PCI_ROM_RESOURCE].start) {
|
||||
pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
|
||||
printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
|
||||
}
|
||||
+#else
|
||||
+ if (dev->resource[PCI_ROM_RESOURCE].start) {
|
||||
+ pci_write_config_dword(dev, PCI_ROM_ADDRESS,
|
||||
+ dev->resource[PCI_ROM_RESOURCE].
|
||||
+ start | PCI_ROM_ADDRESS_ENABLE);
|
||||
+ } else {
|
||||
+ pci_write_config_dword(dev, PCI_ROM_ADDRESS,
|
||||
+ dev->resource[PCI_ROM_RESOURCE].
|
||||
+ start);
|
||||
+ }
|
||||
+
|
||||
+ /* Set IDE controller parameters manually - FIXME: replace magic values */
|
||||
+ {
|
||||
+ byte setting;
|
||||
+
|
||||
+ pci_write_config_word(dev, PCI_COMMAND, 0x0007);
|
||||
+ //pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x5A);
|
||||
+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x13);
|
||||
+
|
||||
+ pci_write_config_byte(dev, 0x40, 0x31);
|
||||
+ pci_write_config_byte(dev, 0x41, 0x31);
|
||||
+ pci_write_config_byte(dev, 0x42, 0x31);
|
||||
+ pci_write_config_byte(dev, 0x43, 0x31);
|
||||
+ // Set IDE Command Speed
|
||||
+ pci_write_config_byte(dev, 0x48, 0x31);
|
||||
+
|
||||
+ // Disable WriteSubSysID & PIOROM
|
||||
+ pci_read_config_byte(dev, 0x49, &setting);
|
||||
+ setting &= 0x07;
|
||||
+ pci_write_config_byte(dev, 0x49, setting);
|
||||
+
|
||||
+ // Enable PCI burst & INTA & PCI memory read multiple, FIFO threshold=80
|
||||
+ pci_read_config_byte(dev, 0x4A, &setting);
|
||||
+ //setting = (setting & 0xFE) | 0xA8;
|
||||
+ setting = (setting & 0xFE) | 0xD8;
|
||||
+ setting = (setting & 0xF7);
|
||||
+ pci_write_config_byte(dev, 0x4A, setting);
|
||||
+
|
||||
+ //pci_write_config_byte(dev, 0x4B, 0x20);
|
||||
+ pci_write_config_byte(dev, 0x4B, 0x2C);
|
||||
+ //pci_write_config_byte(dev, 0x4B, 0x0C);
|
||||
+
|
||||
+ // Set PreRead count: 512 byte
|
||||
+ pci_write_config_byte(dev, 0x4C, 0);
|
||||
+ pci_write_config_word(dev, 0x4D, 0x0002);
|
||||
+ pci_write_config_byte(dev, 0x54, 0);
|
||||
+ pci_write_config_word(dev, 0x55, 0x0002);
|
||||
+ }
|
||||
+#endif
|
||||
|
||||
#if defined(DISPLAY_AEC62XX_TIMINGS) && defined(CONFIG_PROC_FS)
|
||||
aec_devs[n_aec_devs++] = dev;
|
||||
@@ -500,6 +556,7 @@ static void __init init_setup_aec62xx (s
|
||||
|
||||
static void __init init_setup_aec6x80 (struct pci_dev *dev, ide_pci_device_t *d)
|
||||
{
|
||||
+#ifndef CONFIG_BCM947XX /* Causes OOPS on BCM4780 */
|
||||
unsigned long bar4reg = pci_resource_start(dev, 4);
|
||||
|
||||
if (inb(bar4reg+2) & 0x10) {
|
||||
@@ -512,6 +569,7 @@ static void __init init_setup_aec6x80 (s
|
||||
strcpy(d->name, "AEC6280R");
|
||||
}
|
||||
|
||||
+#endif
|
||||
ide_setup_pci_device(dev, d);
|
||||
}
|
||||
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
--- a/drivers/ide/pci/pdc202xx_old.c
|
||||
+++ b/drivers/ide/pci/pdc202xx_old.c
|
||||
@@ -253,23 +253,23 @@ static int pdc202xx_tune_chipset (ide_dr
|
||||
pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
|
||||
|
||||
if (speed < XFER_SW_DMA_0) {
|
||||
- if ((AP & 0x0F) || (BP & 0x07)) {
|
||||
+ if ((AP & 0x0F) || (BP & 0x17)) {
|
||||
/* clear PIO modes of lower 8421 bits of A Register */
|
||||
pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
|
||||
pci_read_config_byte(dev, (drive_pci), &AP);
|
||||
|
||||
/* clear PIO modes of lower 421 bits of B Register */
|
||||
- pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
|
||||
+ pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x17);
|
||||
pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
|
||||
|
||||
pci_read_config_byte(dev, (drive_pci), &AP);
|
||||
pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
|
||||
}
|
||||
} else {
|
||||
- if ((BP & 0xF0) && (CP & 0x0F)) {
|
||||
+ if ((BP & 0xE0) && (CP & 0x0F)) {
|
||||
/* clear DMA modes of upper 842 bits of B Register */
|
||||
/* clear PIO forced mode upper 1 bit of B Register */
|
||||
- pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
|
||||
+ pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xE0);
|
||||
pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
|
||||
|
||||
/* clear DMA modes of lower 8421 bits of C Register */
|
||||
@@ -373,6 +373,9 @@ static int config_chipset_for_dma (ide_d
|
||||
u8 ultra_66 = ((id->dma_ultra & 0x0010) ||
|
||||
(id->dma_ultra & 0x0008)) ? 1 : 0;
|
||||
|
||||
+ if (hwif->rqsize != 256)
|
||||
+ hwif->rqsize = 256;
|
||||
+
|
||||
switch(dev->device) {
|
||||
case PCI_DEVICE_ID_PROMISE_20267:
|
||||
case PCI_DEVICE_ID_PROMISE_20265:
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,20 +0,0 @@
|
|||
--- a/drivers/usb/serial/Config.in
|
||||
+++ b/drivers/usb/serial/Config.in
|
||||
@@ -39,6 +39,7 @@ if [ "$CONFIG_USB_SERIAL" != "n" ]; then
|
||||
dep_tristate ' USB KOBIL chipcard reader (EXPERIMENTAL)' CONFIG_USB_SERIAL_KOBIL_SCT $CONFIG_USB_SERIAL $CONFIG_EXPERIMENTAL
|
||||
dep_tristate ' USB Prolific 2303 Single Port Serial Driver' CONFIG_USB_SERIAL_PL2303 $CONFIG_USB_SERIAL
|
||||
dep_tristate ' USB REINER SCT cyberJack pinpad/e-com chipcard reader (EXPERIMENTAL)' CONFIG_USB_SERIAL_CYBERJACK $CONFIG_USB_SERIAL $CONFIG_EXPERIMENTAL
|
||||
+ dep_tristate ' USB Sierra Wireless Driver' CONFIG_USB_SERIAL_SIERRAWIRELESS $CONFIG_USB_SERIAL
|
||||
dep_tristate ' USB Xircom / Entregra Single Port Serial Driver (EXPERIMENTAL)' CONFIG_USB_SERIAL_XIRCOM $CONFIG_USB_SERIAL $CONFIG_EXPERIMENTAL
|
||||
dep_tristate ' USB ZyXEL omni.net LCD Plus Driver (EXPERIMENTAL)' CONFIG_USB_SERIAL_OMNINET $CONFIG_USB_SERIAL $CONFIG_EXPERIMENTAL
|
||||
fi
|
||||
--- a/drivers/usb/serial/Makefile
|
||||
+++ b/drivers/usb/serial/Makefile
|
||||
@@ -26,6 +26,7 @@ obj-$(CONFIG_USB_SERIAL_CYBERJACK) += c
|
||||
obj-$(CONFIG_USB_SERIAL_IR) += ir-usb.o
|
||||
obj-$(CONFIG_USB_SERIAL_KLSI) += kl5kusb105.o
|
||||
obj-$(CONFIG_USB_SERIAL_KOBIL_SCT) += kobil_sct.o
|
||||
+obj-$(CONFIG_USB_SERIAL_SIERRAWIRELESS) += sierra.o
|
||||
|
||||
# Objects that export symbols.
|
||||
export-objs := usbserial.o
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
--- a/arch/mips/mm/c-r4k.c
|
||||
+++ b/arch/mips/mm/c-r4k.c
|
||||
@@ -325,7 +325,7 @@ static void r4k_flush_cache_mm(struct mm
|
||||
r4k_blast_scache();
|
||||
}
|
||||
|
||||
-static void r4k_flush_cache_page(struct vm_area_struct *vma,
|
||||
+void r4k_flush_cache_page(struct vm_area_struct *vma,
|
||||
unsigned long page)
|
||||
{
|
||||
int exec = vma->vm_flags & VM_EXEC;
|
||||
@@ -385,6 +385,7 @@ static void r4k_flush_cache_page(struct
|
||||
r4k_blast_icache_page_indexed(page);
|
||||
}
|
||||
}
|
||||
+EXPORT_SYMBOL(r4k_flush_cache_page);
|
||||
|
||||
static void r4k_flush_data_cache_page(unsigned long addr)
|
||||
{
|
||||
--- a/arch/mips/mm/Makefile
|
||||
+++ b/arch/mips/mm/Makefile
|
||||
@@ -11,7 +11,7 @@ USE_STANDARD_AS_RULE := true
|
||||
O_TARGET := mm.o
|
||||
|
||||
export-objs := cache.o ioremap.o loadmmu.o remap.o \
|
||||
- tlb-r4k.o tlb-sb1.o
|
||||
+ tlb-r4k.o tlb-sb1.o c-r4k.o
|
||||
obj-y += cache.o extable.o init.o ioremap.o fault.o \
|
||||
loadmmu.o
|
||||
|
||||
|
|
@ -1,66 +0,0 @@
|
|||
--- a/include/linux/netdevice.h
|
||||
+++ b/include/linux/netdevice.h
|
||||
@@ -445,16 +445,12 @@ struct net_device
|
||||
/* bridge stuff */
|
||||
struct net_bridge_port *br_port;
|
||||
|
||||
-#ifdef CONFIG_NET_FASTROUTE
|
||||
#define NETDEV_FASTROUTE_HMASK 0xF
|
||||
/* Semi-private data. Keep it at the end of device struct. */
|
||||
rwlock_t fastpath_lock;
|
||||
struct dst_entry *fastpath[NETDEV_FASTROUTE_HMASK+1];
|
||||
-#endif
|
||||
-#ifdef CONFIG_NET_DIVERT
|
||||
/* this will get initialized at each interface type init routine */
|
||||
struct divert_blk *divert;
|
||||
-#endif /* CONFIG_NET_DIVERT */
|
||||
};
|
||||
|
||||
/* 2.6 compatibility */
|
||||
--- a/include/linux/skbuff.h
|
||||
+++ b/include/linux/skbuff.h
|
||||
@@ -83,7 +83,6 @@
|
||||
#define NET_CALLER(arg) __builtin_return_address(0)
|
||||
#endif
|
||||
|
||||
-#ifdef CONFIG_NETFILTER
|
||||
struct nf_conntrack {
|
||||
atomic_t use;
|
||||
void (*destroy)(struct nf_conntrack *);
|
||||
@@ -92,7 +91,6 @@ struct nf_conntrack {
|
||||
struct nf_ct_info {
|
||||
struct nf_conntrack *master;
|
||||
};
|
||||
-#endif
|
||||
#if defined(CONFIG_IMQ) || defined(CONFIG_IMQ_MODULE)
|
||||
struct nf_info;
|
||||
#endif
|
||||
@@ -201,7 +199,6 @@ struct sk_buff {
|
||||
unsigned char *end; /* End pointer */
|
||||
|
||||
void (*destructor)(struct sk_buff *); /* Destruct function */
|
||||
-#ifdef CONFIG_NETFILTER
|
||||
/* Can be used for communication between hooks. */
|
||||
unsigned long nfmark;
|
||||
/* Cache info */
|
||||
@@ -211,7 +208,6 @@ struct sk_buff {
|
||||
#ifdef CONFIG_NETFILTER_DEBUG
|
||||
unsigned int nf_debug;
|
||||
#endif
|
||||
-#endif /*CONFIG_NETFILTER*/
|
||||
|
||||
#if defined(CONFIG_HIPPI)
|
||||
union{
|
||||
@@ -219,12 +215,8 @@ struct sk_buff {
|
||||
} private;
|
||||
#endif
|
||||
|
||||
-#ifdef CONFIG_NET_SCHED
|
||||
__u32 tc_index; /* traffic control index */
|
||||
-#endif
|
||||
-#if defined(CONFIG_IMQ) || defined(CONFIG_IMQ_MODULE)
|
||||
struct nf_info *nf_info;
|
||||
-#endif
|
||||
};
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
|
@ -1,103 +0,0 @@
|
|||
--- a/drivers/net/b44.c
|
||||
+++ b/drivers/net/b44.c
|
||||
@@ -101,7 +101,8 @@ static int instance = 0;
|
||||
(BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
|
||||
#define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
|
||||
|
||||
-#define RX_PKT_BUF_SZ (1536 + bp->rx_offset + 64)
|
||||
+#define RX_HEADER_OFS (RX_HEADER_LEN + 2)
|
||||
+#define RX_PKT_BUF_SZ (1536 + RX_HEADER_OFS)
|
||||
|
||||
/* minimum number of free TX descriptors required to wake up TX process */
|
||||
#define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
|
||||
@@ -734,10 +735,8 @@ static int b44_alloc_rx_skb(struct b44 *
|
||||
mapping = pci_map_single(bp->pdev, skb->data,
|
||||
RX_PKT_BUF_SZ,
|
||||
PCI_DMA_FROMDEVICE);
|
||||
- skb_reserve(skb, bp->rx_offset);
|
||||
|
||||
- rh = (struct rx_header *)
|
||||
- (skb->data - bp->rx_offset);
|
||||
+ rh = (struct rx_header *) skb->data;
|
||||
rh->len = 0;
|
||||
rh->flags = 0;
|
||||
|
||||
@@ -747,13 +746,13 @@ static int b44_alloc_rx_skb(struct b44 *
|
||||
if (src_map != NULL)
|
||||
src_map->skb = NULL;
|
||||
|
||||
- ctrl = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - bp->rx_offset));
|
||||
+ ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ);
|
||||
if (dest_idx == (B44_RX_RING_SIZE - 1))
|
||||
ctrl |= DESC_CTRL_EOT;
|
||||
|
||||
dp = &bp->rx_ring[dest_idx];
|
||||
dp->ctrl = cpu_to_le32(ctrl);
|
||||
- dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset);
|
||||
+ dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset);
|
||||
|
||||
return RX_PKT_BUF_SZ;
|
||||
}
|
||||
@@ -812,7 +811,7 @@ static int b44_rx(struct b44 *bp, int bu
|
||||
PCI_DMA_FROMDEVICE);
|
||||
rh = (struct rx_header *) skb->data;
|
||||
len = cpu_to_le16(rh->len);
|
||||
- if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) ||
|
||||
+ if ((len > (RX_PKT_BUF_SZ - RX_HEADER_OFS)) ||
|
||||
(rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
|
||||
drop_it:
|
||||
b44_recycle_rx(bp, cons, bp->rx_prod);
|
||||
@@ -844,8 +843,8 @@ static int b44_rx(struct b44 *bp, int bu
|
||||
pci_unmap_single(bp->pdev, map,
|
||||
skb_size, PCI_DMA_FROMDEVICE);
|
||||
/* Leave out rx_header */
|
||||
- skb_put(skb, len+bp->rx_offset);
|
||||
- skb_pull(skb,bp->rx_offset);
|
||||
+ skb_put(skb, len+RX_HEADER_OFS);
|
||||
+ skb_pull(skb,RX_HEADER_OFS);
|
||||
} else {
|
||||
struct sk_buff *copy_skb;
|
||||
|
||||
@@ -858,7 +857,7 @@ static int b44_rx(struct b44 *bp, int bu
|
||||
skb_reserve(copy_skb, 2);
|
||||
skb_put(copy_skb, len);
|
||||
/* DMA sync done above, copy just the actual packet */
|
||||
- memcpy(copy_skb->data, skb->data+bp->rx_offset, len);
|
||||
+ memcpy(copy_skb->data, skb->data+RX_HEADER_OFS, len);
|
||||
|
||||
skb = copy_skb;
|
||||
}
|
||||
@@ -1344,7 +1343,7 @@ static void b44_init_hw(struct b44 *bp)
|
||||
bw32(B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
|
||||
bw32(B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
|
||||
bw32(B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
|
||||
- (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
|
||||
+ (RX_HEADER_OFS << DMARX_CTRL_ROSHIFT)));
|
||||
bw32(B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
|
||||
|
||||
bw32(B44_DMARX_PTR, bp->rx_pending);
|
||||
@@ -1873,13 +1872,7 @@ static int __devinit b44_get_invariants(
|
||||
bp->mdc_port = (eeprom[90] >> 14) & 0x1;
|
||||
}
|
||||
|
||||
- /* With this, plus the rx_header prepended to the data by the
|
||||
- * hardware, we'll land the ethernet header on a 2-byte boundary.
|
||||
- */
|
||||
- bp->rx_offset = 30;
|
||||
-
|
||||
bp->imask = IMASK_DEF;
|
||||
-
|
||||
bp->core_unit = ssb_core_unit(bp);
|
||||
|
||||
/* XXX - really required?
|
||||
--- a/drivers/net/b44.h
|
||||
+++ b/drivers/net/b44.h
|
||||
@@ -518,8 +518,6 @@ struct b44 {
|
||||
#define B44_FLAG_ADV_100FULL 0x08000000
|
||||
#define B44_FLAG_INTERNAL_PHY 0x10000000
|
||||
|
||||
- u32 rx_offset;
|
||||
-
|
||||
u32 msg_enable;
|
||||
|
||||
struct timer_list timer;
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
--- a/net/ipv4/udp.c 2009-12-26 00:06:59.000000000 +0100
|
||||
+++ b/net/ipv4/udp.c 2009-12-27 00:27:05.003012266 +0100
|
||||
@@ -711,7 +711,14 @@
|
||||
skb = skb_recv_datagram(sk, flags, noblock, &err);
|
||||
if (!skb)
|
||||
goto out;
|
||||
-
|
||||
+
|
||||
+ if (skb->nh.iph->version != 4) {
|
||||
+ skb_free_datagram(sk, skb);
|
||||
+ if (noblock)
|
||||
+ return -EAGAIN;
|
||||
+ goto try_again;
|
||||
+ }
|
||||
+
|
||||
copied = skb->len - sizeof(struct udphdr);
|
||||
if (copied > len) {
|
||||
copied = len;
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
#
|
||||
# Copyright (C) 2006 OpenWrt.org
|
||||
#
|
||||
# This is free software, licensed under the GNU General Public License v2.
|
||||
# See /LICENSE for more information.
|
||||
#
|
||||
|
||||
define Profile/Broadcom
|
||||
NAME:=Generic, Broadcom WiFi (default)
|
||||
PACKAGES:=kmod-brcm-wl-old wlc-old nas-old kmod-wlcompat
|
||||
endef
|
||||
|
||||
define Profile/Broadcom/Description
|
||||
Default package set compatible with most BCM947xx hardware
|
||||
endef
|
||||
$(eval $(call Profile,Broadcom))
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue