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ar71xx: fix ath79_soc_rev value for QCA9531 ver. 2 

ath9k expects to get revision id 2 for the QCA9531 ver. 2 rev. 0. This
fixes the very low TX power on some devices like the TP-LINK
TL-WR841ND v10.

As ath79_soc_rev is only used to get the revision number to ath9k on the
QCA9533, just set it to the expected value on the ver. 2.

Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
Tested-by: Felix Kaechele <felix@kaechele.ca>

SVN-Revision: 47262
owl
John Crispin 2015-10-26 09:01:34 +00:00
parent 632c92094a
commit c9426352ce
2 changed files with 22 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
target/linux/ar71xx/patches-4.1/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
View File

@ -413,12 +413,13 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID); id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
major = id & REV_ID_MAJOR_MASK; major = id & REV_ID_MAJOR_MASK;
@@ -152,6 +153,16 @@ static void __init ath79_detect_sys_type @@ -152,6 +153,17 @@ static void __init ath79_detect_sys_type
rev = id & AR934X_REV_ID_REVISION_MASK; rev = id & AR934X_REV_ID_REVISION_MASK;
break; break;
+ case REV_ID_MAJOR_QCA9533_V2: + case REV_ID_MAJOR_QCA9533_V2:
+ ver = 2; + ver = 2;
+ ath79_soc_rev = 2;
+ /* drop through */ + /* drop through */
+ +
+ case REV_ID_MAJOR_QCA9533: + case REV_ID_MAJOR_QCA9533:
@ -430,15 +431,23 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
case REV_ID_MAJOR_QCA9556: case REV_ID_MAJOR_QCA9556:
ath79_soc = ATH79_SOC_QCA9556; ath79_soc = ATH79_SOC_QCA9556;
chip = "9556"; chip = "9556";
@@ -170,7 +181,7 @@ static void __init ath79_detect_sys_type @@ -168,11 +180,12 @@ static void __init ath79_detect_sys_type
panic("ath79: unknown SoC, id:0x%08x", id);
}
ath79_soc_rev = rev; - ath79_soc_rev = rev;
+ if (ver == 1)
+ ath79_soc_rev = rev;
- if (soc_is_qca955x()) - if (soc_is_qca955x())
- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
- chip, rev);
+ if (soc_is_qca953x() || soc_is_qca955x()) + if (soc_is_qca953x() || soc_is_qca955x())
sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", + sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
chip, rev); + chip, ver, rev);
else else
sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
pr_info("SoC: %s\n", ath79_sys_type);
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -105,6 +105,21 @@ @@ -105,6 +105,21 @@

15
target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
View File

@ -452,7 +452,7 @@
return -ENODEV; return -ENODEV;
--- a/arch/mips/ath79/setup.c --- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c
@@ -175,14 +175,29 @@ static void __init ath79_detect_sys_type @@ -176,6 +176,18 @@ static void __init ath79_detect_sys_type
rev = id & QCA955X_REV_ID_REVISION_MASK; rev = id & QCA955X_REV_ID_REVISION_MASK;
break; break;
@ -471,19 +471,20 @@
default: default:
panic("ath79: unknown SoC, id:0x%08x", id); panic("ath79: unknown SoC, id:0x%08x", id);
} }
@@ -183,9 +195,12 @@ static void __init ath79_detect_sys_type
ath79_soc_rev = rev; if (ver == 1)
ath79_soc_rev = rev;
- if (soc_is_qca953x() || soc_is_qca955x()) - if (soc_is_qca953x() || soc_is_qca955x())
- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
+ if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca9561()) + if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca9561())
+ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u", sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
+ chip, ver, rev); chip, ver, rev);
+ else if (soc_is_tp9343()) + else if (soc_is_tp9343())
+ sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u", + sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
chip, rev); + chip, rev);
else else
sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
pr_info("SoC: %s\n", ath79_sys_type);
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -143,6 +143,23 @@ @@ -143,6 +143,23 @@