mirror of https://github.com/hak5/openwrt-owl.git
Florian Fainelli
parent
a1e0545d4b
commit
c879774b35
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@ -2,7 +2,8 @@
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# Makefile for the ADMtek ADM5120 SoC specific parts of the kernel
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#
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obj-y := setup.o prom.o irq.o memory.o int-handler.o adm5120_info.o
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obj-y += gpio.o
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obj-y := setup.o prom.o irq.o memory.o adm5120_info.o
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obj-y += gpio.o
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obj-y += time.o
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EXTRA_AFLAGS := $(CFLAGS)
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@ -1,135 +0,0 @@
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/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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* Interrupt exception dispatch code.
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*
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*/
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#include <linux/autoconf.h>
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#include <asm/asm.h>
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#include <asm/mipsregs.h>
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#include <asm/regdef.h>
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#include <asm/stackframe.h>
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#define STATUS_IE 0x00000001
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/* A lot of complication here is taken away because:
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*
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* 1) We handle one interrupt and return, sitting in a loop and moving across
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* all the pending IRQ bits in the cause register is _NOT_ the answer, the
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* common case is one pending IRQ so optimize in that direction.
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*
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* 2) We need not check against bits in the status register IRQ mask, that
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* would make this routine slow as hell.
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*
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* 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
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* between like BSD spl() brain-damage.
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*
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* Furthermore, the IRQs on the MIPS board look basically (barring software
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* IRQs which we don't use at all and all external interrupt sources are
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* combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
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*
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* MIPS IRQ Source
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* -------- ------
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* 0 Software (ignored)
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* 1 Software (ignored)
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* 2 Combined hardware interrupt (hw0)
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* 3 Hardware (ignored)
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* 4 Hardware (ignored)
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* 5 Hardware (ignored)
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* 6 Hardware (ignored)
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* 7 R4k timer (what we use)
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*
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* Note: On the SEAD board thing are a little bit different.
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* Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
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* wired to UART1.
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*
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* We handle the IRQ according to _our_ priority which is:
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*
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* Highest ---- R4k Timer
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* Lowest ---- Combined hardware interrupt
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*
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* then we just return, if multiple IRQs are pending then we will just take
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* another exception, big deal.
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*/
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.text
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.set noreorder
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.set noat
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.align 5
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NESTED(mipsIRQ, PT_SIZE, sp)
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SAVE_ALL
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CLI
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.set at
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mfc0 s0, CP0_CAUSE
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mfc0 s1, CP0_STATUS
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and s0, s0, s1
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/* First we check for r4k counter/timer IRQ. */
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andi a0, s0, CAUSEF_IP7
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beq a0, zero, 1f
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nop
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move a0, sp
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jal mips_timer_interrupt
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nop
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j ret_from_irq
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nop
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1:
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andi a0, s0, CAUSEF_IP2
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beq a0, zero, 1f
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nop
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move a0, sp
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jal adm5120_hw0_irqdispatch
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nop
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1:
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j ret_from_irq
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nop
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END(mipsIRQ)
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LEAF(mips_int_lock)
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.set noreorder
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mfc0 v0, CP0_STATUS
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li v1, ~STATUS_IE
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and v1, v1, v0
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mtc0 v1, CP0_STATUS
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j ra
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and v0, v0, STATUS_IE
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.set reorder
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END(mips_int_lock)
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LEAF(mips_int_unlock)
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mfc0 v0, CP0_STATUS
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and a0, a0, STATUS_IE
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or v0, v0, a0
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mtc0 v0, CP0_STATUS
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j ra
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nop
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END(mips_int_unlock)
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@ -1,157 +1,203 @@
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/*
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* Copyright (C) ADMtek Incorporated.
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* Creator : daniell@admtek.com.tw
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000, 2001 MIPS Technologies, Inc.
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* Copyright (C) 2001 Ralf Baechle
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* Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
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* $Id$
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*
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* ADM5120 specific interrupt handlers
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*
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* Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu>
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* Copyright (C) 2007 OpenWrt.org
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*
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*/
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#include <linux/autoconf.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/version.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/pm.h>
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#include <linux/ioport.h>
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#include <asm/irq.h>
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#include <asm/time.h>
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#include <asm/mipsregs.h>
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#include <asm/gdb-stub.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/bitops.h>
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#define MIPS_CPU_TIMER_IRQ 7
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#include <asm/mach-adm5120/adm5120_defs.h>
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#include <asm/mach-adm5120/adm5120_irq.h>
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extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
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extern irq_desc_t irq_desc[];
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extern asmlinkage void mipsIRQ(void);
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#define INTC_REG(r) (*(volatile u32 *)(KSEG1ADDR(ADM5120_INTC_BASE) + r))
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int mips_int_lock(void);
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void mips_int_unlock(int);
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static void adm5120_intc_irq_unmask(unsigned int irq);
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static void adm5120_intc_irq_mask(unsigned int irq);
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static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type);
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unsigned int mips_counter_frequency;
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static struct irq_chip adm5120_intc_irq_chip = {
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
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.name = "INTC",
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#else
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.typename = "INTC",
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#endif
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.unmask = adm5120_intc_irq_unmask,
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.mask = adm5120_intc_irq_mask,
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.mask_ack = adm5120_intc_irq_mask,
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.set_type = adm5120_intc_irq_set_type
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};
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#define ADM5120_INTC_REG(reg) (*(volatile u32 *)(KSEG1ADDR(0x12200000+(reg))))
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#define ADM5120_INTC_STATUS ADM5120_INTC_REG(0x00)
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#define ADM5120_INTC_ENABLE ADM5120_INTC_REG(0x08)
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#define ADM5120_INTC_DISABLE ADM5120_INTC_REG(0x0c)
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#define ADM5120_IRQ_MAX 9
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#define ADM5120_IRQ_MASK 0x3ff
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static struct irqaction adm5120_intc_irq_action = {
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.handler = no_action,
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.name = "cascade [INTC]"
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};
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void adm5120_hw0_irqdispatch(struct pt_regs *regs)
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static void adm5120_intc_irq_unmask(unsigned int irq)
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{
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unsigned long intsrc;
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int i;
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unsigned long flags;
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intsrc = ADM5120_INTC_STATUS & ADM5120_IRQ_MASK;
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if (intsrc) {
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for (i = 0; intsrc; intsrc >>= 1, i++)
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if (intsrc & 0x1)
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do_IRQ(i);
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} else
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spurious_interrupt();
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irq -= ADM5120_INTC_IRQ_BASE;
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local_irq_save(flags);
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INTC_REG(INTC_REG_IRQ_ENABLE) = (1 << irq);
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local_irq_restore(flags);
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}
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void mips_timer_interrupt(struct pt_regs *regs)
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static void adm5120_intc_irq_mask(unsigned int irq)
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{
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write_c0_compare(read_c0_count()+ mips_counter_frequency/HZ);
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ll_timer_interrupt(MIPS_CPU_TIMER_IRQ);
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unsigned long flags;
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irq -= ADM5120_INTC_IRQ_BASE;
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local_irq_save(flags);
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INTC_REG(INTC_REG_IRQ_DISABLE) = (1 << irq);
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local_irq_restore(flags);
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}
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/* Main interrupt dispatcher */
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asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
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static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type)
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{
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unsigned int cp0_cause = read_c0_cause() & read_c0_status();
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/* TODO: not yet tested */
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#if 1
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unsigned int sense;
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unsigned long mode;
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int err;
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if (cp0_cause & CAUSEF_IP7) {
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mips_timer_interrupt( regs);
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} else if (cp0_cause & CAUSEF_IP2) {
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adm5120_hw0_irqdispatch( regs);
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}
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}
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void enable_adm5120_irq(unsigned int irq)
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{
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int s;
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/* Disable all interrupts (FIQ/IRQ) */
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s = mips_int_lock();
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if ((irq < 0) || (irq > ADM5120_IRQ_MAX))
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goto err_exit;
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ADM5120_INTC_ENABLE = (1<<irq);
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err_exit:
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/* Restore the interrupts states */
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mips_int_unlock(s);
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}
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void disable_adm5120_irq(unsigned int irq)
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{
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int s;
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/* Disable all interrupts (FIQ/IRQ) */
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s = mips_int_lock();
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if ((irq < 0) || (irq > ADM5120_IRQ_MAX))
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goto err_exit;
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ADM5120_INTC_DISABLE = (1<<irq);
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err_exit:
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/* Restore the interrupts states */
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mips_int_unlock(s);
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}
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unsigned int startup_adm5120_irq(unsigned int irq)
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{
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enable_adm5120_irq(irq);
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err = 0;
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sense = flow_type & (IRQ_TYPE_SENSE_MASK);
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switch (sense) {
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case IRQ_TYPE_NONE:
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case IRQ_TYPE_LEVEL_HIGH:
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break;
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case IRQ_TYPE_LEVEL_LOW:
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switch (irq) {
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case ADM5120_IRQ_GPIO2:
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case ADM5120_IRQ_GPIO4:
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break;
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default:
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err = -EINVAL;
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break;
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}
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break;
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default:
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err = -EINVAL;
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break;
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}
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if (err)
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return err;
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switch (irq) {
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case ADM5120_IRQ_GPIO2:
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case ADM5120_IRQ_GPIO4:
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mode = INTC_REG(INTC_REG_INT_MODE);
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if (sense == IRQ_TYPE_LEVEL_LOW)
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mode |= (1 << (irq-ADM5120_INTC_IRQ_BASE));
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else
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mode &= (1 << (irq-ADM5120_INTC_IRQ_BASE));
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INTC_REG(INTC_REG_INT_MODE) = mode;
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/* fallthrogh */
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default:
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irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
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irq_desc[irq].status |= sense;
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break;
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}
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#endif
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return 0;
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}
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void shutdown_adm5120_irq(unsigned int irq)
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static void adm5120_intc_irq_dispatch(void)
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{
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disable_adm5120_irq(irq);
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unsigned long status;
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int irq;
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#if 1
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/* dispatch only one IRQ at a time */
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status = INTC_REG(INTC_REG_IRQ_STATUS) & INTC_INT_ALL;
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if (status) {
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irq = ADM5120_INTC_IRQ_BASE+fls(status)-1;
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do_IRQ(irq);
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} else
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spurious_interrupt();
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#else
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status = INTC_REG(INTC_REG_IRQ_STATUS) & INTC_INT_ALL;
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if (status) {
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for (irq=ADM5120_INTC_IRQ_BASE; irq <= ADM5120_INTC_IRQ_BASE +
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INTC_IRQ_LAST; irq++, status >>=1) {
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if ((status & 1) == 1)
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do_IRQ(irq);
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}
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} else
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spurious_interrupt();
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#endif
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}
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static inline void ack_adm5120_irq(unsigned int irq_nr)
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asmlinkage void plat_irq_dispatch(void)
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{
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ADM5120_INTC_DISABLE = (1 << irq_nr);
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unsigned long pending;
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pending = read_c0_status() & read_c0_cause();
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if (pending & STATUSF_IP7)
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do_IRQ(ADM5120_IRQ_COUNTER);
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else if (pending & STATUSF_IP2)
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adm5120_intc_irq_dispatch();
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else
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spurious_interrupt();
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}
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static void end_adm5120_irq(unsigned int irq_nr)
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{
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ADM5120_INTC_ENABLE = (1 << irq_nr);
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}
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static hw_irq_controller adm5120_irq_type = {
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.typename = "MIPS",
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.startup = startup_adm5120_irq,
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.shutdown = shutdown_adm5120_irq,
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.enable = enable_adm5120_irq,
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.disable = disable_adm5120_irq,
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.ack = ack_adm5120_irq,
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.end = end_adm5120_irq,
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.set_affinity = NULL,
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};
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void __init arch_init_irq(void)
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#define INTC_IRQ_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
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static void __init adm5120_intc_irq_init(int base)
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{
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int i;
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for (i = 0; i <= ADM5120_IRQ_MAX; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = 0;
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irq_desc[i].depth = 1;
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irq_desc[i].chip = &adm5120_irq_type;
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/* disable all interrupts */
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INTC_REG(INTC_REG_IRQ_DISABLE) = INTC_INT_ALL;
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/* setup all interrupts to generate IRQ instead of FIQ */
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INTC_REG(INTC_REG_INT_MODE) = 0;
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/* set active level for all external interrupts to HIGH */
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INTC_REG(INTC_REG_INT_LEVEL) = 0;
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/* disable usage of the TEST_SOURCE register */
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INTC_REG(INTC_REG_IRQ_SOURCE_SELECT) = 0;
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for(i=ADM5120_INTC_IRQ_BASE; i <= ADM5120_INTC_IRQ_BASE+INTC_IRQ_LAST;
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i++) {
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irq_desc[i].status = INTC_IRQ_STATUS;
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set_irq_chip_and_handler(i, &adm5120_intc_irq_chip,
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handle_level_irq);
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}
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setup_irq(ADM5120_IRQ_INTC, &adm5120_intc_irq_action);
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}
|
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void __init arch_init_irq(void) {
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mips_cpu_irq_init();
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adm5120_intc_irq_init(ADM5120_INTC_IRQ_BASE);
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}
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@ -15,15 +15,13 @@
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#include <asm/io.h>
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||||
#include <asm/time.h>
|
||||
|
||||
#include <adm5120_info.h>
|
||||
#include <asm/mach-adm5120/adm5120_info.h>
|
||||
#include <asm/mach-adm5120/adm5120_defs.h>
|
||||
#include <asm/mach-adm5120/adm5120_irq.h>
|
||||
|
||||
extern void adm5120_time_init(void) __init;
|
||||
|
||||
#define ADM5120_SOFTRESET 0x12000004
|
||||
#define STATUS_IE 0x00000001
|
||||
#define ALLINTS (IE_IRQ0 | IE_IRQ5 | STATUS_IE)
|
||||
|
||||
void mips_time_init(void);
|
||||
|
||||
extern unsigned int mips_counter_frequency;
|
||||
|
||||
void adm5120_restart(char *command)
|
||||
{
|
||||
|
|
@ -43,25 +41,11 @@ void adm5120_power_off(void)
|
|||
adm5120_halt();
|
||||
}
|
||||
|
||||
void __init adm5120_time_init(void)
|
||||
{
|
||||
mips_counter_frequency = adm5120_speed >> 1;
|
||||
}
|
||||
|
||||
void __init plat_timer_setup(struct irqaction *irq)
|
||||
{
|
||||
/* to generate the first timer interrupt */
|
||||
write_c0_compare(read_c0_count()+ mips_counter_frequency/HZ);
|
||||
clear_c0_status(ST0_BEV);
|
||||
set_c0_status(ALLINTS);
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
printk(KERN_INFO "ADM5120 board setup\n");
|
||||
|
||||
board_time_init = adm5120_time_init;
|
||||
//board_timer_setup = mips_timer_setup;
|
||||
|
||||
_machine_restart = adm5120_restart;
|
||||
_machine_halt = adm5120_halt;
|
||||
|
|
@ -75,16 +59,15 @@ const char *get_system_type(void)
|
|||
return adm5120_board_name();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USB
|
||||
static struct resource adm5120_hcd_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x11200000,
|
||||
.end = 0x11200084,
|
||||
.start = ADM5120_USBC_BASE,
|
||||
.end = ADM5120_USBC_BASE+ADM5120_USBC_SIZE-1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 0x3,
|
||||
.end = 0x3,
|
||||
.start = ADM5120_IRQ_USBC,
|
||||
.end = ADM5120_IRQ_USBC,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -105,5 +88,4 @@ static int __init adm5120_init(void)
|
|||
return platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
}
|
||||
|
||||
arch_initcall(adm5120_init);
|
||||
#endif
|
||||
subsys_initcall(adm5120_init);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,99 @@
|
|||
/*
|
||||
* $Id$
|
||||
*
|
||||
* ADM5120 specific PCI fixups
|
||||
*
|
||||
* Copyright (C) ADMtek Incorporated.
|
||||
* Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
|
||||
* Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu>
|
||||
* Copyright (C) 2007 OpenWrt.org
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the
|
||||
* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/autoconf.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/pci_ids.h>
|
||||
#include <linux/pci_regs.h>
|
||||
|
||||
#include <asm/delay.h>
|
||||
#include <asm/bootinfo.h>
|
||||
|
||||
#include <asm/mach-adm5120/adm5120_info.h>
|
||||
#include <asm/mach-adm5120/adm5120_defs.h>
|
||||
#include <asm/mach-adm5120/adm5120_irq.h>
|
||||
|
||||
static void adm5120_pci_fixup(struct pci_dev *dev)
|
||||
{
|
||||
if (dev->devfn !=0)
|
||||
return;
|
||||
|
||||
/* setup COMMAND register */
|
||||
pci_write_config_word(dev, PCI_COMMAND,
|
||||
(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
|
||||
|
||||
/* setup CACHE_LINE_SIZE register */
|
||||
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
|
||||
|
||||
/* setting up BARS */
|
||||
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
|
||||
pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
|
||||
}
|
||||
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADMTEK, PCI_DEVICE_ID_ADMTEK_ADM5120,
|
||||
adm5120_pci_fixup);
|
||||
|
||||
|
||||
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
int irq;
|
||||
|
||||
irq = -1;
|
||||
#if 1
|
||||
/* FIXME: this code should be working on all boards? */
|
||||
if (slot > 0 && slot < 4)
|
||||
irq = ADM5120_IRQ_PCI0+slot-1;
|
||||
#else
|
||||
switch (mips_machtype) {
|
||||
case MACH_ADM5120_RB_111:
|
||||
case MACH_ADM5120_RB_112:
|
||||
case MACH_ADM5120_RB_133:
|
||||
case MACH_ADM5120_RB_133C:
|
||||
case MACH_ADM5120_RB_153:
|
||||
if (slot > 0 && slot < 4)
|
||||
irq = ADM5120_IRQ_PCI0+slot-1;
|
||||
break;
|
||||
default:
|
||||
if (slot > 1 && slot < 5)
|
||||
irq = ADM5120_IRQ_PCI0+slot-2;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
printk(KERN_INFO "PCI: mapping irq for device %s, slot:%u, pin:%u, "
|
||||
"irq:%d\n", pci_name(dev), slot, pin, irq);
|
||||
|
||||
return irq;
|
||||
}
|
||||
|
||||
int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1,17 +1,36 @@
|
|||
/*
|
||||
* Copyright (C) ADMtek Incorporated.
|
||||
* Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
|
||||
* Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu>
|
||||
* Copyright (C) 2007 OpenWrt.org
|
||||
* $Id$
|
||||
*
|
||||
* ADM5120 specific PCI operations
|
||||
*
|
||||
* Copyright (C) ADMtek Incorporated.
|
||||
* Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
|
||||
* Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu>
|
||||
* Copyright (C) 2007 OpenWrt.org
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the
|
||||
* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/autoconf.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <adm5120_defs.h>
|
||||
#include <asm/mach-adm5120/adm5120_defs.h>
|
||||
|
||||
volatile u32* pci_config_address_reg = (volatile u32*)KSEG1ADDR(ADM5120_PCICFG_ADDR);
|
||||
volatile u32* pci_config_data_reg = (volatile u32*)KSEG1ADDR(ADM5120_PCICFG_DATA);
|
||||
|
|
@ -24,14 +43,15 @@ static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
|
|||
*pci_config_address_reg = ((bus->number & 0xff) << 0x10) |
|
||||
((devfn & 0xff) << 0x08) | (where & 0xfc) | PCI_ENABLE;
|
||||
switch (size) {
|
||||
case 1:
|
||||
*val = ((*pci_config_data_reg)>>((where&3)<<3))&0xff;
|
||||
break;
|
||||
case 2:
|
||||
*val = ((*pci_config_data_reg)>>((where&3)<<3))&0xffff;
|
||||
break;
|
||||
default:
|
||||
*val = (*pci_config_data_reg);
|
||||
case 1:
|
||||
*val = ((*pci_config_data_reg)>>((where&3)<<3))&0xff;
|
||||
break;
|
||||
case 2:
|
||||
*val = ((*pci_config_data_reg)>>((where&3)<<3))&0xffff;
|
||||
break;
|
||||
default:
|
||||
*val = (*pci_config_data_reg);
|
||||
break;
|
||||
}
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
|
@ -42,16 +62,16 @@ static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
|
|||
*pci_config_address_reg = ((bus->number & 0xff) << 0x10) |
|
||||
((devfn & 0xff) << 0x08) | (where & 0xfc) | PCI_ENABLE;
|
||||
switch (size) {
|
||||
case 1:
|
||||
*(volatile u8 *)(((int)pci_config_data_reg) +
|
||||
case 1:
|
||||
*(volatile u8 *)(((int)pci_config_data_reg) +
|
||||
(where & 3)) = val;
|
||||
break;
|
||||
case 2:
|
||||
*(volatile u16 *)(((int)pci_config_data_reg) +
|
||||
break;
|
||||
case 2:
|
||||
*(volatile u16 *)(((int)pci_config_data_reg) +
|
||||
(where & 2)) = (val);
|
||||
break;
|
||||
default:
|
||||
*pci_config_data_reg = (val);
|
||||
break;
|
||||
default:
|
||||
*pci_config_data_reg = (val);
|
||||
}
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
|
|
|
|||
|
|
@ -1,38 +1,48 @@
|
|||
/*
|
||||
* Copyright (C) ADMtek Incorporated.
|
||||
* Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
|
||||
* Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu>
|
||||
* Copyright (C) 2007 OpenWrt.org
|
||||
* $Id$
|
||||
*
|
||||
* ADM5120 PCI Host Controller driver
|
||||
*
|
||||
* Copyright (C) ADMtek Incorporated.
|
||||
* Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
|
||||
* Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu>
|
||||
* Copyright (C) 2007 OpenWrt.org
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the
|
||||
* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/autoconf.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <adm5120_info.h>
|
||||
#include <adm5120_defs.h>
|
||||
#include <asm/mach-adm5120/adm5120_info.h>
|
||||
#include <asm/mach-adm5120/adm5120_defs.h>
|
||||
#include <asm/mach-adm5120/adm5120_irq.h>
|
||||
|
||||
extern struct pci_ops adm5120_pci_ops;
|
||||
|
||||
#define PCI_CMM_IOACC_EN 0x1
|
||||
#define PCI_CMM_MEMACC_EN 0x2
|
||||
#define PCI_CMM_MASTER_EN 0x4
|
||||
#define PCI_CMM_DEF \
|
||||
(PCI_CMM_IOACC_EN | PCI_CMM_MEMACC_EN | PCI_CMM_MASTER_EN)
|
||||
|
||||
#define PCI_DEF_CACHE_LINE_SZ 4
|
||||
|
||||
|
||||
struct resource pci_io_resource = {
|
||||
static struct resource pci_io_resource = {
|
||||
.name = "ADM5120 PCI I/O",
|
||||
.start = ADM5120_PCIIO_BASE,
|
||||
.end = ADM5120_PCICFG_ADDR-1,
|
||||
.flags = IORESOURCE_IO
|
||||
};
|
||||
|
||||
struct resource pci_mem_resource = {
|
||||
static struct resource pci_mem_resource = {
|
||||
.name = "ADM5120 PCI MEM",
|
||||
.start = ADM5120_PCIMEM_BASE,
|
||||
.end = ADM5120_PCIIO_BASE-1,
|
||||
|
|
@ -45,32 +55,6 @@ static struct pci_controller adm5120_controller = {
|
|||
.mem_resource = &pci_mem_resource,
|
||||
};
|
||||
|
||||
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
if (slot < 2 || slot > 4)
|
||||
return -1;
|
||||
return slot + 4;
|
||||
}
|
||||
|
||||
static void adm5120_pci_fixup(struct pci_dev *dev)
|
||||
{
|
||||
if (dev->devfn == 0) {
|
||||
pci_write_config_word(dev, PCI_COMMAND, PCI_CMM_DEF);
|
||||
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
|
||||
PCI_DEF_CACHE_LINE_SZ);
|
||||
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
|
||||
pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
|
||||
}
|
||||
}
|
||||
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, adm5120_pci_fixup);
|
||||
|
||||
|
||||
int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init adm5120_pci_setup(void)
|
||||
{
|
||||
int pci_bios;
|
||||
|
|
@ -79,7 +63,7 @@ static int __init adm5120_pci_setup(void)
|
|||
|
||||
printk("adm5120: system has %sPCI BIOS\n", pci_bios ? "" : "no ");
|
||||
if (pci_bios == 0)
|
||||
return 1;
|
||||
return -1;
|
||||
|
||||
/* Avoid ISA compat ranges. */
|
||||
PCIBIOS_MIN_IO = 0x00000000;
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#include "adm5120sw.h"
|
||||
|
||||
#include <asm/mach-adm5120/adm5120_info.h>
|
||||
#include <asm/mach-adm5120/adm5120_irq.h>
|
||||
|
||||
MODULE_AUTHOR("Jeroen Vreeken (pe1rxq@amsat.org)");
|
||||
MODULE_DESCRIPTION("ADM5120 ethernet switch driver");
|
||||
|
|
@ -385,7 +386,7 @@ static int __init adm5120_sw_init(void)
|
|||
int i, err;
|
||||
struct net_device *dev;
|
||||
|
||||
err = request_irq(SW_IRQ, adm5120_sw_irq, 0, "ethernet switch", NULL);
|
||||
err = request_irq(ADM5120_IRQ_SWITCH, adm5120_sw_irq, 0, "ethernet switch", NULL);
|
||||
if (err)
|
||||
goto out;
|
||||
|
||||
|
|
@ -434,7 +435,7 @@ static int __init adm5120_sw_init(void)
|
|||
memset(netdev_priv(dev), 0, sizeof(struct adm5120_sw));
|
||||
((struct adm5120_sw*)netdev_priv(dev))->port = i;
|
||||
dev->base_addr = SW_BASE;
|
||||
dev->irq = SW_IRQ;
|
||||
dev->irq = ADM5120_IRQ_SWITCH;
|
||||
dev->open = adm5120_sw_open;
|
||||
dev->hard_start_xmit = adm5120_sw_tx;
|
||||
dev->stop = adm5120_sw_stop;
|
||||
|
|
@ -469,7 +470,7 @@ out_int:
|
|||
unregister_netdev(adm5120_devs[i-1]);
|
||||
free_netdev(adm5120_devs[i-1]);
|
||||
}
|
||||
free_irq(SW_IRQ, NULL);
|
||||
free_irq(ADM5120_IRQ_SWITCH, NULL);
|
||||
out:
|
||||
printk(KERN_ERR "ADM5120 Ethernet switch init failed\n");
|
||||
return err;
|
||||
|
|
@ -484,7 +485,7 @@ static void __exit adm5120_sw_exit(void)
|
|||
free_netdev(adm5120_devs[i-1]);
|
||||
}
|
||||
|
||||
free_irq(SW_IRQ, NULL);
|
||||
free_irq(ADM5120_IRQ_SWITCH, NULL);
|
||||
|
||||
for (i = 0; i < ADM5120_DMA_RXH; i++) {
|
||||
if (!adm5120_skb_rxh[i])
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@
|
|||
|
||||
#define SW_BASE KSEG1ADDR(0x12000000)
|
||||
#define SW_DEVS 6
|
||||
#define SW_IRQ 9
|
||||
|
||||
#define ETH_TX_TIMEOUT HZ/4
|
||||
#define ETH_FCS 4;
|
||||
|
|
|
|||
|
|
@ -24,12 +24,8 @@
|
|||
#include <linux/tty_flip.h>
|
||||
#include <linux/console.h>
|
||||
|
||||
#define ADM5120_UART_BASE0 0x12600000
|
||||
#define ADM5120_UART_BASE1 0x12800000
|
||||
#define ADM5120_UART_SIZE 0x20
|
||||
|
||||
#define ADM5120_UART_IRQ0 1
|
||||
#define ADM5120_UART_IRQ1 2
|
||||
#include <asm/mach-adm5120/adm5120_defs.h>
|
||||
#include <asm/mach-adm5120/adm5120_irq.h>
|
||||
|
||||
#define ADM5120_UART_REG(base, reg) \
|
||||
(*(volatile u32 *)KSEG1ADDR((base)+(reg)))
|
||||
|
|
@ -421,9 +417,9 @@ static struct uart_ops adm5120ser_ops = {
|
|||
|
||||
static void adm5120console_put(const char c)
|
||||
{
|
||||
while ((ADM5120_UART_REG(ADM5120_UART_BASE0, ADM5120_UART_FR) &
|
||||
while ((ADM5120_UART_REG(ADM5120_UART0_BASE, ADM5120_UART_FR) &
|
||||
ADM5120_UART_TXFF) != 0);
|
||||
ADM5120_UART_REG(ADM5120_UART_BASE0, ADM5120_UART_DATA) = c;
|
||||
ADM5120_UART_REG(ADM5120_UART0_BASE, ADM5120_UART_DATA) = c;
|
||||
}
|
||||
|
||||
static void adm5120console_write(struct console *con, const char *s,
|
||||
|
|
@ -440,14 +436,14 @@ static void adm5120console_write(struct console *con, const char *s,
|
|||
static int __init adm5120console_setup(struct console *con, char *options)
|
||||
{
|
||||
/* Set to 115200 baud, 8N1 and enable FIFO */
|
||||
ADM5120_UART_REG(ADM5120_UART_BASE0, ADM5120_UART_LCR_L) =
|
||||
ADM5120_UART_REG(ADM5120_UART0_BASE, ADM5120_UART_LCR_L) =
|
||||
ADM5120_UART_BAUD115200 & 0xff;
|
||||
ADM5120_UART_REG(ADM5120_UART_BASE0, ADM5120_UART_LCR_M) =
|
||||
ADM5120_UART_REG(ADM5120_UART0_BASE, ADM5120_UART_LCR_M) =
|
||||
ADM5120_UART_BAUD115200 >> 8;
|
||||
ADM5120_UART_REG(ADM5120_UART_BASE0, ADM5120_UART_LCR_H) =
|
||||
ADM5120_UART_REG(ADM5120_UART0_BASE, ADM5120_UART_LCR_H) =
|
||||
ADM5120_UART_W8 | ADM5120_UART_FIFO_EN;
|
||||
/* Enable port */
|
||||
ADM5120_UART_REG(ADM5120_UART_BASE0, ADM5120_UART_CR) =
|
||||
ADM5120_UART_REG(ADM5120_UART0_BASE, ADM5120_UART_CR) =
|
||||
ADM5120_UART_EN;
|
||||
|
||||
return 0;
|
||||
|
|
@ -477,8 +473,8 @@ console_initcall(adm5120console_init);
|
|||
|
||||
static struct uart_port adm5120ser_ports[] = {
|
||||
{
|
||||
.iobase = ADM5120_UART_BASE0,
|
||||
.irq = ADM5120_UART_IRQ0,
|
||||
.iobase = ADM5120_UART0_BASE,
|
||||
.irq = ADM5120_IRQ_UART0,
|
||||
.uartclk = ADM5120_UARTCLK_FREQ,
|
||||
.fifosize = 16,
|
||||
.ops = &adm5120ser_ops,
|
||||
|
|
@ -487,8 +483,8 @@ static struct uart_port adm5120ser_ports[] = {
|
|||
},
|
||||
#if (CONFIG_ADM5120_NR_UARTS > 1)
|
||||
{
|
||||
.iobase = ADM5120_UART_BASE1,
|
||||
.irq = ADM5120_UART_IRQ1,
|
||||
.iobase = ADM5120_UART1_BASE,
|
||||
.irq = ADM5120_IRQ_UART1,
|
||||
.uartclk = ADM5120_UARTCLK_FREQ,
|
||||
.fifosize = 16,
|
||||
.ops = &adm5120ser_ops,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* ADM5120 interrupt controller definitions
|
||||
*
|
||||
* This header file defines the hardware registers of the ADM5120 SoC
|
||||
* built-in interrupt controller.
|
||||
*
|
||||
* Copyright (C) 2007 OpenWrt.org
|
||||
* Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the
|
||||
* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
#ifndef _ADM5120_INTC_H_
|
||||
#define _ADM5120_INTC_H_
|
||||
|
||||
/*
|
||||
* INTC register offsets
|
||||
*/
|
||||
#define INTC_REG_IRQ_STATUS 0x00 /* Interrupt status after masking */
|
||||
#define INTC_REG_IRQ_RAW_STATUS 0x04 /* Interrupt status before masking */
|
||||
#define INTC_REG_IRQ_ENABLE 0x08 /* Used to enable the interrupt sources */
|
||||
#define INTC_REG_IRQ_ENABLE_CLEAR 0x0C /* Used to disable the interrupt sources */
|
||||
#define INTC_REG_IRQ_DISABLE INTC_REG_IRQ_ENABLE_CLEAR
|
||||
#define INTC_REG_INT_MODE 0x14 /* The interrupt mode of the sources */
|
||||
#define INTC_REG_FIQ_STATUS 0x18 /* FIQ status */
|
||||
#define INTC_REG_IRQ_TEST_SOURCE 0x1C
|
||||
#define INTC_REG_IRQ_SOURCE_SELECT 0x20
|
||||
#define INTC_REG_INT_LEVEL 0x24
|
||||
|
||||
/*
|
||||
* INTC IRQ numbers
|
||||
*/
|
||||
#define INTC_IRQ_TIMER 0 /* built in timer */
|
||||
#define INTC_IRQ_UART0 1 /* built-in UART0 */
|
||||
#define INTC_IRQ_UART1 2 /* built-in UART1 */
|
||||
#define INTC_IRQ_USBC 3 /* USB Host Controller */
|
||||
#define INTC_IRQ_GPIO2 4 /* GPIO line 2 */
|
||||
#define INTC_IRQ_GPIO4 5 /* GPIO line 4 */
|
||||
#define INTC_IRQ_PCI0 6 /* PCI slot 2 */
|
||||
#define INTC_IRQ_PCI1 7 /* PCI slot 3 */
|
||||
#define INTC_IRQ_PCI2 8 /* PCI slot 4 */
|
||||
#define INTC_IRQ_SWITCH 9 /* built-in ethernet switch */
|
||||
#define INTC_IRQ_LAST INTC_IRQ_SWITCH
|
||||
#define INTC_IRQ_COUNT 10
|
||||
|
||||
/*
|
||||
* INTC register bits
|
||||
*/
|
||||
#define INTC_INT_TIMER ( 1 << INTC_IRQ_TIMER )
|
||||
#define INTC_INT_UART0 ( 1 << INTC_IRQ_UART0 )
|
||||
#define INTC_INT_UART1 ( 1 << INTC_IRQ_UART1 )
|
||||
#define INTC_INT_USBC ( 1 << INTC_IRQ_USBC )
|
||||
#define INTC_INT_INTX0 ( 1 << INTC_IRQ_INTX0 )
|
||||
#define INTC_INT_INTX1 ( 1 << INTC_IRQ_INTX1 )
|
||||
#define INTC_INT_PCI0 ( 1 << INTC_IRQ_PCI0 )
|
||||
#define INTC_INT_PCI1 ( 1 << INTC_IRQ_PCI1 )
|
||||
#define INTC_INT_PCI2 ( 1 << INTC_IRQ_PCI2 )
|
||||
#define INTC_INT_SWITCH ( 1 << INTC_IRQ_SWITCH )
|
||||
#define INTC_INT_ALL (( 1 << INTC_IRQ_COUNT)-1)
|
||||
|
||||
#endif /* _ADM5120_INTC_H_ */
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* $Id$
|
||||
*
|
||||
* ADM5120 specific IRQ numbers
|
||||
*
|
||||
* Copyright (C) 2007 OpenWrt.org
|
||||
* Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the
|
||||
* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*
|
||||
*/
|
||||
#ifndef _ADM5120_IRQ_H_
|
||||
#define _ADM5120_IRQ_H_
|
||||
|
||||
#include <asm/mach-adm5120/adm5120_intc.h>
|
||||
|
||||
#define MIPS_IRQ_HW0 2
|
||||
#define MIPS_IRQ_COUNTER 7
|
||||
#define MIPS_IRQ_COUNT 8
|
||||
|
||||
#define ADM5120_CPU_IRQ_BASE 0
|
||||
#define ADM5120_INTC_IRQ_BASE (ADM5120_CPU_IRQ_BASE+MIPS_IRQ_COUNT)
|
||||
#define ADM5120_SWITCH_IRQ_BASE (ADM5120_INTC_IRQ_BASE+INTC_IRQ_COUNT)
|
||||
|
||||
#define ADM5120_CPU_IRQ(x) (ADM5120_CPU_IRQ_BASE + (x))
|
||||
#define ADM5120_INTC_IRQ(x) (ADM5120_INTC_IRQ_BASE + (x))
|
||||
|
||||
#define ADM5120_IRQ_INTC ADM5120_CPU_IRQ(MIPS_IRQ_HW0)
|
||||
#define ADM5120_IRQ_COUNTER ADM5120_CPU_IRQ(MIPS_IRQ_COUNTER)
|
||||
|
||||
#define ADM5120_IRQ_TIMER ADM5120_INTC_IRQ(INTC_IRQ_TIMER)
|
||||
#define ADM5120_IRQ_UART0 ADM5120_INTC_IRQ(INTC_IRQ_UART0)
|
||||
#define ADM5120_IRQ_UART1 ADM5120_INTC_IRQ(INTC_IRQ_UART1)
|
||||
#define ADM5120_IRQ_USBC ADM5120_INTC_IRQ(INTC_IRQ_USBC)
|
||||
#define ADM5120_IRQ_GPIO2 ADM5120_INTC_IRQ(INTC_IRQ_GPIO2)
|
||||
#define ADM5120_IRQ_GPIO4 ADM5120_INTC_IRQ(INTC_IRQ_GPIO4)
|
||||
#define ADM5120_IRQ_PCI0 ADM5120_INTC_IRQ(INTC_IRQ_PCI0)
|
||||
#define ADM5120_IRQ_PCI1 ADM5120_INTC_IRQ(INTC_IRQ_PCI1)
|
||||
#define ADM5120_IRQ_PCI2 ADM5120_INTC_IRQ(INTC_IRQ_PCI2)
|
||||
#define ADM5120_IRQ_SWITCH ADM5120_INTC_IRQ(INTC_IRQ_SWITCH)
|
||||
|
||||
#endif
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
diff -urN linux-2.6.19.2/arch/mips/Kconfig linux-2.6.19.2.new/arch/mips/Kconfig
|
||||
--- linux-2.6.19.2/arch/mips/Kconfig 2007-01-10 20:10:37.000000000 +0100
|
||||
+++ linux-2.6.19.2.new/arch/mips/Kconfig 2007-01-23 14:49:38.000000000 +0100
|
||||
@@ -12,6 +12,20 @@
|
||||
@@ -12,6 +12,21 @@
|
||||
prompt "System type"
|
||||
default SGI_IP22
|
||||
|
||||
|
|
@ -10,6 +10,7 @@ diff -urN linux-2.6.19.2/arch/mips/Kconfig linux-2.6.19.2.new/arch/mips/Kconfig
|
|||
+ select SYS_HAS_CPU_MIPS32_R1
|
||||
+ select DMA_NONCOHERENT
|
||||
+ select HW_HAS_PCI
|
||||
+ select IRQ_CPU
|
||||
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
+ select SYS_SUPPORTS_BIG_ENDIAN
|
||||
+ select SYS_SUPPORTS_32BIT_KERNEL
|
||||
|
|
@ -40,14 +41,6 @@ diff -urN linux-2.6.19.2/arch/mips/Makefile linux-2.6.19.2.new/arch/mips/Makefil
|
|||
# Common Alchemy Au1x00 stuff
|
||||
#
|
||||
core-$(CONFIG_SOC_AU1X00) += arch/mips/au1000/common/
|
||||
diff -urN linux-2.6.19.2/arch/mips/pci/Makefile linux-2.6.19.2.new/arch/mips/pci/Makefile
|
||||
--- linux-2.6.19.2/arch/mips/pci/Makefile 2007-01-10 20:10:37.000000000 +0100
|
||||
+++ linux-2.6.19.2.new/arch/mips/pci/Makefile 2007-01-23 14:49:40.000000000 +0100
|
||||
@@ -53,3 +53,4 @@
|
||||
obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
|
||||
obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
|
||||
obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
|
||||
+obj-$(CONFIG_PCI_ADM5120) += ops-adm5120.o pci-adm5120.o
|
||||
diff -urN linux-2.6.19.2/include/asm-mips/bootinfo.h linux-2.6.19.2.new/include/asm-mips/bootinfo.h
|
||||
--- linux-2.6.19.2/include/asm-mips/bootinfo.h 2007-01-10 20:10:37.000000000 +0100
|
||||
+++ linux-2.6.19.2.new/include/asm-mips/bootinfo.h 2007-01-23 14:49:40.000000000 +0100
|
||||
|
|
|
|||
|
|
@ -0,0 +1,20 @@
|
|||
diff -urN linux-2.6.21.1/arch/mips/pci/Makefile linux-2.6.21.1-adm5120/arch/mips/pci/Makefile
|
||||
--- linux-2.6.21.1/arch/mips/pci/Makefile 2007-01-10 20:10:37.000000000 +0100
|
||||
+++ linux-2.6.21.1-adm5120/arch/mips/pci/Makefile 2007-01-23 14:49:40.000000000 +0100
|
||||
@@ -53,3 +53,4 @@
|
||||
obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
|
||||
obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
|
||||
obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
|
||||
+obj-$(CONFIG_PCI_ADM5120) += fixup-adm5120.o ops-adm5120.o pci-adm5120.o
|
||||
--- linux-2.6.21.1.old/include/linux/pci_ids.h 2007-04-27 23:49:26.000000000 +0200
|
||||
+++ linux-2.6.21.1/include/linux/pci_ids.h 2007-05-31 09:36:56.000000000 +0200
|
||||
@@ -1701,6 +1701,9 @@
|
||||
#define PCI_VENDOR_ID_ESDGMBH 0x12fe
|
||||
#define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111
|
||||
|
||||
+#define PCI_VENDOR_ID_ADMTEK 0x1317
|
||||
+#define PCI_DEVICE_ID_ADMTEK_ADM5120 0x5120
|
||||
+
|
||||
#define PCI_VENDOR_ID_SIIG 0x131f
|
||||
#define PCI_SUBVENDOR_ID_SIIG 0x131f
|
||||
#define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000
|
||||
Loading…
Reference in New Issue