mirror of https://github.com/hak5/openwrt-owl.git
parent
7adb67f184
commit
c2c496868e
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@ -237,26 +237,70 @@ static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
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iounmap(base);
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}
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static void ar71xx_set_pll_ge0(u32 val)
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struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
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struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
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static u32 ar71xx_get_eth_pll(unsigned int mac, int speed)
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{
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struct ar71xx_eth_pll_data *pll_data;
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u32 pll_val;
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switch (mac) {
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case 0:
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pll_data = &ar71xx_eth0_pll_data;
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break;
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case 1:
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pll_data = &ar71xx_eth1_pll_data;
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break;
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default:
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BUG();
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}
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switch (speed) {
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case SPEED_10:
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pll_val = pll_data->pll_10;
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break;
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case SPEED_100:
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pll_val = pll_data->pll_100;
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break;
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case SPEED_1000:
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pll_val = pll_data->pll_1000;
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break;
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default:
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BUG();
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}
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return pll_val;
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}
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static void ar71xx_set_pll_ge0(int speed)
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{
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u32 val = ar71xx_get_eth_pll(0, speed);
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ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
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val, AR71XX_ETH0_PLL_SHIFT);
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}
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static void ar71xx_set_pll_ge1(u32 val)
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static void ar71xx_set_pll_ge1(int speed)
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{
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u32 val = ar71xx_get_eth_pll(1, speed);
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ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
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val, AR71XX_ETH1_PLL_SHIFT);
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}
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static void ar91xx_set_pll_ge0(u32 val)
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static void ar91xx_set_pll_ge0(int speed)
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{
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u32 val = ar71xx_get_eth_pll(0, speed);
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ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
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val, AR91XX_ETH0_PLL_SHIFT);
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}
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static void ar91xx_set_pll_ge1(u32 val)
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static void ar91xx_set_pll_ge1(int speed)
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{
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u32 val = ar71xx_get_eth_pll(1, speed);
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ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
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val, AR91XX_ETH1_PLL_SHIFT);
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}
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@ -357,12 +401,66 @@ static struct platform_device ar71xx_eth1_device = {
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},
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};
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#define AR71XX_PLL_VAL_1000 0x00110000
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#define AR71XX_PLL_VAL_100 0x00001099
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#define AR71XX_PLL_VAL_10 0x00991099
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#define AR91XX_PLL_VAL_1000 0x1a000000
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#define AR91XX_PLL_VAL_100 0x13000a44
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#define AR91XX_PLL_VAL_10 0x00441099
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static void __init ar71xx_init_eth_pll_data(unsigned int id)
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{
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struct ar71xx_eth_pll_data *pll_data;
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u32 pll_10, pll_100, pll_1000;
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switch (id) {
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case 0:
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pll_data = &ar71xx_eth0_pll_data;
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break;
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case 1:
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pll_data = &ar71xx_eth1_pll_data;
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break;
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default:
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BUG();
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}
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR7130:
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case AR71XX_SOC_AR7141:
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case AR71XX_SOC_AR7161:
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pll_10 = AR71XX_PLL_VAL_10;
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pll_100 = AR71XX_PLL_VAL_100;
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pll_1000 = AR71XX_PLL_VAL_1000;
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break;
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case AR71XX_SOC_AR9130:
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case AR71XX_SOC_AR9132:
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pll_10 = AR91XX_PLL_VAL_10;
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pll_100 = AR91XX_PLL_VAL_100;
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pll_1000 = AR91XX_PLL_VAL_1000;
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break;
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default:
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BUG();
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}
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if (!pll_data->pll_10)
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pll_data->pll_10 = pll_10;
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if (!pll_data->pll_100)
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pll_data->pll_100 = pll_100;
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if (!pll_data->pll_1000)
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pll_data->pll_1000 = pll_1000;
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}
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static int ar71xx_eth_instance __initdata;
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void __init ar71xx_add_device_eth(unsigned int id)
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{
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struct platform_device *pdev;
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struct ag71xx_platform_data *pdata;
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ar71xx_init_eth_pll_data(id);
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switch (id) {
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case 0:
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switch (ar71xx_eth0_data.phy_if_mode) {
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@ -25,6 +25,15 @@ void ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata,
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void ar71xx_set_mac_base(unsigned char *mac) __init;
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void ar71xx_parse_mac_addr(char *mac_str) __init;
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struct ar71xx_eth_pll_data {
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u32 pll_10;
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u32 pll_100;
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u32 pll_1000;
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};
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extern struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
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extern struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
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extern struct ag71xx_platform_data ar71xx_eth0_data;
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extern struct ag71xx_platform_data ar71xx_eth1_data;
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void ar71xx_add_device_eth(unsigned int id) __init;
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@ -93,6 +93,8 @@ static void __init ap83_setup(void)
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ar71xx_eth1_data.speed = SPEED_1000;
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ar71xx_eth1_data.duplex = DUPLEX_FULL;
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ar71xx_eth1_pll_data.pll_1000 = 0x1f000000;
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ar71xx_add_device_eth(1);
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ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap83_leds_gpio),
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@ -31,7 +31,7 @@ struct ag71xx_platform_data {
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u8 has_ar8216:1;
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void (* ddr_flush)(void);
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void (* set_pll)(u32 pll);
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void (* set_pll)(int speed);
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};
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struct ag71xx_mdio_platform_data {
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@ -27,20 +27,11 @@ static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
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return "?";
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}
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#define AR71XX_PLL_VAL_1000 0x00110000
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#define AR71XX_PLL_VAL_100 0x00001099
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#define AR71XX_PLL_VAL_10 0x00991099
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#define AR91XX_PLL_VAL_1000 0x1a000000
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#define AR91XX_PLL_VAL_100 0x13000a44
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#define AR91XX_PLL_VAL_10 0x00441099
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static void ag71xx_phy_link_update(struct ag71xx *ag)
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{
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struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
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u32 cfg2;
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u32 ifctl;
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u32 pll;
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u32 fifo5;
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u32 mii_speed;
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@ -65,22 +56,16 @@ static void ag71xx_phy_link_update(struct ag71xx *ag)
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case SPEED_1000:
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mii_speed = MII_CTRL_SPEED_1000;
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cfg2 |= MAC_CFG2_IF_1000;
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pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_1000
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: AR71XX_PLL_VAL_1000;
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fifo5 |= FIFO_CFG5_BM;
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break;
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case SPEED_100:
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mii_speed = MII_CTRL_SPEED_100;
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cfg2 |= MAC_CFG2_IF_10_100;
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ifctl |= MAC_IFCTL_SPEED;
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pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_100
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: AR71XX_PLL_VAL_100;
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break;
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case SPEED_10:
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mii_speed = MII_CTRL_SPEED_10;
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cfg2 |= MAC_CFG2_IF_10_100;
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pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_10
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: AR71XX_PLL_VAL_10;
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break;
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default:
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BUG();
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@ -89,7 +74,7 @@ static void ag71xx_phy_link_update(struct ag71xx *ag)
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3,
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pdata->is_ar91xx ? 0x780fff : 0x008001ff);
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pdata->set_pll(pll);
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pdata->set_pll(ag->speed);
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ag71xx_mii_ctrl_set_speed(ag, mii_speed);
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ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
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