mirror of https://github.com/hak5/openwrt-owl.git
parent
c7150f281c
commit
c1ce330694
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@ -78,8 +78,8 @@ mvswitch_mangle_tx(struct sk_buff *skb, struct net_device *dev)
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if (__vlan_hwaccel_get_tag(skb, &vid))
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goto error;
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if ((skb->len <= 62) || (skb_headroom(skb) < MV_HEADER_SIZE)) {
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if (pskb_expand_head(skb, MV_HEADER_SIZE, 0, GFP_ATOMIC))
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if (skb_cloned(skb) || (skb->len <= 62) || (skb_headroom(skb) < MV_HEADER_SIZE)) {
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if (pskb_expand_head(skb, MV_HEADER_SIZE, (skb->len < 62 ? 62 - skb->len : 0), GFP_ATOMIC))
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goto error_expand;
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if (skb->len < 62)
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skb->len = 62;
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@ -216,6 +216,20 @@ mvswitch_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
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}
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static int
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mvswitch_wait_mask(struct phy_device *pdev, int addr, int reg, u16 mask, u16 val)
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{
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int i = 100;
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u16 r;
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do {
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r = r16(pdev, addr, reg) & mask;
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if (r == val)
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return 0;
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} while(--i > 0);
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return -ETIMEDOUT;
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}
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static int
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mvswitch_config_init(struct phy_device *pdev)
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{
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@ -231,6 +245,7 @@ mvswitch_config_init(struct phy_device *pdev)
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pdev->supported = ADVERTISED_100baseT_Full;
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pdev->advertising = ADVERTISED_100baseT_Full;
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dev->phy_ptr = priv;
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dev->irq = PHY_POLL;
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/* initialize default vlans */
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for (i = 0; i < MV_PORTS; i++)
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@ -242,25 +257,22 @@ mvswitch_config_init(struct phy_device *pdev)
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msleep(2); /* wait for the status change to settle in */
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/* put the device in reset and set ATU flags */
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/* put the ATU in reset */
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w16(pdev, MV_SWITCHREG(ATU_CTRL), MV_ATUCTL_RESET);
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i = mvswitch_wait_mask(pdev, MV_SWITCHREG(ATU_CTRL), MV_ATUCTL_RESET, 0);
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if (i < 0) {
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printk("%s: Timeout waiting for the switch to reset.\n", dev->name);
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return i;
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}
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/* set the ATU flags */
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w16(pdev, MV_SWITCHREG(ATU_CTRL),
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MV_ATUCTL_RESET |
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MV_ATUCTL_NO_LEARN |
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MV_ATUCTL_ATU_1K |
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MV_ATUCTL_AGETIME(MV_ATUCTL_AGETIME_MIN) /* minimum without disabling ageing */
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);
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i = 100; /* timeout */
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do {
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if (!(r16(pdev, MV_SWITCHREG(ATU_CTRL)) & MV_ATUCTL_RESET))
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break;
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msleep(1);
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} while (--i > 0);
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if (!i) {
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printk("%s: Timeout waiting for the switch to reset.\n", dev->name);
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return -ETIMEDOUT;
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}
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/* initialize the cpu port */
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w16(pdev, MV_PORTREG(CONTROL, MV_CPUPORT),
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#ifdef HEADER_MODE
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@ -288,7 +300,7 @@ mvswitch_config_init(struct phy_device *pdev)
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}
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/* leave port unconfigured if it's not part of a vlan */
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if (!vlmap)
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break;
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continue;
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/* add the cpu port to the allowed destinations list */
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vlmap |= (1 << MV_CPUPORT);
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@ -299,19 +311,17 @@ mvswitch_config_init(struct phy_device *pdev)
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/* apply vlan settings */
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w16(pdev, MV_PORTREG(VLANMAP, i),
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MV_PORTVLAN_PORTS(vlmap) |
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MV_PORTVLAN_ID(pvid)
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MV_PORTVLAN_ID(i)
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);
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/* re-enable port */
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w16(pdev, MV_PORTREG(CONTROL, i), MV_PORTCTRL_ENABLED);
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w16(pdev, MV_PORTREG(CONTROL, i),
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MV_PORTCTRL_ENABLED
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);
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}
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/* build the target list for the cpu port */
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for (i = 0; i < MV_PORTS; i++)
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vlmap |= (1 << i);
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w16(pdev, MV_PORTREG(VLANMAP, MV_CPUPORT),
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MV_PORTVLAN_PORTS(vlmap)
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MV_PORTVLAN_ID(MV_CPUPORT)
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);
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/* set the port association vector */
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@ -343,11 +353,28 @@ mvswitch_config_init(struct phy_device *pdev)
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}
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static int
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mvswitch_read_status(struct phy_device *phydev)
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mvswitch_read_status(struct phy_device *pdev)
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{
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phydev->speed = SPEED_100;
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phydev->duplex = DUPLEX_FULL;
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phydev->state = PHY_UP;
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pdev->speed = SPEED_100;
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pdev->duplex = DUPLEX_FULL;
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pdev->state = PHY_UP;
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/* XXX ugly workaround: we can't force the switch
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* to gracefully handle hosts moving from one port to another,
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* so we have to regularly clear the ATU database */
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/* wait for the ATU to become available */
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mvswitch_wait_mask(pdev, MV_SWITCHREG(ATU_OP), MV_ATUOP_INPROGRESS, 0);
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/* flush the ATU */
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w16(pdev, MV_SWITCHREG(ATU_OP),
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MV_ATUOP_INPROGRESS |
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MV_ATUOP_FLUSH_ALL
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);
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/* wait for operation to complete */
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mvswitch_wait_mask(pdev, MV_SWITCHREG(ATU_OP), MV_ATUOP_INPROGRESS, 0);
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return 0;
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}
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@ -123,7 +123,21 @@ enum {
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MV_ATUCTL_ATUMASK = (3 << 12),
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MV_ATUCTL_NO_LEARN = (1 << 14),
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MV_ATUCTL_RESET = (1 << 15),
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}
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};
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enum {
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#define MV_ATUOP_DBNUM(_n) ((_n) & 0x0f)
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MV_ATUOP_NOOP = (0 << 12),
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MV_ATUOP_FLUSH_ALL = (1 << 12),
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MV_ATUOP_FLUSH_U = (2 << 12),
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MV_ATUOP_LOAD_DB = (3 << 12),
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MV_ATUOP_GET_NEXT = (4 << 12),
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MV_ATUOP_FLUSH_DB = (5 << 12),
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MV_ATUOP_FLUSH_DB_UU= (6 << 12),
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MV_ATUOP_INPROGRESS = (1 << 15),
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};
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#define MV_IDENT_MASK 0xfff0
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#define MV_IDENT_VALUE 0x0600
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@ -78,8 +78,8 @@ mvswitch_mangle_tx(struct sk_buff *skb, struct net_device *dev)
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if (__vlan_hwaccel_get_tag(skb, &vid))
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goto error;
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if ((skb->len <= 62) || (skb_headroom(skb) < MV_HEADER_SIZE)) {
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if (pskb_expand_head(skb, MV_HEADER_SIZE, 0, GFP_ATOMIC))
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if (skb_cloned(skb) || (skb->len <= 62) || (skb_headroom(skb) < MV_HEADER_SIZE)) {
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if (pskb_expand_head(skb, MV_HEADER_SIZE, (skb->len < 62 ? 62 - skb->len : 0), GFP_ATOMIC))
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goto error_expand;
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if (skb->len < 62)
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skb->len = 62;
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@ -216,6 +216,20 @@ mvswitch_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
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}
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static int
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mvswitch_wait_mask(struct phy_device *pdev, int addr, int reg, u16 mask, u16 val)
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{
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int i = 100;
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u16 r;
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do {
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r = r16(pdev, addr, reg) & mask;
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if (r == val)
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return 0;
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} while(--i > 0);
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return -ETIMEDOUT;
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}
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static int
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mvswitch_config_init(struct phy_device *pdev)
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{
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@ -231,6 +245,7 @@ mvswitch_config_init(struct phy_device *pdev)
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pdev->supported = ADVERTISED_100baseT_Full;
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pdev->advertising = ADVERTISED_100baseT_Full;
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dev->phy_ptr = priv;
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dev->irq = PHY_POLL;
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/* initialize default vlans */
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for (i = 0; i < MV_PORTS; i++)
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@ -242,25 +257,22 @@ mvswitch_config_init(struct phy_device *pdev)
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msleep(2); /* wait for the status change to settle in */
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/* put the device in reset and set ATU flags */
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/* put the ATU in reset */
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w16(pdev, MV_SWITCHREG(ATU_CTRL), MV_ATUCTL_RESET);
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i = mvswitch_wait_mask(pdev, MV_SWITCHREG(ATU_CTRL), MV_ATUCTL_RESET, 0);
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if (i < 0) {
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printk("%s: Timeout waiting for the switch to reset.\n", dev->name);
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return i;
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}
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/* set the ATU flags */
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w16(pdev, MV_SWITCHREG(ATU_CTRL),
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MV_ATUCTL_RESET |
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MV_ATUCTL_NO_LEARN |
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MV_ATUCTL_ATU_1K |
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MV_ATUCTL_AGETIME(MV_ATUCTL_AGETIME_MIN) /* minimum without disabling ageing */
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);
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i = 100; /* timeout */
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do {
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if (!(r16(pdev, MV_SWITCHREG(ATU_CTRL)) & MV_ATUCTL_RESET))
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break;
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msleep(1);
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} while (--i > 0);
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if (!i) {
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printk("%s: Timeout waiting for the switch to reset.\n", dev->name);
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return -ETIMEDOUT;
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}
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/* initialize the cpu port */
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w16(pdev, MV_PORTREG(CONTROL, MV_CPUPORT),
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#ifdef HEADER_MODE
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@ -288,7 +300,7 @@ mvswitch_config_init(struct phy_device *pdev)
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}
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/* leave port unconfigured if it's not part of a vlan */
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if (!vlmap)
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break;
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continue;
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/* add the cpu port to the allowed destinations list */
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vlmap |= (1 << MV_CPUPORT);
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@ -299,19 +311,17 @@ mvswitch_config_init(struct phy_device *pdev)
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/* apply vlan settings */
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w16(pdev, MV_PORTREG(VLANMAP, i),
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MV_PORTVLAN_PORTS(vlmap) |
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MV_PORTVLAN_ID(pvid)
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MV_PORTVLAN_ID(i)
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);
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/* re-enable port */
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w16(pdev, MV_PORTREG(CONTROL, i), MV_PORTCTRL_ENABLED);
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w16(pdev, MV_PORTREG(CONTROL, i),
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MV_PORTCTRL_ENABLED
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);
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}
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/* build the target list for the cpu port */
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for (i = 0; i < MV_PORTS; i++)
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vlmap |= (1 << i);
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w16(pdev, MV_PORTREG(VLANMAP, MV_CPUPORT),
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MV_PORTVLAN_PORTS(vlmap)
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MV_PORTVLAN_ID(MV_CPUPORT)
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);
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/* set the port association vector */
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@ -343,11 +353,28 @@ mvswitch_config_init(struct phy_device *pdev)
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}
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static int
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mvswitch_read_status(struct phy_device *phydev)
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mvswitch_read_status(struct phy_device *pdev)
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{
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phydev->speed = SPEED_100;
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phydev->duplex = DUPLEX_FULL;
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phydev->state = PHY_UP;
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pdev->speed = SPEED_100;
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pdev->duplex = DUPLEX_FULL;
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pdev->state = PHY_UP;
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/* XXX ugly workaround: we can't force the switch
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* to gracefully handle hosts moving from one port to another,
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* so we have to regularly clear the ATU database */
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/* wait for the ATU to become available */
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mvswitch_wait_mask(pdev, MV_SWITCHREG(ATU_OP), MV_ATUOP_INPROGRESS, 0);
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/* flush the ATU */
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w16(pdev, MV_SWITCHREG(ATU_OP),
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MV_ATUOP_INPROGRESS |
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MV_ATUOP_FLUSH_ALL
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);
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/* wait for operation to complete */
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mvswitch_wait_mask(pdev, MV_SWITCHREG(ATU_OP), MV_ATUOP_INPROGRESS, 0);
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return 0;
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}
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@ -123,7 +123,21 @@ enum {
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MV_ATUCTL_ATUMASK = (3 << 12),
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MV_ATUCTL_NO_LEARN = (1 << 14),
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MV_ATUCTL_RESET = (1 << 15),
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}
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};
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enum {
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#define MV_ATUOP_DBNUM(_n) ((_n) & 0x0f)
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MV_ATUOP_NOOP = (0 << 12),
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MV_ATUOP_FLUSH_ALL = (1 << 12),
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MV_ATUOP_FLUSH_U = (2 << 12),
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MV_ATUOP_LOAD_DB = (3 << 12),
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MV_ATUOP_GET_NEXT = (4 << 12),
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MV_ATUOP_FLUSH_DB = (5 << 12),
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MV_ATUOP_FLUSH_DB_UU= (6 << 12),
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MV_ATUOP_INPROGRESS = (1 << 15),
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};
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#define MV_IDENT_MASK 0xfff0
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#define MV_IDENT_VALUE 0x0600
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