bump to v3.8

Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 36014
2013-03-14 18:42:29 +00:00 · 2013-03-14 18:42:29 +00:00 · b98ae2b149
parent 3ab75692f3
commit b98ae2b149
43 changed files with 14590 additions and 1 deletions
--- a/target/linux/lantiq/Makefile
+++ b/target/linux/lantiq/Makefile
@ -11,7 +11,7 @@ BOARDNAME:=Lantiq GPON/XWAY/SVIP
 FEATURES:=squashfs jffs2
 SUBTARGETS=xway ase falcon

-LINUX_VERSION:=3.7.10
+LINUX_VERSION:=3.8.2

 CFLAGS=-Os -pipe -mips32r2 -mtune=mips32r2 -fno-caller-saves -mno-branch-likely

--- a/target/linux/lantiq/config-default
+++ b/target/linux/lantiq/config-default
@ -0,0 +1,163 @@
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_ARCH_SUPPORTS_MSI=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_CEVT_R4K=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CSRC_R4K=y
+CONFIG_CSRC_R4K_LIB=y
+# CONFIG_DEBUG_PINCTRL is not set
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DTC=y
+CONFIG_DT_EASY50712=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_ETHERNET_PACKET_MANGLE=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_MM_LANTIQ=y
+CONFIG_GPIO_STP_XWAY=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_WORK=y
+CONFIG_HAVE_MACH_CLKDEV=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ=250
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_I2C_MUX_PINCTRL is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQ_CPU=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_LANTIQ=y
+CONFIG_LANTIQ_ETOP=y
+CONFIG_LANTIQ_PHY=y
+CONFIG_LANTIQ_WDT=y
+CONFIG_LANTIQ_XRX200=y
+CONFIG_LEDS_GPIO=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MIPS=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+# CONFIG_MIPS_SEAD3 is not set
+# CONFIG_MIPS_VPE_LOADER is not set
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_LANTIQ=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_UIMAGE_SPLIT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DEVICE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PCI=y
+# CONFIG_PCIE_LANTIQ is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_LANTIQ=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_EXYNOS4 is not set
+CONFIG_PINCTRL_LANTIQ=y
+# CONFIG_PINCTRL_SAMSUNG is not set
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PINCTRL_XWAY=y
+CONFIG_PINMUX=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_PROC_DEVICETREE=y
+CONFIG_PSB6970_PHY=y
+CONFIG_RTL8366RB_PHY=y
+CONFIG_RTL8366_SMI=y
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_LANTIQ=y
+# CONFIG_SOC_AMAZON_SE is not set
+# CONFIG_SOC_FALCON is not set
+# CONFIG_SOC_SVIP is not set
+CONFIG_SOC_TYPE_XWAY=y
+CONFIG_SOC_XWAY=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SWCONFIG=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MULTITHREADING=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_UIDGID_CONVERTED=y
+CONFIG_USB_ARCH_HAS_XHCI=y
+CONFIG_USE_OF=y
+CONFIG_XRX200_PHY_FW=y
+CONFIG_ZONE_DMA_FLAG=0
--- a/target/linux/lantiq/patches-3.8/0001-MTD-m25p80-allow-loading-mtd-name-from-OF.patch
+++ b/target/linux/lantiq/patches-3.8/0001-MTD-m25p80-allow-loading-mtd-name-from-OF.patch
@ -0,0 +1,44 @@
+From e65ecb8f256b5839690a240d9b14e303686f9ede Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 29 Jan 2013 21:11:55 +0100
+Subject: [PATCH 01/40] MTD: m25p80: allow loading mtd name from OF
+
+In accordance with the physmap flash we should honour the linux,mtd-name
+property when deciding what name the mtd device has.
+
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mtd/devices/m25p80.c |    5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
+index 4eeeb2d..b12da33 100644
+--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
+@@ -810,10 +810,13 @@ static int m25p_probe(struct spi_device *spi)
+ 	unsigned			i;
+ 	struct mtd_part_parser_data	ppdata;
+ 	struct device_node __maybe_unused *np = spi->dev.of_node;
+	const char __maybe_unused	*of_mtd_name = NULL;
+ 
+ #ifdef CONFIG_MTD_OF_PARTS
+ 	if (!of_device_is_available(np))
+ 		return -ENODEV;
+	of_property_read_string(spi->dev.of_node,
+					"linux,mtd-name", &of_mtd_name);
+ #endif
+ 
+ 	/* Platform data helps sort out which chip type we have, as
+@@ -889,6 +892,8 @@ static int m25p_probe(struct spi_device *spi)
+ 
+ 	if (data && data->name)
+ 		flash->mtd.name = data->name;
+	else if (of_mtd_name)
+		flash->mtd.name = of_mtd_name;
+ 	else
+ 		flash->mtd.name = dev_name(&spi->dev);
+ 
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0002-SPI-MIPS-lantiq-make-use-of-spi_finalize_current_mes.patch
+++ b/target/linux/lantiq/patches-3.8/0002-SPI-MIPS-lantiq-make-use-of-spi_finalize_current_mes.patch
@ -0,0 +1,31 @@
+From 8b921ffd449431543832b0e76389eb289cc78bb8 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 29 Jan 2013 21:24:17 +0100
+Subject: [PATCH 02/40] SPI: MIPS: lantiq: make use of
+ spi_finalize_current_message
+
+Rather than calling m->complete() directly we choose the sane way and call
+spi_finalize_current_message instead.
+
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/spi/spi-falcon.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c
+index 6a6f62e..f9c66c2 100644
+--- a/drivers/spi/spi-falcon.c
+++ b/drivers/spi/spi-falcon.c
+@@ -398,7 +398,7 @@ static int falcon_sflash_xfer_one(struct spi_master *master,
+ 	}
+ 
+ 	m->status = ret;
+-	m->complete(m->context);
+	spi_finalize_current_message(master);
+ 
+ 	return 0;
+ }
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0003-SPI-MIPS-lantiq-set-SPI_MASTER_HALF_DUPLEX-flag.patch
+++ b/target/linux/lantiq/patches-3.8/0003-SPI-MIPS-lantiq-set-SPI_MASTER_HALF_DUPLEX-flag.patch
@ -0,0 +1,29 @@
+From a50f7db5b527c317c4bf2ae44a4ccdc8c7e598ab Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 29 Jan 2013 21:26:39 +0100
+Subject: [PATCH 03/40] SPI: MIPS: lantiq: set SPI_MASTER_HALF_DUPLEX flag
+
+Due to hardware limitations of the spi/flash frontend of the EBU we need to set
+the SPI_MASTER_HALF_DUPLEX flag.
+
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/spi/spi-falcon.c |    1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c
+index f9c66c2..c7a74f0 100644
+--- a/drivers/spi/spi-falcon.c
+++ b/drivers/spi/spi-falcon.c
+@@ -423,6 +423,7 @@ static int falcon_sflash_probe(struct platform_device *pdev)
+ 
+ 	master->mode_bits = SPI_MODE_3;
+ 	master->num_chipselect = 1;
+	master->flags = SPI_MASTER_HALF_DUPLEX;
+ 	master->bus_num = -1;
+ 	master->setup = falcon_sflash_setup;
+ 	master->prepare_transfer_hardware = falcon_sflash_prepare_xfer;
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0004-Document-devicetree-add-OF-documents-for-lantiq-seri.patch
+++ b/target/linux/lantiq/patches-3.8/0004-Document-devicetree-add-OF-documents-for-lantiq-seri.patch
@ -0,0 +1,39 @@
+From 8cd55f4107a3acda4793ed282a114af2f4cb4983 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 20 Jul 2012 18:58:34 +0200
+Subject: [PATCH 04/40] Document: devicetree: add OF documents for lantiq
+ serial port
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Cc: Rob Herring <rob.herring@calxeda.com>
+Cc: devicetree-discuss@lists.ozlabs.org
+---
+ .../devicetree/bindings/serial/lantiq_asc.txt          |   16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/serial/lantiq_asc.txt
+
+diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.txt b/Documentation/devicetree/bindings/serial/lantiq_asc.txt
+new file mode 100644
+index 0000000..5b78591
+--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/lantiq_asc.txt
+@@ -0,0 +1,16 @@
+Lantiq SoC ASC serial controller
+
+Required properties:
+- compatible : Should be "lantiq,asc"
+- reg : Address and length of the register set for the device
+- interrupts: the 3 (tx rx err) interrupt numbers. The interrupt specifier
+  depends on the interrupt-parent interrupt controller.
+
+Example:
+
+asc1: serial@E100C00 {
+	compatible = "lantiq,asc";
+	reg = <0xE100C00 0x400>;
+	interrupt-parent = <&icu0>;
+	interrupts = <112 113 114>;
+};
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0005-PINCTRL-lantiq-pinconf-uses-port-instead-of-pin.patch
+++ b/target/linux/lantiq/patches-3.8/0005-PINCTRL-lantiq-pinconf-uses-port-instead-of-pin.patch
@ -0,0 +1,92 @@
+From 5e19578b807e7ef6e7baf05fb1f69433d5e74667 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 30 Nov 2012 21:11:22 +0100
+Subject: [PATCH 05/40] PINCTRL: lantiq: pinconf uses port instead of pin
+
+The XWAY pinctrl driver invalidly uses the port and not the pin number to work
+out the registeres and bits to be set for the opendrain and pullup/down
+resistors.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/pinctrl/pinctrl-xway.c |   28 ++++++++++++++--------------
+ 1 file changed, 14 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
+index 5f0eb04..69dec9b 100644
+--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
+@@ -441,17 +441,17 @@ static int xway_pinconf_get(struct pinctrl_dev *pctldev,
+ 		if (port == PORT3)
+ 			reg = GPIO3_OD;
+ 		else
+-			reg = GPIO_OD(port);
+			reg = GPIO_OD(pin);
+ 		*config = LTQ_PINCONF_PACK(param,
+-			!!gpio_getbit(info->membase[0], reg, PORT_PIN(port)));
+			!!gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
+ 		break;
+ 
+ 	case LTQ_PINCONF_PARAM_PULL:
+ 		if (port == PORT3)
+ 			reg = GPIO3_PUDEN;
+ 		else
+-			reg = GPIO_PUDEN(port);
+-		if (!gpio_getbit(info->membase[0], reg, PORT_PIN(port))) {
+			reg = GPIO_PUDEN(pin);
+		if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) {
+ 			*config = LTQ_PINCONF_PACK(param, 0);
+ 			break;
+ 		}
+@@ -459,8 +459,8 @@ static int xway_pinconf_get(struct pinctrl_dev *pctldev,
+ 		if (port == PORT3)
+ 			reg = GPIO3_PUDSEL;
+ 		else
+-			reg = GPIO_PUDSEL(port);
+-		if (!gpio_getbit(info->membase[0], reg, PORT_PIN(port)))
+			reg = GPIO_PUDSEL(pin);
+		if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin)))
+ 			*config = LTQ_PINCONF_PACK(param, 2);
+ 		else
+ 			*config = LTQ_PINCONF_PACK(param, 1);
+@@ -488,29 +488,29 @@ static int xway_pinconf_set(struct pinctrl_dev *pctldev,
+ 		if (port == PORT3)
+ 			reg = GPIO3_OD;
+ 		else
+-			reg = GPIO_OD(port);
+-		gpio_setbit(info->membase[0], reg, PORT_PIN(port));
+			reg = GPIO_OD(pin);
+		gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
+ 		break;
+ 
+ 	case LTQ_PINCONF_PARAM_PULL:
+ 		if (port == PORT3)
+ 			reg = GPIO3_PUDEN;
+ 		else
+-			reg = GPIO_PUDEN(port);
+			reg = GPIO_PUDEN(pin);
+ 		if (arg == 0) {
+-			gpio_clearbit(info->membase[0], reg, PORT_PIN(port));
+			gpio_clearbit(info->membase[0], reg, PORT_PIN(pin));
+ 			break;
+ 		}
+-		gpio_setbit(info->membase[0], reg, PORT_PIN(port));
+		gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
+ 
+ 		if (port == PORT3)
+ 			reg = GPIO3_PUDSEL;
+ 		else
+-			reg = GPIO_PUDSEL(port);
+			reg = GPIO_PUDSEL(pin);
+ 		if (arg == 1)
+-			gpio_clearbit(info->membase[0], reg, PORT_PIN(port));
+			gpio_clearbit(info->membase[0], reg, PORT_PIN(pin));
+ 		else if (arg == 2)
+-			gpio_setbit(info->membase[0], reg, PORT_PIN(port));
+			gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
+ 		else
+ 			dev_err(pctldev->dev, "Invalid pull value %d\n", arg);
+ 		break;
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0006-PINCTRL-lantiq-faulty-bit-inversion.patch
+++ b/target/linux/lantiq/patches-3.8/0006-PINCTRL-lantiq-faulty-bit-inversion.patch
@ -0,0 +1,28 @@
+From 694063bb1049c6ff460f137a8011607103bad81b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 30 Jan 2013 18:14:23 +0100
+Subject: [PATCH 06/40] PINCTRL: lantiq: faulty bit inversion
+
+The logic of the OD bit was inverted when calling the pinconf get methode.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/pinctrl/pinctrl-xway.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
+index 69dec9b..c49c9db 100644
+--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
+@@ -443,7 +443,7 @@ static int xway_pinconf_get(struct pinctrl_dev *pctldev,
+ 		else
+ 			reg = GPIO_OD(pin);
+ 		*config = LTQ_PINCONF_PACK(param,
+-			!!gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
+			!gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
+ 		break;
+ 
+ 	case LTQ_PINCONF_PARAM_PULL:
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0007-PINCTRL-lantiq-add-pin_config_group_set-support.patch
+++ b/target/linux/lantiq/patches-3.8/0007-PINCTRL-lantiq-add-pin_config_group_set-support.patch
@ -0,0 +1,157 @@
+From 325ba34823f454c35c814d72022ba736ad56a1d4 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 30 Jan 2013 18:21:48 +0100
+Subject: [PATCH 07/40] PINCTRL: lantiq: add pin_config_group_set support
+
+While converting all the boards supported by OpenWrt to OF I noticed that this
+feature is missing. Adding it makes the devicetrees more readable.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/pinctrl/pinctrl-lantiq.c |   54 ++++++++++++++++++++++++--------------
+ drivers/pinctrl/pinctrl-xway.c   |   15 +++++++++++
+ 2 files changed, 49 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c
+index 15f501d..7d11072 100644
+--- a/drivers/pinctrl/pinctrl-lantiq.c
+++ b/drivers/pinctrl/pinctrl-lantiq.c
+@@ -64,11 +64,13 @@ static void ltq_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
+ 	seq_printf(s, " %s", dev_name(pctldev->dev));
+ }
+ 
+-static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+static void ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+ 				struct device_node *np,
+ 				struct pinctrl_map **map)
+ {
+ 	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
+	struct property *pins = of_find_property(np, "lantiq,pins", NULL);
+	struct property *groups = of_find_property(np, "lantiq,groups", NULL);
+ 	unsigned long configs[3];
+ 	unsigned num_configs = 0;
+ 	struct property *prop;
+@@ -76,8 +78,20 @@ static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+ 	const char *function;
+ 	int ret, i;
+ 
+	if (!pins && !groups) {
+		dev_err(pctldev->dev, "%s defines neither pins nor groups\n",
+			np->name);
+		return;
+	}
+
+	if (pins && groups) {
+		dev_err(pctldev->dev, "%s defines both pins and groups\n",
+			np->name);
+		return;
+	}
+
+ 	ret = of_property_read_string(np, "lantiq,function", &function);
+-	if (!ret) {
+	if (groups && !ret) {
+ 		of_property_for_each_string(np, "lantiq,groups", prop, group) {
+ 			(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
+ 			(*map)->name = function;
+@@ -85,11 +99,6 @@ static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+ 			(*map)->data.mux.function = function;
+ 			(*map)++;
+ 		}
+-		if (of_find_property(np, "lantiq,pins", NULL))
+-			dev_err(pctldev->dev,
+-				"%s mixes pins and groups settings\n",
+-				np->name);
+-		return 0;
+ 	}
+ 
+ 	for (i = 0; i < info->num_params; i++) {
+@@ -103,7 +112,7 @@ static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+ 	}
+ 
+ 	if (!num_configs)
+-		return -EINVAL;
+		return;
+ 
+ 	of_property_for_each_string(np, "lantiq,pins", prop, pin) {
+ 		(*map)->data.configs.configs = kmemdup(configs,
+@@ -115,7 +124,16 @@ static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+ 		(*map)->data.configs.num_configs = num_configs;
+ 		(*map)++;
+ 	}
+-	return 0;
+	of_property_for_each_string(np, "lantiq,groups", prop, group) {
+		(*map)->data.configs.configs = kmemdup(configs,
+					num_configs * sizeof(unsigned long),
+					GFP_KERNEL);
+		(*map)->type = PIN_MAP_TYPE_CONFIGS_GROUP;
+		(*map)->name = group;
+		(*map)->data.configs.group_or_pin = group;
+		(*map)->data.configs.num_configs = num_configs;
+		(*map)++;
+	}
+ }
+ 
+ static int ltq_pinctrl_dt_subnode_size(struct device_node *np)
+@@ -135,23 +153,19 @@ static int ltq_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+ {
+ 	struct pinctrl_map *tmp;
+ 	struct device_node *np;
+-	int ret;
+	int max_maps = 0;
+ 
+-	*num_maps = 0;
+ 	for_each_child_of_node(np_config, np)
+-		*num_maps += ltq_pinctrl_dt_subnode_size(np);
+-	*map = kzalloc(*num_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
+		max_maps += ltq_pinctrl_dt_subnode_size(np);
+	*map = kzalloc(max_maps * sizeof(struct pinctrl_map) * 2, GFP_KERNEL);
+ 	if (!*map)
+ 		return -ENOMEM;
+ 	tmp = *map;
+ 
+-	for_each_child_of_node(np_config, np) {
+-		ret = ltq_pinctrl_dt_subnode_to_map(pctldev, np, &tmp);
+-		if (ret < 0) {
+-			ltq_pinctrl_dt_free_map(pctldev, *map, *num_maps);
+-			return ret;
+-		}
+-	}
+	for_each_child_of_node(np_config, np)
+		ltq_pinctrl_dt_subnode_to_map(pctldev, np, &tmp);
+	*num_maps = ((int)(tmp - *map));
+
+ 	return 0;
+ }
+ 
+diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
+index c49c9db..aa4c8b8 100644
+--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
+@@ -522,9 +522,24 @@ static int xway_pinconf_set(struct pinctrl_dev *pctldev,
+ 	return 0;
+ }
+ 
+int xway_pinconf_group_set(struct pinctrl_dev *pctldev,
+			unsigned selector,
+			unsigned long config)
+{
+	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
+	int i, ret = 0;
+
+	for (i = 0; i < info->grps[selector].npins && !ret; i++)
+		ret = xway_pinconf_set(pctldev,
+				info->grps[selector].pins[i], config);
+
+	return ret;
+}
+
+ static struct pinconf_ops xway_pinconf_ops = {
+ 	.pin_config_get	= xway_pinconf_get,
+ 	.pin_config_set	= xway_pinconf_set,
+	.pin_config_group_set = xway_pinconf_group_set,
+ };
+ 
+ static struct pinctrl_desc xway_pctrl_desc = {
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0008-PINCTRL-lantiq-add-output-pinconf-parameter.patch
+++ b/target/linux/lantiq/patches-3.8/0008-PINCTRL-lantiq-add-output-pinconf-parameter.patch
@ -0,0 +1,68 @@
+From f9441b4f98b5b28f3d2cbebd0a70b227c35451d9 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 30 Jan 2013 18:33:39 +0100
+Subject: [PATCH 08/40] PINCTRL: lantiq: add output pinconf parameter
+
+While converting the boards inside OpenWrt to OF I noticed that the we are
+missing a pinconf parameter to set a pin to output.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/pinctrl/pinctrl-lantiq.h |    1 +
+ drivers/pinctrl/pinctrl-xway.c   |   14 ++++++++++++++
+ 2 files changed, 15 insertions(+)
+
+diff --git a/drivers/pinctrl/pinctrl-lantiq.h b/drivers/pinctrl/pinctrl-lantiq.h
+index 4419d32..6d07f02 100644
+--- a/drivers/pinctrl/pinctrl-lantiq.h
+++ b/drivers/pinctrl/pinctrl-lantiq.h
+@@ -34,6 +34,7 @@ enum ltq_pinconf_param {
+ 	LTQ_PINCONF_PARAM_OPEN_DRAIN,
+ 	LTQ_PINCONF_PARAM_DRIVE_CURRENT,
+ 	LTQ_PINCONF_PARAM_SLEW_RATE,
+	LTQ_PINCONF_PARAM_OUTPUT,
+ };
+ 
+ struct ltq_cfg_param {
+diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
+index aa4c8b8..b23b895 100644
+--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
+@@ -466,6 +466,11 @@ static int xway_pinconf_get(struct pinctrl_dev *pctldev,
+ 			*config = LTQ_PINCONF_PACK(param, 1);
+ 		break;
+ 
+	case LTQ_PINCONF_PARAM_OUTPUT:
+		reg = GPIO_DIR(pin);
+		*config = LTQ_PINCONF_PACK(param,
+			gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
+		break;
+ 	default:
+ 		dev_err(pctldev->dev, "Invalid config param %04x\n", param);
+ 		return -ENOTSUPP;
+@@ -515,6 +520,14 @@ static int xway_pinconf_set(struct pinctrl_dev *pctldev,
+ 			dev_err(pctldev->dev, "Invalid pull value %d\n", arg);
+ 		break;
+ 
+	case LTQ_PINCONF_PARAM_OUTPUT:
+		reg = GPIO_DIR(pin);
+		if (arg == 0)
+			gpio_clearbit(info->membase[0], reg, PORT_PIN(pin));
+		else
+			gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
+		break;
+
+ 	default:
+ 		dev_err(pctldev->dev, "Invalid config param %04x\n", param);
+ 		return -ENOTSUPP;
+@@ -573,6 +586,7 @@ static inline int xway_mux_apply(struct pinctrl_dev *pctrldev,
+ static const struct ltq_cfg_param xway_cfg_params[] = {
+ 	{"lantiq,pull",		LTQ_PINCONF_PARAM_PULL},
+ 	{"lantiq,open-drain",	LTQ_PINCONF_PARAM_OPEN_DRAIN},
+	{"lantiq,output",	LTQ_PINCONF_PARAM_OUTPUT},
+ };
+ 
+ static struct ltq_pinmux_info xway_info = {
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0009-PINCTRL-lantiq-the-pinconf-OD-parameter-argument-was.patch
+++ b/target/linux/lantiq/patches-3.8/0009-PINCTRL-lantiq-the-pinconf-OD-parameter-argument-was.patch
@ -0,0 +1,33 @@
+From 879fe8a24167983d2923f635cb37dc9e02f6cf57 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 30 Jan 2013 18:39:34 +0100
+Subject: [PATCH 09/40] PINCTRL: lantiq: the pinconf OD parameter argument was
+ ignored
+
+When setting the OpenDrain bit we should really honour the argument passed
+inside the devicetree.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/pinctrl/pinctrl-xway.c |    5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
+index b23b895..53cb6a3 100644
+--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
+@@ -494,7 +494,10 @@ static int xway_pinconf_set(struct pinctrl_dev *pctldev,
+ 			reg = GPIO3_OD;
+ 		else
+ 			reg = GPIO_OD(pin);
+-		gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
+		if (arg == 0)
+			gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
+		else
+			gpio_clearbit(info->membase[0], reg, PORT_PIN(pin));
+ 		break;
+ 
+ 	case LTQ_PINCONF_PARAM_PULL:
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0010-PINCTRL-lantiq-only-probe-available-pad-controllers.patch
+++ b/target/linux/lantiq/patches-3.8/0010-PINCTRL-lantiq-only-probe-available-pad-controllers.patch
@ -0,0 +1,30 @@
+From 997390a8802e21b4b57d0ffcd91ad64651f1c2bf Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 30 Jan 2013 20:02:06 +0100
+Subject: [PATCH 10/40] PINCTRL: lantiq: only probe available pad controllers
+
+The template falcon.dtsi lists all 6 pad controllers that can be loaded. Only
+probe those that have status = "okay"; inside the dts file.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/pinctrl/pinctrl-falcon.c |    3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c
+index 8ed20e8..6331c5c 100644
+--- a/drivers/pinctrl/pinctrl-falcon.c
+++ b/drivers/pinctrl/pinctrl-falcon.c
+@@ -398,6 +398,9 @@ static int pinctrl_falcon_probe(struct platform_device *pdev)
+ 		u32 avail;
+ 		int pins;
+ 
+		if (!of_device_is_available(np))
+			continue;
+
+ 		if (!ppdev) {
+ 			dev_err(&pdev->dev, "failed to find pad pdev\n");
+ 			continue;
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0011-PINCTRL-lantiq-one-of-the-boot-leds-was-defined-inco.patch
+++ b/target/linux/lantiq/patches-3.8/0011-PINCTRL-lantiq-one-of-the-boot-leds-was-defined-inco.patch
@ -0,0 +1,30 @@
+From b416a5be614733792cf5fbfce31b6733c37ffa3f Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 30 Jan 2013 20:07:51 +0100
+Subject: [PATCH 11/40] PINCTRL: lantiq: one of the boot leds was defined
+ incorrectly
+
+On the Falcon SoC the bootleds are located on pins 9->14.
+
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/pinctrl/pinctrl-falcon.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c
+index 6331c5c..249a405 100644
+--- a/drivers/pinctrl/pinctrl-falcon.c
+++ b/drivers/pinctrl/pinctrl-falcon.c
+@@ -170,7 +170,7 @@ static const unsigned pins_ntr[] = {GPIO4};
+ static const unsigned pins_ntr8k[] = {GPIO5};
+ static const unsigned pins_hrst[] = {GPIO6};
+ static const unsigned pins_mdio[] = {GPIO7, GPIO8};
+-static const unsigned pins_bled[] = {GPIO7, GPIO10, GPIO11,
+static const unsigned pins_bled[] = {GPIO9, GPIO10, GPIO11,
+ 					GPIO12, GPIO13, GPIO14};
+ static const unsigned pins_asc0[] = {GPIO32, GPIO33};
+ static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36};
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0012-PINCTRL-lantiq-fix-pinconfig-parameters.patch
+++ b/target/linux/lantiq/patches-3.8/0012-PINCTRL-lantiq-fix-pinconfig-parameters.patch
@ -0,0 +1,30 @@
+From ea1a25a2ca058e4b35c5763774e7fad6ab928418 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 30 Jan 2013 20:10:20 +0100
+Subject: [PATCH 12/40] PINCTRL: lantiq: fix pinconfig parameters
+
+The Falcon driver only defined the pinconf parameters but did not pass them
+properly to the underlying api.
+
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/pinctrl/pinctrl-falcon.c |    2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c
+index 249a405..c5a9868 100644
+--- a/drivers/pinctrl/pinctrl-falcon.c
+++ b/drivers/pinctrl/pinctrl-falcon.c
+@@ -360,6 +360,8 @@ static const struct ltq_cfg_param falcon_cfg_params[] = {
+ static struct ltq_pinmux_info falcon_info = {
+ 	.desc		= &falcon_pctrl_desc,
+ 	.apply_mux	= falcon_mux_apply,
+	.params		= falcon_cfg_params,
+	.num_params	= ARRAY_SIZE(falcon_cfg_params),
+ };
+ 
+ 
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0013-PINCTRL-lantiq-add-functionality-to-falcon_pinconf_d.patch
+++ b/target/linux/lantiq/patches-3.8/0013-PINCTRL-lantiq-add-functionality-to-falcon_pinconf_d.patch
@ -0,0 +1,60 @@
+From 98d06bc9e2a2f534aaaf4229aaf871e394234d20 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 30 Jan 2013 20:13:09 +0100
+Subject: [PATCH 13/40] PINCTRL: lantiq: add functionality to
+ falcon_pinconf_dbg_show
+
+The current code only has a stub for falcon_pinconf_dbg_show. This patch adds
+proper functionality.
+
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/pinctrl/pinctrl-falcon.c |   31 +++++++++++++++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+
+diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c
+index c5a9868..4a0d54a 100644
+--- a/drivers/pinctrl/pinctrl-falcon.c
+++ b/drivers/pinctrl/pinctrl-falcon.c
+@@ -315,6 +315,37 @@ static int falcon_pinconf_set(struct pinctrl_dev *pctrldev,
+ static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev,
+ 			struct seq_file *s, unsigned offset)
+ {
+	unsigned long config;
+	struct pin_desc *desc;
+
+	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
+	int port = PORT(offset);
+
+	seq_printf(s, " (port %d) mux %d -- ", port,
+		pad_r32(info->membase[port], LTQ_PADC_MUX(PORT_PIN(offset))));
+
+	config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_PULL, 0);
+	if (!falcon_pinconf_get(pctrldev, offset, &config))
+		seq_printf(s, "pull %d ",
+			(int)LTQ_PINCONF_UNPACK_ARG(config));
+
+	config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_DRIVE_CURRENT, 0);
+	if (!falcon_pinconf_get(pctrldev, offset, &config))
+		seq_printf(s, "drive-current %d ",
+			(int)LTQ_PINCONF_UNPACK_ARG(config));
+
+	config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_SLEW_RATE, 0);
+	if (!falcon_pinconf_get(pctrldev, offset, &config))
+		seq_printf(s, "slew-rate %d ",
+			(int)LTQ_PINCONF_UNPACK_ARG(config));
+
+	desc = pin_desc_get(pctrldev, offset);
+	if (desc) {
+		if (desc->gpio_owner)
+			seq_printf(s, " owner: %s", desc->gpio_owner);
+	} else {
+		seq_printf(s, " not registered");
+	}
+ }
+ 
+ static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev,
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0014-PINCTRL-lantiq-fix-pin-availability-check.patch
+++ b/target/linux/lantiq/patches-3.8/0014-PINCTRL-lantiq-fix-pin-availability-check.patch
@ -0,0 +1,43 @@
+From 51d5029bd9cd0ff85e1df87a4df57e544c52dc34 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 30 Jan 2013 20:16:22 +0100
+Subject: [PATCH 14/40] PINCTRL: lantiq: fix pin availability check
+
+The clock needs to be activated for the check to work. In order to be compatible
+with future silicon make sure that at least 1 pin is available before probing
+the pad controller.
+
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/pinctrl/pinctrl-falcon.c |   11 ++++++++---
+ 1 file changed, 8 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c
+index 4a0d54a..de9d1db 100644
+--- a/drivers/pinctrl/pinctrl-falcon.c
+++ b/drivers/pinctrl/pinctrl-falcon.c
+@@ -455,12 +455,17 @@ static int pinctrl_falcon_probe(struct platform_device *pdev)
+ 				*bank);
+ 			return -ENOMEM;
+ 		}
+		clk_activate(falcon_info.clk[*bank]);
+ 		avail = pad_r32(falcon_info.membase[*bank],
+ 					LTQ_PADC_AVAIL);
+ 		pins = fls(avail);
+-		lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins);
+-		pad_count += pins;
+-		clk_enable(falcon_info.clk[*bank]);
+		if (pins) {
+			lantiq_load_pin_desc(&falcon_pads[pad_count],
+								*bank, pins);
+			pad_count += pins;
+		} else {
+			clk_deactivate(falcon_info.clk[*bank]);
+		}
+ 		dev_dbg(&pdev->dev, "found %s with %d pads\n",
+ 				res.name, pins);
+ 	}
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0015-PINCTRL-lantiq-fix-pin-number-in-ltq_pmx_gpio_reques.patch
+++ b/target/linux/lantiq/patches-3.8/0015-PINCTRL-lantiq-fix-pin-number-in-ltq_pmx_gpio_reques.patch
@ -0,0 +1,31 @@
+From 363f0d3dc146215744363db97606a357310fad3d Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 30 Jan 2013 21:23:22 +0100
+Subject: [PATCH 15/40] PINCTRL: lantiq: fix pin number in
+ ltq_pmx_gpio_request_enable
+
+The mapping logic inside ltq_pmx_gpio_request_enable() was broken. This only
+effected Falcon SoC.
+
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/pinctrl/pinctrl-lantiq.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c
+index 7d11072..a703846 100644
+--- a/drivers/pinctrl/pinctrl-lantiq.c
+++ b/drivers/pinctrl/pinctrl-lantiq.c
+@@ -294,7 +294,7 @@ static int ltq_pmx_gpio_request_enable(struct pinctrl_dev *pctrldev,
+ 				unsigned pin)
+ {
+ 	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
+-	int mfp = match_mfp(info, pin + (range->id * 32));
+	int mfp = match_mfp(info, pin);
+ 	int pin_func;
+ 
+ 	if (mfp < 0) {
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0016-MIPS-lantiq-trivial-typo-fix.patch
+++ b/target/linux/lantiq/patches-3.8/0016-MIPS-lantiq-trivial-typo-fix.patch
@ -0,0 +1,29 @@
+From cc64558db2d91e89e1de174b6ad4a159ac27bf8b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sat, 19 Jan 2013 08:54:23 +0000
+Subject: [PATCH 16/40] MIPS: lantiq: trivial typo fix
+
+"nodes" is written with a single "s"
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4814/
+---
+ arch/mips/lantiq/xway/sysctrl.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
+index 3925e66..1aaa726 100644
+--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
+@@ -305,7 +305,7 @@ void __init ltq_soc_init(void)
+ 
+ 	/* check if all the core register ranges are available */
+ 	if (!np_pmu || !np_cgu || !np_ebu)
+-		panic("Failed to load core nodess from devicetree");
+		panic("Failed to load core nodes from devicetree");
+ 
+ 	if (of_address_to_resource(np_pmu, 0, &res_pmu) ||
+ 			of_address_to_resource(np_cgu, 0, &res_cgu) ||
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0017-MIPS-lantiq-adds-static-clock-for-PP32.patch
+++ b/target/linux/lantiq/patches-3.8/0017-MIPS-lantiq-adds-static-clock-for-PP32.patch
@ -0,0 +1,219 @@
+From 46a704b1b093f4053eceaf8e5f0ab54949afa532 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sat, 19 Jan 2013 08:54:24 +0000
+Subject: [PATCH 17/40] MIPS: lantiq: adds static clock for PP32
+
+The Lantiq DSL SoCs have an internal networking processor. Add code to read
+the static clock rate.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4815/
+---
+ arch/mips/include/asm/mach-lantiq/lantiq.h |    1 +
+ arch/mips/lantiq/clk.c                     |   12 ++++++--
+ arch/mips/lantiq/clk.h                     |    7 ++++-
+ arch/mips/lantiq/falcon/sysctrl.c          |    4 +--
+ arch/mips/lantiq/xway/clk.c                |   43 ++++++++++++++++++++++++++++
+ arch/mips/lantiq/xway/sysctrl.c            |   12 ++++----
+ 6 files changed, 69 insertions(+), 10 deletions(-)
+
+diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
+index 5e8a6e9..76be7a0 100644
+--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
+@@ -41,6 +41,7 @@ extern void clk_deactivate(struct clk *clk);
+ extern struct clk *clk_get_cpu(void);
+ extern struct clk *clk_get_fpi(void);
+ extern struct clk *clk_get_io(void);
+extern struct clk *clk_get_ppe(void);
+ 
+ /* find out what bootsource we have */
+ extern unsigned char ltq_boot_select(void);
+diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
+index ce2f129..d903560 100644
+--- a/arch/mips/lantiq/clk.c
+++ b/arch/mips/lantiq/clk.c
+@@ -26,13 +26,15 @@
+ #include "prom.h"
+ 
+ /* lantiq socs have 3 static clocks */
+-static struct clk cpu_clk_generic[3];
+static struct clk cpu_clk_generic[4];
+ 
+-void clkdev_add_static(unsigned long cpu, unsigned long fpi, unsigned long io)
+void clkdev_add_static(unsigned long cpu, unsigned long fpi,
+			unsigned long io, unsigned long ppe)
+ {
+ 	cpu_clk_generic[0].rate = cpu;
+ 	cpu_clk_generic[1].rate = fpi;
+ 	cpu_clk_generic[2].rate = io;
+	cpu_clk_generic[3].rate = ppe;
+ }
+ 
+ struct clk *clk_get_cpu(void)
+@@ -51,6 +53,12 @@ struct clk *clk_get_io(void)
+ 	return &cpu_clk_generic[2];
+ }
+ 
+struct clk *clk_get_ppe(void)
+{
+	return &cpu_clk_generic[3];
+}
+EXPORT_SYMBOL_GPL(clk_get_ppe);
+
+ static inline int clk_good(struct clk *clk)
+ {
+ 	return clk && !IS_ERR(clk);
+diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h
+index fa67060..77e4bdb 100644
+--- a/arch/mips/lantiq/clk.h
+++ b/arch/mips/lantiq/clk.h
+@@ -27,12 +27,15 @@
+ #define CLOCK_167M	166666667
+ #define CLOCK_196_608M	196608000
+ #define CLOCK_200M	200000000
+#define CLOCK_222M	222000000
+#define CLOCK_240M	240000000
+ #define CLOCK_250M	250000000
+ #define CLOCK_266M	266666666
+ #define CLOCK_300M	300000000
+ #define CLOCK_333M	333333333
+ #define CLOCK_393M	393215332
+ #define CLOCK_400M	400000000
+#define CLOCK_450M	450000000
+ #define CLOCK_500M	500000000
+ #define CLOCK_600M	600000000
+ 
+@@ -64,15 +67,17 @@ struct clk {
+ };
+ 
+ extern void clkdev_add_static(unsigned long cpu, unsigned long fpi,
+-				unsigned long io);
+				unsigned long io, unsigned long ppe);
+ 
+ extern unsigned long ltq_danube_cpu_hz(void);
+ extern unsigned long ltq_danube_fpi_hz(void);
+extern unsigned long ltq_danube_pp32_hz(void);
+ 
+ extern unsigned long ltq_ar9_cpu_hz(void);
+ extern unsigned long ltq_ar9_fpi_hz(void);
+ 
+ extern unsigned long ltq_vr9_cpu_hz(void);
+ extern unsigned long ltq_vr9_fpi_hz(void);
+extern unsigned long ltq_vr9_pp32_hz(void);
+ 
+ #endif
+diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
+index 2d4ced3..ff4894a 100644
+--- a/arch/mips/lantiq/falcon/sysctrl.c
+++ b/arch/mips/lantiq/falcon/sysctrl.c
+@@ -241,9 +241,9 @@ void __init ltq_soc_init(void)
+ 
+ 	/* get our 3 static rates for cpu, fpi and io clocks */
+ 	if (ltq_sys1_r32(SYS1_CPU0CC) & CPU0CC_CPUDIV)
+-		clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M);
+		clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M, 0);
+ 	else
+-		clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M);
+		clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M, 0);
+ 
+ 	/* add our clock domains */
+ 	clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0);
+diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c
+index 9aa17f7..1ab576d 100644
+--- a/arch/mips/lantiq/xway/clk.c
+++ b/arch/mips/lantiq/xway/clk.c
+@@ -53,6 +53,29 @@ unsigned long ltq_danube_cpu_hz(void)
+ 	}
+ }
+ 
+unsigned long ltq_danube_pp32_hz(void)
+{
+	unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 7) & 3;
+	unsigned long clk;
+
+	switch (clksys) {
+	case 1:
+		clk = CLOCK_240M;
+		break;
+	case 2:
+		clk = CLOCK_222M;
+		break;
+	case 3:
+		clk = CLOCK_133M;
+		break;
+	default:
+		clk = CLOCK_266M;
+		break;
+	}
+
+	return clk;
+}
+
+ unsigned long ltq_ar9_sys_hz(void)
+ {
+ 	if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2)
+@@ -149,3 +172,23 @@ unsigned long ltq_vr9_fpi_hz(void)
+ 
+ 	return clk;
+ }
+
+unsigned long ltq_vr9_pp32_hz(void)
+{
+	unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 3;
+	unsigned long clk;
+
+	switch (clksys) {
+	case 1:
+		clk = CLOCK_450M;
+		break;
+	case 2:
+		clk = CLOCK_300M;
+		break;
+	default:
+		clk = CLOCK_500M;
+		break;
+	}
+
+	return clk;
+}
+diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
+index 1aaa726..3390fcd 100644
+--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
+@@ -356,14 +356,16 @@ void __init ltq_soc_init(void)
+ 
+ 	if (of_machine_is_compatible("lantiq,ase")) {
+ 		if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
+-			clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
+			clkdev_add_static(CLOCK_266M, CLOCK_133M,
+						CLOCK_133M, CLOCK_266M);
+ 		else
+-			clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
+			clkdev_add_static(CLOCK_133M, CLOCK_133M,
+						CLOCK_133M, CLOCK_133M);
+ 		clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY),
+ 		clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY);
+ 	} else if (of_machine_is_compatible("lantiq,vr9")) {
+ 		clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
+-				ltq_vr9_fpi_hz());
+				ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
+ 		clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY);
+ 		clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK);
+ 		clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI);
+@@ -376,10 +378,10 @@ void __init ltq_soc_init(void)
+ 				PMU_PPE_QSB | PMU_PPE_TOP);
+ 	} else if (of_machine_is_compatible("lantiq,ar9")) {
+ 		clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
+-				ltq_ar9_fpi_hz());
+				ltq_ar9_fpi_hz(), CLOCK_250M);
+ 		clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH);
+ 	} else {
+ 		clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
+-				ltq_danube_fpi_hz());
+				ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
+ 	}
+ }
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0018-MIPS-lantiq-improve-pci-reset-gpio-handling.patch
+++ b/target/linux/lantiq/patches-3.8/0018-MIPS-lantiq-improve-pci-reset-gpio-handling.patch
@ -0,0 +1,40 @@
+From b6684dd3036513e4f91986fe982356512458f711 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sat, 19 Jan 2013 08:54:26 +0000
+Subject: [PATCH 18/40] MIPS: lantiq: improve pci reset gpio handling
+
+We need to make sure that the reset gpio is available and also set a sane
+default state.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4817/
+---
+ arch/mips/pci/pci-lantiq.c |   12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
+index 9568178..f32664b 100644
+--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
+@@ -129,8 +129,16 @@ static int ltq_pci_startup(struct platform_device *pdev)
+ 
+ 	/* setup reset gpio used by pci */
+ 	reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
+-	if (gpio_is_valid(reset_gpio))
+-		devm_gpio_request(&pdev->dev, reset_gpio, "pci-reset");
+	if (gpio_is_valid(reset_gpio)) {
+		int ret = devm_gpio_request(&pdev->dev,
+						reset_gpio, "pci-reset");
+		if (ret) {
+			dev_err(&pdev->dev,
+				"failed to request gpio %d\n", reset_gpio);
+			return ret;
+		}
+		gpio_direction_output(reset_gpio, 1);
+	}
+ 
+ 	/* enable auto-switching between PCI and EBU */
+ 	ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0019-MIPS-lantiq-rework-external-irq-code.patch
+++ b/target/linux/lantiq/patches-3.8/0019-MIPS-lantiq-rework-external-irq-code.patch
@ -0,0 +1,216 @@
+From d8f6bf3fb606ee8fdd5b7aff4aedb54e30792b84 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sat, 19 Jan 2013 08:54:27 +0000
+Subject: [PATCH 19/40] MIPS: lantiq: rework external irq code
+
+This code makes the irqs used by the EIU loadable from the DT. Additionally we
+add a helper that allows the pinctrl layer to map external irqs to real irq
+numbers.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4818/
+---
+ arch/mips/include/asm/mach-lantiq/lantiq.h |    1 +
+ arch/mips/lantiq/irq.c                     |  105 +++++++++++++++++++---------
+ 2 files changed, 74 insertions(+), 32 deletions(-)
+
+diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
+index 76be7a0..f196cce 100644
+--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
+@@ -34,6 +34,7 @@ extern spinlock_t ebu_lock;
+ extern void ltq_disable_irq(struct irq_data *data);
+ extern void ltq_mask_and_ack_irq(struct irq_data *data);
+ extern void ltq_enable_irq(struct irq_data *data);
+extern int ltq_eiu_get_irq(int exin);
+ 
+ /* clock handling */
+ extern int clk_activate(struct clk *clk);
+diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
+index a7935bf..5119487 100644
+--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
+@@ -33,17 +33,10 @@
+ /* register definitions - external irqs */
+ #define LTQ_EIU_EXIN_C		0x0000
+ #define LTQ_EIU_EXIN_INIC	0x0004
+#define LTQ_EIU_EXIN_INC	0x0008
+ #define LTQ_EIU_EXIN_INEN	0x000C
+ 
+-/* irq numbers used by the external interrupt unit (EIU) */
+-#define LTQ_EIU_IR0		(INT_NUM_IM4_IRL0 + 30)
+-#define LTQ_EIU_IR1		(INT_NUM_IM3_IRL0 + 31)
+-#define LTQ_EIU_IR2		(INT_NUM_IM1_IRL0 + 26)
+-#define LTQ_EIU_IR3		INT_NUM_IM1_IRL0
+-#define LTQ_EIU_IR4		(INT_NUM_IM1_IRL0 + 1)
+-#define LTQ_EIU_IR5		(INT_NUM_IM1_IRL0 + 2)
+-#define LTQ_EIU_IR6		(INT_NUM_IM2_IRL0 + 30)
+-#define XWAY_EXIN_COUNT		3
+/* number of external interrupts */
+ #define MAX_EIU			6
+ 
+ /* the performance counter */
+@@ -72,20 +65,19 @@
+ int gic_present;
+ #endif
+ 
+-static unsigned short ltq_eiu_irq[MAX_EIU] = {
+-	LTQ_EIU_IR0,
+-	LTQ_EIU_IR1,
+-	LTQ_EIU_IR2,
+-	LTQ_EIU_IR3,
+-	LTQ_EIU_IR4,
+-	LTQ_EIU_IR5,
+-};
+-
+ static int exin_avail;
+static struct resource ltq_eiu_irq[MAX_EIU];
+ static void __iomem *ltq_icu_membase[MAX_IM];
+ static void __iomem *ltq_eiu_membase;
+ static struct irq_domain *ltq_domain;
+ 
+int ltq_eiu_get_irq(int exin)
+{
+	if (exin < exin_avail)
+		return ltq_eiu_irq[exin].start;
+	return -1;
+}
+
+ void ltq_disable_irq(struct irq_data *d)
+ {
+ 	u32 ier = LTQ_ICU_IM0_IER;
+@@ -128,19 +120,65 @@ void ltq_enable_irq(struct irq_data *d)
+ 	ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
+ }
+ 
+static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
+{
+	int i;
+
+	for (i = 0; i < MAX_EIU; i++) {
+		if (d->hwirq == ltq_eiu_irq[i].start) {
+			int val = 0;
+			int edge = 0;
+
+			switch (type) {
+			case IRQF_TRIGGER_NONE:
+				break;
+			case IRQF_TRIGGER_RISING:
+				val = 1;
+				edge = 1;
+				break;
+			case IRQF_TRIGGER_FALLING:
+				val = 2;
+				edge = 1;
+				break;
+			case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
+				val = 3;
+				edge = 1;
+				break;
+			case IRQF_TRIGGER_HIGH:
+				val = 5;
+				break;
+			case IRQF_TRIGGER_LOW:
+				val = 6;
+				break;
+			default:
+				pr_err("invalid type %d for irq %ld\n",
+					type, d->hwirq);
+				return -EINVAL;
+			}
+
+			if (edge)
+				irq_set_handler(d->hwirq, handle_edge_irq);
+
+			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
+				(val << (i * 4)), LTQ_EIU_EXIN_C);
+		}
+	}
+
+	return 0;
+}
+
+ static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
+ {
+ 	int i;
+ 
+ 	ltq_enable_irq(d);
+ 	for (i = 0; i < MAX_EIU; i++) {
+-		if (d->hwirq == ltq_eiu_irq[i]) {
+-			/* low level - we should really handle set_type */
+-			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
+-				(0x6 << (i * 4)), LTQ_EIU_EXIN_C);
+		if (d->hwirq == ltq_eiu_irq[i].start) {
+			/* by default we are low level triggered */
+			ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
+ 			/* clear all pending */
+-			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~BIT(i),
+-				LTQ_EIU_EXIN_INIC);
+			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i),
+				LTQ_EIU_EXIN_INC);
+ 			/* enable */
+ 			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
+ 				LTQ_EIU_EXIN_INEN);
+@@ -157,7 +195,7 @@ static void ltq_shutdown_eiu_irq(struct irq_data *d)
+ 
+ 	ltq_disable_irq(d);
+ 	for (i = 0; i < MAX_EIU; i++) {
+-		if (d->hwirq == ltq_eiu_irq[i]) {
+		if (d->hwirq == ltq_eiu_irq[i].start) {
+ 			/* disable */
+ 			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
+ 				LTQ_EIU_EXIN_INEN);
+@@ -186,6 +224,7 @@ static struct irq_chip ltq_eiu_type = {
+ 	.irq_ack = ltq_ack_irq,
+ 	.irq_mask = ltq_disable_irq,
+ 	.irq_mask_ack = ltq_mask_and_ack_irq,
+	.irq_set_type = ltq_eiu_settype,
+ };
+ 
+ static void ltq_hw_irqdispatch(int module)
+@@ -301,7 +340,7 @@ static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
+ 		return 0;
+ 
+ 	for (i = 0; i < exin_avail; i++)
+-		if (hw == ltq_eiu_irq[i])
+		if (hw == ltq_eiu_irq[i].start)
+ 			chip = &ltq_eiu_type;
+ 
+ 	irq_set_chip_and_handler(hw, chip, handle_level_irq);
+@@ -323,7 +362,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
+ {
+ 	struct device_node *eiu_node;
+ 	struct resource res;
+-	int i;
+	int i, ret;
+ 
+ 	for (i = 0; i < MAX_IM; i++) {
+ 		if (of_address_to_resource(node, i, &res))
+@@ -340,17 +379,19 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
+ 	}
+ 
+ 	/* the external interrupts are optional and xway only */
+-	eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu");
+	eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
+ 	if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
+ 		/* find out how many external irq sources we have */
+-		const __be32 *count = of_get_property(node,
+-							"lantiq,count",	NULL);
+		exin_avail = of_irq_count(eiu_node);
+ 
+-		if (count)
+-			exin_avail = *count;
+ 		if (exin_avail > MAX_EIU)
+ 			exin_avail = MAX_EIU;
+ 
+		ret = of_irq_to_resource_table(eiu_node,
+						ltq_eiu_irq, exin_avail);
+		if (ret != exin_avail)
+			panic("failed to load external irq resources\n");
+
+ 		if (request_mem_region(res.start, resource_size(&res),
+ 							res.name) < 0)
+ 			pr_err("Failed to request eiu memory");
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0020-MIPS-lantiq-adds-4dword-burst-length-for-dma.patch
+++ b/target/linux/lantiq/patches-3.8/0020-MIPS-lantiq-adds-4dword-burst-length-for-dma.patch
@ -0,0 +1,34 @@
+From 5be3837d01ea56e1455781f1b51764bd896973f2 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 6 Dec 2012 11:59:23 +0100
+Subject: [PATCH 20/40] MIPS: lantiq: adds 4dword burst length for dma
+
+---
+ arch/mips/lantiq/xway/dma.c |    4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
+index e44a186..c7684c9 100644
+--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
+@@ -47,6 +47,7 @@
+ #define DMA_IRQ_ACK		0x7e		/* IRQ status register */
+ #define DMA_POLL		BIT(31)		/* turn on channel polling */
+ #define DMA_CLK_DIV4		BIT(6)		/* polling clock divider */
+#define DMA_4W_BURST		BIT(2)		/* 4 word burst length */
+ #define DMA_2W_BURST		BIT(1)		/* 2 word burst length */
+ #define DMA_MAX_CHANNEL		20		/* the soc has 20 channels */
+ #define DMA_ETOP_ENDIANNESS	(0xf << 8) /* endianness swap etop channels */
+@@ -195,7 +196,8 @@ ltq_dma_init_port(int p)
+ 		 * Tell the DMA engine to swap the endianness of data frames and
+ 		 * drop packets if the channel arbitration fails.
+ 		 */
+-		ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN,
+		ltq_dma_w32_mask(0, (DMA_4W_BURST << 4) | (DMA_4W_BURST << 2) |
+			DMA_ETOP_ENDIANNESS | DMA_PDEN,
+ 			LTQ_DMA_PCTRL);
+ 		break;
+ 
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0021-GPIO-MIPS-add-gpio-driver-for-falcon-SoC.patch
+++ b/target/linux/lantiq/patches-3.8/0021-GPIO-MIPS-add-gpio-driver-for-falcon-SoC.patch
@ -0,0 +1,404 @@
+From ff3d0dd789882ad552a5224d34e5db426e1c45fe Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sat, 23 Jun 2012 15:32:33 +0200
+Subject: [PATCH 21/40] GPIO: MIPS: add gpio driver for falcon SoC
+
+Add driver for GPIO blocks found on Lantiq FALCON SoC. The SoC has 5 banks of
+up to 32 pads. The GPIO blocks have a per pin IRQs.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Cc: linux-kernel@vger.kernel.org
+---
+ drivers/gpio/Kconfig       |    5 +
+ drivers/gpio/Makefile      |    1 +
+ drivers/gpio/gpio-falcon.c |  349 ++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 355 insertions(+)
+ create mode 100644 drivers/gpio/gpio-falcon.c
+
+diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
+index 682de75..e8d84fa 100644
+--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
+@@ -133,6 +133,11 @@ config GPIO_EP93XX
+ 	depends on ARCH_EP93XX
+ 	select GPIO_GENERIC
+ 
+config GPIO_FALCON
+	def_bool y
+	depends on MIPS && SOC_FALCON
+	select GPIO_GENERIC
+
+ config GPIO_MM_LANTIQ
+ 	bool "Lantiq Memory mapped GPIOs"
+ 	depends on LANTIQ && SOC_XWAY
+diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
+index c5aebd0..9bdbb91 100644
+--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
+@@ -24,6 +24,7 @@ obj-$(CONFIG_GPIO_DA9055)	+= gpio-da9055.o
+ obj-$(CONFIG_ARCH_DAVINCI)	+= gpio-davinci.o
+ obj-$(CONFIG_GPIO_EM)		+= gpio-em.o
+ obj-$(CONFIG_GPIO_EP93XX)	+= gpio-ep93xx.o
+obj-$(CONFIG_GPIO_FALCON)	+= gpio-falcon.o
+ obj-$(CONFIG_GPIO_GE_FPGA)	+= gpio-ge.o
+ obj-$(CONFIG_GPIO_ICH)		+= gpio-ich.o
+ obj-$(CONFIG_GPIO_IT8761E)	+= gpio-it8761e.o
+diff --git a/drivers/gpio/gpio-falcon.c b/drivers/gpio/gpio-falcon.c
+new file mode 100644
+index 0000000..ae8b55d
+--- /dev/null
+++ b/drivers/gpio/gpio-falcon.c
+@@ -0,0 +1,349 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
+ *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/export.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/platform_device.h>
+
+#include <lantiq_soc.h>
+
+/* Data Output Register */
+#define GPIO_OUT            0x00000000
+/* Data Input Register */
+#define GPIO_IN             0x00000004
+/* Direction Register */
+#define GPIO_DIR            0x00000008
+/* External Interrupt Control Register 0 */
+#define GPIO_EXINTCR0       0x00000018
+/* External Interrupt Control Register 1 */
+#define GPIO_EXINTCR1       0x0000001C
+/* IRN Capture Register */
+#define GPIO_IRNCR          0x00000020
+/* IRN Interrupt Configuration Register */
+#define GPIO_IRNCFG		0x0000002C
+/* IRN Interrupt Enable Set Register */
+#define GPIO_IRNRNSET       0x00000030
+/* IRN Interrupt Enable Clear Register */
+#define GPIO_IRNENCLR       0x00000034
+/* Output Set Register */
+#define GPIO_OUTSET         0x00000040
+/* Output Cler Register */
+#define GPIO_OUTCLR         0x00000044
+/* Direction Clear Register */
+#define GPIO_DIRSET         0x00000048
+/* Direction Set Register */
+#define GPIO_DIRCLR         0x0000004C
+
+/* turn a gpio_chip into a falcon_gpio_port */
+#define ctop(c)		container_of(c, struct falcon_gpio_port, gpio_chip)
+/* turn a irq_data into a falcon_gpio_port */
+#define itop(i)		((struct falcon_gpio_port *) irq_get_chip_data(i->irq))
+
+#define port_r32(p, reg)	ltq_r32(p->port + reg)
+#define port_w32(p, val, reg)	ltq_w32(val, p->port + reg)
+#define port_w32_mask(p, clear, set, reg) \
+		port_w32(p, (port_r32(p, reg) & ~(clear)) | (set), reg)
+
+#define MAX_PORTS		5
+#define PINS_PER_PORT		32
+
+struct falcon_gpio_port {
+	struct gpio_chip gpio_chip;
+	void __iomem *port;
+	unsigned int irq_base;
+	unsigned int chained_irq;
+	struct clk *clk;
+	char name[6];
+};
+
+static int falcon_gpio_direction_input(struct gpio_chip *chip,
+					unsigned int offset)
+{
+	port_w32(ctop(chip), 1 << offset, GPIO_DIRCLR);
+
+	return 0;
+}
+
+static void falcon_gpio_set(struct gpio_chip *chip, unsigned int offset,
+					int value)
+{
+	if (value)
+		port_w32(ctop(chip), 1 << offset, GPIO_OUTSET);
+	else
+		port_w32(ctop(chip), 1 << offset, GPIO_OUTCLR);
+}
+
+static int falcon_gpio_direction_output(struct gpio_chip *chip,
+					unsigned int offset, int value)
+{
+	falcon_gpio_set(chip, offset, value);
+	port_w32(ctop(chip), 1 << offset, GPIO_DIRSET);
+
+	return 0;
+}
+
+static int falcon_gpio_get(struct gpio_chip *chip, unsigned int offset)
+{
+	if ((port_r32(ctop(chip), GPIO_DIR) >> offset) & 1)
+		return (port_r32(ctop(chip), GPIO_OUT) >> offset) & 1;
+	else
+		return (port_r32(ctop(chip), GPIO_IN) >> offset) & 1;
+}
+
+static int falcon_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+	int gpio = chip->base + offset;
+
+	return pinctrl_request_gpio(gpio);
+}
+
+static void falcon_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+	int gpio = chip->base + offset;
+
+	pinctrl_free_gpio(gpio);
+}
+
+static int falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+	return ctop(chip)->irq_base + offset;
+}
+
+static void falcon_gpio_disable_irq(struct irq_data *d)
+{
+	unsigned int offset = d->irq - itop(d)->irq_base;
+
+	port_w32(itop(d), 1 << offset, GPIO_IRNENCLR);
+}
+
+static void falcon_gpio_enable_irq(struct irq_data *d)
+{
+	unsigned int offset = d->irq - itop(d)->irq_base;
+
+	port_w32(itop(d), 1 << offset, GPIO_IRNRNSET);
+}
+
+static void falcon_gpio_ack_irq(struct irq_data *d)
+{
+	unsigned int offset = d->irq - itop(d)->irq_base;
+
+	port_w32(itop(d), 1 << offset, GPIO_IRNCR);
+}
+
+static void falcon_gpio_mask_and_ack_irq(struct irq_data *d)
+{
+	unsigned int offset = d->irq - itop(d)->irq_base;
+
+	port_w32(itop(d), 1 << offset, GPIO_IRNENCLR);
+	port_w32(itop(d), 1 << offset, GPIO_IRNCR);
+}
+
+static struct irq_chip falcon_gpio_irq_chip;
+static int falcon_gpio_irq_type(struct irq_data *d, unsigned int type)
+{
+	unsigned int offset = d->irq - itop(d)->irq_base;
+	unsigned int mask = 1 << offset;
+
+	if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
+		return 0;
+
+	if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) {
+		/* level triggered */
+		port_w32_mask(itop(d), 0, mask, GPIO_IRNCFG);
+		irq_set_chip_and_handler_name(d->irq,
+			&falcon_gpio_irq_chip, handle_level_irq, "mux");
+	} else {
+		/* edge triggered */
+		port_w32_mask(itop(d), mask, 0, GPIO_IRNCFG);
+		irq_set_chip_and_handler_name(d->irq,
+			&falcon_gpio_irq_chip, handle_simple_irq, "mux");
+	}
+
+	if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
+		port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR0);
+		port_w32_mask(itop(d), 0, mask, GPIO_EXINTCR1);
+	} else {
+		if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0)
+			/* positive logic: rising edge, high level */
+			port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR0);
+		else
+			/* negative logic: falling edge, low level */
+			port_w32_mask(itop(d), 0, mask, GPIO_EXINTCR0);
+		port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR1);
+	}
+
+	return gpio_direction_input(itop(d)->gpio_chip.base + offset);
+}
+
+static void falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+	struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc);
+	unsigned long irncr;
+	int offset;
+
+	/* acknowledge interrupt */
+	irncr = port_r32(gpio_port, GPIO_IRNCR);
+	port_w32(gpio_port, irncr, GPIO_IRNCR);
+
+	desc->irq_data.chip->irq_ack(&desc->irq_data);
+
+	for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio)
+		generic_handle_irq(gpio_port->irq_base + offset);
+}
+
+static int falcon_gpio_irq_map(struct irq_domain *d, unsigned int irq,
+				irq_hw_number_t hw)
+{
+	struct falcon_gpio_port *port = d->host_data;
+
+	irq_set_chip_and_handler_name(irq, &falcon_gpio_irq_chip,
+			handle_simple_irq, "mux");
+	irq_set_chip_data(irq, port);
+
+	/* set to negative logic (falling edge, low level) */
+	port_w32_mask(port, 0, 1 << hw, GPIO_EXINTCR0);
+	return 0;
+}
+
+static struct irq_chip falcon_gpio_irq_chip = {
+	.name = "gpio_irq_mux",
+	.irq_mask = falcon_gpio_disable_irq,
+	.irq_unmask = falcon_gpio_enable_irq,
+	.irq_ack = falcon_gpio_ack_irq,
+	.irq_mask_ack = falcon_gpio_mask_and_ack_irq,
+	.irq_set_type = falcon_gpio_irq_type,
+};
+
+static const struct irq_domain_ops irq_domain_ops = {
+	.xlate = irq_domain_xlate_onetwocell,
+	.map = falcon_gpio_irq_map,
+};
+
+static struct irqaction gpio_cascade = {
+	.handler = no_action,
+	.flags = IRQF_DISABLED,
+	.name = "gpio_cascade",
+};
+
+static int falcon_gpio_probe(struct platform_device *pdev)
+{
+	struct pinctrl_gpio_range *gpio_range;
+	struct device_node *node = pdev->dev.of_node;
+	const __be32 *bank = of_get_property(node, "lantiq,bank", NULL);
+	struct falcon_gpio_port *gpio_port;
+	struct resource *gpiores, irqres;
+	int ret, size;
+
+	if (!bank || *bank >= MAX_PORTS)
+		return -ENODEV;
+
+	size = pinctrl_falcon_get_range_size(*bank);
+	if (size < 1) {
+		dev_err(&pdev->dev, "pad not loaded for bank %d\n", *bank);
+		return size;
+	}
+
+	gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!gpiores)
+		return -ENODEV;
+
+	gpio_range = devm_kzalloc(&pdev->dev, sizeof(struct pinctrl_gpio_range),
+				GFP_KERNEL);
+	if (!gpio_range)
+		return -ENOMEM;
+
+	gpio_port = devm_kzalloc(&pdev->dev, sizeof(struct falcon_gpio_port),
+				GFP_KERNEL);
+	if (!gpio_port)
+		return -ENOMEM;
+	snprintf(gpio_port->name, 6, "gpio%d", *bank);
+	gpio_port->gpio_chip.label = gpio_port->name;
+	gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input;
+	gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output;
+	gpio_port->gpio_chip.get = falcon_gpio_get;
+	gpio_port->gpio_chip.set = falcon_gpio_set;
+	gpio_port->gpio_chip.request = falcon_gpio_request;
+	gpio_port->gpio_chip.free = falcon_gpio_free;
+	gpio_port->gpio_chip.base = -1;
+	gpio_port->gpio_chip.ngpio = size;
+	gpio_port->gpio_chip.dev = &pdev->dev;
+
+	gpio_port->port = devm_request_and_ioremap(&pdev->dev, gpiores);
+	if (!gpio_port->port) {
+		dev_err(&pdev->dev, "Could not map io ranges\n");
+		return -ENOMEM;
+	}
+
+	gpio_port->clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(gpio_port->clk)) {
+		dev_err(&pdev->dev, "Could not get clock\n");
+		return PTR_ERR(gpio_port->clk);
+	}
+	clk_enable(gpio_port->clk);
+
+	if (of_irq_to_resource_table(node, &irqres, 1) == 1) {
+		gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * *bank);
+		gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
+		gpio_port->chained_irq = irqres.start;
+		irq_domain_add_legacy(node, size, gpio_port->irq_base, 0,
+					&irq_domain_ops, gpio_port);
+		setup_irq(irqres.start, &gpio_cascade);
+		irq_set_handler_data(irqres.start, gpio_port);
+		irq_set_chained_handler(irqres.start, falcon_gpio_irq_handler);
+	}
+
+	ret = gpiochip_add(&gpio_port->gpio_chip);
+	if (!ret)
+		platform_set_drvdata(pdev, gpio_port);
+
+	gpio_range->name = "FALCON GPIO";
+	gpio_range->id = *bank;
+	gpio_range->base = gpio_port->gpio_chip.base;
+	gpio_range->npins = gpio_port->gpio_chip.ngpio;
+	gpio_range->gc = &gpio_port->gpio_chip;
+	pinctrl_falcon_add_gpio_range(gpio_range);
+
+	return ret;
+}
+
+static const struct of_device_id falcon_gpio_match[] = {
+	{ .compatible = "lantiq,gpio-falcon" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, falcon_gpio_match);
+
+static struct platform_driver falcon_gpio_driver = {
+	.probe = falcon_gpio_probe,
+	.driver = {
+		.name = "gpio-falcon",
+		.owner = THIS_MODULE,
+		.of_match_table = falcon_gpio_match,
+	},
+};
+
+int __init falcon_gpio_init(void)
+{
+	int ret;
+
+	pr_info("FALC(tm) ON GPIO Driver, (C) 2012 Lantiq Deutschland Gmbh\n");
+	ret = platform_driver_register(&falcon_gpio_driver);
+	if (ret)
+		pr_err("falcon_gpio: Error registering platform driver!");
+	return ret;
+}
+
+subsys_initcall(falcon_gpio_init);
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0022-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch
+++ b/target/linux/lantiq/patches-3.8/0022-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch
--- a/target/linux/lantiq/patches-3.8/0023-USB-fix-roothub-for-IFXHCD.patch
+++ b/target/linux/lantiq/patches-3.8/0023-USB-fix-roothub-for-IFXHCD.patch
@ -0,0 +1,38 @@
+From e6c3c0d86a581e0738e18e5a3369ded8527a3315 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 6 Dec 2012 19:59:53 +0100
+Subject: [PATCH 23/40] USB: fix roothub for IFXHCD
+
+---
+ arch/mips/lantiq/Kconfig |    1 +
+ drivers/usb/core/hub.c   |    2 +-
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
+index c002191..675310a 100644
+--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
+@@ -3,6 +3,7 @@ if LANTIQ
+ config SOC_TYPE_XWAY
+ 	bool
+ 	select PINCTRL_XWAY
+	select USB_ARCH_HAS_HCD
+ 	default n
+ 
+ choice
+diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
+index cbf7168..5cddead 100644
+--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
+@@ -4006,7 +4006,7 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1,
+ 		udev->ttport = hdev->ttport;
+ 	} else if (udev->speed != USB_SPEED_HIGH
+ 			&& hdev->speed == USB_SPEED_HIGH) {
+-		if (!hub->tt.hub) {
+		if (hdev->parent && !hub->tt.hub) {
+ 			dev_err(&udev->dev, "parent hub has no TT\n");
+ 			retval = -EINVAL;
+ 			goto fail;
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0024-SPI-MIPS-lantiq-adds-spi-xway.patch
+++ b/target/linux/lantiq/patches-3.8/0024-SPI-MIPS-lantiq-adds-spi-xway.patch
--- a/target/linux/lantiq/patches-3.8/0025-NET-MIPS-lantiq-adds-xrx200-net.patch
+++ b/target/linux/lantiq/patches-3.8/0025-NET-MIPS-lantiq-adds-xrx200-net.patch
--- a/target/linux/lantiq/patches-3.8/0026-NET-MIPS-lantiq-update-etop-driver-for-devicetree.patch
+++ b/target/linux/lantiq/patches-3.8/0026-NET-MIPS-lantiq-update-etop-driver-for-devicetree.patch
@ -0,0 +1,832 @@
+From 32010516999c75d8e8ea95779137438f4f6d06ae Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 13 Mar 2013 09:32:16 +0100
+Subject: [PATCH 26/40] NET: MIPS: lantiq: update etop driver for devicetree
+
+---
+ drivers/net/ethernet/lantiq_etop.c |  496 +++++++++++++++++++++++++-----------
+ 1 file changed, 351 insertions(+), 145 deletions(-)
+
+diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
+index c124e67..91a37f1 100644
+--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
+@@ -12,7 +12,7 @@
+  *   along with this program; if not, write to the Free Software
+  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+  *
+- *   Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
+  */
+ 
+ #include <linux/kernel.h>
+@@ -36,6 +36,10 @@
+ #include <linux/io.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/of_net.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+ 
+ #include <asm/checksum.h>
+ 
+@@ -71,25 +75,61 @@
+ #define ETOP_MII_REVERSE	0xe
+ #define ETOP_PLEN_UNDER		0x40
+ #define ETOP_CGEN		0x800
+-
+-/* use 2 static channels for TX/RX */
+-#define LTQ_ETOP_TX_CHANNEL	1
+-#define LTQ_ETOP_RX_CHANNEL	6
+-#define IS_TX(x)		(x == LTQ_ETOP_TX_CHANNEL)
+-#define IS_RX(x)		(x == LTQ_ETOP_RX_CHANNEL)
+-
+#define ETOP_CFG_MII0		0x01
+
+#define LTQ_GBIT_MDIO_CTL	0xCC
+#define LTQ_GBIT_MDIO_DATA	0xd0
+#define LTQ_GBIT_GCTL0		0x68
+#define LTQ_GBIT_PMAC_HD_CTL	0x8c
+#define LTQ_GBIT_P0_CTL		0x4
+#define LTQ_GBIT_PMAC_RX_IPG	0xa8
+#define LTQ_GBIT_RGMII_CTL	0x78
+
+#define PMAC_HD_CTL_AS		(1 << 19)
+#define PMAC_HD_CTL_RXSH	(1 << 22)
+
+/* Switch Enable (0=disable, 1=enable) */
+#define GCTL0_SE		0x80000000
+/* Disable MDIO auto polling (0=disable, 1=enable) */
+#define PX_CTL_DMDIO		0x00400000
+
+/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */
+#define MDC_CLOCK_MASK		0xff000000
+#define MDC_CLOCK_OFFSET	24
+
+/* register information for the gbit's MDIO bus */
+#define MDIO_XR9_REQUEST	0x00008000
+#define MDIO_XR9_READ		0x00000800
+#define MDIO_XR9_WRITE		0x00000400
+#define MDIO_XR9_REG_MASK	0x1f
+#define MDIO_XR9_ADDR_MASK	0x1f
+#define MDIO_XR9_RD_MASK	0xffff
+#define MDIO_XR9_REG_OFFSET	0
+#define MDIO_XR9_ADDR_OFFSET	5
+#define MDIO_XR9_WR_OFFSET	16
+
+#define LTQ_DMA_ETOP	((of_machine_is_compatible("lantiq,ase")) ? \
+			(INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
+
+/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
+ #define ltq_etop_r32(x)		ltq_r32(ltq_etop_membase + (x))
+ #define ltq_etop_w32(x, y)	ltq_w32(x, ltq_etop_membase + (y))
+ #define ltq_etop_w32_mask(x, y, z)	\
+ 		ltq_w32_mask(x, y, ltq_etop_membase + (z))
+ 
+-#define DRV_VERSION	"1.0"
+#define ltq_gbit_r32(x)		ltq_r32(ltq_gbit_membase + (x))
+#define ltq_gbit_w32(x, y)	ltq_w32(x, ltq_gbit_membase + (y))
+#define ltq_gbit_w32_mask(x, y, z)	\
+		ltq_w32_mask(x, y, ltq_gbit_membase + (z))
+
+#define DRV_VERSION	"1.2"
+ 
+ static void __iomem *ltq_etop_membase;
+static void __iomem *ltq_gbit_membase;
+ 
+ struct ltq_etop_chan {
+-	int idx;
+ 	int tx_free;
+	int irq;
+ 	struct net_device *netdev;
+ 	struct napi_struct napi;
+ 	struct ltq_dma_channel dma;
+@@ -99,22 +139,35 @@ struct ltq_etop_chan {
+ struct ltq_etop_priv {
+ 	struct net_device *netdev;
+ 	struct platform_device *pdev;
+-	struct ltq_eth_data *pldata;
+ 	struct resource *res;
+ 
+ 	struct mii_bus *mii_bus;
+ 	struct phy_device *phydev;
+ 
+-	struct ltq_etop_chan ch[MAX_DMA_CHAN];
+-	int tx_free[MAX_DMA_CHAN >> 1];
+	struct ltq_etop_chan txch;
+	struct ltq_etop_chan rxch;
+
+	int tx_irq;
+	int rx_irq;
+
+	const void *mac;
+	int mii_mode;
+ 
+ 	spinlock_t lock;
+
+	struct clk *clk_ppe;
+	struct clk *clk_switch;
+	struct clk *clk_ephy;
+	struct clk *clk_ephycgu;
+ };
+ 
+static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
+				int phy_reg, u16 phy_data);
+
+ static int
+ ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
+ {
+-	ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
+	ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
+ 	if (!ch->skb[ch->dma.desc])
+ 		return -ENOMEM;
+ 	ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
+@@ -149,8 +202,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan *ch)
+ 	spin_unlock_irqrestore(&priv->lock, flags);
+ 
+ 	skb_put(skb, len);
+	skb->dev = ch->netdev;
+ 	skb->protocol = eth_type_trans(skb, ch->netdev);
+ 	netif_receive_skb(skb);
+	ch->netdev->stats.rx_packets++;
+	ch->netdev->stats.rx_bytes += len;
+ }
+ 
+ static int
+@@ -158,8 +214,10 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget)
+ {
+ 	struct ltq_etop_chan *ch = container_of(napi,
+ 				struct ltq_etop_chan, napi);
+	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
+ 	int rx = 0;
+ 	int complete = 0;
+	unsigned long flags;
+ 
+ 	while ((rx < budget) && !complete) {
+ 		struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
+@@ -173,7 +231,9 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget)
+ 	}
+ 	if (complete || !rx) {
+ 		napi_complete(&ch->napi);
+		spin_lock_irqsave(&priv->lock, flags);
+ 		ltq_dma_ack_irq(&ch->dma);
+		spin_unlock_irqrestore(&priv->lock, flags);
+ 	}
+ 	return rx;
+ }
+@@ -185,12 +245,14 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget)
+ 		container_of(napi, struct ltq_etop_chan, napi);
+ 	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
+ 	struct netdev_queue *txq =
+-		netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
+		netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
+ 	unsigned long flags;
+ 
+ 	spin_lock_irqsave(&priv->lock, flags);
+ 	while ((ch->dma.desc_base[ch->tx_free].ctl &
+ 			(LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
+		ch->netdev->stats.tx_packets++;
+		ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
+ 		dev_kfree_skb_any(ch->skb[ch->tx_free]);
+ 		ch->skb[ch->tx_free] = NULL;
+ 		memset(&ch->dma.desc_base[ch->tx_free], 0,
+@@ -203,7 +265,9 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget)
+ 	if (netif_tx_queue_stopped(txq))
+ 		netif_tx_start_queue(txq);
+ 	napi_complete(&ch->napi);
+	spin_lock_irqsave(&priv->lock, flags);
+ 	ltq_dma_ack_irq(&ch->dma);
+	spin_unlock_irqrestore(&priv->lock, flags);
+ 	return 1;
+ }
+ 
+@@ -211,9 +275,10 @@ static irqreturn_t
+ ltq_etop_dma_irq(int irq, void *_priv)
+ {
+ 	struct ltq_etop_priv *priv = _priv;
+-	int ch = irq - LTQ_DMA_CH0_INT;
+-
+-	napi_schedule(&priv->ch[ch].napi);
+	if (irq == priv->txch.dma.irq)
+		napi_schedule(&priv->txch.napi);
+	else
+		napi_schedule(&priv->rxch.napi);
+ 	return IRQ_HANDLED;
+ }
+ 
+@@ -225,7 +290,7 @@ ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
+ 	ltq_dma_free(&ch->dma);
+ 	if (ch->dma.irq)
+ 		free_irq(ch->dma.irq, priv);
+-	if (IS_RX(ch->idx)) {
+	if (ch == &priv->txch) {
+ 		int desc;
+ 		for (desc = 0; desc < LTQ_DESC_NUM; desc++)
+ 			dev_kfree_skb_any(ch->skb[ch->dma.desc]);
+@@ -236,23 +301,59 @@ static void
+ ltq_etop_hw_exit(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	int i;
+ 
+-	ltq_pmu_disable(PMU_PPE);
+-	for (i = 0; i < MAX_DMA_CHAN; i++)
+-		if (IS_TX(i) || IS_RX(i))
+-			ltq_etop_free_channel(dev, &priv->ch[i]);
+	clk_disable(priv->clk_ppe);
+
+	if (of_machine_is_compatible("lantiq,ar9"))
+		clk_disable(priv->clk_switch);
+
+	if (of_machine_is_compatible("lantiq,ase")) {
+		clk_disable(priv->clk_ephy);
+		clk_disable(priv->clk_ephycgu);
+	}
+
+	ltq_etop_free_channel(dev, &priv->txch);
+	ltq_etop_free_channel(dev, &priv->rxch);
+}
+
+static void
+ltq_etop_gbit_init(struct net_device *dev)
+{
+	struct ltq_etop_priv *priv = netdev_priv(dev);
+
+	clk_enable(priv->clk_switch);
+
+	ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
+	/** Disable MDIO auto polling mode */
+	ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
+	/* set 1522 packet size */
+	ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
+	/* disable pmac & dmac headers */
+	ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
+		LTQ_GBIT_PMAC_HD_CTL);
+	/* Due to traffic halt when burst length 8,
+		replace default IPG value with 0x3B */
+	ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
+	/* set mdc clock to 2.5 MHz */
+	ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,
+		LTQ_GBIT_RGMII_CTL);
+ }
+ 
+ static int
+ ltq_etop_hw_init(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	int i;
+	int mii_mode = priv->mii_mode;
+
+	clk_enable(priv->clk_ppe);
+ 
+-	ltq_pmu_enable(PMU_PPE);
+	if (of_machine_is_compatible("lantiq,ar9")) {
+		ltq_etop_gbit_init(dev);
+		/* force the etops link to the gbit to MII */
+		mii_mode = PHY_INTERFACE_MODE_MII;
+	}
+ 
+-	switch (priv->pldata->mii_mode) {
+	switch (mii_mode) {
+ 	case PHY_INTERFACE_MODE_RMII:
+ 		ltq_etop_w32_mask(ETOP_MII_MASK,
+ 			ETOP_MII_REVERSE, LTQ_ETOP_CFG);
+@@ -264,39 +365,68 @@ ltq_etop_hw_init(struct net_device *dev)
+ 		break;
+ 
+ 	default:
+		if (of_machine_is_compatible("lantiq,ase")) {
+			clk_enable(priv->clk_ephy);
+			/* disable external MII */
+			ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
+			/* enable clock for internal PHY */
+			clk_enable(priv->clk_ephycgu);
+			/* we need to write this magic to the internal phy to
+			   make it work */
+			ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
+			pr_info("Selected EPHY mode\n");
+			break;
+		}
+ 		netdev_err(dev, "unknown mii mode %d\n",
+-			priv->pldata->mii_mode);
+			mii_mode);
+ 		return -ENOTSUPP;
+ 	}
+ 
+ 	/* enable crc generation */
+ 	ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
+ 
+	return 0;
+}
+
+static int
+ltq_etop_dma_init(struct net_device *dev)
+{
+	struct ltq_etop_priv *priv = netdev_priv(dev);
+	int tx = priv->tx_irq - LTQ_DMA_ETOP;
+	int rx = priv->rx_irq - LTQ_DMA_ETOP;
+	int err;
+
+ 	ltq_dma_init_port(DMA_PORT_ETOP);
+ 
+-	for (i = 0; i < MAX_DMA_CHAN; i++) {
+-		int irq = LTQ_DMA_CH0_INT + i;
+-		struct ltq_etop_chan *ch = &priv->ch[i];
+-
+-		ch->idx = ch->dma.nr = i;
+-
+-		if (IS_TX(i)) {
+-			ltq_dma_alloc_tx(&ch->dma);
+-			request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
+-				"etop_tx", priv);
+-		} else if (IS_RX(i)) {
+-			ltq_dma_alloc_rx(&ch->dma);
+-			for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
+-					ch->dma.desc++)
+-				if (ltq_etop_alloc_skb(ch))
+-					return -ENOMEM;
+-			ch->dma.desc = 0;
+-			request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
+-				"etop_rx", priv);
+	priv->txch.dma.nr = tx;
+	ltq_dma_alloc_tx(&priv->txch.dma);
+	err = request_irq(priv->tx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
+		"eth_tx", priv);
+	if (err) {
+		netdev_err(dev, "failed to allocate tx irq\n");
+		goto err_out;
+	}
+	priv->txch.dma.irq = priv->tx_irq;
+
+	priv->rxch.dma.nr = rx;
+	ltq_dma_alloc_rx(&priv->rxch.dma);
+	for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
+			priv->rxch.dma.desc++) {
+		if (ltq_etop_alloc_skb(&priv->rxch)) {
+			netdev_err(dev, "failed to allocate skbs\n");
+			err = -ENOMEM;
+			goto err_out;
+ 		}
+-		ch->dma.irq = irq;
+ 	}
+-	return 0;
+	priv->rxch.dma.desc = 0;
+	err = request_irq(priv->rx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
+		"eth_rx", priv);
+	if (err)
+		netdev_err(dev, "failed to allocate rx irq\n");
+	else
+		priv->rxch.dma.irq = priv->rx_irq;
+err_out:
+	return err;
+ }
+ 
+ static void
+@@ -312,7 +442,10 @@ ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+ 
+-	return phy_ethtool_gset(priv->phydev, cmd);
+	if (priv->phydev)
+		return phy_ethtool_gset(priv->phydev, cmd);
+	else
+		return 0;
+ }
+ 
+ static int
+@@ -320,7 +453,10 @@ ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+ 
+-	return phy_ethtool_sset(priv->phydev, cmd);
+	if (priv->phydev)
+		return phy_ethtool_sset(priv->phydev, cmd);
+	else
+		return 0;
+ }
+ 
+ static int
+@@ -328,7 +464,10 @@ ltq_etop_nway_reset(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+ 
+-	return phy_start_aneg(priv->phydev);
+	if (priv->phydev)
+		return phy_start_aneg(priv->phydev);
+	else
+		return 0;
+ }
+ 
+ static const struct ethtool_ops ltq_etop_ethtool_ops = {
+@@ -339,6 +478,39 @@ static const struct ethtool_ops ltq_etop_ethtool_ops = {
+ };
+ 
+ static int
+ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
+		int phy_reg, u16 phy_data)
+{
+	u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
+		(phy_data << MDIO_XR9_WR_OFFSET) |
+		((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
+		((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
+
+	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
+		;
+	ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
+	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
+		;
+	return 0;
+}
+
+static int
+ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
+{
+	u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
+		((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
+		((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
+
+	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
+		;
+	ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
+	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
+		;
+	val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
+	return val;
+}
+
+static int
+ ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
+ {
+ 	u32 val = MDIO_REQUEST |
+@@ -379,14 +551,18 @@ ltq_etop_mdio_probe(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+ 	struct phy_device *phydev = NULL;
+-	int phy_addr;
+-
+-	for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
+-		if (priv->mii_bus->phy_map[phy_addr]) {
+-			phydev = priv->mii_bus->phy_map[phy_addr];
+-			break;
+-		}
+-	}
+	u32 phy_supported =  (SUPPORTED_10baseT_Half
+			| SUPPORTED_10baseT_Full
+			| SUPPORTED_100baseT_Half
+			| SUPPORTED_100baseT_Full
+			| SUPPORTED_Autoneg
+			| SUPPORTED_MII
+			| SUPPORTED_TP);
+
+	if (of_machine_is_compatible("lantiq,ase"))
+		phydev = priv->mii_bus->phy_map[8];
+	else
+		phydev = priv->mii_bus->phy_map[0];
+ 
+ 	if (!phydev) {
+ 		netdev_err(dev, "no PHY found\n");
+@@ -394,21 +570,18 @@ ltq_etop_mdio_probe(struct net_device *dev)
+ 	}
+ 
+ 	phydev = phy_connect(dev, dev_name(&phydev->dev), &ltq_etop_mdio_link,
+-			0, priv->pldata->mii_mode);
+			0, priv->mii_mode);
+ 
+ 	if (IS_ERR(phydev)) {
+ 		netdev_err(dev, "Could not attach to PHY\n");
+ 		return PTR_ERR(phydev);
+ 	}
+ 
+-	phydev->supported &= (SUPPORTED_10baseT_Half
+-			      | SUPPORTED_10baseT_Full
+-			      | SUPPORTED_100baseT_Half
+-			      | SUPPORTED_100baseT_Full
+-			      | SUPPORTED_Autoneg
+-			      | SUPPORTED_MII
+-			      | SUPPORTED_TP);
+	if (of_machine_is_compatible("lantiq,ar9"))
+		phy_supported |= SUPPORTED_1000baseT_Half
+			| SUPPORTED_1000baseT_Full;
+ 
+	phydev->supported &= phy_supported;
+ 	phydev->advertising = phydev->supported;
+ 	priv->phydev = phydev;
+ 	pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
+@@ -433,8 +606,13 @@ ltq_etop_mdio_init(struct net_device *dev)
+ 	}
+ 
+ 	priv->mii_bus->priv = dev;
+-	priv->mii_bus->read = ltq_etop_mdio_rd;
+-	priv->mii_bus->write = ltq_etop_mdio_wr;
+	if (of_machine_is_compatible("lantiq,ar9")) {
+		priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
+		priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
+	} else {
+		priv->mii_bus->read = ltq_etop_mdio_rd;
+		priv->mii_bus->write = ltq_etop_mdio_wr;
+	}
+ 	priv->mii_bus->name = "ltq_mii";
+ 	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+ 		priv->pdev->name, priv->pdev->id);
+@@ -483,17 +661,19 @@ static int
+ ltq_etop_open(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	int i;
+	unsigned long flags;
+ 
+-	for (i = 0; i < MAX_DMA_CHAN; i++) {
+-		struct ltq_etop_chan *ch = &priv->ch[i];
+	napi_enable(&priv->txch.napi);
+	napi_enable(&priv->rxch.napi);
+
+	spin_lock_irqsave(&priv->lock, flags);
+	ltq_dma_open(&priv->txch.dma);
+	ltq_dma_open(&priv->rxch.dma);
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	if (priv->phydev)
+		phy_start(priv->phydev);
+ 
+-		if (!IS_TX(i) && (!IS_RX(i)))
+-			continue;
+-		ltq_dma_open(&ch->dma);
+-		napi_enable(&ch->napi);
+-	}
+-	phy_start(priv->phydev);
+ 	netif_tx_start_all_queues(dev);
+ 	return 0;
+ }
+@@ -502,18 +682,19 @@ static int
+ ltq_etop_stop(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	int i;
+	unsigned long flags;
+ 
+ 	netif_tx_stop_all_queues(dev);
+-	phy_stop(priv->phydev);
+-	for (i = 0; i < MAX_DMA_CHAN; i++) {
+-		struct ltq_etop_chan *ch = &priv->ch[i];
+	if (priv->phydev)
+		phy_stop(priv->phydev);
+	napi_disable(&priv->txch.napi);
+	napi_disable(&priv->rxch.napi);
+
+	spin_lock_irqsave(&priv->lock, flags);
+	ltq_dma_close(&priv->txch.dma);
+	ltq_dma_close(&priv->rxch.dma);
+	spin_unlock_irqrestore(&priv->lock, flags);
+ 
+-		if (!IS_RX(i) && !IS_TX(i))
+-			continue;
+-		napi_disable(&ch->napi);
+-		ltq_dma_close(&ch->dma);
+-	}
+ 	return 0;
+ }
+ 
+@@ -523,16 +704,16 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
+ 	int queue = skb_get_queue_mapping(skb);
+ 	struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
+-	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
+-	int len;
+	struct ltq_dma_desc *desc =
+		&priv->txch.dma.desc_base[priv->txch.dma.desc];
+ 	unsigned long flags;
+ 	u32 byte_offset;
+	int len;
+ 
+ 	len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
+ 
+-	if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
+-		dev_kfree_skb_any(skb);
+	if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
+			priv->txch.skb[priv->txch.dma.desc]) {
+ 		netdev_err(dev, "tx ring full\n");
+ 		netif_tx_stop_queue(txq);
+ 		return NETDEV_TX_BUSY;
+@@ -540,7 +721,7 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
+ 
+ 	/* dma needs to start on a 16 byte aligned address */
+ 	byte_offset = CPHYSADDR(skb->data) % 16;
+-	ch->skb[ch->dma.desc] = skb;
+	priv->txch.skb[priv->txch.dma.desc] = skb;
+ 
+ 	dev->trans_start = jiffies;
+ 
+@@ -550,11 +731,11 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
+ 	wmb();
+ 	desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
+ 		LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
+-	ch->dma.desc++;
+-	ch->dma.desc %= LTQ_DESC_NUM;
+	priv->txch.dma.desc++;
+	priv->txch.dma.desc %= LTQ_DESC_NUM;
+ 	spin_unlock_irqrestore(&priv->lock, flags);
+ 
+-	if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
+	if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
+ 		netif_tx_stop_queue(txq);
+ 
+ 	return NETDEV_TX_OK;
+@@ -633,34 +814,32 @@ ltq_etop_init(struct net_device *dev)
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+ 	struct sockaddr mac;
+ 	int err;
+-	bool random_mac = false;
+ 
+ 	ether_setup(dev);
+ 	dev->watchdog_timeo = 10 * HZ;
+ 	err = ltq_etop_hw_init(dev);
+ 	if (err)
+ 		goto err_hw;
+	err = ltq_etop_dma_init(dev);
+	if (err)
+		goto err_hw;
+
+ 	ltq_etop_change_mtu(dev, 1500);
+ 
+-	memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
+	memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
+ 	if (!is_valid_ether_addr(mac.sa_data)) {
+ 		pr_warn("etop: invalid MAC, using random\n");
+-		eth_random_addr(mac.sa_data);
+-		random_mac = true;
+		random_ether_addr(mac.sa_data);
+ 	}
+ 
+ 	err = ltq_etop_set_mac_address(dev, &mac);
+ 	if (err)
+ 		goto err_netdev;
+-
+-	/* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
+-	if (random_mac)
+-		dev->addr_assign_type |= NET_ADDR_RANDOM;
+-
+ 	ltq_etop_set_multicast_list(dev);
+-	err = ltq_etop_mdio_init(dev);
+-	if (err)
+-		goto err_netdev;
+	if (!ltq_etop_mdio_init(dev))
+		dev->ethtool_ops = &ltq_etop_ethtool_ops;
+	else
+		pr_warn("etop: mdio probe failed\n");;
+ 	return 0;
+ 
+ err_netdev:
+@@ -680,6 +859,9 @@ ltq_etop_tx_timeout(struct net_device *dev)
+ 	err = ltq_etop_hw_init(dev);
+ 	if (err)
+ 		goto err_hw;
+	err = ltq_etop_dma_init(dev);
+	if (err)
+		goto err_hw;
+ 	dev->trans_start = jiffies;
+ 	netif_wake_queue(dev);
+ 	return;
+@@ -703,14 +885,19 @@ static const struct net_device_ops ltq_eth_netdev_ops = {
+ 	.ndo_tx_timeout = ltq_etop_tx_timeout,
+ };
+ 
+-static int __init
+static int __devinit
+ ltq_etop_probe(struct platform_device *pdev)
+ {
+ 	struct net_device *dev;
+ 	struct ltq_etop_priv *priv;
+-	struct resource *res;
+	struct resource *res, *gbit_res, irqres[2];
+ 	int err;
+-	int i;
+
+	err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
+	if (err != 2) {
+		dev_err(&pdev->dev, "failed to get etop irqs\n");
+		return -EINVAL;
+	}
+ 
+ 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	if (!res) {
+@@ -736,30 +923,58 @@ ltq_etop_probe(struct platform_device *pdev)
+ 		goto err_out;
+ 	}
+ 
+-	dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
+-	if (!dev) {
+-		err = -ENOMEM;
+-		goto err_out;
+	if (of_machine_is_compatible("lantiq,ar9")) {
+		gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		if (!gbit_res) {
+			dev_err(&pdev->dev, "failed to get gbit resource\n");
+			err = -ENOENT;
+			goto err_out;
+		}
+		ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
+			gbit_res->start, resource_size(gbit_res));
+		if (!ltq_gbit_membase) {
+			dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
+				pdev->id);
+			err = -ENOMEM;
+			goto err_out;
+		}
+ 	}
+
+	dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
+ 	strcpy(dev->name, "eth%d");
+ 	dev->netdev_ops = &ltq_eth_netdev_ops;
+-	dev->ethtool_ops = &ltq_etop_ethtool_ops;
+ 	priv = netdev_priv(dev);
+ 	priv->res = res;
+ 	priv->pdev = pdev;
+-	priv->pldata = dev_get_platdata(&pdev->dev);
+ 	priv->netdev = dev;
+	priv->tx_irq = irqres[0].start;
+	priv->rx_irq = irqres[1].start;
+	priv->mii_mode = of_get_phy_mode(pdev->dev.of_node);
+	priv->mac = of_get_mac_address(pdev->dev.of_node);
+
+	priv->clk_ppe = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(priv->clk_ppe))
+		return PTR_ERR(priv->clk_ppe);
+	if (of_machine_is_compatible("lantiq,ar9")) {
+		priv->clk_switch = clk_get(&pdev->dev, "switch");
+		if (IS_ERR(priv->clk_switch))
+			return PTR_ERR(priv->clk_switch);
+	}
+	if (of_machine_is_compatible("lantiq,ase")) {
+		priv->clk_ephy = clk_get(&pdev->dev, "ephy");
+		if (IS_ERR(priv->clk_ephy))
+			return PTR_ERR(priv->clk_ephy);
+		priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
+		if (IS_ERR(priv->clk_ephycgu))
+			return PTR_ERR(priv->clk_ephycgu);
+	}
+
+ 	spin_lock_init(&priv->lock);
+ 
+-	for (i = 0; i < MAX_DMA_CHAN; i++) {
+-		if (IS_TX(i))
+-			netif_napi_add(dev, &priv->ch[i].napi,
+-				ltq_etop_poll_tx, 8);
+-		else if (IS_RX(i))
+-			netif_napi_add(dev, &priv->ch[i].napi,
+-				ltq_etop_poll_rx, 32);
+-		priv->ch[i].netdev = dev;
+-	}
+	netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
+	netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
+	priv->txch.netdev = dev;
+	priv->rxch.netdev = dev;
+ 
+ 	err = register_netdev(dev);
+ 	if (err)
+@@ -788,32 +1003,23 @@ ltq_etop_remove(struct platform_device *pdev)
+ 	return 0;
+ }
+ 
+static const struct of_device_id ltq_etop_match[] = {
+	{ .compatible = "lantiq,etop-xway" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, ltq_etop_match);
+
+ static struct platform_driver ltq_mii_driver = {
+	.probe = ltq_etop_probe,
+ 	.remove = ltq_etop_remove,
+ 	.driver = {
+ 		.name = "ltq_etop",
+ 		.owner = THIS_MODULE,
+		.of_match_table = ltq_etop_match,
+ 	},
+ };
+ 
+-int __init
+-init_ltq_etop(void)
+-{
+-	int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
+-
+-	if (ret)
+-		pr_err("ltq_etop: Error registering platform driver!");
+-	return ret;
+-}
+-
+-static void __exit
+-exit_ltq_etop(void)
+-{
+-	platform_driver_unregister(&ltq_mii_driver);
+-}
+-
+-module_init(init_ltq_etop);
+-module_exit(exit_ltq_etop);
+module_platform_driver(ltq_mii_driver);
+ 
+ MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+ MODULE_DESCRIPTION("Lantiq SoC ETOP");
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0027-NET-PHY-adds-driver-for-lantiq-PHY11G.patch
+++ b/target/linux/lantiq/patches-3.8/0027-NET-PHY-adds-driver-for-lantiq-PHY11G.patch
@ -0,0 +1,270 @@
+From 0721e9f0502e633390044e651970692213283686 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 13 Mar 2013 09:30:22 +0100
+Subject: [PATCH 27/40] NET: PHY: adds driver for lantiq PHY11G
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/net/phy/Kconfig  |    5 ++
+ drivers/net/phy/Makefile |    1 +
+ drivers/net/phy/lantiq.c |  220 ++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 226 insertions(+)
+ create mode 100644 drivers/net/phy/lantiq.c
+
+diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
+index 961f0b2..41a2992 100644
+--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
+@@ -107,6 +107,11 @@ config MICREL_PHY
+ 	---help---
+ 	  Supports the KSZ9021, VSC8201, KS8001 PHYs.
+ 
+config LANTIQ_PHY
+	tristate "Driver for Lantiq PHYs"
+	---help---
+	  Supports the 11G and 22E PHYs.
+
+ config FIXED_PHY
+ 	bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
+ 	depends on PHYLIB=y
+diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
+index 9645e38..e2eeee3 100644
+--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
+@@ -23,6 +23,7 @@ obj-$(CONFIG_NATIONAL_PHY)	+= national.o
+ obj-$(CONFIG_DP83640_PHY)	+= dp83640.o
+ obj-$(CONFIG_STE10XP)		+= ste10Xp.o
+ obj-$(CONFIG_MICREL_PHY)	+= micrel.o
+obj-$(CONFIG_LANTIQ_PHY)        += lantiq.o
+ obj-$(CONFIG_MDIO_OCTEON)	+= mdio-octeon.o
+ obj-$(CONFIG_MICREL_KS8995MA)	+= spi_ks8995.o
+ obj-$(CONFIG_AT803X_PHY)	+= at803x.o
+diff --git a/drivers/net/phy/lantiq.c b/drivers/net/phy/lantiq.c
+new file mode 100644
+index 0000000..418dff0
+--- /dev/null
+++ b/drivers/net/phy/lantiq.c
+@@ -0,0 +1,220 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/phy.h>
+
+#define MII_MMDCTRL		0x0d
+#define MII_MMDDATA		0x0e
+
+#define MII_VR9_11G_IMASK	0x19	/* interrupt mask */
+#define MII_VR9_11G_ISTAT	0x1a	/* interrupt status */
+
+#define INT_VR9_11G_WOL		BIT(15)	/* Wake-On-LAN */
+#define INT_VR9_11G_ANE		BIT(11)	/* Auto-Neg error */
+#define INT_VR9_11G_ANC		BIT(10)	/* Auto-Neg complete */
+#define INT_VR9_11G_ADSC	BIT(5)	/* Link auto-downspeed detect */
+#define INT_VR9_11G_DXMC	BIT(2)	/* Duplex mode change */
+#define INT_VR9_11G_LSPC	BIT(1)	/* Link speed change */
+#define INT_VR9_11G_LSTC	BIT(0)	/* Link state change */
+#define INT_VR9_11G_MASK	(INT_VR9_11G_LSTC | INT_VR9_11G_ADSC)
+
+#define ADVERTISED_MPD		BIT(10)	/* Multi-port device */
+
+#define MMD_DEVAD		0x1f
+#define MMD_ACTYPE_SHIFT	14
+#define MMD_ACTYPE_ADDRESS	(0 << MMD_ACTYPE_SHIFT)
+#define MMD_ACTYPE_DATA		(1 << MMD_ACTYPE_SHIFT)
+#define MMD_ACTYPE_DATA_PI	(2 << MMD_ACTYPE_SHIFT)
+#define MMD_ACTYPE_DATA_PIWR	(3 << MMD_ACTYPE_SHIFT)
+
+static __maybe_unused int vr9_gphy_mmd_read(struct phy_device *phydev,
+						u16 regnum)
+{
+	phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
+	phy_write(phydev, MII_MMDDATA, regnum);
+	phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
+
+	return phy_read(phydev, MII_MMDDATA);
+}
+
+static __maybe_unused int vr9_gphy_mmd_write(struct phy_device *phydev,
+						u16 regnum, u16 val)
+{
+	phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
+	phy_write(phydev, MII_MMDDATA, regnum);
+	phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
+	phy_write(phydev, MII_MMDDATA, val);
+
+	return 0;
+}
+
+static int vr9_gphy_config_init(struct phy_device *phydev)
+{
+	int err;
+
+	dev_dbg(&phydev->dev, "%s\n", __func__);
+
+	/* Mask all interrupts */
+	err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
+	if (err)
+		return err;
+
+	/* Clear all pending interrupts */
+	phy_read(phydev, MII_VR9_11G_ISTAT);
+
+	return 0;
+}
+
+static int vr9_gphy_config_aneg(struct phy_device *phydev)
+{
+	int reg, err;
+
+	/* Advertise as multi-port device */
+	reg = phy_read(phydev, MII_CTRL1000);
+	reg |= ADVERTISED_MPD;
+	err = phy_write(phydev, MII_CTRL1000, reg);
+	if (err)
+		return err;
+
+	return genphy_config_aneg(phydev);
+}
+
+static int vr9_gphy_ack_interrupt(struct phy_device *phydev)
+{
+	int reg;
+
+	/*
+	 * Possible IRQ numbers:
+	 * - IM3_IRL18 for GPHY0
+	 * - IM3_IRL17 for GPHY1
+	 *
+	 * Due to a silicon bug IRQ lines are not really independent from
+	 * each other. Sometimes the two lines are driven at the same time
+	 * if only one GPHY core raises the interrupt.
+	 */
+
+	reg = phy_read(phydev, MII_VR9_11G_ISTAT);
+
+	return (reg < 0) ? reg : 0;
+}
+
+static int vr9_gphy_did_interrupt(struct phy_device *phydev)
+{
+	int reg;
+
+	reg = phy_read(phydev, MII_VR9_11G_ISTAT);
+
+	return reg > 0;
+}
+
+static int vr9_gphy_config_intr(struct phy_device *phydev)
+{
+	int err;
+
+	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
+		err = phy_write(phydev, MII_VR9_11G_IMASK, INT_VR9_11G_MASK);
+	else
+		err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
+
+	return err;
+}
+
+static struct phy_driver lantiq_phy[] = {
+	{
+		.phy_id		= 0xd565a400,
+		.phy_id_mask	= 0xffffffff,
+		.name		= "Lantiq XWAY PEF7071",
+		.features	= (PHY_GBIT_FEATURES | SUPPORTED_Pause),
+		.flags		= 0, /*PHY_HAS_INTERRUPT,*/
+		.config_init	= vr9_gphy_config_init,
+		.config_aneg	= vr9_gphy_config_aneg,
+		.read_status	= genphy_read_status,
+		.ack_interrupt	= vr9_gphy_ack_interrupt,
+		.did_interrupt	= vr9_gphy_did_interrupt,
+		.config_intr	= vr9_gphy_config_intr,
+		.driver		= { .owner = THIS_MODULE },
+	}, {
+		.phy_id		= 0x030260D0,
+		.phy_id_mask	= 0xfffffff0,
+		.name		= "Lantiq XWAY VR9 GPHY 11G v1.3",
+		.features	= (PHY_GBIT_FEATURES | SUPPORTED_Pause),
+		.flags		= 0, /*PHY_HAS_INTERRUPT,*/
+		.config_init	= vr9_gphy_config_init,
+		.config_aneg	= vr9_gphy_config_aneg,
+		.read_status	= genphy_read_status,
+		.ack_interrupt	= vr9_gphy_ack_interrupt,
+		.did_interrupt	= vr9_gphy_did_interrupt,
+		.config_intr	= vr9_gphy_config_intr,
+		.driver		= { .owner = THIS_MODULE },
+	}, {
+		.phy_id		= 0xd565a408,
+		.phy_id_mask	= 0xfffffff8,
+		.name		= "Lantiq XWAY VR9 GPHY 11G v1.4",
+		.features	= (PHY_GBIT_FEATURES | SUPPORTED_Pause),
+		.flags		= 0, /*PHY_HAS_INTERRUPT,*/
+		.config_init	= vr9_gphy_config_init,
+		.config_aneg	= vr9_gphy_config_aneg,
+		.read_status	= genphy_read_status,
+		.ack_interrupt	= vr9_gphy_ack_interrupt,
+		.did_interrupt	= vr9_gphy_did_interrupt,
+		.config_intr	= vr9_gphy_config_intr,
+		.driver		= { .owner = THIS_MODULE },
+	}, {
+		.phy_id		= 0xd565a418,
+		.phy_id_mask	= 0xfffffff8,
+		.name		= "Lantiq XWAY XRX PHY22F v1.4",
+		.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
+		.flags		= 0, /*PHY_HAS_INTERRUPT,*/
+		.config_init	= vr9_gphy_config_init,
+		.config_aneg	= vr9_gphy_config_aneg,
+		.read_status	= genphy_read_status,
+		.ack_interrupt	= vr9_gphy_ack_interrupt,
+		.did_interrupt	= vr9_gphy_did_interrupt,
+		.config_intr	= vr9_gphy_config_intr,
+		.driver		= { .owner = THIS_MODULE },
+	},
+};
+
+static int __init ltq_phy_init(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++) {
+		int err = phy_driver_register(&lantiq_phy[i]);
+		if (err)
+			pr_err("lantiq_phy: failed to load %s\n", lantiq_phy[i].name);
+	}
+
+	return 0;
+}
+
+static void __exit ltq_phy_exit(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++)
+		phy_driver_unregister(&lantiq_phy[i]);
+}
+
+module_init(ltq_phy_init);
+module_exit(ltq_phy_exit);
+
+MODULE_DESCRIPTION("Lantiq PHY drivers");
+MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
+MODULE_LICENSE("GPL");
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0028-NET-lantiq-adds-PHY11G-firmware-blobs.patch
+++ b/target/linux/lantiq/patches-3.8/0028-NET-lantiq-adds-PHY11G-firmware-blobs.patch
@ -0,0 +1,373 @@
+From 9664031d0f35be450330bf30ded1c359b9074251 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 22 Oct 2012 09:26:24 +0200
+Subject: [PATCH 28/40] NET: lantiq: adds PHY11G firmware blobs
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ firmware/Makefile       |    2 +
+ firmware/lantiq/COPYING |  286 +++++++++++++++++++++++++++++++++++++++++++++++
+ firmware/lantiq/README  |   45 ++++++++
+ 3 files changed, 333 insertions(+)
+ create mode 100644 firmware/lantiq/COPYING
+ create mode 100644 firmware/lantiq/README
+
+diff --git a/firmware/Makefile b/firmware/Makefile
+index cbb09ce..cdc0aef 100644
+--- a/firmware/Makefile
+++ b/firmware/Makefile
+@@ -134,6 +134,8 @@ fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_PDA) += keyspan_pda/keyspan_pda.fw
+ fw-shipped-$(CONFIG_USB_SERIAL_XIRCOM) += keyspan_pda/xircom_pgs.fw
+ fw-shipped-$(CONFIG_USB_VICAM) += vicam/firmware.fw
+ fw-shipped-$(CONFIG_VIDEO_CPIA2) += cpia2/stv0672_vp4.bin
+fw-shipped-$(CONFIG_SOC_TYPE_XWAY) += lantiq/vr9_phy11g_a1x.bin
+fw-shipped-$(CONFIG_SOC_TYPE_XWAY) += lantiq/vr9_phy11g_a2x.bin
+ fw-shipped-$(CONFIG_YAM) += yam/1200.bin yam/9600.bin
+ 
+ fw-shipped-all := $(fw-shipped-y) $(fw-shipped-m) $(fw-shipped-)
+diff --git a/firmware/lantiq/COPYING b/firmware/lantiq/COPYING
+new file mode 100644
+index 0000000..5ec70b2
+--- /dev/null
+++ b/firmware/lantiq/COPYING
+@@ -0,0 +1,286 @@
+All firmware files are copyrighted by Lantiq Deutschland GmbH.
+The files have been extracted from header files found in Lantiq BSPs.
+If not stated otherwise all files are licensed under GPL.
+
+=======================================================================
+
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+     59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+			    Preamble
+
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+diff --git a/firmware/lantiq/README b/firmware/lantiq/README
+new file mode 100644
+index 0000000..cb1a10a
+--- /dev/null
+++ b/firmware/lantiq/README
+@@ -0,0 +1,45 @@
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# (C) Copyright 2007 - 2012
+# Lantiq Deutschland GmbH
+#
+# (C) Copyright 2012
+# Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
+#
+
+#
+# How to use
+#
+Configure kernel with:
+CONFIG_FW_LOADER=y
+CONFIG_EXTRA_FIRMWARE_DIR="FIRMWARE_DIR"
+CONFIG_EXTRA_FIRMWARE="FIRMWARE_FILES"
+
+where FIRMWARE_DIR should point to this git tree and FIRMWARE_FILES is a list
+of space separated files from list below.
+
+#
+# Firmware files
+#
+
+# GPHY core on Lantiq XWAY VR9 v1.1
+lantiq/vr9_phy11g_a1x.bin
+lantiq/vr9_phy22f_a1x.bin
+
+# GPHY core on Lantiq XWAY VR9 v1.1
+lantiq/vr9_phy11g_a2x.bin
+lantiq/vr9_phy22f_a2x.bin
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0029-NET-lantiq-adds-gphy-clock.patch
+++ b/target/linux/lantiq/patches-3.8/0029-NET-lantiq-adds-gphy-clock.patch
@ -0,0 +1,24 @@
+From 9dee771f3a7e51411a408cbb1070e73a50cbd285 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 13 Mar 2013 09:47:44 +0100
+Subject: [PATCH 29/40] NET: lantiq: adds gphy clock
+
+---
+ arch/mips/lantiq/xway/sysctrl.c |    1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
+index 3390fcd..c24924f 100644
+--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
+@@ -376,6 +376,7 @@ void __init ltq_soc_init(void)
+ 				PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
+ 				PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
+ 				PMU_PPE_QSB | PMU_PPE_TOP);
+		clkdev_add_pmu("1f203000.rcu", "gphy", 0, PMU_GPHY);
+ 	} else if (of_machine_is_compatible("lantiq,ar9")) {
+ 		clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
+ 				ltq_ar9_fpi_hz(), CLOCK_250M);
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0030-MIPS-lantiq-add-pcie-driver.patch
+++ b/target/linux/lantiq/patches-3.8/0030-MIPS-lantiq-add-pcie-driver.patch
--- a/target/linux/lantiq/patches-3.8/0031-MIPS-lantiq-adds-minimal-dcdc-driver.patch
+++ b/target/linux/lantiq/patches-3.8/0031-MIPS-lantiq-adds-minimal-dcdc-driver.patch
@ -0,0 +1,106 @@
+From 1f95983593d5b6634c13ead8f923237484dc611e Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 5 Dec 2012 17:38:48 +0100
+Subject: [PATCH 31/40] MIPS: lantiq: adds minimal dcdc driver
+
+This driver so far only reads the core voltage.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/lantiq/xway/Makefile |    2 +-
+ arch/mips/lantiq/xway/dcdc.c   |   74 ++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 75 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/lantiq/xway/dcdc.c
+
+diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
+index 7a13660..087497d 100644
+--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
+@@ -1,3 +1,3 @@
+-obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o
+obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
+ 
+ obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
+diff --git a/arch/mips/lantiq/xway/dcdc.c b/arch/mips/lantiq/xway/dcdc.c
+new file mode 100644
+index 0000000..8dd871a
+--- /dev/null
+++ b/arch/mips/lantiq/xway/dcdc.c
+@@ -0,0 +1,74 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
+ *  Copyright (C) 2010 Sameer Ahmad, Lantiq GmbH
+ */
+
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of_irq.h>
+
+#include <lantiq_soc.h>
+
+/* Bias and regulator Setup Register */
+#define DCDC_BIAS_VREG0	0xa
+/* Bias and regulator Setup Register */
+#define DCDC_BIAS_VREG1	0xb
+
+#define dcdc_w8(x, y)	ltq_w8((x), dcdc_membase + (y))
+#define dcdc_r8(x)	ltq_r8(dcdc_membase + (x))
+
+static void __iomem *dcdc_membase;
+
+static int dcdc_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "Failed to get resource\n");
+		return -ENOMEM;
+	}
+
+	/* remap dcdc register range */
+	dcdc_membase = devm_request_and_ioremap(&pdev->dev, res);
+	if (!dcdc_membase) {
+		dev_err(&pdev->dev, "Failed to remap resource\n");
+		return -ENOMEM;
+	}
+
+	dev_info(&pdev->dev, "Core Voltage : %d mV\n", dcdc_r8(DCDC_BIAS_VREG1) * 8);
+
+	return 0;
+}
+
+static const struct of_device_id dcdc_match[] = {
+	{ .compatible = "lantiq,dcdc-xrx200" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, dcdc_match);
+
+static struct platform_driver dcdc_driver = {
+	.probe = dcdc_probe,
+	.driver = {
+		.name = "dcdc-xrx200",
+		.owner = THIS_MODULE,
+		.of_match_table = dcdc_match,
+	},
+};
+
+int __init dcdc_init(void)
+{
+	int ret = platform_driver_register(&dcdc_driver);
+
+	if (ret)
+		pr_info("dcdc: Error registering platform driver\n");
+	return ret;
+}
+
+arch_initcall(dcdc_init);
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0032-MTD-lantiq-Add-NAND-support-on-Lantiq-Falcon-SoC.patch
+++ b/target/linux/lantiq/patches-3.8/0032-MTD-lantiq-Add-NAND-support-on-Lantiq-Falcon-SoC.patch
@ -0,0 +1,138 @@
+From 2fd60458657ac96ab71ba4831cfb397145b3c989 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 30 Jan 2013 21:12:47 +0100
+Subject: [PATCH 32/40] MTD: lantiq: Add NAND support on Lantiq Falcon SoC.
+
+The driver uses plat_nand. As the platform_device is loaded from DT, we need
+to lookup the node and attach our falcon specific "struct platform_nand_data"
+to it.
+
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mtd/nand/Kconfig       |    8 ++++
+ drivers/mtd/nand/Makefile      |    1 +
+ drivers/mtd/nand/falcon_nand.c |   83 ++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 92 insertions(+)
+ create mode 100644 drivers/mtd/nand/falcon_nand.c
+
+diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
+index 5819eb5..058939d 100644
+--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
+@@ -575,4 +575,12 @@ config MTD_NAND_XWAY
+ 	  Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
+ 	  to the External Bus Unit (EBU).
+ 
+config MTD_NAND_FALCON
+	tristate "Support for NAND on Lantiq FALC-ON SoC"
+	depends on LANTIQ && SOC_FALCON
+	select MTD_NAND_PLATFORM
+	help
+	  Enables support for NAND Flash chips on Lantiq FALC-ON SoCs. NAND is
+	  attached to the External Bus Unit (EBU).
+
+ endif # MTD_NAND
+diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
+index d76d912..1a61bf0 100644
+--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
+@@ -53,5 +53,6 @@ obj-$(CONFIG_MTD_NAND_JZ4740)		+= jz4740_nand.o
+ obj-$(CONFIG_MTD_NAND_GPMI_NAND)	+= gpmi-nand/
+ obj-$(CONFIG_MTD_NAND_XWAY)		+= xway_nand.o
+ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)	+= bcm47xxnflash/
+obj-$(CONFIG_MTD_NAND_FALCON)		+= falcon_nand.o
+ 
+ nand-objs := nand_base.o nand_bbt.o
+diff --git a/drivers/mtd/nand/falcon_nand.c b/drivers/mtd/nand/falcon_nand.c
+new file mode 100644
+index 0000000..13458d3
+--- /dev/null
+++ b/drivers/mtd/nand/falcon_nand.c
+@@ -0,0 +1,83 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/mtd/nand.h>
+#include <linux/of_platform.h>
+
+#include <lantiq_soc.h>
+
+/* address lines used for NAND control signals */
+#define NAND_ADDR_ALE		0x10000
+#define NAND_ADDR_CLE		0x20000
+
+/* Ready/Busy Status */
+#define MODCON_STS		0x0002
+
+/* Ready/Busy Status Edge */
+#define MODCON_STSEDGE		0x0004
+#define LTQ_EBU_MODCON		0x000C
+
+static const char const *part_probes[] = { "cmdlinepart", "ofpart", NULL };
+
+static int falcon_nand_ready(struct mtd_info *mtd)
+{
+	u32 modcon = ltq_ebu_r32(LTQ_EBU_MODCON);
+
+	return (((modcon & (MODCON_STS | MODCON_STSEDGE)) ==
+						(MODCON_STS | MODCON_STSEDGE)));
+}
+
+static void falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+	unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE);
+
+		if (ctrl & NAND_CLE)
+			nandaddr |= NAND_ADDR_CLE;
+		if (ctrl & NAND_ALE)
+			nandaddr |= NAND_ADDR_ALE;
+
+		this->IO_ADDR_W = (void __iomem *) nandaddr;
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+static struct platform_nand_data falcon_nand_data = {
+	.chip = {
+		.nr_chips		= 1,
+		.chip_delay		= 25,
+		.part_probe_types	= part_probes,
+	},
+	.ctrl = {
+		.cmd_ctrl		= falcon_hwcontrol,
+		.dev_ready		= falcon_nand_ready,
+	}
+};
+
+int __init falcon_register_nand(void)
+{
+	struct device_node *node;
+	struct platform_device *pdev;
+
+	node = of_find_compatible_node(NULL, NULL, "lantiq,nand-falcon");
+	if (!node)
+		return -1;
+	pdev = of_find_device_by_node(node);
+	if (pdev)
+		pdev->dev.platform_data = &falcon_nand_data;
+	of_node_put(node);
+	return 0;
+}
+
+arch_initcall(falcon_register_nand);
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0033-MTD-lantiq-xway-make-nand-actually-work.patch
+++ b/target/linux/lantiq/patches-3.8/0033-MTD-lantiq-xway-make-nand-actually-work.patch
@ -0,0 +1,122 @@
+From cc77f36d2ea812027dc2a8a94c788c4c145f82dc Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 22 Oct 2012 10:25:39 +0200
+Subject: [PATCH 33/40] MTD: lantiq: xway: make nand actually work
+
+http://lists.infradead.org/pipermail/linux-mtd/2012-September/044240.html
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mtd/nand/xway_nand.c |   54 +++++++++++++++++++++++++++++++++++-------
+ 1 file changed, 45 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/mtd/nand/xway_nand.c b/drivers/mtd/nand/xway_nand.c
+index 3f81dc8..49b2e47 100644
+--- a/drivers/mtd/nand/xway_nand.c
+++ b/drivers/mtd/nand/xway_nand.c
+@@ -54,19 +54,29 @@
+ #define NAND_CON_CSMUX		(1 << 1)
+ #define NAND_CON_NANDM		1
+ 
+static u32 xway_latchcmd;
+
+ static void xway_reset_chip(struct nand_chip *chip)
+ {
+ 	unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
+ 	unsigned long flags;
+	unsigned long timeout;
+ 
+ 	nandaddr &= ~NAND_WRITE_ADDR;
+ 	nandaddr |= NAND_WRITE_CMD;
+ 
+ 	/* finish with a reset */
+	timeout = jiffies + msecs_to_jiffies(200);
+
+ 	spin_lock_irqsave(&ebu_lock, flags);
+
+ 	writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr);
+-	while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
+-		;
+	do {
+		if ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
+			break;
+		cond_resched();
+	} while (!time_after_eq(jiffies, timeout));
+
+ 	spin_unlock_irqrestore(&ebu_lock, flags);
+ }
+ 
+@@ -94,17 +104,15 @@ static void xway_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+ 	unsigned long flags;
+ 
+ 	if (ctrl & NAND_CTRL_CHANGE) {
+-		nandaddr &= ~(NAND_WRITE_CMD | NAND_WRITE_ADDR);
+ 		if (ctrl & NAND_CLE)
+-			nandaddr |= NAND_WRITE_CMD;
+-		else
+-			nandaddr |= NAND_WRITE_ADDR;
+-		this->IO_ADDR_W = (void __iomem *) nandaddr;
+			xway_latchcmd = NAND_WRITE_CMD;
+		else if (ctrl & NAND_ALE)
+			xway_latchcmd = NAND_WRITE_ADDR;
+ 	}
+ 
+ 	if (cmd != NAND_CMD_NONE) {
+ 		spin_lock_irqsave(&ebu_lock, flags);
+-		writeb(cmd, this->IO_ADDR_W);
+		writeb(cmd, (void __iomem *) (nandaddr | xway_latchcmd));
+ 		while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
+ 			;
+ 		spin_unlock_irqrestore(&ebu_lock, flags);
+@@ -124,12 +132,38 @@ static unsigned char xway_read_byte(struct mtd_info *mtd)
+ 	int ret;
+ 
+ 	spin_lock_irqsave(&ebu_lock, flags);
+-	ret = ltq_r8((void __iomem *)(nandaddr + NAND_READ_DATA));
+	ret = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA));
+ 	spin_unlock_irqrestore(&ebu_lock, flags);
+ 
+ 	return ret;
+ }
+ 
+static void xway_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+	struct nand_chip *this = mtd->priv;
+	unsigned long nandaddr = (unsigned long) this->IO_ADDR_R;
+	unsigned long flags;
+	int i;
+
+	spin_lock_irqsave(&ebu_lock, flags);
+	for (i = 0; i < len; i++)
+		buf[i] = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA));
+	spin_unlock_irqrestore(&ebu_lock, flags);
+}
+
+static void xway_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	struct nand_chip *this = mtd->priv;
+	unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
+	unsigned long flags;
+	int i;
+
+	spin_lock_irqsave(&ebu_lock, flags);
+	for (i = 0; i < len; i++)
+		ltq_w8(buf[i], (void __iomem *)nandaddr);
+	spin_unlock_irqrestore(&ebu_lock, flags);
+}
+
+ static int xway_nand_probe(struct platform_device *pdev)
+ {
+ 	struct nand_chip *this = platform_get_drvdata(pdev);
+@@ -175,6 +209,8 @@ static struct platform_nand_data xway_nand_data = {
+ 		.dev_ready	= xway_dev_ready,
+ 		.select_chip	= xway_select_chip,
+ 		.read_byte	= xway_read_byte,
+		.read_buf	= xway_read_buf,
+		.write_buf	= xway_write_buf,
+ 	}
+ };
+ 
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0034-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch
+++ b/target/linux/lantiq/patches-3.8/0034-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch
@ -0,0 +1,29 @@
+From 88bc909507f7e9347a24e38185a11a38e51cc773 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 13 Mar 2013 10:04:34 +0100
+Subject: [PATCH 34/40] MTD: lantiq: handle NO_XIP on cfi0001 flash
+
+---
+ drivers/mtd/maps/lantiq-flash.c |    6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mtd/maps/lantiq-flash.c b/drivers/mtd/maps/lantiq-flash.c
+index 3c3c791..343cfaa 100644
+--- a/drivers/mtd/maps/lantiq-flash.c
+++ b/drivers/mtd/maps/lantiq-flash.c
+@@ -134,7 +134,11 @@ ltq_mtd_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	ltq_mtd->map = kzalloc(sizeof(struct map_info), GFP_KERNEL);
+-	ltq_mtd->map->phys = ltq_mtd->res->start;
+	if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
+		ltq_mtd->map->phys = NO_XIP;
+	else
+		ltq_mtd->map->phys = ltq_mtd->res->start;
+	ltq_mtd->res->start;
+ 	ltq_mtd->map->size = resource_size(ltq_mtd->res);
+ 	ltq_mtd->map->virt = devm_request_and_ioremap(&pdev->dev, ltq_mtd->res);
+ 	if (!ltq_mtd->map->virt) {
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0035-owrt-generic-dtb-image-hack.patch
+++ b/target/linux/lantiq/patches-3.8/0035-owrt-generic-dtb-image-hack.patch
@ -0,0 +1,26 @@
+From d9e7323db95818a92fc38e47e386ffb1a6fead5d Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 13 Mar 2013 09:34:03 +0100
+Subject: [PATCH 35/40] owrt: generic dtb image hack
+
+---
+ arch/mips/kernel/head.S |    3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
+index fcf9731..dc7fa6e 100644
+--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
+@@ -140,6 +140,9 @@ FEXPORT(__kernel_entry)
+ 	j	kernel_entry
+ #endif
+ 
+	.ascii  "OWRTDTB:"
+	EXPORT(__image_dtb)
+	.fill   0x4000
+ 	__REF
+ 
+ NESTED(kernel_entry, 16, sp)			# kernel entry point
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0036-owrt-lantiq-dtb-image-hack.patch
+++ b/target/linux/lantiq/patches-3.8/0036-owrt-lantiq-dtb-image-hack.patch
@ -0,0 +1,48 @@
+From 5128799df668a7ff5b2861fab39f9f788369eb43 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 13 Mar 2013 09:36:16 +0100
+Subject: [PATCH 36/40] owrt: lantiq dtb image hack
+
+---
+ arch/mips/lantiq/Makefile |    2 --
+ arch/mips/lantiq/prom.c   |    4 +++-
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile
+index d6bdc57..690257a 100644
+--- a/arch/mips/lantiq/Makefile
+++ b/arch/mips/lantiq/Makefile
+@@ -6,8 +6,6 @@
+ 
+ obj-y := irq.o clk.o prom.o
+ 
+-obj-y += dts/
+-
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+ 
+ obj-$(CONFIG_SOC_TYPE_XWAY) += xway/
+diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
+index 9f9e875..72b183a 100644
+--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
+@@ -57,6 +57,8 @@ static void __init prom_init_cmdline(void)
+ 	}
+ }
+ 
+extern struct boot_param_header __image_dtb;
+
+ void __init plat_mem_setup(void)
+ {
+ 	ioport_resource.start = IOPORT_RESOURCE_START;
+@@ -70,7 +72,7 @@ void __init plat_mem_setup(void)
+ 	 * Load the builtin devicetree. This causes the chosen node to be
+ 	 * parsed resulting in our memory appearing
+ 	 */
+-	__dt_setup_arch(&__dtb_start);
+	__dt_setup_arch(&__image_dtb);
+ }
+ 
+ void __init device_tree_init(void)
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0037-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch
+++ b/target/linux/lantiq/patches-3.8/0037-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch
@ -0,0 +1,570 @@
+From 0c9b05716ac0e597ae0f81a96ff68e54716decc9 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 13 Mar 2013 10:02:58 +0100
+Subject: [PATCH 37/40] owrt: lantiq: wifi and ethernet eeprom handling
+
+---
+ arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h  |    6 +
+ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |    3 +
+ arch/mips/lantiq/xway/Makefile                     |    3 +
+ arch/mips/lantiq/xway/ath_eep.c                    |  206 ++++++++++++++++++++
+ arch/mips/lantiq/xway/eth_mac.c                    |   76 ++++++++
+ arch/mips/lantiq/xway/pci-ath-fixup.c              |  109 +++++++++++
+ arch/mips/lantiq/xway/rt_eep.c                     |   60 ++++++
+ drivers/net/ethernet/lantiq_etop.c                 |   10 +-
+ 8 files changed, 469 insertions(+), 4 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h
+ create mode 100644 arch/mips/lantiq/xway/ath_eep.c
+ create mode 100644 arch/mips/lantiq/xway/eth_mac.c
+ create mode 100644 arch/mips/lantiq/xway/pci-ath-fixup.c
+ create mode 100644 arch/mips/lantiq/xway/rt_eep.c
+
+diff --git a/arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h b/arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h
+new file mode 100644
+index 0000000..095d2619
+--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h
+@@ -0,0 +1,6 @@
+#ifndef _PCI_ATH_FIXUP
+#define _PCI_ATH_FIXUP
+
+void ltq_pci_ath_fixup(unsigned slot, u16 *cal_data) __init;
+
+#endif /* _PCI_ATH_FIXUP */
+diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+index 133336b..779715c 100644
+--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+@@ -90,5 +90,8 @@ int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr);
+ extern void ltq_pmu_enable(unsigned int module);
+ extern void ltq_pmu_disable(unsigned int module);
+ 
+/* allow the ethernet driver to load a flash mapped mac addr */
+const u8* ltq_get_eth_mac(void);
+
+ #endif /* CONFIG_SOC_TYPE_XWAY */
+ #endif /* _LTQ_XWAY_H__ */
+diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
+index 087497d..51f0eba 100644
+--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
+@@ -1,3 +1,6 @@
+ obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
+ 
+obj-y += eth_mac.o
+obj-$(CONFIG_PCI) += ath_eep.o rt_eep.o pci-ath-fixup.o
+
+ obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
+diff --git a/arch/mips/lantiq/xway/ath_eep.c b/arch/mips/lantiq/xway/ath_eep.c
+new file mode 100644
+index 0000000..96da7c1
+--- /dev/null
+++ b/arch/mips/lantiq/xway/ath_eep.c
+@@ -0,0 +1,206 @@
+/*
+ *  Copyright (C) 2011 Luca Olivetti <luca@ventoso.org>
+ *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ *  Copyright (C) 2011 Andrej Vlašić <andrej.vlasic0@gmail.com>
+ *  Copyright (C) 2013 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/etherdevice.h>
+#include <linux/ath5k_platform.h>
+#include <linux/ath9k_platform.h>
+#include <linux/pci.h>
+#include <pci-ath-fixup.h>
+
+extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev);
+struct ath5k_platform_data ath5k_pdata;
+struct ath9k_platform_data ath9k_pdata = {
+	.led_pin = -1,
+};
+static u16 ath5k_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS];
+static u8 athxk_eeprom_mac[6];
+
+static int ath9k_pci_plat_dev_init(struct pci_dev *dev)
+{
+	dev->dev.platform_data = &ath9k_pdata;
+	return 0;
+}
+
+int __init of_ath9k_eeprom_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct resource *eep_res, *mac_res;
+	void __iomem *eep, *mac;
+	int mac_offset;
+	u32 mac_inc = 0, pci_slot = 0;
+	int i;
+	u16 *eepdata, sum, el;
+
+	eep_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	mac_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+
+	if (!eep_res) {
+		dev_err(&pdev->dev, "failed to load eeprom address\n");
+		return -ENODEV;
+	}
+	if (resource_size(eep_res) != ATH9K_PLAT_EEP_MAX_WORDS) {
+		dev_err(&pdev->dev, "eeprom has an invalid size\n");
+		return -EINVAL;
+	}
+
+	eep = ioremap(eep_res->start, resource_size(eep_res));
+	memcpy_fromio(ath9k_pdata.eeprom_data, eep, ATH9K_PLAT_EEP_MAX_WORDS);
+
+	if (of_find_property(np, "ath,eep-swap", NULL)) {
+		ath9k_pdata.endian_check = true;
+
+		dev_info(&pdev->dev, "endian check enabled.\n");
+	}
+
+	if (of_find_property(np, "ath,eep-csum", NULL)) {
+		sum = ath9k_pdata.eeprom_data[0x200>>1];
+		el = sum / sizeof(u16) - 2;  /* skip length and (old) checksum */
+		eepdata = (u16 *) (&ath9k_pdata.eeprom_data[0x204>>1]); /* after checksum */
+		for (i = 0; i < el; i++)
+			sum ^= *eepdata++;
+		sum ^= 0xffff;
+		ath9k_pdata.eeprom_data[0x202>>1] = sum;
+
+		dev_info(&pdev->dev, "checksum fixed.\n");
+	}
+
+	if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) {
+		memcpy_fromio(athxk_eeprom_mac, (void*) ath9k_pdata.eeprom_data, 6);
+	} else if (mac_res) {
+		if (resource_size(mac_res) != 6) {
+			dev_err(&pdev->dev, "mac has an invalid size\n");
+			return -EINVAL;
+		}
+		mac = ioremap(mac_res->start, resource_size(mac_res));
+		memcpy_fromio(athxk_eeprom_mac, mac, 6);
+	} else {
+		dev_warn(&pdev->dev, "using random mac\n");
+		random_ether_addr(athxk_eeprom_mac);
+	}
+
+	if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc))
+		athxk_eeprom_mac[5] += mac_inc;
+
+	ath9k_pdata.macaddr = athxk_eeprom_mac;
+	ltq_pci_plat_dev_init = ath9k_pci_plat_dev_init;
+
+	if (!of_property_read_u32(np, "ath,pci-slot", &pci_slot)) {
+		ltq_pci_ath_fixup(pci_slot, ath9k_pdata.eeprom_data);
+
+		dev_info(&pdev->dev, "pci slot: %u\n", pci_slot);
+	}
+
+	dev_info(&pdev->dev, "loaded ath9k eeprom\n");
+
+	return 0;
+}
+
+static struct of_device_id ath9k_eeprom_ids[] = {
+	{ .compatible = "ath9k,eeprom" },
+	{ }
+};
+
+static struct platform_driver ath9k_eeprom_driver = {
+	.driver		= {
+		.name		= "ath9k,eeprom",
+		.owner	= THIS_MODULE,
+		.of_match_table	= of_match_ptr(ath9k_eeprom_ids),
+	},
+};
+
+static int __init of_ath9k_eeprom_init(void)
+{
+	return platform_driver_probe(&ath9k_eeprom_driver, of_ath9k_eeprom_probe);
+}
+arch_initcall(of_ath9k_eeprom_init);
+
+
+static int ath5k_pci_plat_dev_init(struct pci_dev *dev)
+{
+	dev->dev.platform_data = &ath5k_pdata;
+	return 0;
+}
+
+int __init of_ath5k_eeprom_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct resource *eep_res, *mac_res;
+	void __iomem *eep, *mac;
+	int mac_offset;
+	u32 mac_inc = 0;
+	int i;
+
+	eep_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	mac_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+
+	if (!eep_res) {
+		dev_err(&pdev->dev, "failed to load eeprom address\n");
+		return -ENODEV;
+	}
+	if (resource_size(eep_res) != ATH5K_PLAT_EEP_MAX_WORDS) {
+		dev_err(&pdev->dev, "eeprom has an invalid size\n");
+		return -EINVAL;
+	}
+
+	eep = ioremap(eep_res->start, resource_size(eep_res));
+	memcpy_fromio(ath5k_eeprom_data, eep, ATH5K_PLAT_EEP_MAX_WORDS);
+
+	if (of_find_property(np, "ath,eep-swap", NULL))
+		for (i = 0; i < (ATH5K_PLAT_EEP_MAX_WORDS >> 1); i++)
+				ath5k_eeprom_data[i] = swab16(ath5k_eeprom_data[i]);
+
+	if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) {
+		memcpy_fromio(athxk_eeprom_mac, (void*) ath5k_eeprom_data, 6);
+	} else if (mac_res) {
+		if (resource_size(mac_res) != 6) {
+			dev_err(&pdev->dev, "mac has an invalid size\n");
+			return -EINVAL;
+		}
+		mac = ioremap(mac_res->start, resource_size(mac_res));
+		memcpy_fromio(athxk_eeprom_mac, mac, 6);
+	} else {
+		dev_warn(&pdev->dev, "using random mac\n");
+		random_ether_addr(athxk_eeprom_mac);
+	}
+
+	if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc))
+		athxk_eeprom_mac[5] += mac_inc;
+
+	ath5k_pdata.eeprom_data = ath5k_eeprom_data;
+	ath5k_pdata.macaddr = athxk_eeprom_mac;
+	ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init;
+
+	dev_info(&pdev->dev, "loaded ath5k eeprom\n");
+
+	return 0;
+}
+
+static struct of_device_id ath5k_eeprom_ids[] = {
+	{ .compatible = "ath5k,eeprom" },
+	{ }
+};
+
+static struct platform_driver ath5k_eeprom_driver = {
+	.driver		= {
+		.name		= "ath5k,eeprom",
+		.owner	= THIS_MODULE,
+		.of_match_table	= of_match_ptr(ath5k_eeprom_ids),
+	},
+};
+
+static int __init of_ath5k_eeprom_init(void)
+{
+	return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
+}
+device_initcall(of_ath5k_eeprom_init);
+diff --git a/arch/mips/lantiq/xway/eth_mac.c b/arch/mips/lantiq/xway/eth_mac.c
+new file mode 100644
+index 0000000..d288a0e
+--- /dev/null
+++ b/arch/mips/lantiq/xway/eth_mac.c
+@@ -0,0 +1,76 @@
+/*
+ *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/if_ether.h>
+
+static u8 eth_mac[6];
+static int eth_mac_set;
+
+const u8* ltq_get_eth_mac(void)
+{
+	return eth_mac;
+}
+
+static int __init setup_ethaddr(char *str)
+{
+	eth_mac_set = mac_pton(str, eth_mac);
+	return !eth_mac_set;
+}
+__setup("ethaddr=", setup_ethaddr);
+
+int __init of_eth_mac_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct resource *mac_res;
+	void __iomem *mac;
+	u32 mac_inc = 0;
+
+	if (eth_mac_set) {
+		dev_err(&pdev->dev, "mac was already set by bootloader\n");
+		return -EINVAL;
+	}
+	mac_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	if (!mac_res) {
+		dev_err(&pdev->dev, "failed to load mac\n");
+		return -EINVAL;
+	}
+	if (resource_size(mac_res) != 6) {
+		dev_err(&pdev->dev, "mac has an invalid size\n");
+		return -EINVAL;
+	}
+	mac = ioremap(mac_res->start, resource_size(mac_res));
+	memcpy_fromio(eth_mac, mac, 6);
+
+	if (!of_property_read_u32(np, "mac-increment", &mac_inc))
+		eth_mac[5] += mac_inc;
+
+	return 0;
+}
+
+static struct of_device_id eth_mac_ids[] = {
+	{ .compatible = "lantiq,eth-mac" },
+	{ /* sentinel */ }
+};
+
+static struct platform_driver eth_mac_driver = {
+	.driver		= {
+		.name		= "lantiq,eth-mac",
+		.owner	= THIS_MODULE,
+		.of_match_table	= of_match_ptr(eth_mac_ids),
+	},
+};
+
+static int __init of_eth_mac_init(void)
+{
+	return platform_driver_probe(&eth_mac_driver, of_eth_mac_probe);
+}
+device_initcall(of_eth_mac_init);
+diff --git a/arch/mips/lantiq/xway/pci-ath-fixup.c b/arch/mips/lantiq/xway/pci-ath-fixup.c
+new file mode 100644
+index 0000000..c87ffb2
+--- /dev/null
+++ b/arch/mips/lantiq/xway/pci-ath-fixup.c
+@@ -0,0 +1,109 @@
+/*
+ *  Atheros AP94 reference board PCI initialization
+ *
+ *  Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <lantiq_soc.h>
+
+#define LTQ_PCI_MEM_BASE		0x18000000
+
+struct ath_fixup {
+	u16		*cal_data;
+	unsigned	slot;
+};
+
+static int ath_num_fixups;
+static struct ath_fixup ath_fixups[2];
+
+static void ath_pci_fixup(struct pci_dev *dev)
+{
+	void __iomem *mem;
+	u16 *cal_data = NULL;
+	u16 cmd;
+	u32 bar0;
+	u32 val;
+	unsigned i;
+
+	for (i = 0; i < ath_num_fixups; i++) {
+		if (ath_fixups[i].cal_data == NULL)
+			continue;
+
+		if (ath_fixups[i].slot != PCI_SLOT(dev->devfn))
+			continue;
+
+		cal_data = ath_fixups[i].cal_data;
+		break;
+	}
+
+	if (cal_data == NULL)
+		return;
+
+	if (*cal_data != 0xa55a) {
+		pr_err("pci %s: invalid calibration data\n", pci_name(dev));
+		return;
+	}
+
+	pr_info("pci %s: fixup device configuration\n", pci_name(dev));
+
+	mem = ioremap(LTQ_PCI_MEM_BASE, 0x10000);
+	if (!mem) {
+		pr_err("pci %s: ioremap error\n", pci_name(dev));
+		return;
+	}
+
+	pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
+	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, LTQ_PCI_MEM_BASE);
+	pci_read_config_word(dev, PCI_COMMAND, &cmd);
+	cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_write_config_word(dev, PCI_COMMAND, cmd);
+
+	/* set pointer to first reg address */
+	cal_data += 3;
+	while (*cal_data != 0xffff) {
+		u32 reg;
+		reg = *cal_data++;
+		val = *cal_data++;
+		val |= (*cal_data++) << 16;
+
+		ltq_w32(swab32(val), mem + reg);
+		udelay(100);
+	}
+
+	pci_read_config_dword(dev, PCI_VENDOR_ID, &val);
+	dev->vendor = val & 0xffff;
+	dev->device = (val >> 16) & 0xffff;
+
+	pci_read_config_dword(dev, PCI_CLASS_REVISION, &val);
+	dev->revision = val & 0xff;
+	dev->class = val >> 8; /* upper 3 bytes */
+
+	pr_info("pci %s: fixup info: [%04x:%04x] revision %02x class %#08x\n", 
+		pci_name(dev), dev->vendor, dev->device, dev->revision, dev->class);
+
+	pci_read_config_word(dev, PCI_COMMAND, &cmd);
+	cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+	pci_write_config_word(dev, PCI_COMMAND, cmd);
+
+	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
+
+	iounmap(mem);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath_pci_fixup);
+
+void __init ltq_pci_ath_fixup(unsigned slot, u16 *cal_data)
+{
+	if (ath_num_fixups >= ARRAY_SIZE(ath_fixups))
+		return;
+
+	ath_fixups[ath_num_fixups].slot = slot;
+	ath_fixups[ath_num_fixups].cal_data = cal_data;
+	ath_num_fixups++;
+}
+diff --git a/arch/mips/lantiq/xway/rt_eep.c b/arch/mips/lantiq/xway/rt_eep.c
+new file mode 100644
+index 0000000..00f2d4c
+--- /dev/null
+++ b/arch/mips/lantiq/xway/rt_eep.c
+@@ -0,0 +1,60 @@
+/*
+ *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/rt2x00_platform.h>
+
+extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev);
+static struct rt2x00_platform_data rt2x00_pdata;
+
+static int rt2x00_pci_plat_dev_init(struct pci_dev *dev)
+{
+	dev->dev.platform_data = &rt2x00_pdata;
+	return 0;
+}
+
+int __init of_ralink_eeprom_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	const char *eeprom;
+
+	if (of_property_read_string(np, "ralink,eeprom", &eeprom)) {
+		dev_err(&pdev->dev, "failed to load eeprom filename\n");
+		return 0;
+	}
+
+	rt2x00_pdata.eeprom_file_name = kstrdup(eeprom, GFP_KERNEL);
+//	rt2x00_pdata.mac_address = mac;
+	ltq_pci_plat_dev_init = rt2x00_pci_plat_dev_init;
+
+	dev_info(&pdev->dev, "using %s as eeprom\n", eeprom);
+
+	return 0;
+}
+
+static struct of_device_id ralink_eeprom_ids[] = {
+	{ .compatible = "ralink,eeprom" },
+	{ }
+};
+
+static struct platform_driver ralink_eeprom_driver = {
+	.driver		= {
+		.name		= "ralink,eeprom",
+		.owner	= THIS_MODULE,
+		.of_match_table	= of_match_ptr(ralink_eeprom_ids),
+	},
+};
+
+static int __init of_ralink_eeprom_init(void)
+{
+	return platform_driver_probe(&ralink_eeprom_driver, of_ralink_eeprom_probe);
+}
+device_initcall(of_ralink_eeprom_init);
+diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
+index 91a37f1..fa23a7e 100644
+--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
+@@ -826,7 +826,8 @@ ltq_etop_init(struct net_device *dev)
+ 
+ 	ltq_etop_change_mtu(dev, 1500);
+ 
+-	memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
+	if (priv->mac)
+		memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
+ 	if (!is_valid_ether_addr(mac.sa_data)) {
+ 		pr_warn("etop: invalid MAC, using random\n");
+ 		random_ether_addr(mac.sa_data);
+@@ -885,8 +886,7 @@ static const struct net_device_ops ltq_eth_netdev_ops = {
+ 	.ndo_tx_timeout = ltq_etop_tx_timeout,
+ };
+ 
+-static int __devinit
+-ltq_etop_probe(struct platform_device *pdev)
+static int ltq_etop_probe(struct platform_device *pdev)
+ {
+ 	struct net_device *dev;
+ 	struct ltq_etop_priv *priv;
+@@ -950,7 +950,9 @@ ltq_etop_probe(struct platform_device *pdev)
+ 	priv->tx_irq = irqres[0].start;
+ 	priv->rx_irq = irqres[1].start;
+ 	priv->mii_mode = of_get_phy_mode(pdev->dev.of_node);
+-	priv->mac = of_get_mac_address(pdev->dev.of_node);
+	priv->mac = ltq_get_eth_mac();
+	if (!priv->mac)
+		priv->mac = of_get_mac_address(pdev->dev.of_node);
+ 
+ 	priv->clk_ppe = clk_get(&pdev->dev, NULL);
+ 	if (IS_ERR(priv->clk_ppe))
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0038-owrt-lantiq-handle-vmmc-memory-reservation.patch
+++ b/target/linux/lantiq/patches-3.8/0038-owrt-lantiq-handle-vmmc-memory-reservation.patch
@ -0,0 +1,95 @@
+From 6af001cc662f4aa3740c550ac43c6b6f75df67c8 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 13 Mar 2013 10:04:01 +0100
+Subject: [PATCH 38/40] owrt: lantiq: handle vmmc memory reservation
+
+---
+ arch/mips/lantiq/xway/Makefile |    2 +-
+ arch/mips/lantiq/xway/vmmc.c   |   63 ++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 64 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/lantiq/xway/vmmc.c
+
+diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
+index 51f0eba..3a01d22 100644
+--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
+@@ -1,6 +1,6 @@
+ obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
+ 
+-obj-y += eth_mac.o
+obj-y += eth_mac.o vmmc.o
+ obj-$(CONFIG_PCI) += ath_eep.o rt_eep.o pci-ath-fixup.o
+ 
+ obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
+diff --git a/arch/mips/lantiq/xway/vmmc.c b/arch/mips/lantiq/xway/vmmc.c
+new file mode 100644
+index 0000000..6dedf77
+--- /dev/null
+++ b/arch/mips/lantiq/xway/vmmc.c
+@@ -0,0 +1,63 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of_gpio.h>
+#include <linux/dma-mapping.h>
+
+#include <lantiq_soc.h>
+
+static unsigned int *cp1_base = 0;
+unsigned int* ltq_get_cp1_base(void)
+{
+	if (!cp1_base)
+		panic("no cp1 base was set\n");
+	return cp1_base;
+}
+EXPORT_SYMBOL(ltq_get_cp1_base);
+
+static int vmmc_probe(struct platform_device *pdev)
+{
+#define CP1_SIZE       (1 << 20)
+	int gpio_count;
+	dma_addr_t dma;
+	cp1_base =
+		(void*)CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, &dma, GFP_ATOMIC));
+
+	gpio_count = of_gpio_count(pdev->dev.of_node);
+	while (gpio_count) {
+		enum of_gpio_flags flags;
+		int gpio = of_get_gpio_flags(pdev->dev.of_node, --gpio_count, &flags);
+		if (gpio_request(gpio, "vmmc-relay"))
+			continue;
+		dev_info(&pdev->dev, "requested GPIO %d\n", gpio);
+		gpio_direction_output(gpio, (flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1));
+	}
+
+	dev_info(&pdev->dev, "reserved %dMB at 0x%p", CP1_SIZE >> 20, cp1_base);
+
+	return 0;
+}
+
+static const struct of_device_id vmmc_match[] = {
+	{ .compatible = "lantiq,vmmc" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, vmmc_match);
+
+static struct platform_driver vmmc_driver = {
+	.probe = vmmc_probe,
+	.driver = {
+		.name = "lantiq,vmmc",
+		.owner = THIS_MODULE,
+		.of_match_table = vmmc_match,
+	},
+};
+
+module_platform_driver(vmmc_driver);
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0039-owrt-lantiq-backport-old-timer-code.patch
+++ b/target/linux/lantiq/patches-3.8/0039-owrt-lantiq-backport-old-timer-code.patch
--- a/target/linux/lantiq/patches-3.8/0040-owrt-lantiq-add-atm-hack.patch
+++ b/target/linux/lantiq/patches-3.8/0040-owrt-lantiq-add-atm-hack.patch
@ -0,0 +1,518 @@
+From ae15f50544e6012c998ef59f6c12e334da3c9bff Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 3 Aug 2012 10:27:25 +0200
+Subject: [PATCH 40/40] owrt: lantiq: add atm hack
+
+---
+ arch/mips/include/asm/mach-lantiq/lantiq_atm.h |  196 +++++++++++++++++++++++
+ arch/mips/include/asm/mach-lantiq/lantiq_ptm.h |  203 ++++++++++++++++++++++++
+ arch/mips/lantiq/irq.c                         |    2 +
+ arch/mips/mm/cache.c                           |    2 +
+ include/uapi/linux/atm.h                       |    6 +
+ net/atm/common.c                               |    6 +
+ net/atm/proc.c                                 |    2 +-
+ 7 files changed, 416 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h
+ create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
+
+diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_atm.h b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
+new file mode 100644
+index 0000000..bf045a9
+--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
+@@ -0,0 +1,196 @@
+/******************************************************************************
+**
+** FILE NAME    : ifx_atm.h
+** PROJECT      : UEIP
+** MODULES      : ATM
+**
+** DATE         : 17 Jun 2009
+** AUTHOR       : Xu Liang
+** DESCRIPTION  : Global ATM driver header file
+** COPYRIGHT    :       Copyright (c) 2006
+**                      Infineon Technologies AG
+**                      Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+**    This program is free software; you can redistribute it and/or modify
+**    it under the terms of the GNU General Public License as published by
+**    the Free Software Foundation; either version 2 of the License, or
+**    (at your option) any later version.
+**
+** HISTORY
+** $Date        $Author         $Comment
+** 07 JUL 2009  Xu Liang        Init Version
+*******************************************************************************/
+
+#ifndef IFX_ATM_H
+#define IFX_ATM_H
+
+
+
+/*!
+  \defgroup IFX_ATM UEIP Project - ATM driver module
+  \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
+ */
+
+/*!
+  \defgroup IFX_ATM_IOCTL IOCTL Commands
+  \ingroup IFX_ATM
+  \brief IOCTL Commands used by user application.
+ */
+
+/*!
+  \defgroup IFX_ATM_STRUCT Structures
+  \ingroup IFX_ATM
+  \brief Structures used by user application.
+ */
+
+/*!
+  \file ifx_atm.h
+  \ingroup IFX_ATM
+  \brief ATM driver header file
+ */
+
+
+
+/*
+ * ####################################
+ *              Definition
+ * ####################################
+ */
+
+/*!
+  \addtogroup IFX_ATM_STRUCT
+ */
+/*@{*/
+
+/*
+ *  ATM MIB
+ */
+
+/*!
+  \struct atm_cell_ifEntry_t
+  \brief Structure used for Cell Level MIB Counters.
+
+  User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL".
+ */
+typedef struct {
+	__u32	ifHCInOctets_h;     /*!< byte counter of ingress cells (upper 32 bits, total 64 bits)   */
+	__u32	ifHCInOctets_l;     /*!< byte counter of ingress cells (lower 32 bits, total 64 bits)   */
+	__u32	ifHCOutOctets_h;    /*!< byte counter of egress cells (upper 32 bits, total 64 bits)    */
+	__u32	ifHCOutOctets_l;    /*!< byte counter of egress cells (lower 32 bits, total 64 bits)    */
+	__u32	ifInErrors;         /*!< counter of error ingress cells     */
+	__u32	ifInUnknownProtos;  /*!< counter of unknown ingress cells   */
+	__u32	ifOutErrors;        /*!< counter of error egress cells      */
+} atm_cell_ifEntry_t;
+
+/*!
+  \struct atm_aal5_ifEntry_t
+  \brief Structure used for AAL5 Frame Level MIB Counters.
+
+  User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5".
+ */
+typedef struct {
+	__u32	ifHCInOctets_h;     /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
+	__u32	ifHCInOctets_l;     /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
+	__u32	ifHCOutOctets_h;    /*!< byte counter of egress packets (upper 32 bits, total 64 bits)  */
+	__u32	ifHCOutOctets_l;    /*!< byte counter of egress packets (lower 32 bits, total 64 bits)  */
+	__u32	ifInUcastPkts;      /*!< counter of ingress packets         */
+	__u32	ifOutUcastPkts;     /*!< counter of egress packets          */
+	__u32	ifInErrors;         /*!< counter of error ingress packets   */
+	__u32	ifInDiscards;       /*!< counter of dropped ingress packets */
+	__u32	ifOutErros;         /*!< counter of error egress packets    */
+	__u32	ifOutDiscards;      /*!< counter of dropped egress packets  */
+} atm_aal5_ifEntry_t;
+
+/*!
+  \struct atm_aal5_vcc_t
+  \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
+
+  This structure is a part of structure "atm_aal5_vcc_x_t".
+ */
+typedef struct {
+	__u32	aal5VccCrcErrors;       /*!< counter of ingress packets with CRC error  */
+	__u32	aal5VccSarTimeOuts;     /*!< counter of ingress packets with Re-assemble timeout    */  //no timer support yet
+	__u32	aal5VccOverSizedSDUs;   /*!< counter of oversized ingress packets       */
+} atm_aal5_vcc_t;
+
+/*!
+  \struct atm_aal5_vcc_x_t
+  \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
+
+  User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC".
+ */
+typedef struct {
+	int             vpi;        /*!< VPI of the VCC to get MIB counters */
+	int             vci;        /*!< VCI of the VCC to get MIB counters */
+	atm_aal5_vcc_t  mib_vcc;    /*!< structure to get MIB counters      */
+} atm_aal5_vcc_x_t;
+
+/*@}*/
+
+
+
+/*
+ * ####################################
+ *                IOCTL
+ * ####################################
+ */
+
+/*!
+  \addtogroup IFX_ATM_IOCTL
+ */
+/*@{*/
+
+/*
+ *  ioctl Command
+ */
+/*!
+  \brief ATM IOCTL Magic Number
+ */
+#define PPE_ATM_IOC_MAGIC       'o'
+/*!
+  \brief ATM IOCTL Command - Get Cell Level MIB Counters
+
+   This command is obsolete. User can get cell level MIB from DSL API.
+   This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
+ */
+#define PPE_ATM_MIB_CELL        _IOW(PPE_ATM_IOC_MAGIC,  0, atm_cell_ifEntry_t)
+/*!
+  \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
+
+   Get AAL5 packet counters.
+   This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
+ */
+#define PPE_ATM_MIB_AAL5        _IOW(PPE_ATM_IOC_MAGIC,  1, atm_aal5_ifEntry_t)
+/*!
+  \brief ATM IOCTL Command - Get Per PVC MIB Counters
+
+   Get AAL5 packet counters for each PVC.
+   This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
+ */
+#define PPE_ATM_MIB_VCC         _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
+/*!
+  \brief Total Number of ATM IOCTL Commands
+ */
+#define PPE_ATM_IOC_MAXNR       3
+
+/*@}*/
+
+
+
+/*
+ * ####################################
+ *                 API
+ * ####################################
+ */
+
+#ifdef __KERNEL__
+struct port_cell_info {
+    unsigned int    port_num;
+    unsigned int    tx_link_rate[2];
+};
+#endif
+
+
+
+#endif  //  IFX_ATM_H
+
+diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
+new file mode 100644
+index 0000000..698e5c3
+--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
+@@ -0,0 +1,203 @@
+/******************************************************************************
+**
+** FILE NAME    : ifx_ptm.h
+** PROJECT      : UEIP
+** MODULES      : PTM
+**
+** DATE         : 17 Jun 2009
+** AUTHOR       : Xu Liang
+** DESCRIPTION  : Global PTM driver header file
+** COPYRIGHT    :       Copyright (c) 2006
+**                      Infineon Technologies AG
+**                      Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+**    This program is free software; you can redistribute it and/or modify
+**    it under the terms of the GNU General Public License as published by
+**    the Free Software Foundation; either version 2 of the License, or
+**    (at your option) any later version.
+**
+** HISTORY
+** $Date        $Author         $Comment
+** 07 JUL 2009  Xu Liang        Init Version
+*******************************************************************************/
+
+#ifndef IFX_PTM_H
+#define IFX_PTM_H
+
+
+
+/*!
+  \defgroup IFX_PTM UEIP Project - PTM driver module
+  \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9.
+ */
+
+/*!
+  \defgroup IFX_PTM_IOCTL IOCTL Commands
+  \ingroup IFX_PTM
+  \brief IOCTL Commands used by user application.
+ */
+
+/*!
+  \defgroup IFX_PTM_STRUCT Structures
+  \ingroup IFX_PTM
+  \brief Structures used by user application.
+ */
+
+/*!
+  \file ifx_ptm.h
+  \ingroup IFX_PTM
+  \brief PTM driver header file
+ */
+
+
+
+/*
+ * ####################################
+ *              Definition
+ * ####################################
+ */
+
+
+
+/*
+ * ####################################
+ *                IOCTL
+ * ####################################
+ */
+
+/*!
+  \addtogroup IFX_PTM_IOCTL
+ */
+/*@{*/
+
+/*
+ *  ioctl Command
+ */
+/*!
+  \brief PTM IOCTL Command - Get codeword MIB counters.
+
+  This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters.
+ */
+#define IFX_PTM_MIB_CW_GET              SIOCDEVPRIVATE + 1
+/*!
+  \brief PTM IOCTL Command - Get packet MIB counters.
+
+  This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters.
+ */
+#define IFX_PTM_MIB_FRAME_GET           SIOCDEVPRIVATE + 2
+/*!
+  \brief PTM IOCTL Command - Get firmware configuration (CRC).
+
+  This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC).
+ */
+#define IFX_PTM_CFG_GET                 SIOCDEVPRIVATE + 3
+/*!
+  \brief PTM IOCTL Command - Set firmware configuration (CRC).
+
+  This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC).
+ */
+#define IFX_PTM_CFG_SET                 SIOCDEVPRIVATE + 4
+/*!
+  \brief PTM IOCTL Command - Program priority value to TX queue mapping.
+
+  This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping.
+ */
+#define IFX_PTM_MAP_PKT_PRIO_TO_Q       SIOCDEVPRIVATE + 14
+
+/*@}*/
+
+
+/*!
+  \addtogroup IFX_PTM_STRUCT
+ */
+/*@{*/
+
+/*
+ *  ioctl Data Type
+ */
+
+/*!
+  \typedef PTM_CW_IF_ENTRY_T
+  \brief Wrapping of structure "ptm_cw_ifEntry_t".
+ */
+/*!
+  \struct ptm_cw_ifEntry_t
+  \brief Structure used for CodeWord level MIB counters.
+ */
+typedef struct ptm_cw_ifEntry_t {
+    uint32_t    ifRxNoIdleCodewords;    /*!< output, number of ingress user codeword */
+    uint32_t    ifRxIdleCodewords;      /*!< output, number of ingress idle codeword */
+    uint32_t    ifRxCodingViolation;    /*!< output, number of error ingress codeword */
+    uint32_t    ifTxNoIdleCodewords;    /*!< output, number of egress user codeword */
+    uint32_t    ifTxIdleCodewords;      /*!< output, number of egress idle codeword */
+} PTM_CW_IF_ENTRY_T;
+
+/*!
+  \typedef PTM_FRAME_MIB_T
+  \brief Wrapping of structure "ptm_frame_mib_t".
+ */
+/*!
+  \struct ptm_frame_mib_t
+  \brief Structure used for packet level MIB counters.
+ */
+typedef struct ptm_frame_mib_t {
+    uint32_t    RxCorrect;      /*!< output, number of ingress packet */
+    uint32_t    TC_CrcError;    /*!< output, number of egress packet with CRC error */
+    uint32_t    RxDropped;      /*!< output, number of dropped ingress packet */
+    uint32_t    TxSend;         /*!< output, number of egress packet */
+} PTM_FRAME_MIB_T;
+
+/*!
+  \typedef IFX_PTM_CFG_T
+  \brief Wrapping of structure "ptm_cfg_t".
+ */
+/*!
+  \struct ptm_cfg_t
+  \brief Structure used for ETH/TC CRC configuration.
+ */
+typedef struct ptm_cfg_t {
+    uint32_t    RxEthCrcPresent;    /*!< input/output, ingress packet has ETH CRC */
+    uint32_t    RxEthCrcCheck;      /*!< input/output, check ETH CRC of ingress packet */
+    uint32_t    RxTcCrcCheck;       /*!< input/output, check TC CRC of ingress codeword */
+    uint32_t    RxTcCrcLen;         /*!< input/output, length of TC CRC of ingress codeword */
+    uint32_t    TxEthCrcGen;        /*!< input/output, generate ETH CRC for egress packet */
+    uint32_t    TxTcCrcGen;         /*!< input/output, generate TC CRC for egress codeword */
+    uint32_t    TxTcCrcLen;         /*!< input/output, length of TC CRC of egress codeword */
+} IFX_PTM_CFG_T;
+
+/*!
+  \typedef IFX_PTM_PRIO_Q_MAP_T
+  \brief Wrapping of structure "ppe_prio_q_map".
+ */
+/*!
+  \struct ppe_prio_q_map
+  \brief Structure used for Priority Value to TX Queue mapping.
+ */
+typedef struct ppe_prio_q_map {
+    int             pkt_prio;
+    int             qid;
+    int             vpi;    //  ignored in eth interface
+    int             vci;    //  ignored in eth interface
+} IFX_PTM_PRIO_Q_MAP_T;
+
+/*@}*/
+
+
+
+/*
+ * ####################################
+ *                 API
+ * ####################################
+ */
+
+#ifdef __KERNEL__
+struct port_cell_info {
+    unsigned int    port_num;
+    unsigned int    tx_link_rate[2];
+};
+#endif
+
+
+
+#endif  //  IFX_PTM_H
+
+diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
+index 5119487..6d2c486 100644
+--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
+@@ -14,6 +14,7 @@
+ #include <linux/of_platform.h>
+ #include <linux/of_address.h>
+ #include <linux/of_irq.h>
+#include <linux/module.h>
+ 
+ #include <asm/bootinfo.h>
+ #include <asm/irq_cpu.h>
+@@ -99,6 +100,7 @@ void ltq_mask_and_ack_irq(struct irq_data *d)
+ 	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
+ 	ltq_icu_w32(im, BIT(offset), isr);
+ }
+EXPORT_SYMBOL(ltq_mask_and_ack_irq);
+ 
+ static void ltq_ack_irq(struct irq_data *d)
+ {
+diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
+index 07cec44..a3e3872 100644
+--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
+@@ -57,6 +57,8 @@ void (*_dma_cache_wback)(unsigned long start, unsigned long size);
+ void (*_dma_cache_inv)(unsigned long start, unsigned long size);
+ 
+ EXPORT_SYMBOL(_dma_cache_wback_inv);
+EXPORT_SYMBOL(_dma_cache_wback);
+EXPORT_SYMBOL(_dma_cache_inv);
+ 
+ #endif /* CONFIG_DMA_NONCOHERENT */
+ 
+diff --git a/include/uapi/linux/atm.h b/include/uapi/linux/atm.h
+index 88399db..78c8bbc 100644
+--- a/include/uapi/linux/atm.h
+++ b/include/uapi/linux/atm.h
+@@ -130,8 +130,14 @@
+ #define ATM_ABR		4
+ #define ATM_ANYCLASS	5		/* compatible with everything */
+ 
+#define ATM_VBR_NRT     ATM_VBR
+#define ATM_VBR_RT      6
+#define ATM_UBR_PLUS    7
+#define ATM_GFR         8
+
+ #define ATM_MAX_PCR	-1		/* maximum available PCR */
+ 
+
+ struct atm_trafprm {
+ 	unsigned char	traffic_class;	/* traffic class (ATM_UBR, ...) */
+ 	int		max_pcr;	/* maximum PCR in cells per second */
+diff --git a/net/atm/common.c b/net/atm/common.c
+index 806fc0a..82bc78e 100644
+--- a/net/atm/common.c
+++ b/net/atm/common.c
+@@ -62,11 +62,17 @@ static void vcc_remove_socket(struct sock *sk)
+ 	write_unlock_irq(&vcc_sklist_lock);
+ }
+ 
+struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL;
+EXPORT_SYMBOL(ifx_atm_alloc_tx);
+
+ static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size)
+ {
+ 	struct sk_buff *skb;
+ 	struct sock *sk = sk_atm(vcc);
+ 
+	if (ifx_atm_alloc_tx != NULL)
+		return ifx_atm_alloc_tx(vcc, size);
+
+ 	if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) {
+ 		pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n",
+ 			 sk_wmem_alloc_get(sk), size, sk->sk_sndbuf);
+diff --git a/net/atm/proc.c b/net/atm/proc.c
+index 0d020de..9fdb539 100644
+--- a/net/atm/proc.c
+++ b/net/atm/proc.c
+@@ -154,7 +154,7 @@ static void *vcc_seq_next(struct seq_file *seq, void *v, loff_t *pos)
+ static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
+ {
+ 	static const char *const class_name[] = {
+-		"off", "UBR", "CBR", "VBR", "ABR"};
+		"off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
+ 	static const char *const aal_name[] = {
+ 		"---",	"1",	"2",	"3/4",	/*  0- 3 */
+ 		"???",	"5",	"???",	"???",	/*  4- 7 */
+-- 
+1.7.10.4
+
--- a/target/linux/lantiq/patches-3.8/0041-owrt-mtd-split.patch
+++ b/target/linux/lantiq/patches-3.8/0041-owrt-mtd-split.patch
@ -0,0 +1,221 @@
+From 2a295753a10823a47542c779a25bbb1f52c71281 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 3 Aug 2012 10:27:13 +0200
+Subject: [PATCH 19/25] owrt mtd split
+
+---
+ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |    1 +
+ arch/mips/lantiq/setup.c                           |    7 +
+ drivers/mtd/Kconfig                                |    4 +
+ drivers/mtd/mtdpart.c                              |  173 +++++++++++++++++++-
+ 4 files changed, 184 insertions(+), 1 deletions(-)
+
+--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
+@@ -31,6 +31,10 @@ config MTD_ROOTFS_SPLIT
+ 	bool "Automatically split 'rootfs' partition for squashfs"
+ 	default y
+ 
+config MTD_UIMAGE_SPLIT
+	bool "Automatically split 'linux' partition into 'kernel' and 'rootfs'"
+	default y
+
+ config MTD_REDBOOT_PARTS
+ 	tristate "RedBoot partition table parsing"
+ 	---help---
+--- a/drivers/mtd/mtdpart.c
+++ b/drivers/mtd/mtdpart.c
+@@ -844,6 +844,168 @@ static int refresh_rootfs_split(struct m
+ }
+ #endif /* CONFIG_MTD_ROOTFS_SPLIT */
+ 
+#ifdef CONFIG_MTD_UIMAGE_SPLIT
+static unsigned long find_uimage_size(struct mtd_info *mtd,
+				      unsigned long offset)
+{
+#define UBOOT_MAGIC	0x56190527
+	unsigned long magic = 0;
+	unsigned long temp;
+	size_t len;
+	int ret;
+
+	ret = mtd_read(mtd, offset, 4, &len, (void *)&magic);
+	if (ret || len != sizeof(magic))
+		return 0;
+
+	if (le32_to_cpu(magic) != UBOOT_MAGIC)
+		return 0;
+
+	ret = mtd_read(mtd, offset + 12, 4, &len, (void *)&temp);
+	if (ret || len != sizeof(temp))
+		return 0;
+
+	return temp + 0x40;
+}
+
+static unsigned long find_eva_size(struct mtd_info *mtd,
+				      unsigned long offset)
+{
+#define EVA_MAGIC	0xfeed1281
+	unsigned long magic = 0;
+	unsigned long temp;
+	size_t len;
+	int ret;
+
+	ret = mtd_read(mtd, offset, 4, &len, (void *)&magic);
+	if (ret || len != sizeof(magic))
+		return 0;
+
+	if (le32_to_cpu(magic) != EVA_MAGIC)
+		return 0;
+
+	ret = mtd_read(mtd, offset + 4, 4, &len, (void *)&temp);
+	if (ret || len != sizeof(temp))
+		return 0;
+
+	/* add eva header size */
+	temp = le32_to_cpu(temp) + 0x18;
+
+	temp &= ~0xffff;
+	temp += 0x10000;
+	return temp;
+}
+
+static int detect_squashfs_partition(struct mtd_info *mtd, unsigned long offset)
+{
+	unsigned long temp;
+	size_t len;
+	int ret;
+
+	ret = mtd_read(mtd, offset, 4, &len, (void *)&temp);
+	if (ret || len != sizeof(temp))
+		return 0;
+
+
+	return le32_to_cpu(temp) == SQUASHFS_MAGIC;
+}
+
+static int detect_eva_squashfs_partition(struct mtd_info *mtd, unsigned long offset)
+{
+	unsigned long temp;
+	size_t len;
+	int ret;
+
+	ret = mtd_read(mtd, offset, 4, &len, (void *)&temp);
+	if (ret || len != sizeof(temp))
+		return 0;
+
+	return be32_to_cpu(temp) == SQUASHFS_MAGIC;
+}
+
+static unsigned long find_brnimage_size(struct mtd_info *mtd,
+					unsigned long offset)
+{
+	unsigned long buf[4];
+	// Assume at most 2MB of kernel image
+	unsigned long end = offset + (2 << 20);
+	unsigned long ptr = offset + 0x400 - 12;
+	size_t len;
+	int ret;
+
+	while (ptr < end) {
+		long size_min = ptr - 0x400 - 12 - offset;
+		long size_max = ptr + 12 - offset;
+		ret = mtd_read(mtd, ptr, 16, &len, (void *)buf);
+		if (ret || len != 16)
+			return 0;
+
+		if (le32_to_cpu(buf[0]) < size_min ||
+		    le32_to_cpu(buf[0]) > size_max) {
+			ptr += 0x400;
+			continue;
+		}
+
+		if (le32_to_cpu(buf[3]) == SQUASHFS_MAGIC)
+			return ptr + 12 - offset;
+
+		ptr += 0x400;
+	}
+
+	return 0;
+}
+
+static int split_uimage(struct mtd_info *mtd,
+			const struct mtd_partition *part)
+{
+	static struct mtd_partition split_partitions[] = {
+		{
+			.name = "kernel",
+			.offset = 0x0,
+			.size = 0x0,
+		}, {
+			.name = "rootfs",
+			.offset = 0x0,
+			.size = 0x0,
+		},
+	};
+
+	split_partitions[0].size = find_uimage_size(mtd, part->offset);
+	if (!split_partitions[0].size) {
+		split_partitions[0].size = find_eva_size(mtd, part->offset);
+		if (!split_partitions[0].size) {
+			split_partitions[0].size = find_brnimage_size(mtd, part->offset);
+			if (!split_partitions[0].size) {
+				printk(KERN_NOTICE "no uImage or brnImage or eva found in linux partition\n");
+				return -1;
+			}
+		}
+	}
+
+	if (detect_eva_squashfs_partition(mtd,
+				       part->offset
+				       + split_partitions[0].size)) {
+		split_partitions[0].size += 0x100;
+		pr_info("found eva dummy squashfs behind kernel\n");
+	} else if (!detect_squashfs_partition(mtd,
+				       part->offset
+				       + split_partitions[0].size)) {
+		split_partitions[0].size &= ~(mtd->erasesize - 1);
+		split_partitions[0].size += mtd->erasesize;
+	} else {
+		pr_info("found squashfs behind kernel\n");
+	}
+
+	split_partitions[0].offset = part->offset;
+	split_partitions[1].offset = part->offset + split_partitions[0].size;
+	split_partitions[1].size = part->size - split_partitions[0].size;
+
+	add_mtd_partitions(mtd, split_partitions, 2);
+
+	return 0;
+}
+#endif
+
+ /*
+  * This function, given a master MTD object and a partition table, creates
+  * and registers slave MTD objects which are bound to the master according to
+@@ -860,7 +1022,7 @@ int add_mtd_partitions(struct mtd_info *
+ 	struct mtd_part *slave;
+ 	uint64_t cur_offset = 0;
+ 	int i;
+-#ifdef CONFIG_MTD_ROOTFS_SPLIT
+#if defined(CONFIG_MTD_ROOTFS_SPLIT) || defined(CONFIG_MTD_UIMAGE_SPLIT)
+ 	int ret;
+ #endif
+ 
+@@ -877,6 +1039,15 @@ int add_mtd_partitions(struct mtd_info *
+ 
+ 		add_mtd_device(&slave->mtd);
+ 
+#ifdef CONFIG_MTD_UIMAGE_SPLIT
+		if (!strcmp(parts[i].name, "linux")) {
+			ret = split_uimage(master, &parts[i]);
+
+			if (ret)
+				printk(KERN_WARNING "Can't split linux partition\n");
+		}
+#endif
+
+ 		if (!strcmp(parts[i].name, "rootfs")) {
+ #ifdef CONFIG_MTD_ROOTFS_ROOT_DEV
+ 			if (ROOT_DEV == 0) {