mirror of https://github.com/hak5/openwrt-owl.git
parent
e0a748c051
commit
b8eb34e5c3
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@ -1,15 +0,0 @@
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Replace udelay(3000) with mdelay(3), because udelay(3000) fails on ARM
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
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--- a/drivers/net/wireless/ath9k/recv.c
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+++ b/drivers/net/wireless/ath9k/recv.c
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@@ -737,7 +737,7 @@
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ath9k_hw_stoppcurecv(ah); /* disable PCU */
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ath9k_hw_setrxfilter(ah, 0); /* clear recv filter */
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stopped = ath9k_hw_stopdmarecv(ah); /* disable DMA engine */
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- udelay(3000); /* 3ms is long enough for 1 frame */
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+ mdelay(3); /* 3ms is long enough for 1 frame */
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tsf = ath9k_hw_gettsf64(ah);
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sc->sc_rxlink = NULL; /* just in case */
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return stopped;
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@ -1,15 +0,0 @@
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Add missing include statements
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
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--- a/drivers/net/wireless/ath9k/regd.c
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+++ b/drivers/net/wireless/ath9k/regd.c
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@@ -14,6 +14,8 @@
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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+#include <linux/kernel.h>
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+#include <linux/slab.h>
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#include "ath9k.h"
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#include "regd.h"
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#include "regd_common.h"
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@ -1,23 +0,0 @@
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Add missing device ID for AR9160
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
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--- a/drivers/net/wireless/ath9k/hw.c
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+++ b/drivers/net/wireless/ath9k/hw.c
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@@ -8329,6 +8329,8 @@
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case AR5416_DEVID_PCI:
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case AR5416_DEVID_PCIE:
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return "Atheros 5416";
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+ case AR9160_DEVID_PCI:
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+ return "Atheros 9160";
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case AR9280_DEVID_PCI:
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case AR9280_DEVID_PCIE:
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return "Atheros 9280";
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@@ -8350,6 +8352,7 @@
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switch (devid) {
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case AR5416_DEVID_PCI:
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case AR5416_DEVID_PCIE:
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+ case AR9160_DEVID_PCI:
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case AR9280_DEVID_PCI:
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case AR9280_DEVID_PCIE:
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ah = ath9k_hw_do_attach(devid, sc, mem, error);
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@ -1,16 +0,0 @@
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Fix a return code check for ath9k_hw_nvram_read, this function returns
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AH_TRUE when the call succeeded
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
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--- a/drivers/net/wireless/ath9k/hw.c
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+++ b/drivers/net/wireless/ath9k/hw.c
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@@ -803,7 +803,7 @@
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u_int16_t magic, magic2;
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int addr;
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- if (ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
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+ if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
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&magic)) {
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HDPRINTF(ah, HAL_DBG_EEPROM,
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"%s: Reading Magic # failed\n", __func__);
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@ -1,64 +0,0 @@
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Remove the descriptor swap, as the driver already configures the hardware for
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descriptor swapping on big endian systems
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
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--- a/drivers/net/wireless/ath9k/core.c
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+++ b/drivers/net/wireless/ath9k/core.c
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@@ -2141,22 +2141,6 @@
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memzero(dd, sizeof(*dd));
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}
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-/*
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- * Endian Swap for transmit descriptor
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- *
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- * XXX: Move cpu_to_le32() into hw.c and anywhere we set them, then
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- * remove this.
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-*/
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-void ath_desc_swap(struct ath_desc *ds)
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-{
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- ds->ds_link = cpu_to_le32(ds->ds_link);
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- ds->ds_data = cpu_to_le32(ds->ds_data);
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- ds->ds_ctl0 = cpu_to_le32(ds->ds_ctl0);
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- ds->ds_ctl1 = cpu_to_le32(ds->ds_ctl1);
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- ds->ds_hw[0] = cpu_to_le32(ds->ds_hw[0]);
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- ds->ds_hw[1] = cpu_to_le32(ds->ds_hw[1]);
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-}
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-
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/*************/
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/* Utilities */
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/*************/
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--- a/drivers/net/wireless/ath9k/beacon.c
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+++ b/drivers/net/wireless/ath9k/beacon.c
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@@ -140,11 +140,6 @@
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series[0].RateFlags = (ctsrate) ? HAL_RATESERIES_RTS_CTS : 0;
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ath9k_hw_set11n_ratescenario(ah, ds, ds, 0,
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ctsrate, ctsduration, series, 4, 0);
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-
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- /* NB: The desc swap function becomes void,
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- * if descriptor swapping is not enabled
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- */
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- ath_desc_swap(ds);
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}
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/* Move everything from the vap's mcast queue to the hardware cab queue.
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--- a/drivers/net/wireless/ath9k/core.h
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+++ b/drivers/net/wireless/ath9k/core.h
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@@ -384,7 +384,6 @@
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void ath_descdma_cleanup(struct ath_softc *sc,
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struct ath_descdma *dd,
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struct list_head *head);
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-void ath_desc_swap(struct ath_desc *ds);
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/******/
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/* RX */
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--- a/drivers/net/wireless/ath9k/xmit.c
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+++ b/drivers/net/wireless/ath9k/xmit.c
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@@ -2062,7 +2062,6 @@
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AH_TRUE, /* first segment */
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(n_sg == 1) ? AH_TRUE : AH_FALSE, /* last segment */
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ds); /* first descriptor */
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- ath_desc_swap(ds);
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bf->bf_lastfrm = bf;
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bf->bf_ht = txctl->ht;
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@ -1,16 +0,0 @@
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This patch fixes another endianness issue.
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DMA descriptors must always be accessed in native endianness.
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
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--- a/drivers/net/wireless/ath9k/xmit.c
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+++ b/drivers/net/wireless/ath9k/xmit.c
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@@ -168,7 +168,7 @@
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__func__, txq->axq_qnum,
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ito64(bf->bf_daddr), bf->bf_desc);
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} else {
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- *txq->axq_link = cpu_to_le32(bf->bf_daddr);
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+ *txq->axq_link = bf->bf_daddr;
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DPRINTF(sc, ATH_DEBUG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n",
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__func__,
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txq->axq_qnum, txq->axq_link,
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@ -1169,8 +1169,7 @@ void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u_int32_t *txqs);
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void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
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void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah,
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struct ath_desc *ds, u_int vmf);
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enum hal_bool ath9k_hw_SetTxPowerLimit(struct ath_hal *ah, u_int32_t limit,
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u_int16_t tpcInDb);
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enum hal_bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit);
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enum hal_bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
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int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum hal_tx_queue type,
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const struct hal_txq_info *qInfo);
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@ -140,11 +140,6 @@ static void ath_beacon_setup(struct ath_softc *sc,
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series[0].RateFlags = (ctsrate) ? HAL_RATESERIES_RTS_CTS : 0;
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ath9k_hw_set11n_ratescenario(ah, ds, ds, 0,
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ctsrate, ctsduration, series, 4, 0);
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/* NB: The desc swap function becomes void,
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* if descriptor swapping is not enabled
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*/
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ath_desc_swap(ds);
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}
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/* Move everything from the vap's mcast queue to the hardware cab queue.
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@ -164,7 +159,7 @@ static void empty_mcastq_into_cabq(struct ath_hal *ah,
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if (!cabq->axq_link)
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ath9k_hw_puttxbuf(ah, cabq->axq_qnum, bfmcast->bf_daddr);
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else
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*cabq->axq_link = cpu_to_le32(bfmcast->bf_daddr);
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*cabq->axq_link = bfmcast->bf_daddr;
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/* append the private vap mcast list to the cabq */
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@ -693,11 +688,7 @@ void ath9k_beacon_tasklet(unsigned long data)
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if (if_id != ATH_IF_ID_ANY) {
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bf = ath_beacon_generate(sc, if_id);
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if (bf != NULL) {
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if (bflink != &bfaddr)
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*bflink = cpu_to_le32(
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bf->bf_daddr);
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else
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*bflink = bf->bf_daddr;
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*bflink = bf->bf_daddr;
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bflink = &bf->bf_desc->ds_link;
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bc++;
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}
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@ -452,7 +452,7 @@ int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
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* if we're switching; e.g. 11a to 11b/g.
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*/
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ath_chan_change(sc, hchan);
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ath_update_txpow(sc, 0); /* update tx power state */
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ath_update_txpow(sc); /* update tx power state */
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/*
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* Re-enable interrupts.
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*/
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@ -1020,7 +1020,7 @@ int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
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* This is needed only to setup initial state
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* but it's best done after a reset.
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*/
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ath_update_txpow(sc, 0);
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ath_update_txpow(sc);
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/*
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* Setup the hardware after reset:
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@ -1111,7 +1111,7 @@ static int ath_reset_end(struct ath_softc *sc, u_int32_t flag)
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*/
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ath_chan_change(sc, &sc->sc_curchan);
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ath_update_txpow(sc, 0); /* update tx power state */
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ath_update_txpow(sc); /* update tx power state */
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if (sc->sc_beacons)
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ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
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@ -1827,29 +1827,20 @@ int ath_keyset(struct ath_softc *sc,
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* Set Transmit power in HAL
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*
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* This routine makes the actual HAL calls to set the new transmit power
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* limit. This also calls back into the protocol layer setting the max
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* transmit power limit.
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* limit.
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*/
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void ath_update_txpow(struct ath_softc *sc, u_int16_t tpcInDb)
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void ath_update_txpow(struct ath_softc *sc)
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{
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struct ath_hal *ah = sc->sc_ah;
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u_int32_t txpow, txpowlimit;
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u_int32_t txpow;
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txpowlimit = (sc->sc_config.txpowlimit_override) ?
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sc->sc_config.txpowlimit_override : sc->sc_config.txpowlimit;
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if (sc->sc_curtxpow != txpowlimit) {
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ath9k_hw_SetTxPowerLimit(ah, txpowlimit, tpcInDb);
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if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
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ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
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/* read back in case value is clamped */
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ath9k_hw_getcapability(ah, HAL_CAP_TXPOW, 1, &txpow);
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sc->sc_curtxpow = txpow;
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}
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/* Fetch max tx power level and update protocal stack */
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ath9k_hw_getcapability(ah, HAL_CAP_TXPOW, 2, &txpow);
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ath__update_txpow(sc, sc->sc_curtxpow, txpow);
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}
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/* Return the current country and domain information */
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@ -2141,22 +2132,6 @@ void ath_descdma_cleanup(struct ath_softc *sc,
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memzero(dd, sizeof(*dd));
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}
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/*
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* Endian Swap for transmit descriptor
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*
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* XXX: Move cpu_to_le32() into hw.c and anywhere we set them, then
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* remove this.
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*/
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void ath_desc_swap(struct ath_desc *ds)
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{
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ds->ds_link = cpu_to_le32(ds->ds_link);
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ds->ds_data = cpu_to_le32(ds->ds_data);
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ds->ds_ctl0 = cpu_to_le32(ds->ds_ctl0);
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ds->ds_ctl1 = cpu_to_le32(ds->ds_ctl1);
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ds->ds_hw[0] = cpu_to_le32(ds->ds_hw[0]);
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ds->ds_hw[1] = cpu_to_le32(ds->ds_hw[1]);
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}
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/*************/
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/* Utilities */
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/*************/
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@ -384,7 +384,6 @@ void ath_desc_free(struct ath_softc *sc);
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void ath_descdma_cleanup(struct ath_softc *sc,
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struct ath_descdma *dd,
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struct list_head *head);
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void ath_desc_swap(struct ath_desc *ds);
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/******/
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/* RX */
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@ -1212,7 +1211,7 @@ int ath_keyset(struct ath_softc *sc,
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int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
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int ath_get_mac80211_qnum(u_int queue, struct ath_softc *sc);
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void ath_setslottime(struct ath_softc *sc);
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void ath_update_txpow(struct ath_softc *sc, u_int16_t tpcInDb);
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void ath_update_txpow(struct ath_softc *sc);
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int ath_cabq_update(struct ath_softc *);
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void ath_get_currentCountry(struct ath_softc *sc,
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struct hal_country_entry *ctry);
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@ -1228,9 +1227,6 @@ void ath_skb_unmap_single(struct ath_softc *sc,
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int direction,
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dma_addr_t *pa);
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void ath_mcast_merge(struct ath_softc *sc, u_int32_t mfilt[2]);
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void ath__update_txpow(struct ath_softc *sc,
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u_int16_t txpowlimit,
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u_int16_t txpowlevel);
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enum hal_ht_macmode ath_cwm_macmode(struct ath_softc *sc);
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#endif /* CORE_H */
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@ -803,7 +803,7 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
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u_int16_t magic, magic2;
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int addr;
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if (ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
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if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
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&magic)) {
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HDPRINTF(ah, HAL_DBG_EEPROM,
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"%s: Reading Magic # failed\n", __func__);
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@ -852,9 +852,14 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
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else
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el = ahp->ah_eeprom.baseEepHeader.length;
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if (el < sizeof(struct ar5416_eeprom))
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el = sizeof(struct ar5416_eeprom) / sizeof(u_int16_t);
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else
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el = el / sizeof(u_int16_t);
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eepdata = (u_int16_t *) (&ahp->ah_eeprom);
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for (i = 0; i <
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min(el, sizeof(struct ar5416_eeprom)) / sizeof(u_int16_t); i++)
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for (i = 0; i < el; i++)
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sum ^= *eepdata++;
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if (need_swap) {
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@ -6389,9 +6394,7 @@ ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u_int8_t numChains)
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AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
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}
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enum hal_bool
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ath9k_hw_SetTxPowerLimit(struct ath_hal *ah, u_int32_t limit,
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u_int16_t tpcInDb)
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enum hal_bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit)
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{
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struct ath_hal_5416 *ahp = AH5416(ah);
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struct hal_channel_internal *ichan = ah->ah_curchan;
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@ -8329,6 +8332,8 @@ static const char *ath9k_hw_devname(u_int16_t devid)
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case AR5416_DEVID_PCI:
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case AR5416_DEVID_PCIE:
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return "Atheros 5416";
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case AR9160_DEVID_PCI:
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return "Atheros 9160";
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case AR9280_DEVID_PCI:
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case AR9280_DEVID_PCIE:
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return "Atheros 9280";
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@ -8350,6 +8355,7 @@ struct ath_hal *ath9k_hw_attach(u_int16_t devid, void *sc, void __iomem *mem,
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switch (devid) {
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case AR5416_DEVID_PCI:
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case AR5416_DEVID_PCIE:
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case AR9160_DEVID_PCI:
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case AR9280_DEVID_PCI:
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case AR9280_DEVID_PCIE:
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ah = ath9k_hw_do_attach(devid, sc, mem, error);
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@ -525,6 +525,7 @@ static int ath9k_config(struct ieee80211_hw *hw,
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hchan.channel = curchan->center_freq;
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hchan.channelFlags = ath_chan2flags(curchan, sc);
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sc->sc_config.txpowlimit = 2 * conf->power_level;
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/* set h/w channel */
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if (ath_set_channel(sc, &hchan) < 0)
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@ -1061,13 +1062,6 @@ void ath_setup_channel_list(struct ath_softc *sc,
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}
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}
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void ath__update_txpow(struct ath_softc *sc,
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u_int16_t txpowlimit,
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u_int16_t txpowlevel)
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{
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}
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void ath_get_beaconconfig(struct ath_softc *sc,
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int if_id,
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struct ath_beacon_config *conf)
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@ -737,7 +737,7 @@ enum hal_bool ath_stoprecv(struct ath_softc *sc)
|
|||
ath9k_hw_stoppcurecv(ah); /* disable PCU */
|
||||
ath9k_hw_setrxfilter(ah, 0); /* clear recv filter */
|
||||
stopped = ath9k_hw_stopdmarecv(ah); /* disable DMA engine */
|
||||
udelay(3000); /* 3ms is long enough for 1 frame */
|
||||
mdelay(3); /* 3ms is long enough for 1 frame */
|
||||
tsf = ath9k_hw_gettsf64(ah);
|
||||
sc->sc_rxlink = NULL; /* just in case */
|
||||
return stopped;
|
||||
|
@ -1380,7 +1380,7 @@ dma_addr_t ath_skb_map_single(struct ath_softc *sc,
|
|||
* Use skb's entire data area instead.
|
||||
*/
|
||||
*pa = pci_map_single(sc->pdev, skb->data,
|
||||
skb->end - skb->head, direction);
|
||||
skb_end_pointer(skb) - skb->head, direction);
|
||||
return *pa;
|
||||
}
|
||||
|
||||
|
@ -1390,5 +1390,6 @@ void ath_skb_unmap_single(struct ath_softc *sc,
|
|||
dma_addr_t *pa)
|
||||
{
|
||||
/* Unmap skb's entire data area */
|
||||
pci_unmap_single(sc->pdev, *pa, skb->end - skb->head, direction);
|
||||
pci_unmap_single(sc->pdev, *pa,
|
||||
skb_end_pointer(skb) - skb->head, direction);
|
||||
}
|
||||
|
|
|
@ -14,6 +14,8 @@
|
|||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/slab.h>
|
||||
#include "ath9k.h"
|
||||
#include "regd.h"
|
||||
#include "regd_common.h"
|
||||
|
|
|
@ -121,7 +121,7 @@ static void ath_tx_mcastqaddbuf(struct ath_softc *sc,
|
|||
DPRINTF(sc, ATH_DEBUG_TX_PROC,
|
||||
"%s: txq depth = %d\n", __func__, txq->axq_depth);
|
||||
if (txq->axq_link != NULL) {
|
||||
*txq->axq_link = cpu_to_le32(bf->bf_daddr);
|
||||
*txq->axq_link = bf->bf_daddr;
|
||||
DPRINTF(sc, ATH_DEBUG_XMIT,
|
||||
"%s: link[%u](%p)=%llx (%p)\n",
|
||||
__func__,
|
||||
|
@ -168,7 +168,7 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc,
|
|||
__func__, txq->axq_qnum,
|
||||
ito64(bf->bf_daddr), bf->bf_desc);
|
||||
} else {
|
||||
*txq->axq_link = cpu_to_le32(bf->bf_daddr);
|
||||
*txq->axq_link = bf->bf_daddr;
|
||||
DPRINTF(sc, ATH_DEBUG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n",
|
||||
__func__,
|
||||
txq->axq_qnum, txq->axq_link,
|
||||
|
@ -2062,7 +2062,6 @@ static int ath_tx_start_dma(struct ath_softc *sc,
|
|||
AH_TRUE, /* first segment */
|
||||
(n_sg == 1) ? AH_TRUE : AH_FALSE, /* last segment */
|
||||
ds); /* first descriptor */
|
||||
ath_desc_swap(ds);
|
||||
|
||||
bf->bf_lastfrm = bf;
|
||||
bf->bf_ht = txctl->ht;
|
||||
|
|
Loading…
Reference in New Issue