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lantiq: use the same functionality for all ethernet phys led 

The VGV7510KW22 has the leds for LAN1-3 connected to pin1 of the phys
and the led for LAN4 connect to pin0 of the phy. This results with the
current configuration in a fast flashing LAN4 led as soon as a network
cable is connected. Something similar was reported on the forum[1] for
the VGV7519 as well.

Since it isn't predicable to which pin a (single) phy led is connected,
use the (default) pin1 functionality

    Constant On: 10/100/1000MBit
    Blink Fast: None
    Blink Slow: None
    Pulse: TX/RX

for all ethernet phy leds.

After checking pictures of all vr9 boards, it looks like only the VG3503J
has more than one led connected per phy. Using the phy led device tree
bindings to assign the functionality to the "additional" leds, the
VG3503J phy leds should behave as before.

Signed-off-by: Mathias Kresin <openwrt@kresin.me>

[1] https://forum.openwrt.org/viewtopic.php?pid=321523

SVN-Revision: 49270
owl
blogic 2016-04-29 11:35:05 +00:00 committed by Jo-Philipp Wich
parent 6249269322
commit b529387d8c
2 changed files with 14 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
target/linux/lantiq/dts/VG3503J.dtsi
View File

@ -153,10 +153,18 @@
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
lantiq,led0h = <0x42>;
lantiq,led0l = <0x10>;
lantiq,led2h = <0x20>;
lantiq,led2l = <0x00>;
};
phy13: ethernet-phy@13 {
reg = <0x13>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
lantiq,led0h = <0x42>;
lantiq,led0l = <0x10>;
lantiq,led2h = <0x20>;
lantiq,led2l = <0x00>;
};
};
};

12
target/linux/lantiq/patches-4.4/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch
View File

@ -165,14 +165,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+
+ vr9_gphy_mmd_write(phydev, 0x1e0, 0xc5);
+ vr9_gphy_mmd_write(phydev, 0x1e1, 0x67);
+ vr9_gphy_mmd_write(phydev, 0x1e2, 0x42);
+ vr9_gphy_mmd_write(phydev, 0x1e3, 0x10);
+ vr9_gphy_mmd_write(phydev, 0x1e2, 0x70);
+ vr9_gphy_mmd_write(phydev, 0x1e3, 0x03);
+ vr9_gphy_mmd_write(phydev, 0x1e4, 0x70);
+ vr9_gphy_mmd_write(phydev, 0x1e5, 0x03);
+ vr9_gphy_mmd_write(phydev, 0x1e6, 0x20);
+ vr9_gphy_mmd_write(phydev, 0x1e7, 0x00);
+ vr9_gphy_mmd_write(phydev, 0x1e8, 0x40);
+ vr9_gphy_mmd_write(phydev, 0x1e9, 0x20);
+ vr9_gphy_mmd_write(phydev, 0x1e6, 0x70);
+ vr9_gphy_mmd_write(phydev, 0x1e7, 0x03);
+ vr9_gphy_mmd_write(phydev, 0x1e8, 0x70);
+ vr9_gphy_mmd_write(phydev, 0x1e9, 0x03);
+
+ vr9_gphy_of_reg_init(phydev);
+