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ramips: implement clock API for RT305X 

SVN-Revision: 25124
owl
Gabor Juhos 2011-01-26 20:48:35 +00:00
parent f9e74383a9
commit b0ffa70248
7 changed files with 148 additions and 41 deletions
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6
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h
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@ -1,7 +1,7 @@
/*
* Ralink RT305x SoC specific definitions
*
* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
*
* Parts of this file are based on Ralink's 2.6.21 BSP
*
@ -17,10 +17,6 @@
#include <linux/io.h>
void rt305x_detect_sys_type(void);
void rt305x_detect_sys_freq(void);
extern unsigned long rt305x_cpu_freq;
extern unsigned long rt305x_sys_freq;
#define RT305X_MEM_SIZE_MIN (2 * 1024 * 1024)
#define RT305X_MEM_SIZE_MAX (64 * 1024 * 1024)

4
target/linux/ramips/files/arch/mips/ralink/rt305x/Makefile
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@ -1,13 +1,13 @@
#
# Makefile for the Ralink RT305x SoC specific parts of the kernel
#
# Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License version 2 as published
# by the Free Software Foundation.
obj-y := irq.o setup.o devices.o rt305x.o
obj-y := irq.o setup.o devices.o rt305x.o clock.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o

93
target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c Normal file
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@ -0,0 +1,93 @@
/*
* Ralink RT305X clock API
*
* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <asm/mach-ralink/common.h>
#include <asm/mach-ralink/rt305x.h>
#include <asm/mach-ralink/rt305x_regs.h>
#include "common.h"
struct clk {
unsigned long rate;
};
static struct clk rt305x_cpu_clk;
static struct clk rt305x_sys_clk;
static struct clk rt305x_wdt_clk;
static struct clk rt305x_uart_clk;
void __init rt305x_clocks_init(void)
{
u32 t;
t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG);
t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
switch (t) {
case SYSTEM_CONFIG_CPUCLK_320:
rt305x_cpu_clk.rate = 320000000;
break;
case SYSTEM_CONFIG_CPUCLK_384:
rt305x_cpu_clk.rate = 384000000;
break;
}
rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
rt305x_uart_clk.rate = rt305x_sys_clk.rate;
rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
}
/*
* Linux clock API
*/
struct clk *clk_get(struct device *dev, const char *id)
{
if (!strcmp(id, "sys"))
return &rt305x_sys_clk;
if (!strcmp(id, "cpu"))
return &rt305x_cpu_clk;
if (!strcmp(id, "wdt"))
return &rt305x_wdt_clk;
if (!strcmp(id, "uart"))
return &rt305x_uart_clk;
return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);
int clk_enable(struct clk *clk)
{
return 0;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);
void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);

16
target/linux/ramips/files/arch/mips/ralink/rt305x/common.h Normal file
View File

@ -0,0 +1,16 @@
/*
* Ralink RT305x SoC common defines
*
* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _RT305X_COMMON_H
#define _RT305X_COMMON_H
void rt305x_clocks_init(void);
#endif /* _RT305X_COMMON_H */

10
target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c
View File

@ -10,6 +10,8 @@
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/physmap.h>
@ -150,7 +152,13 @@ static struct platform_device rt305x_esw_device = {
void __init rt305x_register_ethernet(void)
{
ramips_eth_data.sys_freq = rt305x_sys_freq;
struct clk *clk;
clk = clk_get(NULL, "sys");
if (IS_ERR(clk))
panic("unable to get SYS clock, err=%ld", PTR_ERR(clk));
ramips_eth_data.sys_freq = clk_get_rate(clk);
platform_device_register(&rt305x_esw_device);
platform_device_register(&rt305x_eth_device);

27
target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c
View File

@ -1,7 +1,7 @@
/*
* Ralink RT305x SoC specific setup
*
* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Parts of this file are based on Ralink's 2.6.21 BSP
@ -20,12 +20,6 @@
#include <asm/mach-ralink/rt305x.h>
#include <asm/mach-ralink/rt305x_regs.h>
unsigned long rt305x_cpu_freq;
EXPORT_SYMBOL_GPL(rt305x_cpu_freq);
unsigned long rt305x_sys_freq;
EXPORT_SYMBOL_GPL(rt305x_sys_freq);
void __iomem * rt305x_sysc_base;
void __iomem * rt305x_memc_base;
@ -49,25 +43,6 @@ void __init rt305x_detect_sys_type(void)
(id & CHIP_ID_REV_MASK));
}
void __init rt305x_detect_sys_freq(void)
{
u32 t;
t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG);
t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
switch (t) {
case SYSTEM_CONFIG_CPUCLK_320:
rt305x_cpu_freq = 320000000;
break;
case SYSTEM_CONFIG_CPUCLK_384:
rt305x_cpu_freq = 384000000;
break;
}
rt305x_sys_freq = rt305x_cpu_freq / 3;
}
static void rt305x_gpio_reserve(int first, int last)
{
for (; first <= last; first++)

33
target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c
View File

@ -1,7 +1,7 @@
/*
* Ralink RT305x SoC specific setup
*
* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
*
* Parts of this file are based on Ralink's 2.6.21 BSP
*
@ -13,6 +13,8 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <asm/mips_machine.h>
#include <asm/reboot.h>
@ -21,6 +23,7 @@
#include <asm/mach-ralink/common.h>
#include <asm/mach-ralink/rt305x.h>
#include <asm/mach-ralink/rt305x_regs.h>
#include "common.h"
static void rt305x_restart(char *command)
{
@ -44,27 +47,43 @@ unsigned int __cpuinit get_c0_compare_irq(void)
void __init ramips_soc_setup(void)
{
struct clk *clk;
rt305x_sysc_base = ioremap_nocache(RT305X_SYSC_BASE, PAGE_SIZE);
rt305x_memc_base = ioremap_nocache(RT305X_MEMC_BASE, PAGE_SIZE);
rt305x_detect_sys_type();
rt305x_detect_sys_freq();
rt305x_clocks_init();
clk = clk_get(NULL, "cpu");
if (IS_ERR(clk))
panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type,
rt305x_cpu_freq / 1000000,
(rt305x_cpu_freq % 1000000) * 100 / 1000000);
clk_get_rate(clk) / 1000000,
(clk_get_rate(clk) % 1000000) * 100 / 1000000);
_machine_restart = rt305x_restart;
_machine_halt = rt305x_halt;
pm_power_off = rt305x_halt;
ramips_early_serial_setup(0, RT305X_UART0_BASE, rt305x_sys_freq,
clk = clk_get(NULL, "uart");
if (IS_ERR(clk))
panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
ramips_early_serial_setup(0, RT305X_UART0_BASE, clk_get_rate(clk),
RT305X_INTC_IRQ_UART0);
ramips_early_serial_setup(1, RT305X_UART1_BASE, rt305x_sys_freq,
ramips_early_serial_setup(1, RT305X_UART1_BASE, clk_get_rate(clk),
RT305X_INTC_IRQ_UART1);
}
void __init plat_time_init(void)
{
mips_hpt_frequency = rt305x_cpu_freq / 2;
struct clk *clk;
clk = clk_get(NULL, "cpu");
if (IS_ERR(clk))
panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
mips_hpt_frequency = clk_get_rate(clk) / 2;
}