mirror of https://github.com/hak5/openwrt-owl.git
Gabor Juhos
parent
6032279e79
commit
ad66840108
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@ -18,7 +18,7 @@ ifneq ($(CONFIG_LINUX_2_6_21)$(CONFIG_LINUX_2_6_23)$(CONFIG_LINUX_2_6_24)$(CONFI
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PATCH_DIR:=./patches-old
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PATCH_DIR:=./patches-old
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else
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else
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PKG_VERSION:=2009-03-31
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PKG_VERSION:=2009-03-31
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PKG_RELEASE:=1
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PKG_RELEASE:=2
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PKG_SOURCE_URL:= \
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PKG_SOURCE_URL:= \
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http://www.orbit-lab.org/kernel/compat-wireless-2.6/2009/03 \
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http://www.orbit-lab.org/kernel/compat-wireless-2.6/2009/03 \
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http://wireless.kernel.org/download/compat-wireless-2.6
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http://wireless.kernel.org/download/compat-wireless-2.6
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@ -0,0 +1,104 @@
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From dd51972ba5d11df434faf9171fe02c0cc48d35c1 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Wed, 29 Apr 2009 08:52:16 +0200
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Subject: [PATCH] ath9k: uninline ath9k_io{read,write}32 routines
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The spin_lock handling uses lots of instructions on some archs.
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With this patch the size of the ath9k module will be significantly
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smaller.
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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---
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Example results on different platforms:
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xscale: 468344 -> 293022 (62.6%)
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mips32: 549847 -> 389421 (70.8%)
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mips32r2: 510520 -> 394020 (77.2%)
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ppc40x: 365153 -> 296928 (81.3%)
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drivers/net/wireless/ath9k/ath9k.h | 33 +------------------------------
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drivers/net/wireless/ath9k/hw.c | 32 +++++++++++++++++++++++++++++++
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2 files changed, 34 insertions(+), 31 deletions(-)
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--- a/drivers/net/wireless/ath9k/ath9k.h
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+++ b/drivers/net/wireless/ath9k/ath9k.h
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@@ -721,36 +721,7 @@ void ath9k_wiphy_pause_all_forced(struct
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bool ath9k_wiphy_scanning(struct ath_softc *sc);
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void ath9k_wiphy_work(struct work_struct *work);
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-/*
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- * Read and write, they both share the same lock. We do this to serialize
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- * reads and writes on Atheros 802.11n PCI devices only. This is required
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- * as the FIFO on these devices can only accept sanely 2 requests. After
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- * that the device goes bananas. Serializing the reads/writes prevents this
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- * from happening.
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- */
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-
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-static inline void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
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-{
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- if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
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- unsigned long flags;
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- spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
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- iowrite32(val, ah->ah_sc->mem + reg_offset);
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- spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
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- } else
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- iowrite32(val, ah->ah_sc->mem + reg_offset);
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-}
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-
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-static inline unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
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-{
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- u32 val;
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- if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
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- unsigned long flags;
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- spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
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- val = ioread32(ah->ah_sc->mem + reg_offset);
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- spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
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- } else
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- val = ioread32(ah->ah_sc->mem + reg_offset);
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- return val;
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-}
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+void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val);
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+unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset);
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#endif /* ATH9K_H */
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--- a/drivers/net/wireless/ath9k/hw.c
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+++ b/drivers/net/wireless/ath9k/hw.c
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@@ -84,6 +84,38 @@ static u32 ath9k_hw_mac_to_clks(struct a
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return ath9k_hw_mac_clks(ah, usecs);
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}
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+/*
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+ * Read and write, they both share the same lock. We do this to serialize
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+ * reads and writes on Atheros 802.11n PCI devices only. This is required
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+ * as the FIFO on these devices can only accept sanely 2 requests. After
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+ * that the device goes bananas. Serializing the reads/writes prevents this
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+ * from happening.
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+ */
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+
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+void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
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+{
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+ if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
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+ unsigned long flags;
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+ spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
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+ iowrite32(val, ah->ah_sc->mem + reg_offset);
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+ spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
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+ } else
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+ iowrite32(val, ah->ah_sc->mem + reg_offset);
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+}
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+
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+unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
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+{
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+ u32 val;
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+ if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
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+ unsigned long flags;
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+ spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
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+ val = ioread32(ah->ah_sc->mem + reg_offset);
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+ spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
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+ } else
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+ val = ioread32(ah->ah_sc->mem + reg_offset);
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+ return val;
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+}
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+
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bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
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{
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int i;
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