mirror of https://github.com/hak5/openwrt-owl.git
atheros: convert AR5312 GPIO code to platform driver
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> SVN-Revision: 42511owl
John Crispin
parent
0e86c116cb
commit
a8799105d7
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@ -44,6 +44,7 @@ CONFIG_GENERIC_NET_UTILS=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIO_AR5312=y
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CONFIG_GPIO_DEVRES=y
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CONFIG_GPIO_SYSFS=y
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# CONFIG_HAMRADIO is not set
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@ -1292,7 +1292,7 @@
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+#endif /* __ASM_MACH_AR231X_AR2315_REGS_H */
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
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@@ -0,0 +1,247 @@
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@@ -0,0 +1,235 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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@ -1525,24 +1525,12 @@
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+#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
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+#define MEM_CFG1_AC1_S 12
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+
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+/* GPIO Address Map */
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+#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
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+#define AR5312_GPIO_DO (AR5312_GPIO + 0x00) /* output register */
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+#define AR5312_GPIO_DI (AR5312_GPIO + 0x04) /* intput register */
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+#define AR5312_GPIO_CR (AR5312_GPIO + 0x08) /* control register */
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+
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+/* GPIO Control Register bit field definitions */
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+#define AR5312_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
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+#define AR5312_GPIO_CR_O(x) (0 << (x)) /* mask for output */
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+#define AR5312_GPIO_CR_I(x) (1 << (x)) /* mask for input */
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+#define AR5312_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt*/
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+#define AR5312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
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+#define AR5312_NUM_GPIO 8
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+
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+#endif /* __ASM_MACH_AR231X_AR5312_REGS_H */
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--- /dev/null
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+++ b/arch/mips/ar231x/ar5312.c
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@@ -0,0 +1,536 @@
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@@ -0,0 +1,476 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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@ -1687,51 +1675,6 @@
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+ irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
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+}
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+
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+/*
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+ * gpiolib implementations
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+ */
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+static int
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+ar5312_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
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+{
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+ return (ar231x_read_reg(AR5312_GPIO_DI) >> gpio) & 1;
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+}
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+
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+static void
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+ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
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+{
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+ u32 reg = ar231x_read_reg(AR5312_GPIO_DO);
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+
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+ reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
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+ ar231x_write_reg(AR5312_GPIO_DO, reg);
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+}
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+
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+static int
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+ar5312_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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+{
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+ ar231x_mask_reg(AR5312_GPIO_CR, 0, 1 << gpio);
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+ return 0;
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+}
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+
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+static int
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+ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
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+{
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+ ar231x_mask_reg(AR5312_GPIO_CR, 1 << gpio, 0);
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+ ar5312_gpio_set_value(chip, gpio, value);
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+ return 0;
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+}
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+
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+static struct gpio_chip ar5312_gpio_chip = {
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+ .label = "ar5312-gpio",
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+ .direction_input = ar5312_gpio_direction_input,
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+ .direction_output = ar5312_gpio_direction_output,
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+ .set = ar5312_gpio_set_value,
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+ .get = ar5312_gpio_get_value,
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+ .base = 0,
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+ .ngpio = AR5312_NUM_GPIO, /* 8 */
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+};
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+
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+/* end of gpiolib */
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+
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+static void ar5312_device_reset_set(u32 mask)
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+{
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+ u32 val;
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@ -2024,20 +1967,6 @@
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+ mips_hpt_frequency = ar5312_cpu_frequency() / 2;
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+}
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+
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+static int __init
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+ar5312_gpio_init(void)
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+{
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+ int ret = gpiochip_add(&ar5312_gpio_chip);
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+
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+ if (ret) {
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+ pr_err("%s: failed to add gpiochip\n", ar5312_gpio_chip.label);
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+ return ret;
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+ }
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+ pr_info("%s: registered %d GPIOs\n", ar5312_gpio_chip.label,
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+ ar5312_gpio_chip.ngpio);
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+ return ret;
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+}
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+
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+void __init
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+ar5312_prom_init(void)
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+{
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@ -2060,7 +1989,6 @@
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+ devid >>= AR5312_REV_WMAC_MIN_S;
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+ devid &= AR5312_REV_CHIP;
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+ ar231x_board.devid = (u16)devid;
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+ ar5312_gpio_init();
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+}
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+
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+void __init
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@ -0,0 +1,194 @@
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--- a/arch/mips/ar231x/Kconfig
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+++ b/arch/mips/ar231x/Kconfig
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@@ -1,6 +1,7 @@
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config SOC_AR5312
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bool "Atheros 5312/2312+ support"
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depends on ATHEROS_AR231X
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+ select GPIO_AR5312
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default y
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config SOC_AR2315
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--- a/arch/mips/ar231x/ar5312.c
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+++ b/arch/mips/ar231x/ar5312.c
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@@ -192,6 +192,22 @@ static struct platform_device ar5312_phy
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.num_resources = 1,
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};
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+static struct resource ar5312_gpio_res[] = {
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+ {
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+ .name = "ar5312-gpio",
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+ .flags = IORESOURCE_MEM,
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+ .start = AR5312_GPIO,
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+ .end = AR5312_GPIO + 0x0c - 1,
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+ },
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+};
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+
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+static struct platform_device ar5312_gpio = {
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+ .name = "ar5312-gpio",
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+ .id = -1,
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+ .resource = ar5312_gpio_res,
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+ .num_resources = ARRAY_SIZE(ar5312_gpio_res),
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+};
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+
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#ifdef CONFIG_LEDS_GPIO
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static struct gpio_led ar5312_leds[] = {
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{ .name = "wlan", .gpio = 0, .active_low = 1, },
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@@ -282,6 +298,8 @@ int __init ar5312_init_devices(void)
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platform_device_register(&ar5312_physmap_flash);
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+ platform_device_register(&ar5312_gpio);
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+
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#ifdef CONFIG_LEDS_GPIO
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ar5312_leds[0].gpio = config->sys_led_gpio;
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platform_device_register(&ar5312_gpio_leds);
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--- a/drivers/gpio/Kconfig
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+++ b/drivers/gpio/Kconfig
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@@ -108,6 +108,13 @@ config GPIO_MAX730X
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comment "Memory mapped GPIO drivers:"
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+config GPIO_AR5312
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+ bool "AR5312 SoC GPIO support"
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+ default y if SOC_AR5312
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+ depends on SOC_AR5312
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+ help
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+ Say yes here to enable GPIO support for Atheros AR5312/AR2312+ SoCs.
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+
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config GPIO_CLPS711X
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tristate "CLPS711X GPIO support"
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depends on ARCH_CLPS711X || COMPILE_TEST
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--- a/drivers/gpio/Makefile
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+++ b/drivers/gpio/Makefile
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@@ -15,6 +15,7 @@ obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o
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obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o
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obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o
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obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
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+obj-$(CONFIG_GPIO_AR5312) += gpio-ar5312.o
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obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
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obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
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obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o
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--- /dev/null
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+++ b/drivers/gpio/gpio-ar5312.c
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@@ -0,0 +1,121 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
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+ * Copyright (C) 2006 FON Technology, SL.
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+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
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+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
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+ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/platform_device.h>
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+#include <linux/gpio.h>
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+
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+#define DRIVER_NAME "ar5312-gpio"
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+
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+#define AR5312_GPIO_DO 0x00 /* output register */
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+#define AR5312_GPIO_DI 0x04 /* intput register */
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+#define AR5312_GPIO_CR 0x08 /* control register */
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+
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+#define AR5312_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
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+#define AR5312_GPIO_CR_O(x) (0 << (x)) /* mask for output */
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+#define AR5312_GPIO_CR_I(x) (1 << (x)) /* mask for input */
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+#define AR5312_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */
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+#define AR5312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
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+
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+#define AR5312_GPIO_NUM 8
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+
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+static void __iomem *ar5312_mem;
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+
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+static inline u32 ar5312_gpio_reg_read(unsigned reg)
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+{
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+ return __raw_readl(ar5312_mem + reg);
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+}
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+
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+static inline void ar5312_gpio_reg_write(unsigned reg, u32 val)
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+{
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+ __raw_writel(val, ar5312_mem + reg);
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+}
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+
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+static inline void ar5312_gpio_reg_mask(unsigned reg, u32 mask, u32 val)
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+{
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+ ar5312_gpio_reg_write(reg, (ar5312_gpio_reg_read(reg) & ~mask) | val);
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+}
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+
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+static int ar5312_gpio_get_val(struct gpio_chip *chip, unsigned gpio)
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+{
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+ return (ar5312_gpio_reg_read(AR5312_GPIO_DI) >> gpio) & 1;
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+}
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+
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+static void ar5312_gpio_set_val(struct gpio_chip *chip, unsigned gpio, int val)
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+{
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+ u32 reg = ar5312_gpio_reg_read(AR5312_GPIO_DO);
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+
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+ reg = val ? reg | (1 << gpio) : reg & ~(1 << gpio);
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+ ar5312_gpio_reg_write(AR5312_GPIO_DO, reg);
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+}
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+
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+static int ar5312_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
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+{
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+ ar5312_gpio_reg_mask(AR5312_GPIO_CR, 0, 1 << gpio);
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+ return 0;
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+}
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+
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+static int ar5312_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int val)
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+{
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+ ar5312_gpio_reg_mask(AR5312_GPIO_CR, 1 << gpio, 0);
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+ ar5312_gpio_set_val(chip, gpio, val);
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+ return 0;
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+}
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+
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+static struct gpio_chip ar5312_gpio_chip = {
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+ .label = DRIVER_NAME,
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+ .direction_input = ar5312_gpio_dir_in,
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+ .direction_output = ar5312_gpio_dir_out,
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+ .set = ar5312_gpio_set_val,
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+ .get = ar5312_gpio_get_val,
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+ .base = 0,
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+ .ngpio = AR5312_GPIO_NUM,
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+};
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+
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+static int ar5312_gpio_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct resource *res;
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+ int ret;
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+
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+ if (ar5312_mem)
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+ return -EBUSY;
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ ar5312_mem = devm_ioremap_resource(dev, res);
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+ if (IS_ERR(ar5312_mem))
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+ return PTR_ERR(ar5312_mem);
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+
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+ ar5312_gpio_chip.dev = dev;
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+ ret = gpiochip_add(&ar5312_gpio_chip);
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+ if (ret) {
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+ dev_err(dev, "failed to add gpiochip\n");
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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+static struct platform_driver ar5312_gpio_driver = {
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+ .probe = ar5312_gpio_probe,
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+ .driver = {
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+ .name = DRIVER_NAME,
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+ .owner = THIS_MODULE,
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+ }
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+};
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+
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+static int __init ar5312_gpio_init(void)
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+{
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+ return platform_driver_register(&ar5312_gpio_driver);
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+}
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+subsys_initcall(ar5312_gpio_init);
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@ -358,7 +358,7 @@
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+}
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--- a/arch/mips/ar231x/Kconfig
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+++ b/arch/mips/ar231x/Kconfig
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@@ -7,3 +7,10 @@ config SOC_AR2315
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@@ -8,3 +8,10 @@ config SOC_AR2315
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bool "Atheros 2315+ support"
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depends on ATHEROS_AR231X
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default y
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