mirror of https://github.com/hak5/openwrt-owl.git
ipq806x: clean up dts patching in 4.9
Do not patch upstream files, overwrite them entirely. The upstream files are buggy for a number of devices and this significantly simplifies the patch structure Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: John Crispin <john@phrozen.org>owl
Felix Fietkau
parent
ddf577b0b2
commit
a531d37fab
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@ -0,0 +1,241 @@
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#include "qcom-ipq8064-v1.0.dtsi"
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/ {
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model = "Qualcomm IPQ8064/AP148";
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compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
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memory@0 {
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reg = <0x42000000 0x1e000000>;
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device_type = "memory";
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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rsvd@41200000 {
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reg = <0x41200000 0x300000>;
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no-map;
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};
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};
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aliases {
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serial0 = &gsbi4_serial;
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mdio-gpio0 = &mdio0;
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};
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chosen {
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linux,stdout-path = "serial0:115200n8";
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};
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soc {
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pinmux@800000 {
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i2c4_pins: i2c4_pinmux {
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pins = "gpio12", "gpio13";
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function = "gsbi4";
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bias-disable;
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};
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spi_pins: spi_pins {
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mux {
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pins = "gpio18", "gpio19", "gpio21";
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function = "gsbi5";
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drive-strength = <10>;
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bias-none;
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};
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};
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nand_pins: nand_pins {
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mux {
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pins = "gpio34", "gpio35", "gpio36",
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"gpio37", "gpio38", "gpio39",
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"gpio40", "gpio41", "gpio42",
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"gpio43", "gpio44", "gpio45",
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"gpio46", "gpio47";
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function = "nand";
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drive-strength = <10>;
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bias-disable;
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};
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pullups {
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pins = "gpio39";
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bias-pull-up;
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};
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hold {
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pins = "gpio40", "gpio41", "gpio42",
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"gpio43", "gpio44", "gpio45",
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"gpio46", "gpio47";
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bias-bus-hold;
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};
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};
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mdio0_pins: mdio0_pins {
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mux {
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pins = "gpio0", "gpio1";
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function = "gpio";
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drive-strength = <8>;
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bias-disable;
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};
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};
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rgmii2_pins: rgmii2_pins {
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mux {
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pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
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"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
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function = "rgmii2";
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drive-strength = <8>;
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bias-disable;
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};
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};
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};
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gsbi@16300000 {
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qcom,mode = <GSBI_PROT_I2C_UART>;
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status = "ok";
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serial@16340000 {
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status = "ok";
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};
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/*
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* The i2c device on gsbi4 should not be enabled.
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* On ipq806x designs gsbi4 i2c is meant for exclusive
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* RPM usage. Turning this on in kernel manifests as
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* i2c failure for the RPM.
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*/
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};
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gsbi5: gsbi@1a200000 {
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qcom,mode = <GSBI_PROT_SPI>;
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status = "ok";
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spi4: spi@1a280000 {
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status = "ok";
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spi-max-frequency = <50000000>;
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pinctrl-0 = <&spi_pins>;
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pinctrl-names = "default";
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cs-gpios = <&qcom_pinmux 20 0>;
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flash: m25p80@0 {
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compatible = "s25fl256s1";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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reg = <0>;
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linux,part-probe = "qcom-smem";
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};
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};
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};
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sata-phy@1b400000 {
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status = "ok";
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};
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sata@29000000 {
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status = "ok";
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};
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phy@100f8800 { /* USB3 port 1 HS phy */
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status = "ok";
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};
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phy@100f8830 { /* USB3 port 1 SS phy */
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status = "ok";
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};
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phy@110f8800 { /* USB3 port 0 HS phy */
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status = "ok";
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};
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phy@110f8830 { /* USB3 port 0 SS phy */
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status = "ok";
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};
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usb30@0 {
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status = "ok";
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};
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usb30@1 {
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status = "ok";
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};
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pcie0: pci@1b500000 {
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status = "ok";
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phy-tx0-term-offset = <7>;
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};
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pcie1: pci@1b700000 {
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status = "ok";
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phy-tx0-term-offset = <7>;
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};
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nand@1ac00000 {
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status = "ok";
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pinctrl-0 = <&nand_pins>;
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pinctrl-names = "default";
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nand-ecc-strength = <4>;
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nand-bus-width = <8>;
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linux,part-probe = "qcom-smem";
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};
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mdio0: mdio {
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compatible = "virtual,mdio-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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gpios = <&qcom_pinmux 1 0 &qcom_pinmux 0 0>;
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pinctrl-0 = <&mdio0_pins>;
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pinctrl-names = "default";
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phy0: ethernet-phy@0 {
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device_type = "ethernet-phy";
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reg = <0>;
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qca,ar8327-initvals = <
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0x00004 0x7600000 /* PAD0_MODE */
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0x00008 0x1000000 /* PAD5_MODE */
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0x0000c 0x80 /* PAD6_MODE */
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0x000e4 0x6a545 /* MAC_POWER_SEL */
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0x000e0 0xc74164de /* SGMII_CTRL */
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0x0007c 0x4e /* PORT0_STATUS */
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0x00094 0x4e /* PORT6_STATUS */
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>;
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};
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phy4: ethernet-phy@4 {
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device_type = "ethernet-phy";
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reg = <4>;
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};
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};
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gmac1: ethernet@37200000 {
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status = "ok";
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phy-mode = "rgmii";
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qcom,id = <1>;
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pinctrl-0 = <&rgmii2_pins>;
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pinctrl-names = "default";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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gmac2: ethernet@37400000 {
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status = "ok";
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phy-mode = "sgmii";
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qcom,id = <2>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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&adm_dma {
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status = "ok";
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};
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File diff suppressed because it is too large
Load Diff
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@ -1,52 +0,0 @@
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From eb694e964310ba402d6ff99f08e0ef78345e7397 Mon Sep 17 00:00:00 2001
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From: Thomas Pedersen <twp@codeaurora.org>
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Date: Mon, 16 May 2016 17:58:52 -0700
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Subject: [PATCH 03/37] arm: qcom: dts: ipq8064: Add ADM device node
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Original patch by Andy Gross.
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Signed-off-by: Andy Gross <agross@codeaurora.org>
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Signed-off-by: Thomas Pedersen <twp@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 21 +++++++++++++++++++++
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1 file changed, 21 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -1,9 +1,11 @@
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/dts-v1/;
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#include "skeleton.dtsi"
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+#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
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#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Qualcomm IPQ8064";
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@@ -342,5 +344,24 @@
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#reset-cells = <1>;
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};
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+ adm_dma: dma@18300000 {
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+ compatible = "qcom,adm";
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+ reg = <0x18300000 0x100000>;
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+ interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
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+ #dma-cells = <1>;
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+
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+ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
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+ clock-names = "core", "iface";
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+
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+ resets = <&gcc ADM0_RESET>,
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+ <&gcc ADM0_PBUS_RESET>,
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+ <&gcc ADM0_C0_RESET>,
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+ <&gcc ADM0_C1_RESET>,
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+ <&gcc ADM0_C2_RESET>;
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+ reset-names = "clk", "pbus", "c0", "c1", "c2";
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+ qcom,ee = <0>;
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+
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+ status = "disabled";
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+ };
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};
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};
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@ -1,38 +0,0 @@
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From c6d45af259eb4fb2a598c0396c6dd580b1658558 Mon Sep 17 00:00:00 2001
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From: Thomas Pedersen <twp@codeaurora.org>
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Date: Mon, 16 May 2016 17:58:53 -0700
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Subject: [PATCH 04/37] arm: qcom: dts: Add NAND controller node for ipq806x
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Original patch by Archit Taneja.
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Signed-off-by: Archit Taneja <architt@codeaurora.org>
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Signed-off-by: Thomas Pedersen <twp@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 17 +++++++++++++++++
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1 file changed, 17 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -363,5 +363,22 @@
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status = "disabled";
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};
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+
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+ nand@1ac00000 {
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+ compatible = "qcom,ipq806x-nand";
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+ reg = <0x1ac00000 0x800>;
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+
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+ clocks = <&gcc EBI2_CLK>,
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+ <&gcc EBI2_AON_CLK>;
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+ clock-names = "core", "aon";
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+
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+ dmas = <&adm_dma 3>;
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+ dma-names = "rxtx";
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+ qcom,cmd-crci = <15>;
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+ qcom,data-crci = <3>;
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+
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+ status = "disabled";
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+ };
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+
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};
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};
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@ -1,74 +0,0 @@
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From f8d0939eca47f56449ec583810a6ff41a1caaa91 Mon Sep 17 00:00:00 2001
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From: Thomas Pedersen <twp@codeaurora.org>
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Date: Mon, 16 May 2016 17:58:54 -0700
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Subject: [PATCH 05/37] arm: qcom: dts: Enable NAND node on IPQ8064 AP148
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platform
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Original patch by Archit Taneja.
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Enable the NAND controller node on the AP148 platform. Provide pinmux
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information.
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Signed-off-by: Archit Taneja <architt@codeaurora.org>
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Signed-off-by: Thomas Pedersen <twp@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 42 ++++++++++++++++++++++++++++++
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1 file changed, 42 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -38,6 +38,28 @@
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bias-none;
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};
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};
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+ nand_pins: nand_pins {
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+ mux {
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+ pins = "gpio34", "gpio35", "gpio36",
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+ "gpio37", "gpio38", "gpio39",
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+ "gpio40", "gpio41", "gpio42",
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+ "gpio43", "gpio44", "gpio45",
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+ "gpio46", "gpio47";
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+ function = "nand";
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+ drive-strength = <10>;
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+ bias-disable;
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+ };
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+ pullups {
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+ pins = "gpio39";
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+ bias-pull-up;
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+ };
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+ hold {
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+ pins = "gpio40", "gpio41", "gpio42",
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+ "gpio43", "gpio44", "gpio45",
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+ "gpio46", "gpio47";
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+ bias-bus-hold;
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+ };
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+ };
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};
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gsbi@16300000 {
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@@ -98,5 +120,25 @@
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ports-implemented = <0x1>;
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status = "ok";
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};
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+
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+ nand@1ac00000 {
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+ status = "ok";
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+
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+ pinctrl-0 = <&nand_pins>;
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+ pinctrl-names = "default";
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+
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+ nandcs@0 {
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+ compatible = "qcom,nandcs";
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+ reg = <0>;
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+
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+ nand-ecc-strength = <4>;
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+ nand-ecc-step-size = <512>;
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+ nand-bus-width = <8>;
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+ };
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+ };
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};
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};
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+
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+&adm_dma {
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+ status = "ok";
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+};
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@ -0,0 +1,27 @@
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From 8f68331e14dff9a101f2d0e1d6bec84a031f27ee Mon Sep 17 00:00:00 2001
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From: John Crispin <john@phrozen.org>
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Date: Thu, 9 Mar 2017 11:03:18 +0100
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Subject: [PATCH 69/69] arm: boot: add dts files
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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arch/arm/boot/dts/Makefile | 8 ++++++++
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1 file changed, 8 insertions(+)
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -619,6 +619,14 @@ dtb-$(CONFIG_ARCH_QCOM) += \
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qcom-ipq4019-ap.dk01.1-c1.dtb \
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qcom-ipq4019-ap.dk04.1-c1.dtb \
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qcom-ipq8064-ap148.dtb \
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+ qcom-ipq8064-c2600.dtb \
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+ qcom-ipq8064-d7800.dtb \
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+ qcom-ipq8064-db149.dtb \
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+ qcom-ipq8064-ea8500.dtb \
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+ qcom-ipq8064-r7500.dtb \
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+ qcom-ipq8064-r7500v2.dtb \
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+ qcom-ipq8065-nbg6817.dtb \
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+ qcom-ipq8065-r7800.dtb \
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qcom-msm8660-surf.dtb \
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qcom-msm8960-cdp.dtb \
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qcom-msm8974-lge-nexus5-hammerhead.dtb \
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@ -1,995 +0,0 @@
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -619,6 +619,14 @@ dtb-$(CONFIG_ARCH_QCOM) += \
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qcom-ipq4019-ap.dk01.1-c1.dtb \
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qcom-ipq4019-ap.dk04.1-c1.dtb \
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qcom-ipq8064-ap148.dtb \
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+ qcom-ipq8064-c2600.dtb \
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+ qcom-ipq8064-d7800.dtb \
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+ qcom-ipq8064-db149.dtb \
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+ qcom-ipq8064-ea8500.dtb \
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+ qcom-ipq8064-r7500.dtb \
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+ qcom-ipq8064-r7500v2.dtb \
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+ qcom-ipq8065-nbg6817.dtb \
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+ qcom-ipq8065-r7800.dtb \
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qcom-msm8660-surf.dtb \
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qcom-msm8960-cdp.dtb \
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qcom-msm8974-lge-nexus5-hammerhead.dtb \
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -60,6 +60,25 @@
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bias-bus-hold;
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};
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};
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+
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+ mdio0_pins: mdio0_pins {
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+ mux {
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+ pins = "gpio0", "gpio1";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
|
||||
+ };
|
||||
+
|
||||
+ rgmii2_pins: rgmii2_pins {
|
||||
+ mux {
|
||||
+ pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
+ "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
+ function = "rgmii2";
|
||||
+ drive-strength = <8>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
gsbi@16300000 {
|
||||
@@ -69,14 +88,12 @@
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
- i2c4: i2c@16380000 {
|
||||
- status = "ok";
|
||||
-
|
||||
- clock-frequency = <200000>;
|
||||
-
|
||||
- pinctrl-0 = <&i2c4_pins>;
|
||||
- pinctrl-names = "default";
|
||||
- };
|
||||
+ /*
|
||||
+ * The i2c device on gsbi4 should not be enabled.
|
||||
+ * On ipq806x designs gsbi4 i2c is meant for exclusive
|
||||
+ * RPM usage. Turning this on in kernel manifests as
|
||||
+ * i2c failure for the RPM.
|
||||
+ */
|
||||
};
|
||||
|
||||
gsbi5: gsbi@1a200000 {
|
||||
@@ -99,15 +116,7 @@
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
|
||||
- partition@0 {
|
||||
- label = "rootfs";
|
||||
- reg = <0x0 0x1000000>;
|
||||
- };
|
||||
-
|
||||
- partition@1 {
|
||||
- label = "scratch";
|
||||
- reg = <0x1000000 0x1000000>;
|
||||
- };
|
||||
+ linux,part-probe = "qcom-smem";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -121,19 +130,102 @@
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
+ phy@100f8800 { /* USB3 port 1 HS phy */
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ phy@100f8830 { /* USB3 port 1 SS phy */
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ phy@110f8800 { /* USB3 port 0 HS phy */
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ phy@110f8830 { /* USB3 port 0 SS phy */
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb30@0 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb30@1 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ pcie0: pci@1b500000 {
|
||||
+ status = "ok";
|
||||
+ phy-tx0-term-offset = <7>;
|
||||
+ };
|
||||
+
|
||||
+ pcie1: pci@1b700000 {
|
||||
+ status = "ok";
|
||||
+ phy-tx0-term-offset = <7>;
|
||||
+ };
|
||||
+
|
||||
nand@1ac00000 {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
- nandcs@0 {
|
||||
- compatible = "qcom,nandcs";
|
||||
+ nand-ecc-strength = <4>;
|
||||
+ nand-bus-width = <8>;
|
||||
+
|
||||
+ linux,part-probe = "qcom-smem";
|
||||
+ };
|
||||
+
|
||||
+ mdio0: mdio {
|
||||
+ compatible = "virtual,mdio-gpio";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ gpios = <&qcom_pinmux 1 0 &qcom_pinmux 0 0>;
|
||||
+ pinctrl-0 = <&mdio0_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ phy0: ethernet-phy@0 {
|
||||
+ device_type = "ethernet-phy";
|
||||
reg = <0>;
|
||||
+ qca,ar8327-initvals = <
|
||||
+ 0x00004 0x7600000 /* PAD0_MODE */
|
||||
+ 0x00008 0x1000000 /* PAD5_MODE */
|
||||
+ 0x0000c 0x80 /* PAD6_MODE */
|
||||
+ 0x000e4 0x6a545 /* MAC_POWER_SEL */
|
||||
+ 0x000e0 0xc74164de /* SGMII_CTRL */
|
||||
+ 0x0007c 0x4e /* PORT0_STATUS */
|
||||
+ 0x00094 0x4e /* PORT6_STATUS */
|
||||
+ >;
|
||||
+ };
|
||||
+
|
||||
+ phy4: ethernet-phy@4 {
|
||||
+ device_type = "ethernet-phy";
|
||||
+ reg = <4>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gmac1: ethernet@37200000 {
|
||||
+ status = "ok";
|
||||
+ phy-mode = "rgmii";
|
||||
+ qcom,id = <1>;
|
||||
+
|
||||
+ pinctrl-0 = <&rgmii2_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ fixed-link {
|
||||
+ speed = <1000>;
|
||||
+ full-duplex;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gmac2: ethernet@37400000 {
|
||||
+ status = "ok";
|
||||
+ phy-mode = "sgmii";
|
||||
+ qcom,id = <2>;
|
||||
|
||||
- nand-ecc-strength = <4>;
|
||||
- nand-ecc-step-size = <512>;
|
||||
- nand-bus-width = <8>;
|
||||
+ fixed-link {
|
||||
+ speed = <1000>;
|
||||
+ full-duplex;
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
@@ -1,11 +1,13 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
-#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
|
||||
+#include <dt-bindings/mfd/qcom-rpm.h>
|
||||
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
|
||||
#include <dt-bindings/soc/qcom,gsbi.h>
|
||||
+#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm IPQ8064";
|
||||
@@ -16,7 +18,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
- cpu@0 {
|
||||
+ cpu0: cpu@0 {
|
||||
compatible = "qcom,krait";
|
||||
enable-method = "qcom,kpss-acc-v1";
|
||||
device_type = "cpu";
|
||||
@@ -24,9 +26,18 @@
|
||||
next-level-cache = <&L2>;
|
||||
qcom,acc = <&acc0>;
|
||||
qcom,saw = <&saw0>;
|
||||
+ clocks = <&kraitcc 0>, <&kraitcc 4>;
|
||||
+ clock-names = "cpu", "l2";
|
||||
+ clock-latency = <100000>;
|
||||
+ cpu-supply = <&smb208_s2a>;
|
||||
+ voltage-tolerance = <5>;
|
||||
+ cooling-min-state = <0>;
|
||||
+ cooling-max-state = <10>;
|
||||
+ #cooling-cells = <2>;
|
||||
+ cpu-idle-states = <&CPU_SPC>;
|
||||
};
|
||||
|
||||
- cpu@1 {
|
||||
+ cpu1: cpu@1 {
|
||||
compatible = "qcom,krait";
|
||||
enable-method = "qcom,kpss-acc-v1";
|
||||
device_type = "cpu";
|
||||
@@ -34,11 +45,120 @@
|
||||
next-level-cache = <&L2>;
|
||||
qcom,acc = <&acc1>;
|
||||
qcom,saw = <&saw1>;
|
||||
+ clocks = <&kraitcc 1>, <&kraitcc 4>;
|
||||
+ clock-names = "cpu", "l2";
|
||||
+ clock-latency = <100000>;
|
||||
+ cpu-supply = <&smb208_s2b>;
|
||||
+ cooling-min-state = <0>;
|
||||
+ cooling-max-state = <10>;
|
||||
+ #cooling-cells = <2>;
|
||||
+ cpu-idle-states = <&CPU_SPC>;
|
||||
};
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
+ qcom,saw = <&saw_l2>;
|
||||
+ };
|
||||
+
|
||||
+ qcom,l2 {
|
||||
+ qcom,l2-rates = <384000000 1000000000 1200000000>;
|
||||
+ };
|
||||
+
|
||||
+ idle-states {
|
||||
+ CPU_SPC: spc {
|
||||
+ compatible = "qcom,idle-state-spc",
|
||||
+ "arm,idle-state";
|
||||
+ entry-latency-us = <400>;
|
||||
+ exit-latency-us = <900>;
|
||||
+ min-residency-us = <3000>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ thermal-zones {
|
||||
+ cpu-thermal0 {
|
||||
+ polling-delay-passive = <250>;
|
||||
+ polling-delay = <1000>;
|
||||
+
|
||||
+ thermal-sensors = <&gcc 5>;
|
||||
+ coefficients = <1132 0>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu_alert0: trip0 {
|
||||
+ temperature = <75000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ cpu_crit0: trip1 {
|
||||
+ temperature = <110000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cpu-thermal1 {
|
||||
+ polling-delay-passive = <250>;
|
||||
+ polling-delay = <1000>;
|
||||
+
|
||||
+ thermal-sensors = <&gcc 6>;
|
||||
+ coefficients = <1132 0>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu_alert1: trip0 {
|
||||
+ temperature = <75000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ cpu_crit1: trip1 {
|
||||
+ temperature = <110000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cpu-thermal2 {
|
||||
+ polling-delay-passive = <250>;
|
||||
+ polling-delay = <1000>;
|
||||
+
|
||||
+ thermal-sensors = <&gcc 7>;
|
||||
+ coefficients = <1199 0>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu_alert2: trip0 {
|
||||
+ temperature = <75000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ cpu_crit2: trip1 {
|
||||
+ temperature = <110000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cpu-thermal3 {
|
||||
+ polling-delay-passive = <250>;
|
||||
+ polling-delay = <1000>;
|
||||
+
|
||||
+ thermal-sensors = <&gcc 8>;
|
||||
+ coefficients = <1132 0>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu_alert3: trip0 {
|
||||
+ temperature = <75000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ cpu_crit3: trip1 {
|
||||
+ temperature = <110000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
||||
|
||||
@@ -57,7 +177,7 @@
|
||||
no-map;
|
||||
};
|
||||
|
||||
- smem@41000000 {
|
||||
+ smem: smem@41000000 {
|
||||
reg = <0x41000000 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
@@ -67,13 +187,13 @@
|
||||
cxo_board {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
- clock-frequency = <19200000>;
|
||||
+ clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
pxo_board {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
- clock-frequency = <27000000>;
|
||||
+ clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
sleep_clk: sleep_clk {
|
||||
@@ -83,6 +203,46 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ kraitcc: clock-controller {
|
||||
+ compatible = "qcom,krait-cc-v1";
|
||||
+ #clock-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
+ qcom,pvs {
|
||||
+ qcom,pvs-format-a;
|
||||
+ qcom,speed0-pvs0-bin-v0 =
|
||||
+ < 1400000000 1250000 >,
|
||||
+ < 1200000000 1200000 >,
|
||||
+ < 1000000000 1150000 >,
|
||||
+ < 800000000 1100000 >,
|
||||
+ < 600000000 1050000 >,
|
||||
+ < 384000000 1000000 >;
|
||||
+
|
||||
+ qcom,speed0-pvs1-bin-v0 =
|
||||
+ < 1400000000 1175000 >,
|
||||
+ < 1200000000 1125000 >,
|
||||
+ < 1000000000 1075000 >,
|
||||
+ < 800000000 1025000 >,
|
||||
+ < 600000000 975000 >,
|
||||
+ < 384000000 925000 >;
|
||||
+
|
||||
+ qcom,speed0-pvs2-bin-v0 =
|
||||
+ < 1400000000 1125000 >,
|
||||
+ < 1200000000 1075000 >,
|
||||
+ < 1000000000 1025000 >,
|
||||
+ < 800000000 995000 >,
|
||||
+ < 600000000 925000 >,
|
||||
+ < 384000000 875000 >;
|
||||
+
|
||||
+ qcom,speed0-pvs3-bin-v0 =
|
||||
+ < 1400000000 1050000 >,
|
||||
+ < 1200000000 1000000 >,
|
||||
+ < 1000000000 950000 >,
|
||||
+ < 800000000 900000 >,
|
||||
+ < 600000000 850000 >,
|
||||
+ < 384000000 800000 >;
|
||||
+ };
|
||||
+
|
||||
soc: soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@@ -104,6 +264,85 @@
|
||||
reg-names = "lpass-lpaif";
|
||||
};
|
||||
|
||||
+ qfprom: qfprom@700000 {
|
||||
+ compatible = "qcom,qfprom", "syscon";
|
||||
+ reg = <0x00700000 0x1000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges;
|
||||
+
|
||||
+ tsens_calib: calib {
|
||||
+ reg = <0x400 0x10>;
|
||||
+ };
|
||||
+ tsens_backup: backup_calib {
|
||||
+ reg = <0x410 0x10>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rpm@108000 {
|
||||
+ compatible = "qcom,rpm-ipq8064";
|
||||
+ reg = <0x108000 0x1000>;
|
||||
+ qcom,ipc = <&l2cc 0x8 2>;
|
||||
+
|
||||
+ interrupts = <0 19 0>,
|
||||
+ <0 21 0>,
|
||||
+ <0 22 0>;
|
||||
+ interrupt-names = "ack",
|
||||
+ "err",
|
||||
+ "wakeup";
|
||||
+
|
||||
+ clocks = <&gcc RPM_MSG_RAM_H_CLK>;
|
||||
+ clock-names = "ram";
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ rpmcc: clock-controller {
|
||||
+ compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
|
||||
+ #clock-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
+ regulators {
|
||||
+ compatible = "qcom,rpm-smb208-regulators";
|
||||
+
|
||||
+ smb208_s1a: s1a {
|
||||
+ regulator-min-microvolt = <1050000>;
|
||||
+ regulator-max-microvolt = <1150000>;
|
||||
+
|
||||
+ qcom,switch-mode-frequency = <1200000>;
|
||||
+
|
||||
+ };
|
||||
+
|
||||
+ smb208_s1b: s1b {
|
||||
+ regulator-min-microvolt = <1050000>;
|
||||
+ regulator-max-microvolt = <1150000>;
|
||||
+
|
||||
+ qcom,switch-mode-frequency = <1200000>;
|
||||
+ };
|
||||
+
|
||||
+ smb208_s2a: s2a {
|
||||
+ regulator-min-microvolt = < 800000>;
|
||||
+ regulator-max-microvolt = <1250000>;
|
||||
+
|
||||
+ qcom,switch-mode-frequency = <1200000>;
|
||||
+ };
|
||||
+
|
||||
+ smb208_s2b: s2b {
|
||||
+ regulator-min-microvolt = < 800000>;
|
||||
+ regulator-max-microvolt = <1250000>;
|
||||
+
|
||||
+ qcom,switch-mode-frequency = <1200000>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rng@1a500000 {
|
||||
+ compatible = "qcom,prng";
|
||||
+ reg = <0x1a500000 0x200>;
|
||||
+ clocks = <&gcc PRNG_CLK>;
|
||||
+ clock-names = "core";
|
||||
+ };
|
||||
+
|
||||
qcom_pinmux: pinmux@800000 {
|
||||
compatible = "qcom,ipq8064-pinctrl";
|
||||
reg = <0x800000 0x4000>;
|
||||
@@ -113,6 +352,34 @@
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 16 0x4>;
|
||||
+
|
||||
+ pcie0_pins: pcie0_pinmux {
|
||||
+ mux {
|
||||
+ pins = "gpio3";
|
||||
+ function = "pcie1_rst";
|
||||
+ drive-strength = <2>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie1_pins: pcie1_pinmux {
|
||||
+ mux {
|
||||
+ pins = "gpio48";
|
||||
+ function = "pcie2_rst";
|
||||
+ drive-strength = <2>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie2_pins: pcie2_pinmux {
|
||||
+ mux {
|
||||
+ pins = "gpio63";
|
||||
+ function = "pcie3_rst";
|
||||
+ drive-strength = <2>;
|
||||
+ bias-disable;
|
||||
+ output-low;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
intc: interrupt-controller@2000000 {
|
||||
@@ -124,8 +391,7 @@
|
||||
};
|
||||
|
||||
timer@200a000 {
|
||||
- compatible = "qcom,kpss-timer",
|
||||
- "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
|
||||
+ compatible = "qcom,kpss-timer", "qcom,msm-timer";
|
||||
interrupts = <1 1 0x301>,
|
||||
<1 2 0x301>,
|
||||
<1 3 0x301>,
|
||||
@@ -142,25 +408,44 @@
|
||||
acc0: clock-controller@2088000 {
|
||||
compatible = "qcom,kpss-acc-v1";
|
||||
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
|
||||
+ clock-output-names = "acpu0_aux";
|
||||
};
|
||||
|
||||
acc1: clock-controller@2098000 {
|
||||
compatible = "qcom,kpss-acc-v1";
|
||||
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
|
||||
+ clock-output-names = "acpu1_aux";
|
||||
};
|
||||
|
||||
+ l2cc: clock-controller@2011000 {
|
||||
+ compatible = "qcom,kpss-gcc", "syscon";
|
||||
+ reg = <0x2011000 0x1000>;
|
||||
+ clock-output-names = "acpu_l2_aux";
|
||||
+ };
|
||||
+
|
||||
saw0: regulator@2089000 {
|
||||
- compatible = "qcom,saw2";
|
||||
+ compatible = "qcom,saw2", "syscon";
|
||||
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
|
||||
regulator;
|
||||
};
|
||||
|
||||
saw1: regulator@2099000 {
|
||||
- compatible = "qcom,saw2";
|
||||
+ compatible = "qcom,saw2", "syscon";
|
||||
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
|
||||
regulator;
|
||||
};
|
||||
|
||||
+ saw_l2: regulator@02012000 {
|
||||
+ compatible = "qcom,saw2", "syscon";
|
||||
+ reg = <0x02012000 0x1000>;
|
||||
+ regulator;
|
||||
+ };
|
||||
+
|
||||
+ sic_non_secure: sic-non-secure@12100000 {
|
||||
+ compatible = "syscon";
|
||||
+ reg = <0x12100000 0x10000>;
|
||||
+ };
|
||||
+
|
||||
gsbi2: gsbi@12480000 {
|
||||
compatible = "qcom,gsbi-v1.0.0";
|
||||
cell-index = <2>;
|
||||
@@ -328,8 +613,12 @@
|
||||
gcc: clock-controller@900000 {
|
||||
compatible = "qcom,gcc-ipq8064";
|
||||
reg = <0x00900000 0x4000>;
|
||||
+ nvmem-cells = <&tsens_calib>, <&tsens_backup>;
|
||||
+ nvmem-cell-names = "calib", "calib_backup";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
+ #power-domain-cells = <1>;
|
||||
+ #thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
tcsr: syscon@1a400000 {
|
||||
@@ -344,10 +633,259 @@
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
+ sfpb_mutex_block: syscon@1200600 {
|
||||
+ compatible = "syscon";
|
||||
+ reg = <0x01200600 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ hs_phy_1: phy@100f8800 {
|
||||
+ compatible = "qcom,dwc3-hs-usb-phy";
|
||||
+ reg = <0x100f8800 0x30>;
|
||||
+ clocks = <&gcc USB30_1_UTMI_CLK>;
|
||||
+ clock-names = "ref";
|
||||
+ #phy-cells = <0>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ ss_phy_1: phy@100f8830 {
|
||||
+ compatible = "qcom,dwc3-ss-usb-phy";
|
||||
+ reg = <0x100f8830 0x30>;
|
||||
+ clocks = <&gcc USB30_1_MASTER_CLK>;
|
||||
+ clock-names = "ref";
|
||||
+ #phy-cells = <0>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ hs_phy_0: phy@110f8800 {
|
||||
+ compatible = "qcom,dwc3-hs-usb-phy";
|
||||
+ reg = <0x110f8800 0x30>;
|
||||
+ clocks = <&gcc USB30_0_UTMI_CLK>;
|
||||
+ clock-names = "ref";
|
||||
+ #phy-cells = <0>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ ss_phy_0: phy@110f8830 {
|
||||
+ compatible = "qcom,dwc3-ss-usb-phy";
|
||||
+ reg = <0x110f8830 0x30>;
|
||||
+ clocks = <&gcc USB30_0_MASTER_CLK>;
|
||||
+ clock-names = "ref";
|
||||
+ #phy-cells = <0>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ usb3_0: usb30@0 {
|
||||
+ compatible = "qcom,dwc3";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ clocks = <&gcc USB30_0_MASTER_CLK>;
|
||||
+ clock-names = "core";
|
||||
+
|
||||
+ syscon-tcsr = <&tcsr 0xb0 1>;
|
||||
+
|
||||
+ ranges;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ dwc3@11000000 {
|
||||
+ compatible = "snps,dwc3";
|
||||
+ reg = <0x11000000 0xcd00>;
|
||||
+ interrupts = <0 110 0x4>;
|
||||
+ phys = <&hs_phy_0>, <&ss_phy_0>;
|
||||
+ phy-names = "usb2-phy", "usb3-phy";
|
||||
+ dr_mode = "host";
|
||||
+ snps,dis_u3_susphy_quirk;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb3_1: usb30@1 {
|
||||
+ compatible = "qcom,dwc3";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ clocks = <&gcc USB30_1_MASTER_CLK>;
|
||||
+ clock-names = "core";
|
||||
+
|
||||
+ syscon-tcsr = <&tcsr 0xb0 0>;
|
||||
+
|
||||
+ ranges;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ dwc3@10000000 {
|
||||
+ compatible = "snps,dwc3";
|
||||
+ reg = <0x10000000 0xcd00>;
|
||||
+ interrupts = <0 205 0x4>;
|
||||
+ phys = <&hs_phy_1>, <&ss_phy_1>;
|
||||
+ phy-names = "usb2-phy", "usb3-phy";
|
||||
+ dr_mode = "host";
|
||||
+ snps,dis_u3_susphy_quirk;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie0: pci@1b500000 {
|
||||
+ compatible = "qcom,pcie-v0";
|
||||
+ reg = <0x1b500000 0x1000
|
||||
+ 0x1b502000 0x80
|
||||
+ 0x1b600000 0x100
|
||||
+ 0x0ff00000 0x100000>;
|
||||
+ reg-names = "dbi", "elbi", "parf", "config";
|
||||
+ device_type = "pci";
|
||||
+ linux,pci-domain = <0>;
|
||||
+ bus-range = <0x00 0xff>;
|
||||
+ num-lanes = <1>;
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+
|
||||
+ ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
|
||||
+ 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
|
||||
+
|
||||
+ interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
|
||||
+ interrupt-names = "msi";
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-map-mask = <0 0 0 0x7>;
|
||||
+ interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
+ <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
+ <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
+ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
+
|
||||
+ clocks = <&gcc PCIE_A_CLK>,
|
||||
+ <&gcc PCIE_H_CLK>,
|
||||
+ <&gcc PCIE_PHY_CLK>,
|
||||
+ <&gcc PCIE_AUX_CLK>,
|
||||
+ <&gcc PCIE_ALT_REF_CLK>;
|
||||
+ clock-names = "core", "iface", "phy", "aux", "ref";
|
||||
+
|
||||
+ assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
|
||||
+ assigned-clock-rates = <100000000>;
|
||||
+
|
||||
+ resets = <&gcc PCIE_ACLK_RESET>,
|
||||
+ <&gcc PCIE_HCLK_RESET>,
|
||||
+ <&gcc PCIE_POR_RESET>,
|
||||
+ <&gcc PCIE_PCI_RESET>,
|
||||
+ <&gcc PCIE_PHY_RESET>,
|
||||
+ <&gcc PCIE_EXT_RESET>;
|
||||
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
||||
+
|
||||
+ pinctrl-0 = <&pcie0_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie1: pci@1b700000 {
|
||||
+ compatible = "qcom,pcie-v0";
|
||||
+ reg = <0x1b700000 0x1000
|
||||
+ 0x1b702000 0x80
|
||||
+ 0x1b800000 0x100
|
||||
+ 0x31f00000 0x100000>;
|
||||
+ reg-names = "dbi", "elbi", "parf", "config";
|
||||
+ device_type = "pci";
|
||||
+ linux,pci-domain = <1>;
|
||||
+ bus-range = <0x00 0xff>;
|
||||
+ num-lanes = <1>;
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+
|
||||
+ ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
|
||||
+ 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
|
||||
+
|
||||
+ interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
|
||||
+ interrupt-names = "msi";
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-map-mask = <0 0 0 0x7>;
|
||||
+ interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
+ <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
+ <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
+ <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
+
|
||||
+ clocks = <&gcc PCIE_1_A_CLK>,
|
||||
+ <&gcc PCIE_1_H_CLK>,
|
||||
+ <&gcc PCIE_1_PHY_CLK>,
|
||||
+ <&gcc PCIE_1_AUX_CLK>,
|
||||
+ <&gcc PCIE_1_ALT_REF_CLK>;
|
||||
+ clock-names = "core", "iface", "phy", "aux", "ref";
|
||||
+
|
||||
+ assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
|
||||
+ assigned-clock-rates = <100000000>;
|
||||
+
|
||||
+ resets = <&gcc PCIE_1_ACLK_RESET>,
|
||||
+ <&gcc PCIE_1_HCLK_RESET>,
|
||||
+ <&gcc PCIE_1_POR_RESET>,
|
||||
+ <&gcc PCIE_1_PCI_RESET>,
|
||||
+ <&gcc PCIE_1_PHY_RESET>,
|
||||
+ <&gcc PCIE_1_EXT_RESET>;
|
||||
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
||||
+
|
||||
+ pinctrl-0 = <&pcie1_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pcie2: pci@1b900000 {
|
||||
+ compatible = "qcom,pcie-v0";
|
||||
+ reg = <0x1b900000 0x1000
|
||||
+ 0x1b902000 0x80
|
||||
+ 0x1ba00000 0x100
|
||||
+ 0x35f00000 0x100000>;
|
||||
+ reg-names = "dbi", "elbi", "parf", "config";
|
||||
+ device_type = "pci";
|
||||
+ linux,pci-domain = <2>;
|
||||
+ bus-range = <0x00 0xff>;
|
||||
+ num-lanes = <1>;
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+
|
||||
+ ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
|
||||
+ 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
|
||||
+
|
||||
+ interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
|
||||
+ interrupt-names = "msi";
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-map-mask = <0 0 0 0x7>;
|
||||
+ interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
+ <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
+ <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
+ <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
+
|
||||
+ clocks = <&gcc PCIE_2_A_CLK>,
|
||||
+ <&gcc PCIE_2_H_CLK>,
|
||||
+ <&gcc PCIE_2_PHY_CLK>,
|
||||
+ <&gcc PCIE_2_AUX_CLK>,
|
||||
+ <&gcc PCIE_2_ALT_REF_CLK>;
|
||||
+ clock-names = "core", "iface", "phy", "aux", "ref";
|
||||
+
|
||||
+ assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
|
||||
+ assigned-clock-rates = <100000000>;
|
||||
+
|
||||
+ resets = <&gcc PCIE_2_ACLK_RESET>,
|
||||
+ <&gcc PCIE_2_HCLK_RESET>,
|
||||
+ <&gcc PCIE_2_POR_RESET>,
|
||||
+ <&gcc PCIE_2_PCI_RESET>,
|
||||
+ <&gcc PCIE_2_PHY_RESET>,
|
||||
+ <&gcc PCIE_2_EXT_RESET>;
|
||||
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
||||
+
|
||||
+ pinctrl-0 = <&pcie2_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
adm_dma: dma@18300000 {
|
||||
compatible = "qcom,adm";
|
||||
reg = <0x18300000 0x100000>;
|
||||
- interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
|
||||
+ interrupts = <0 170 0>;
|
||||
#dma-cells = <1>;
|
||||
|
||||
clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
|
||||
@@ -365,7 +903,7 @@
|
||||
};
|
||||
|
||||
nand@1ac00000 {
|
||||
- compatible = "qcom,ipq806x-nand";
|
||||
+ compatible = "qcom,ebi2-nandc";
|
||||
reg = <0x1ac00000 0x800>;
|
||||
|
||||
clocks = <&gcc EBI2_CLK>,
|
||||
@@ -380,5 +918,103 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ nss_common: syscon@03000000 {
|
||||
+ compatible = "syscon";
|
||||
+ reg = <0x03000000 0x0000FFFF>;
|
||||
+ };
|
||||
+
|
||||
+ qsgmii_csr: syscon@1bb00000 {
|
||||
+ compatible = "syscon";
|
||||
+ reg = <0x1bb00000 0x000001FF>;
|
||||
+ };
|
||||
+
|
||||
+ gmac0: ethernet@37000000 {
|
||||
+ device_type = "network";
|
||||
+ compatible = "qcom,ipq806x-gmac";
|
||||
+ reg = <0x37000000 0x200000>;
|
||||
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "macirq";
|
||||
+
|
||||
+ qcom,nss-common = <&nss_common>;
|
||||
+ qcom,qsgmii-csr = <&qsgmii_csr>;
|
||||
+
|
||||
+ clocks = <&gcc GMAC_CORE1_CLK>;
|
||||
+ clock-names = "stmmaceth";
|
||||
+
|
||||
+ resets = <&gcc GMAC_CORE1_RESET>;
|
||||
+ reset-names = "stmmaceth";
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gmac1: ethernet@37200000 {
|
||||
+ device_type = "network";
|
||||
+ compatible = "qcom,ipq806x-gmac";
|
||||
+ reg = <0x37200000 0x200000>;
|
||||
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "macirq";
|
||||
+
|
||||
+ qcom,nss-common = <&nss_common>;
|
||||
+ qcom,qsgmii-csr = <&qsgmii_csr>;
|
||||
+
|
||||
+ clocks = <&gcc GMAC_CORE2_CLK>;
|
||||
+ clock-names = "stmmaceth";
|
||||
+
|
||||
+ resets = <&gcc GMAC_CORE2_RESET>;
|
||||
+ reset-names = "stmmaceth";
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gmac2: ethernet@37400000 {
|
||||
+ device_type = "network";
|
||||
+ compatible = "qcom,ipq806x-gmac";
|
||||
+ reg = <0x37400000 0x200000>;
|
||||
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "macirq";
|
||||
+
|
||||
+ qcom,nss-common = <&nss_common>;
|
||||
+ qcom,qsgmii-csr = <&qsgmii_csr>;
|
||||
+
|
||||
+ clocks = <&gcc GMAC_CORE3_CLK>;
|
||||
+ clock-names = "stmmaceth";
|
||||
+
|
||||
+ resets = <&gcc GMAC_CORE3_RESET>;
|
||||
+ reset-names = "stmmaceth";
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gmac3: ethernet@37600000 {
|
||||
+ device_type = "network";
|
||||
+ compatible = "qcom,ipq806x-gmac";
|
||||
+ reg = <0x37600000 0x200000>;
|
||||
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "macirq";
|
||||
+
|
||||
+ qcom,nss-common = <&nss_common>;
|
||||
+ qcom,qsgmii-csr = <&qsgmii_csr>;
|
||||
+
|
||||
+ clocks = <&gcc GMAC_CORE4_CLK>;
|
||||
+ clock-names = "stmmaceth";
|
||||
+
|
||||
+ resets = <&gcc GMAC_CORE4_RESET>;
|
||||
+ reset-names = "stmmaceth";
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sfpb_mutex: sfpb-mutex {
|
||||
+ compatible = "qcom,sfpb-mutex";
|
||||
+ syscon = <&sfpb_mutex_block 4 4>;
|
||||
+
|
||||
+ #hwlock-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
+ smem {
|
||||
+ compatible = "qcom,smem";
|
||||
+ memory-region = <&smem>;
|
||||
+ hwlocks = <&sfpb_mutex 3>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue