mirror of https://github.com/hak5/openwrt-owl.git
gemini: add 3.18 support
Signed-off-by: Roman Yeryomin <roman@advem.lv> SVN-Revision: 45033owl
Felix Fietkau
parent
8ef68a2005
commit
a304f3d2b6
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@ -0,0 +1,163 @@
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CONFIG_ALIGNMENT_TRAP=y
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CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
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CONFIG_ARCH_GEMINI=y
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CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
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CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
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CONFIG_ARCH_NR_GPIO=0
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CONFIG_ARCH_REQUIRE_GPIOLIB=y
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# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
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# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
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CONFIG_ARCH_USES_GETTIMEOFFSET=y
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CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
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CONFIG_ARM=y
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# CONFIG_ARM_CPU_SUSPEND is not set
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CONFIG_ARM_L1_CACHE_SHIFT=5
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CONFIG_ARM_NR_BANKS=8
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CONFIG_ARM_PATCH_PHYS_VIRT=y
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# CONFIG_ARPD is not set
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CONFIG_ATA=y
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CONFIG_ATAGS=y
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# CONFIG_CACHE_L2X0 is not set
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CONFIG_CC_OPTIMIZE_FOR_SIZE=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,19200 mem=32M"
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CONFIG_CMDLINE_FROM_BOOTLOADER=y
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CONFIG_CPU_32v4=y
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CONFIG_CPU_ABRT_EV4=y
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# CONFIG_CPU_BPREDICT_DISABLE is not set
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CONFIG_CPU_CACHE_FA=y
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CONFIG_CPU_CACHE_VIVT=y
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CONFIG_CPU_COPY_FA=y
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CONFIG_CPU_CP15=y
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CONFIG_CPU_CP15_MMU=y
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# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
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CONFIG_CPU_FA526=y
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# CONFIG_CPU_ICACHE_DISABLE is not set
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CONFIG_CPU_PABRT_LEGACY=y
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CONFIG_CPU_TLB_FA=y
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CONFIG_CPU_USE_DOMAINS=y
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CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
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# CONFIG_DEBUG_USER is not set
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CONFIG_DEBUG_UART_PHYS=0x42000000
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CONFIG_DEBUG_UART_VIRT=0xf4200000
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CONFIG_DEBUG_UART_8250_SHIFT=2
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# CONFIG_DEBUG_UART_8250_WORD is not set
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# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
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# CONFIG_DLCI is not set
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CONFIG_DMADEVICES=y
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CONFIG_DNOTIFY=y
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# CONFIG_DW_DMAC_CORE is not set
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# CONFIG_DW_DMAC_PCI is not set
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CONFIG_FRAME_POINTER=y
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CONFIG_GEMINI_MEM_SWAP=y
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CONFIG_GEMINI_SL351X=y
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CONFIG_GEMINI_WATCHDOG=y
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CONFIG_GENERIC_ATOMIC64=y
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CONFIG_GENERIC_BUG=y
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CONFIG_GENERIC_IDLE_POLL_SETUP=y
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CONFIG_GENERIC_IO=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_STRNCPY_FROM_USER=y
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CONFIG_GENERIC_STRNLEN_USER=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIO_DEVRES=y
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CONFIG_GPIO_SYSFS=y
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CONFIG_HARDIRQS_SW_RESEND=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT=y
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# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
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CONFIG_HAVE_ARCH_JUMP_LABEL=y
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CONFIG_HAVE_ARCH_KGDB=y
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CONFIG_HAVE_ARCH_PFN_VALID=y
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CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
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CONFIG_HAVE_ARCH_TRACEHOOK=y
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# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
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CONFIG_HAVE_BPF_JIT=y
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CONFIG_HAVE_CONTEXT_TRACKING=y
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CONFIG_HAVE_C_RECORDMCOUNT=y
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CONFIG_HAVE_DEBUG_KMEMLEAK=y
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CONFIG_HAVE_DMA_API_DEBUG=y
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CONFIG_HAVE_DMA_ATTRS=y
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CONFIG_HAVE_DMA_CONTIGUOUS=y
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CONFIG_HAVE_DYNAMIC_FTRACE=y
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CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
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CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACER=y
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CONFIG_HAVE_GENERIC_DMA_COHERENT=y
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CONFIG_HAVE_GENERIC_HARDIRQS=y
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CONFIG_HAVE_IDE=y
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CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
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CONFIG_HAVE_KERNEL_GZIP=y
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CONFIG_HAVE_KERNEL_LZMA=y
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CONFIG_HAVE_KERNEL_LZO=y
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CONFIG_HAVE_KERNEL_XZ=y
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CONFIG_HAVE_LATENCYTOP_SUPPORT=y
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CONFIG_HAVE_MEMBLOCK=y
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CONFIG_HAVE_NET_DSA=y
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CONFIG_HAVE_OPROFILE=y
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CONFIG_HAVE_PERF_EVENTS=y
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CONFIG_HAVE_PROC_CPU=y
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CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
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CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
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CONFIG_HAVE_UID16=y
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CONFIG_HWMON=y
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CONFIG_HW_RANDOM=y
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CONFIG_I2C=y
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CONFIG_I2C_BOARDINFO=y
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CONFIG_I2C_CHARDEV=y
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CONFIG_INITRAMFS_SOURCE=""
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# CONFIG_IP_ADVANCED_ROUTER is not set
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CONFIG_IP_PIMSM_V1=y
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CONFIG_IP_PIMSM_V2=y
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CONFIG_IRQ_WORK=y
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CONFIG_KTIME_SCALAR=y
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CONFIG_LEGACY_PTYS=y
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CONFIG_LEGACY_PTY_COUNT=256
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# CONFIG_MACH_NAS4220B is not set
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# CONFIG_MACH_RUT100 is not set
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CONFIG_MACH_WBD111=y
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CONFIG_MACH_WBD222=y
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CONFIG_MDIO_BITBANG=y
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CONFIG_MDIO_BOARDINFO=y
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CONFIG_MDIO_GPIO=y
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CONFIG_MIGHT_HAVE_PCI=y
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CONFIG_MODULES_USE_ELF_REL=y
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CONFIG_MTD_PHYSMAP=y
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CONFIG_NEED_DMA_MAP_STATE=y
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CONFIG_NEED_KUSER_HELPERS=y
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CONFIG_NEED_MACH_GPIO_H=y
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CONFIG_NEED_PER_CPU_KM=y
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CONFIG_NET_VENDOR_GEMINI=y
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CONFIG_OLD_SIGACTION=y
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CONFIG_OLD_SIGSUSPEND3=y
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CONFIG_PAGEFLAGS_EXTENDED=y
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CONFIG_PAGE_OFFSET=0xC0000000
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CONFIG_PATA_GEMINI=y
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CONFIG_PCI=y
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CONFIG_PERF_USE_VMALLOC=y
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CONFIG_PHYLIB=y
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# CONFIG_PREEMPT_RCU is not set
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# CONFIG_RCU_STALL_COMMON is not set
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_GEMINI=y
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# CONFIG_SCHED_HRTICK is not set
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# CONFIG_SCSI_DMA is not set
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CONFIG_SPLIT_PTLOCK_CPUS=999999
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CONFIG_SYS_SUPPORTS_APM_EMULATION=y
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CONFIG_TICK_CPU_ACCOUNTING=y
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CONFIG_UID16=y
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CONFIG_UIDGID_CONVERTED=y
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CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h"
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CONFIG_USB_ARCH_HAS_XHCI=y
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CONFIG_USB_SUPPORT=y
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CONFIG_VECTORS_BASE=0xffff0000
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CONFIG_VM_EVENT_COUNTERS=y
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CONFIG_WAN=y
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CONFIG_XZ_DEC_ARM=y
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CONFIG_XZ_DEC_BCJ=y
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CONFIG_ZBOOT_ROM_BSS=0x0
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CONFIG_ZBOOT_ROM_TEXT=0x0
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CONFIG_ZONE_DMA_FLAG=0
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@ -0,0 +1,51 @@
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--- a/drivers/rtc/Kconfig
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+++ b/drivers/rtc/Kconfig
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@@ -1182,6 +1182,15 @@ config RTC_DRV_BFIN
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This driver can also be built as a module. If so, the module
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will be called rtc-bfin.
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+config RTC_DRV_GEMINI
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+ tristate "Gemini SoC RTC"
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+ help
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+ If you say Y here you will get support for the
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+ RTC found on Gemini SoC's.
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+
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+ This driver can also be built as a module. If so, the module
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+ will be called rtc-gemini.
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+
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config RTC_DRV_RS5C313
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tristate "Ricoh RS5C313"
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depends on SH_LANDISK
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--- a/drivers/rtc/Makefile
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+++ b/drivers/rtc/Makefile
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@@ -60,6 +60,7 @@ obj-$(CONFIG_RTC_DRV_DS3234) += rtc-ds3234.o
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obj-$(CONFIG_RTC_DRV_EM3027) += rtc-em3027.o
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obj-$(CONFIG_RTC_DRV_EP93XX) += rtc-ep93xx.o
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obj-$(CONFIG_RTC_DRV_FM3130) += rtc-fm3130.o
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+obj-$(CONFIG_RTC_DRV_GEMINI) += rtc-gemini.o
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obj-$(CONFIG_RTC_DRV_GENERIC) += rtc-generic.o
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obj-$(CONFIG_RTC_DRV_HID_SENSOR_TIME) += rtc-hid-sensor-time.o
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obj-$(CONFIG_RTC_DRV_HYM8563) += rtc-hym8563.o
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--- a/arch/arm/mach-gemini/common.h
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+++ b/arch/arm/mach-gemini/common.h
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@@ -18,9 +18,9 @@ extern void gemini_map_io(void);
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extern void gemini_init_irq(void);
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extern void gemini_timer_init(void);
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extern void gemini_gpio_init(void);
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-extern void platform_register_rtc(void);
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/* Common platform devices registration functions */
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+extern int platform_register_rtc(void);
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extern int platform_register_uart(void);
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extern int platform_register_pflash(unsigned int size,
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struct mtd_partition *parts,
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--- a/arch/arm/mach-gemini/devices.c
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+++ b/arch/arm/mach-gemini/devices.c
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@@ -17,6 +17,7 @@
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#include <mach/irqs.h>
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#include <mach/hardware.h>
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#include <mach/global_reg.h>
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+#include "common.h"
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static struct plat_serial8250_port serial_platform_data[] = {
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{
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@ -0,0 +1,25 @@
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--- a/arch/arm/mach-gemini/reset.c
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+++ b/arch/arm/mach-gemini/reset.c
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@@ -11,10 +11,11 @@
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#define __MACH_SYSTEM_H
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#include <linux/io.h>
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+#include <linux/reboot.h>
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#include <mach/hardware.h>
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#include <mach/global_reg.h>
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-void gemini_restart(char mode, const char *cmd)
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+void gemini_restart(enum reboot_mode mode, const char *cmd)
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{
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__raw_writel(RESET_GLOBAL | RESET_CPU1,
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IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET);
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--- a/arch/arm/mach-gemini/common.h 2014-08-23 07:06:06.014200638 -0500
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+++ b/arch/arm/mach-gemini/common.h 2014-08-23 07:07:33.450536466 -0500
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@@ -26,6 +26,6 @@
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struct mtd_partition *parts,
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unsigned int nr_parts);
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-extern void gemini_restart(char mode, const char *cmd);
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+extern void gemini_restart(enum reboot_mode mode, const char *cmd);
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#endif /* __GEMINI_COMMON_H__ */
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@ -0,0 +1,21 @@
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--- a/arch/arm/mach-gemini/gpio.c 2015-03-01 10:34:52.492113048 +0100
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+++ b/arch/arm/mach-gemini/gpio.c 2015-03-01 10:34:59.876498159 +0100
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@@ -196,12 +196,18 @@
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return 0;
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}
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+static int gemini_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
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+{
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+ return gpio + GPIO_IRQ_BASE;
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+}
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+
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static struct gpio_chip gemini_gpio_chip = {
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.label = "Gemini",
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.direction_input = gemini_gpio_direction_input,
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.get = gemini_gpio_get,
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.direction_output = gemini_gpio_direction_output,
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.set = gemini_gpio_set,
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+ .to_irq = gemini_gpio_to_irq,
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.base = 0,
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.ngpio = GPIO_PORT_NUM * 32,
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};
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@ -0,0 +1,41 @@
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--- a/arch/arm/mm/cache-fa.S 2011-01-05 01:50:19.000000000 +0100
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+++ b/arch/arm/mm/cache-fa.S 2012-07-25 14:30:40.883639094 +0200
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@@ -24,7 +24,8 @@
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/*
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* The size of one data cache line.
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*/
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-#define CACHE_DLINESIZE 16
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+#define CACHE_DLINESIZE 16
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+#define CACHE_DLINESHIFT 4
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/*
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* The total size of the data cache.
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@@ -169,7 +170,17 @@
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* - start - virtual start address
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* - end - virtual end address
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*/
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+__flush_whole_dcache:
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+ mcr p15, 0, r0, c7, c14, 0 @ clean/invalidate D cache
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+ mov r0, #0
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+ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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+ mov pc, lr
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+
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fa_dma_inv_range:
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+ sub r3, r1, r0 @ calculate total size
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+ cmp r3, #CACHE_DLIMIT @ total size >= limit?
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+ bhs __flush_whole_dcache @ flush whole D cache
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+
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tst r0, #CACHE_DLINESIZE - 1
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bic r0, r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
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@@ -193,6 +204,10 @@
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* - end - virtual end address
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*/
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fa_dma_clean_range:
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+ sub r3, r1, r0 @ calculate total size
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+ cmp r3, #CACHE_DLIMIT @ total size >= limit?
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+ bhs __flush_whole_dcache @ flush whole D cache
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+
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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@ -0,0 +1,410 @@
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--- /dev/null
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+++ b/drivers/watchdog/gemini_wdt.c
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@@ -0,0 +1,378 @@
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+/*
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+ * Watchdog driver for Cortina Systems Gemini SoC
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+ *
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+ * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/module.h>
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+#include <linux/io.h>
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+#include <linux/fs.h>
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+#include <linux/uaccess.h>
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+#include <linux/miscdevice.h>
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+#include <linux/platform_device.h>
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+#include <linux/watchdog.h>
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+#include <linux/slab.h>
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+
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+#define GEMINI_WDCOUNTER 0x0
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+#define GEMINI_WDLOAD 0x4
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+#define GEMINI_WDRESTART 0x8
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+
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+#define WDRESTART_MAGIC 0x5AB9
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+
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+#define GEMINI_WDCR 0xC
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+
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+#define WDCR_CLOCK_5MHZ (1 << 4)
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+#define WDCR_SYS_RST (1 << 1)
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+#define WDCR_ENABLE (1 << 0)
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+
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+#define WDT_CLOCK 5000000 /* 5 MHz */
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+#define WDT_DEFAULT_TIMEOUT 13
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+#define WDT_MAX_TIMEOUT (0xFFFFFFFF / WDT_CLOCK)
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+
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+/* status bits */
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+#define WDT_ACTIVE 0
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+#define WDT_OK_TO_CLOSE 1
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+
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+static unsigned int timeout = WDT_DEFAULT_TIMEOUT;
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+static int nowayout = WATCHDOG_NOWAYOUT;
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+
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+static DEFINE_SPINLOCK(gemini_wdt_lock);
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+
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+static struct platform_device *gemini_wdt_dev;
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+
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+struct gemini_wdt_struct {
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+ struct resource *res;
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+ struct device *dev;
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+ void __iomem *base;
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+ unsigned long status;
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+};
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+
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+static struct watchdog_info gemini_wdt_info = {
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+ .identity = "Gemini watchdog",
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+ .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING |
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+ WDIOF_SETTIMEOUT,
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+};
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+
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+/* Disable the watchdog. */
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+static void gemini_wdt_stop(struct gemini_wdt_struct *gemini_wdt)
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+{
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+ spin_lock(&gemini_wdt_lock);
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+
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+ __raw_writel(0, gemini_wdt->base + GEMINI_WDCR);
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+
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+ clear_bit(WDT_ACTIVE, &gemini_wdt->status);
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+
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+ spin_unlock(&gemini_wdt_lock);
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+}
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+
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+/* Service the watchdog */
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+static void gemini_wdt_service(struct gemini_wdt_struct *gemini_wdt)
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+{
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+ __raw_writel(WDRESTART_MAGIC, gemini_wdt->base + GEMINI_WDRESTART);
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+}
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+
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+/* Enable and reset the watchdog. */
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+static void gemini_wdt_start(struct gemini_wdt_struct *gemini_wdt)
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+{
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+ spin_lock(&gemini_wdt_lock);
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+
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+ __raw_writel(timeout * WDT_CLOCK, gemini_wdt->base + GEMINI_WDLOAD);
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+
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+ gemini_wdt_service(gemini_wdt);
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+
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+ /* set clock before enabling */
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+ __raw_writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST,
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+ gemini_wdt->base + GEMINI_WDCR);
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||||
+
|
||||
+ __raw_writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST | WDCR_ENABLE,
|
||||
+ gemini_wdt->base + GEMINI_WDCR);
|
||||
+
|
||||
+ set_bit(WDT_ACTIVE, &gemini_wdt->status);
|
||||
+
|
||||
+ spin_unlock(&gemini_wdt_lock);
|
||||
+}
|
||||
+
|
||||
+/* Watchdog device is opened, and watchdog starts running. */
|
||||
+static int gemini_wdt_open(struct inode *inode, struct file *file)
|
||||
+{
|
||||
+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(gemini_wdt_dev);
|
||||
+
|
||||
+ if (test_bit(WDT_ACTIVE, &gemini_wdt->status))
|
||||
+ return -EBUSY;
|
||||
+
|
||||
+ file->private_data = gemini_wdt;
|
||||
+
|
||||
+ gemini_wdt_start(gemini_wdt);
|
||||
+
|
||||
+ return nonseekable_open(inode, file);
|
||||
+}
|
||||
+
|
||||
+/* Close the watchdog device. */
|
||||
+static int gemini_wdt_close(struct inode *inode, struct file *file)
|
||||
+{
|
||||
+ struct gemini_wdt_struct *gemini_wdt = file->private_data;
|
||||
+
|
||||
+ /* Disable the watchdog if possible */
|
||||
+ if (test_bit(WDT_OK_TO_CLOSE, &gemini_wdt->status))
|
||||
+ gemini_wdt_stop(gemini_wdt);
|
||||
+ else
|
||||
+ dev_warn(gemini_wdt->dev, "Device closed unexpectedly - timer will not stop\n");
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+/* Handle commands from user-space. */
|
||||
+static long gemini_wdt_ioctl(struct file *file, unsigned int cmd,
|
||||
+ unsigned long arg)
|
||||
+{
|
||||
+ struct gemini_wdt_struct *gemini_wdt = file->private_data;
|
||||
+
|
||||
+ int value;
|
||||
+
|
||||
+ switch (cmd) {
|
||||
+ case WDIOC_KEEPALIVE:
|
||||
+ gemini_wdt_service(gemini_wdt);
|
||||
+ return 0;
|
||||
+
|
||||
+ case WDIOC_GETSUPPORT:
|
||||
+ return copy_to_user((struct watchdog_info *)arg, &gemini_wdt_info,
|
||||
+ sizeof(gemini_wdt_info)) ? -EFAULT : 0;
|
||||
+
|
||||
+ case WDIOC_SETTIMEOUT:
|
||||
+ if (get_user(value, (int *)arg))
|
||||
+ return -EFAULT;
|
||||
+
|
||||
+ if ((value < 1) || (value > WDT_MAX_TIMEOUT))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ timeout = value;
|
||||
+
|
||||
+ /* restart wdt to use new timeout */
|
||||
+ gemini_wdt_stop(gemini_wdt);
|
||||
+ gemini_wdt_start(gemini_wdt);
|
||||
+
|
||||
+ /* Fall through */
|
||||
+ case WDIOC_GETTIMEOUT:
|
||||
+ return put_user(timeout, (int *)arg);
|
||||
+
|
||||
+ case WDIOC_GETTIMELEFT:
|
||||
+ value = __raw_readl(gemini_wdt->base + GEMINI_WDCOUNTER);
|
||||
+ return put_user(value / WDT_CLOCK, (int *)arg);
|
||||
+
|
||||
+ default:
|
||||
+ return -ENOTTY;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+/* Refresh the watchdog whenever device is written to. */
|
||||
+static ssize_t gemini_wdt_write(struct file *file, const char *data,
|
||||
+ size_t len, loff_t *ppos)
|
||||
+{
|
||||
+ struct gemini_wdt_struct *gemini_wdt = file->private_data;
|
||||
+
|
||||
+ if (len) {
|
||||
+ if (!nowayout) {
|
||||
+ size_t i;
|
||||
+
|
||||
+ clear_bit(WDT_OK_TO_CLOSE, &gemini_wdt->status);
|
||||
+ for (i = 0; i != len; i++) {
|
||||
+ char c;
|
||||
+
|
||||
+ if (get_user(c, data + i))
|
||||
+ return -EFAULT;
|
||||
+ if (c == 'V')
|
||||
+ set_bit(WDT_OK_TO_CLOSE,
|
||||
+ &gemini_wdt->status);
|
||||
+ }
|
||||
+ }
|
||||
+ gemini_wdt_service(gemini_wdt);
|
||||
+ }
|
||||
+
|
||||
+ return len;
|
||||
+}
|
||||
+
|
||||
+static const struct file_operations gemini_wdt_fops = {
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .llseek = no_llseek,
|
||||
+ .unlocked_ioctl = gemini_wdt_ioctl,
|
||||
+ .open = gemini_wdt_open,
|
||||
+ .release = gemini_wdt_close,
|
||||
+ .write = gemini_wdt_write,
|
||||
+};
|
||||
+
|
||||
+static struct miscdevice gemini_wdt_miscdev = {
|
||||
+ .minor = WATCHDOG_MINOR,
|
||||
+ .name = "watchdog",
|
||||
+ .fops = &gemini_wdt_fops,
|
||||
+};
|
||||
+
|
||||
+static void gemini_wdt_shutdown(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
|
||||
+
|
||||
+ gemini_wdt_stop(gemini_wdt);
|
||||
+}
|
||||
+
|
||||
+static int gemini_wdt_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ int ret;
|
||||
+ int res_size;
|
||||
+ struct resource *res;
|
||||
+ void __iomem *base;
|
||||
+ struct gemini_wdt_struct *gemini_wdt;
|
||||
+ unsigned int reg;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ if (!res) {
|
||||
+ dev_err(&pdev->dev, "can't get device resources\n");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ res_size = resource_size(res);
|
||||
+ if (!request_mem_region(res->start, res_size, res->name)) {
|
||||
+ dev_err(&pdev->dev, "can't allocate %d bytes at %d address\n",
|
||||
+ res_size, res->start);
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ base = ioremap(res->start, res_size);
|
||||
+ if (!base) {
|
||||
+ dev_err(&pdev->dev, "ioremap failed\n");
|
||||
+ ret = -EIO;
|
||||
+ goto fail0;
|
||||
+ }
|
||||
+
|
||||
+ gemini_wdt = kzalloc(sizeof(struct gemini_wdt_struct), GFP_KERNEL);
|
||||
+ if (!gemini_wdt) {
|
||||
+ dev_err(&pdev->dev, "can't allocate interface\n");
|
||||
+ ret = -ENOMEM;
|
||||
+ goto fail1;
|
||||
+ }
|
||||
+
|
||||
+ /* Setup gemini_wdt driver structure */
|
||||
+ gemini_wdt->base = base;
|
||||
+ gemini_wdt->res = res;
|
||||
+
|
||||
+ /* Set up platform driver data */
|
||||
+ platform_set_drvdata(pdev, gemini_wdt);
|
||||
+ gemini_wdt_dev = pdev;
|
||||
+
|
||||
+ if (gemini_wdt_miscdev.parent) {
|
||||
+ ret = -EBUSY;
|
||||
+ goto fail2;
|
||||
+ }
|
||||
+
|
||||
+ gemini_wdt_miscdev.parent = &pdev->dev;
|
||||
+
|
||||
+ reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR);
|
||||
+ if (reg & WDCR_ENABLE) {
|
||||
+ /* Watchdog was enabled by the bootloader, disable it. */
|
||||
+ reg &= ~(WDCR_ENABLE);
|
||||
+ __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR);
|
||||
+ }
|
||||
+
|
||||
+ ret = misc_register(&gemini_wdt_miscdev);
|
||||
+ if (ret)
|
||||
+ goto fail2;
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+fail2:
|
||||
+ platform_set_drvdata(pdev, NULL);
|
||||
+ kfree(gemini_wdt);
|
||||
+fail1:
|
||||
+ iounmap(base);
|
||||
+fail0:
|
||||
+ release_mem_region(res->start, res_size);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int gemini_wdt_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
|
||||
+
|
||||
+ platform_set_drvdata(pdev, NULL);
|
||||
+ misc_deregister(&gemini_wdt_miscdev);
|
||||
+ gemini_wdt_dev = NULL;
|
||||
+ iounmap(gemini_wdt->base);
|
||||
+ release_mem_region(gemini_wdt->res->start, resource_size(gemini_wdt->res));
|
||||
+
|
||||
+ kfree(gemini_wdt);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+#ifdef CONFIG_PM
|
||||
+static int gemini_wdt_suspend(struct platform_device *pdev, pm_message_t message)
|
||||
+{
|
||||
+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
|
||||
+ unsigned int reg;
|
||||
+
|
||||
+ reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR);
|
||||
+ reg &= ~(WDCR_WDENABLE);
|
||||
+ __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int gemini_wdt_resume(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
|
||||
+ unsigned int reg;
|
||||
+
|
||||
+ if (gemini_wdt->status) {
|
||||
+ reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR);
|
||||
+ reg |= WDCR_WDENABLE;
|
||||
+ __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+#else
|
||||
+#define gemini_wdt_suspend NULL
|
||||
+#define gemini_wdt_resume NULL
|
||||
+#endif
|
||||
+
|
||||
+static struct platform_driver gemini_wdt_driver = {
|
||||
+ .probe = gemini_wdt_probe,
|
||||
+ .remove = gemini_wdt_remove,
|
||||
+ .shutdown = gemini_wdt_shutdown,
|
||||
+ .suspend = gemini_wdt_suspend,
|
||||
+ .resume = gemini_wdt_resume,
|
||||
+ .driver = {
|
||||
+ .name = "gemini-wdt",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static int __init gemini_wdt_init(void)
|
||||
+{
|
||||
+ return platform_driver_probe(&gemini_wdt_driver, gemini_wdt_probe);
|
||||
+}
|
||||
+
|
||||
+static void __exit gemini_wdt_exit(void)
|
||||
+{
|
||||
+ platform_driver_unregister(&gemini_wdt_driver);
|
||||
+}
|
||||
+
|
||||
+module_init(gemini_wdt_init);
|
||||
+module_exit(gemini_wdt_exit);
|
||||
+
|
||||
+module_param(timeout, uint, 0);
|
||||
+MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
|
||||
+
|
||||
+module_param(nowayout, int, 0);
|
||||
+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
|
||||
+
|
||||
+MODULE_AUTHOR("Paulius Zaleckas");
|
||||
+MODULE_DESCRIPTION("Watchdog driver for Gemini");
|
||||
+MODULE_LICENSE("GPL");
|
||||
+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
|
||||
+MODULE_ALIAS("platform:gemini-wdt");
|
||||
--- a/drivers/watchdog/Kconfig
|
||||
+++ b/drivers/watchdog/Kconfig
|
||||
@@ -199,6 +199,16 @@ config 977_WATCHDOG
|
||||
|
||||
Not sure? It's safe to say N.
|
||||
|
||||
+config GEMINI_WATCHDOG
|
||||
+ tristate "Gemini watchdog"
|
||||
+ depends on ARCH_GEMINI
|
||||
+ help
|
||||
+ Say Y here if to include support for the watchdog timer
|
||||
+ embedded in the Cortina Systems Gemini family of devices.
|
||||
+
|
||||
+ To compile this driver as a module, choose M here: the
|
||||
+ module will be called gemini_wdt.
|
||||
+
|
||||
config IXP4XX_WATCHDOG
|
||||
tristate "IXP4xx Watchdog"
|
||||
depends on ARCH_IXP4XX
|
||||
--- a/drivers/watchdog/Makefile
|
||||
+++ b/drivers/watchdog/Makefile
|
||||
@@ -37,6 +37,7 @@ obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.
|
||||
obj-$(CONFIG_TWL4030_WATCHDOG) += twl4030_wdt.o
|
||||
obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
|
||||
obj-$(CONFIG_977_WATCHDOG) += wdt977.o
|
||||
+obj-$(CONFIG_GEMINI_WATCHDOG) += gemini_wdt.o
|
||||
obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o
|
||||
obj-$(CONFIG_KS8695_WATCHDOG) += ks8695_wdt.o
|
||||
obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
--- a/arch/arm/mach-gemini/devices.c
|
||||
+++ b/arch/arm/mach-gemini/devices.c
|
||||
@@ -117,3 +117,20 @@ int __init platform_register_rtc(void)
|
||||
return platform_device_register(&gemini_rtc_device);
|
||||
}
|
||||
|
||||
+static struct resource wdt_resource = {
|
||||
+ .start = GEMINI_WAQTCHDOG_BASE,
|
||||
+ .end = GEMINI_WAQTCHDOG_BASE + 0x18,
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+};
|
||||
+
|
||||
+static struct platform_device wdt_device = {
|
||||
+ .name = "gemini-wdt",
|
||||
+ .id = 0,
|
||||
+ .resource = &wdt_resource,
|
||||
+ .num_resources = 1,
|
||||
+};
|
||||
+
|
||||
+int __init platform_register_watchdog(void)
|
||||
+{
|
||||
+ return platform_device_register(&wdt_device);
|
||||
+}
|
||||
--- a/arch/arm/mach-gemini/common.h
|
||||
+++ b/arch/arm/mach-gemini/common.h
|
||||
@@ -25,6 +25,7 @@ extern int platform_register_uart(void);
|
||||
extern int platform_register_pflash(unsigned int size,
|
||||
struct mtd_partition *parts,
|
||||
unsigned int nr_parts);
|
||||
+extern int platform_register_watchdog(void);
|
||||
|
||||
extern void gemini_restart(enum reboot_mode mode, const char *cmd);
|
||||
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
--- a/arch/arm/mach-gemini/board-nas4220b.c
|
||||
+++ b/arch/arm/mach-gemini/board-nas4220b.c
|
||||
@@ -95,6 +95,7 @@ static void __init ib4220b_init(void)
|
||||
platform_device_register(&ib4220b_led_device);
|
||||
platform_device_register(&ib4220b_key_device);
|
||||
platform_register_rtc();
|
||||
+ platform_register_watchdog();
|
||||
}
|
||||
|
||||
MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
|
||||
--- a/arch/arm/mach-gemini/board-wbd111.c
|
||||
+++ b/arch/arm/mach-gemini/board-wbd111.c
|
||||
@@ -122,6 +122,7 @@ static void __init wbd111_init(void)
|
||||
platform_device_register(&wbd111_leds_device);
|
||||
platform_device_register(&wbd111_keys_device);
|
||||
platform_register_rtc();
|
||||
+ platform_register_watchdog();
|
||||
}
|
||||
|
||||
MACHINE_START(WBD111, "Wiliboard WBD-111")
|
||||
--- a/arch/arm/mach-gemini/board-wbd222.c
|
||||
+++ b/arch/arm/mach-gemini/board-wbd222.c
|
||||
@@ -122,6 +122,7 @@ static void __init wbd222_init(void)
|
||||
platform_device_register(&wbd222_leds_device);
|
||||
platform_device_register(&wbd222_keys_device);
|
||||
platform_register_rtc();
|
||||
+ platform_register_watchdog();
|
||||
}
|
||||
|
||||
MACHINE_START(WBD222, "Wiliboard WBD-222")
|
||||
--- a/arch/arm/mach-gemini/board-rut1xx.c
|
||||
+++ b/arch/arm/mach-gemini/board-rut1xx.c
|
||||
@@ -80,6 +80,7 @@ static void __init rut1xx_init(void)
|
||||
platform_device_register(&rut1xx_leds);
|
||||
platform_device_register(&rut1xx_keys_device);
|
||||
platform_register_rtc();
|
||||
+ platform_register_watchdog();
|
||||
}
|
||||
|
||||
MACHINE_START(RUT100, "Teltonika RUT100")
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,210 @@
|
|||
--- a/arch/arm/mach-gemini/board-nas4220b.c 2011-04-21 13:19:09.878432930 +0200
|
||||
+++ b/arch/arm/mach-gemini/board-nas4220b.c 2011-04-21 13:30:37.555082365 +0200
|
||||
@@ -28,9 +28,27 @@
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/global_reg.h>
|
||||
+#include <mach/gmac.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
+static struct mdio_gpio_platform_data ib4220b_mdio = {
|
||||
+ .mdc = 22,
|
||||
+ .mdio = 21,
|
||||
+ .phy_mask = ~(1 << 1),
|
||||
+};
|
||||
+
|
||||
+static struct platform_device ib4220b_phy_device = {
|
||||
+ .name = "mdio-gpio",
|
||||
+ .id = 0,
|
||||
+ .dev = { .platform_data = &ib4220b_mdio, },
|
||||
+};
|
||||
+
|
||||
+static struct gemini_gmac_platform_data ib4220b_gmac_data = {
|
||||
+ .bus_id[0] = "gpio-0:01",
|
||||
+ .interface[0] = PHY_INTERFACE_MODE_RGMII,
|
||||
+};
|
||||
+
|
||||
static struct gpio_led ib4220b_leds[] = {
|
||||
{
|
||||
.name = "nas4220b:orange:hdd",
|
||||
@@ -87,9 +105,39 @@
|
||||
},
|
||||
};
|
||||
|
||||
+static void __init ib4220b_gmac_init(void)
|
||||
+{
|
||||
+ unsigned int val;
|
||||
+
|
||||
+ val = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
|
||||
+ GLOBAL_IO_DRIVING_CTRL));
|
||||
+ val |= (0x3 << GMAC0_PADS_SHIFT) | (0x3 << GMAC1_PADS_SHIFT);
|
||||
+ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
|
||||
+ GLOBAL_IO_DRIVING_CTRL));
|
||||
+
|
||||
+ val = (0x0 << GMAC0_RXDV_SKEW_SHIFT) | (0xf << GMAC0_RXC_SKEW_SHIFT) |
|
||||
+ (0x7 << GMAC0_TXEN_SKEW_SHIFT) | (0xb << GMAC0_TXC_SKEW_SHIFT) |
|
||||
+ (0x0 << GMAC1_RXDV_SKEW_SHIFT) | (0xf << GMAC1_RXC_SKEW_SHIFT) |
|
||||
+ (0x7 << GMAC1_TXEN_SKEW_SHIFT) | (0xa << GMAC1_TXC_SKEW_SHIFT);
|
||||
+ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
|
||||
+ GLOBAL_GMAC_CTRL_SKEW_CTRL));
|
||||
+
|
||||
+ writel(0x77777777, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
|
||||
+ GLOBAL_GMAC0_DATA_SKEW_CTRL));
|
||||
+ writel(0x77777777, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
|
||||
+ GLOBAL_GMAC1_DATA_SKEW_CTRL));
|
||||
+
|
||||
+ val = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
|
||||
+ GLOBAL_ARBITRATION1_CTRL)) & ~BURST_LENGTH_MASK;
|
||||
+ val |= (0x20 << BURST_LENGTH_SHIFT) | GMAC0_HIGH_PRIO | GMAC1_HIGH_PRIO;
|
||||
+ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
|
||||
+ GLOBAL_ARBITRATION1_CTRL));
|
||||
+}
|
||||
+
|
||||
static void __init ib4220b_init(void)
|
||||
{
|
||||
gemini_gpio_init();
|
||||
+ ib4220b_gmac_init();
|
||||
platform_register_uart();
|
||||
platform_register_pflash(SZ_16M, NULL, 0);
|
||||
platform_device_register(&ib4220b_led_device);
|
||||
@@ -96,6 +144,8 @@
|
||||
platform_device_register(&ib4220b_key_device);
|
||||
platform_register_rtc();
|
||||
platform_register_watchdog();
|
||||
+ platform_device_register(&ib4220b_phy_device);
|
||||
+ platform_register_ethernet(&ib4220b_gmac_data);
|
||||
}
|
||||
|
||||
MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
|
||||
--- a/arch/arm/mach-gemini/board-wbd111.c
|
||||
+++ b/arch/arm/mach-gemini/board-wbd111.c
|
||||
@@ -22,9 +22,29 @@
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
+#include <mach/gmac.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
+static struct mdio_gpio_platform_data wbd111_mdio = {
|
||||
+ .mdc = 22,
|
||||
+ .mdio = 21,
|
||||
+ .phy_mask = ~(1 << 1),
|
||||
+};
|
||||
+
|
||||
+static struct platform_device wbd111_phy_device = {
|
||||
+ .name = "mdio-gpio",
|
||||
+ .id = 0,
|
||||
+ .dev = {
|
||||
+ .platform_data = &wbd111_mdio,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static struct gemini_gmac_platform_data gmac_data = {
|
||||
+ .bus_id[0] = "gpio-0:01",
|
||||
+ .interface[0] = PHY_INTERFACE_MODE_MII,
|
||||
+};
|
||||
+
|
||||
static struct gpio_keys_button wbd111_keys[] = {
|
||||
{
|
||||
.code = KEY_SETUP,
|
||||
@@ -123,6 +143,8 @@ static void __init wbd111_init(void)
|
||||
platform_device_register(&wbd111_keys_device);
|
||||
platform_register_rtc();
|
||||
platform_register_watchdog();
|
||||
+ platform_device_register(&wbd111_phy_device);
|
||||
+ platform_register_ethernet(&gmac_data);
|
||||
}
|
||||
|
||||
MACHINE_START(WBD111, "Wiliboard WBD-111")
|
||||
--- a/arch/arm/mach-gemini/board-wbd222.c
|
||||
+++ b/arch/arm/mach-gemini/board-wbd222.c
|
||||
@@ -22,9 +22,31 @@
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
+#include <mach/gmac.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
+static struct mdio_gpio_platform_data wbd222_mdio = {
|
||||
+ .mdc = 22,
|
||||
+ .mdio = 21,
|
||||
+ .phy_mask = ~((1 << 1) | (1 << 3)),
|
||||
+};
|
||||
+
|
||||
+static struct platform_device wbd222_phy_device = {
|
||||
+ .name = "mdio-gpio",
|
||||
+ .id = 0,
|
||||
+ .dev = {
|
||||
+ .platform_data = &wbd222_mdio,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static struct gemini_gmac_platform_data gmac_data = {
|
||||
+ .bus_id[0] = "gpio-0:01",
|
||||
+ .interface[0] = PHY_INTERFACE_MODE_MII,
|
||||
+ .bus_id[1] = "gpio-0:03",
|
||||
+ .interface[1] = PHY_INTERFACE_MODE_MII,
|
||||
+};
|
||||
+
|
||||
static struct gpio_keys_button wbd222_keys[] = {
|
||||
{
|
||||
.code = KEY_SETUP,
|
||||
@@ -123,6 +145,8 @@ static void __init wbd222_init(void)
|
||||
platform_device_register(&wbd222_keys_device);
|
||||
platform_register_rtc();
|
||||
platform_register_watchdog();
|
||||
+ platform_device_register(&wbd222_phy_device);
|
||||
+ platform_register_ethernet(&gmac_data);
|
||||
}
|
||||
|
||||
MACHINE_START(WBD222, "Wiliboard WBD-222")
|
||||
--- a/arch/arm/mach-gemini/board-rut1xx.c
|
||||
+++ b/arch/arm/mach-gemini/board-rut1xx.c
|
||||
@@ -15,13 +15,35 @@
|
||||
#include <linux/input.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/sizes.h>
|
||||
+#include <linux/mdio-gpio.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
+#include <mach/gmac.h>
|
||||
+
|
||||
#include "common.h"
|
||||
|
||||
+static struct mdio_gpio_platform_data rut1xx_mdio = {
|
||||
+ .mdc = 22,
|
||||
+ .mdio = 21,
|
||||
+ .phy_mask = ~(1 << 1),
|
||||
+};
|
||||
+
|
||||
+static struct platform_device rut1xx_phy_device = {
|
||||
+ .name = "mdio-gpio",
|
||||
+ .id = 0,
|
||||
+ .dev = {
|
||||
+ .platform_data = &rut1xx_mdio,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static struct gemini_gmac_platform_data gmac_data = {
|
||||
+ .bus_id[0] = "gpio-0:01",
|
||||
+ .interface[0] = PHY_INTERFACE_MODE_MII,
|
||||
+};
|
||||
+
|
||||
static struct gpio_keys_button rut1xx_keys[] = {
|
||||
{
|
||||
.code = KEY_SETUP,
|
||||
@@ -81,6 +103,8 @@ static void __init rut1xx_init(void)
|
||||
platform_device_register(&rut1xx_keys_device);
|
||||
platform_register_rtc();
|
||||
platform_register_watchdog();
|
||||
+ platform_device_register(&rut1xx_phy_device);
|
||||
+ platform_register_ethernet(&gmac_data);
|
||||
}
|
||||
|
||||
MACHINE_START(RUT100, "Teltonika RUT100")
|
||||
|
|
@ -0,0 +1,213 @@
|
|||
--- a/arch/arm/mach-gemini/devices.c 2011-04-23 01:00:16.738137491 +0200
|
||||
+++ b/arch/arm/mach-gemini/devices.c 2011-04-23 01:06:55.539299920 +0200
|
||||
@@ -188,3 +188,64 @@
|
||||
|
||||
return platform_device_register(ðernet_device);
|
||||
}
|
||||
+
|
||||
+static struct resource usb0_resources[] = {
|
||||
+ {
|
||||
+ .start = GEMINI_USB0_BASE,
|
||||
+ .end = GEMINI_USB0_BASE + 0xfff,
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+ },
|
||||
+ {
|
||||
+ .start = IRQ_USB0,
|
||||
+ .end = IRQ_USB0,
|
||||
+ .flags = IORESOURCE_IRQ,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static struct resource usb1_resources[] = {
|
||||
+ {
|
||||
+ .start = GEMINI_USB1_BASE,
|
||||
+ .end = GEMINI_USB1_BASE + 0xfff,
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+ },
|
||||
+ {
|
||||
+ .start = IRQ_USB1,
|
||||
+ .end = IRQ_USB1,
|
||||
+ .flags = IORESOURCE_IRQ,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static u64 usb0_dmamask = 0xffffffffUL;
|
||||
+static u64 usb1_dmamask = 0xffffffffUL;
|
||||
+
|
||||
+static struct platform_device usb_device[] = {
|
||||
+ {
|
||||
+ .name = "ehci-fotg2",
|
||||
+ .id = 0,
|
||||
+ .dev = {
|
||||
+ .dma_mask = &usb0_dmamask,
|
||||
+ .coherent_dma_mask = 0xffffffff,
|
||||
+ },
|
||||
+ .num_resources = ARRAY_SIZE(usb0_resources),
|
||||
+ .resource = usb0_resources,
|
||||
+ },
|
||||
+ {
|
||||
+ .name = "ehci-fotg2",
|
||||
+ .id = 1,
|
||||
+ .dev = {
|
||||
+ .dma_mask = &usb1_dmamask,
|
||||
+ .coherent_dma_mask = 0xffffffff,
|
||||
+ },
|
||||
+ .num_resources = ARRAY_SIZE(usb1_resources),
|
||||
+ .resource = usb1_resources,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+int __init platform_register_usb(unsigned int id)
|
||||
+{
|
||||
+ if (id > 1)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ return platform_device_register(&usb_device[id]);
|
||||
+}
|
||||
+
|
||||
--- a/arch/arm/mach-gemini/common.h 2011-04-23 01:09:31.413161153 +0200
|
||||
+++ b/arch/arm/mach-gemini/common.h 2011-04-23 01:09:52.426358514 +0200
|
||||
@@ -28,6 +28,7 @@
|
||||
unsigned int nr_parts);
|
||||
extern int platform_register_watchdog(void);
|
||||
extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata);
|
||||
+extern int platform_register_usb(unsigned int id);
|
||||
|
||||
extern void gemini_restart(enum reboot_mode mode, const char *cmd);
|
||||
|
||||
--- a/drivers/usb/host/ehci-hcd.c
|
||||
+++ b/drivers/usb/host/ehci-hcd.c
|
||||
@@ -345,12 +345,14 @@ static void ehci_silence_controller(struct ehci_hcd *ehci)
|
||||
spin_lock_irq(&ehci->lock);
|
||||
ehci->rh_state = EHCI_RH_HALTED;
|
||||
ehci_turn_off_all_ports(ehci);
|
||||
|
||||
+#ifndef CONFIG_ARCH_GEMINI
|
||||
/* make BIOS/etc use companion controller during reboot */
|
||||
ehci_writel(ehci, 0, &ehci->regs->configured_flag);
|
||||
|
||||
/* unblock posted writes */
|
||||
ehci_readl(ehci, &ehci->regs->configured_flag);
|
||||
+#endif
|
||||
spin_unlock_irq(&ehci->lock);
|
||||
}
|
||||
|
||||
@@ -602,7 +604,9 @@ static int ehci_run (struct usb_hcd *hcd)
|
||||
// Philips, Intel, and maybe others need CMD_RUN before the
|
||||
// root hub will detect new devices (why?); NEC doesn't
|
||||
ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
|
||||
+#ifndef CONFIG_ARCH_GEMINI
|
||||
ehci->command |= CMD_RUN;
|
||||
+#endif
|
||||
ehci_writel(ehci, ehci->command, &ehci->regs->command);
|
||||
dbg_cmd (ehci, "init", ehci->command);
|
||||
|
||||
@@ -622,9 +626,11 @@ static int ehci_run (struct usb_hcd *hcd)
|
||||
*/
|
||||
down_write(&ehci_cf_port_reset_rwsem);
|
||||
ehci->rh_state = EHCI_RH_RUNNING;
|
||||
+#ifndef CONFIG_ARCH_GEMINI
|
||||
ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
|
||||
ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
|
||||
msleep(5);
|
||||
+#endif
|
||||
up_write(&ehci_cf_port_reset_rwsem);
|
||||
ehci->last_periodic_enable = ktime_get_real();
|
||||
|
||||
@@ -762,9 +768,10 @@ static irqreturn_t ehci_irq (struct usb_hcd *hcd)
|
||||
pcd_status = status;
|
||||
|
||||
/* resume root hub? */
|
||||
+#ifndef CONFIG_ARCH_GEMINI
|
||||
if (ehci->rh_state == EHCI_RH_SUSPENDED)
|
||||
usb_hcd_resume_root_hub(hcd);
|
||||
-
|
||||
+#endif
|
||||
/* get per-port change detect bits */
|
||||
if (ehci->has_ppcd)
|
||||
ppcd = status >> 16;
|
||||
@@ -1243,6 +1250,11 @@ MODULE_DESCRIPTION(DRIVER_DESC);
|
||||
MODULE_AUTHOR (DRIVER_AUTHOR);
|
||||
MODULE_LICENSE ("GPL");
|
||||
|
||||
+#ifdef CONFIG_ARCH_GEMINI
|
||||
+#include "ehci-fotg2.c"
|
||||
+#define PLATFORM_DRIVER ehci_fotg2_driver
|
||||
+#endif
|
||||
+
|
||||
#ifdef CONFIG_USB_EHCI_FSL
|
||||
#include "ehci-fsl.c"
|
||||
#define PLATFORM_DRIVER ehci_fsl_driver
|
||||
--- a/drivers/usb/host/ehci-timer.c 2012-12-24 18:35:19.695560879 +0100
|
||||
+++ b/drivers/usb/host/ehci-timer.c 2012-12-24 18:39:39.813308000 +0100
|
||||
@@ -208,7 +208,9 @@
|
||||
|
||||
/* Clean up the mess */
|
||||
ehci->rh_state = EHCI_RH_HALTED;
|
||||
+#ifndef CONFIG_ARCH_GEMINI
|
||||
ehci_writel(ehci, 0, &ehci->regs->configured_flag);
|
||||
+#endif
|
||||
ehci_writel(ehci, 0, &ehci->regs->intr_enable);
|
||||
ehci_work(ehci);
|
||||
end_unlink_async(ehci);
|
||||
--- a/drivers/usb/host/ehci.h
|
||||
+++ b/drivers/usb/host/ehci.h
|
||||
@@ -656,7 +656,12 @@ static inline unsigned int
|
||||
ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
|
||||
{
|
||||
if (ehci_is_TDI(ehci)) {
|
||||
- switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
|
||||
+#ifdef CONFIG_ARCH_GEMINI
|
||||
+ portsc = readl(ehci_to_hcd(ehci)->regs + 0x80);
|
||||
+ switch ((portsc>>22)&3) {
|
||||
+#else
|
||||
+ switch ((portsc>>26)&3) {
|
||||
+#endif
|
||||
case 0:
|
||||
return 0;
|
||||
case 1:
|
||||
--- a/drivers/usb/host/ehci-hub.c
|
||||
+++ b/drivers/usb/host/ehci-hub.c
|
||||
@@ -1072,6 +1072,11 @@ static int ehci_hub_control (
|
||||
/* see what we found out */
|
||||
temp = check_reset_complete (ehci, wIndex, status_reg,
|
||||
ehci_readl(ehci, status_reg));
|
||||
+#ifdef CONFIG_ARCH_GEMINI
|
||||
+ /* restart schedule */
|
||||
+ ehci->command |= CMD_RUN;
|
||||
+ ehci_writel(ehci, ehci->command, &ehci->regs->command);
|
||||
+#endif
|
||||
}
|
||||
|
||||
/* transfer dedicated ports to the companion hc */
|
||||
--- a/include/linux/usb/ehci_def.h 2012-12-24 15:01:10.168320497 +0100
|
||||
+++ b/include/linux/usb/ehci_def.h 2012-12-24 15:11:43.335575000 +0100
|
||||
@@ -110,9 +110,14 @@
|
||||
u32 frame_list; /* points to periodic list */
|
||||
/* ASYNCLISTADDR: offset 0x18 */
|
||||
u32 async_next; /* address of next async queue head */
|
||||
-
|
||||
+#ifndef CONFIG_ARCH_GEMINI
|
||||
u32 reserved1[2];
|
||||
-
|
||||
+#else
|
||||
+ u32 reserved1;
|
||||
+ /* PORTSC: offset 0x20 for Faraday OTG */
|
||||
+ u32 port_status[1];
|
||||
+#endif
|
||||
+
|
||||
/* TXFILLTUNING: offset 0x24 */
|
||||
u32 txfill_tuning; /* TX FIFO Tuning register */
|
||||
#define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */
|
||||
@@ -123,8 +128,11 @@
|
||||
u32 configured_flag;
|
||||
#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
|
||||
|
||||
+#ifndef CONFIG_ARCH_GEMINI
|
||||
/* PORTSC: offset 0x44 */
|
||||
u32 port_status[0]; /* up to N_PORTS */
|
||||
+#endif
|
||||
+
|
||||
/* EHCI 1.1 addendum */
|
||||
#define PORTSC_SUSPEND_STS_ACK 0
|
||||
#define PORTSC_SUSPEND_STS_NYET 1
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
--- a/arch/arm/mach-gemini/board-wbd111.c
|
||||
+++ b/arch/arm/mach-gemini/board-wbd111.c
|
||||
@@ -145,6 +145,7 @@ static void __init wbd111_init(void)
|
||||
platform_register_watchdog();
|
||||
platform_device_register(&wbd111_phy_device);
|
||||
platform_register_ethernet(&gmac_data);
|
||||
+ platform_register_usb(0);
|
||||
}
|
||||
|
||||
MACHINE_START(WBD111, "Wiliboard WBD-111")
|
||||
--- a/arch/arm/mach-gemini/board-wbd222.c
|
||||
+++ b/arch/arm/mach-gemini/board-wbd222.c
|
||||
@@ -147,6 +147,7 @@ static void __init wbd222_init(void)
|
||||
platform_register_watchdog();
|
||||
platform_device_register(&wbd222_phy_device);
|
||||
platform_register_ethernet(&gmac_data);
|
||||
+ platform_register_usb(0);
|
||||
}
|
||||
|
||||
MACHINE_START(WBD222, "Wiliboard WBD-222")
|
||||
--- a/arch/arm/mach-gemini/board-rut1xx.c
|
||||
+++ b/arch/arm/mach-gemini/board-rut1xx.c
|
||||
@@ -105,6 +105,7 @@ static void __init rut1xx_init(void)
|
||||
platform_register_watchdog();
|
||||
platform_device_register(&rut1xx_phy_device);
|
||||
platform_register_ethernet(&gmac_data);
|
||||
+ platform_register_usb(0);
|
||||
}
|
||||
|
||||
MACHINE_START(RUT100, "Teltonika RUT100")
|
||||
--- a/arch/arm/mach-gemini/board-nas4220b.c
|
||||
+++ b/arch/arm/mach-gemini/board-nas4220b.c
|
||||
@@ -134,10 +134,23 @@
|
||||
GLOBAL_ARBITRATION1_CTRL));
|
||||
}
|
||||
|
||||
+static void __init usb_ib4220b_init(void)
|
||||
+{
|
||||
+ unsigned int val;
|
||||
+
|
||||
+ val = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
|
||||
+ GLOBAL_MISC_CTRL));
|
||||
+ val &= ~(USB0_PLUG_MINIB | USB1_PLUG_MINIB);
|
||||
+ val |= USB0_VBUS_ON | USB1_VBUS_ON;
|
||||
+ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
|
||||
+ GLOBAL_MISC_CTRL));
|
||||
+}
|
||||
+
|
||||
static void __init ib4220b_init(void)
|
||||
{
|
||||
gemini_gpio_init();
|
||||
ib4220b_gmac_init();
|
||||
+ usb_ib4220b_init();
|
||||
platform_register_uart();
|
||||
platform_register_pflash(SZ_16M, NULL, 0);
|
||||
platform_device_register(&ib4220b_led_device);
|
||||
@@ -146,6 +159,8 @@ static void __init ib4220b_init(void)
|
||||
platform_register_watchdog();
|
||||
platform_device_register(&ib4220b_phy_device);
|
||||
platform_register_ethernet(&ib4220b_gmac_data);
|
||||
+ platform_register_usb(0);
|
||||
+ platform_register_usb(1);
|
||||
}
|
||||
|
||||
MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
|
||||
|
|
@ -0,0 +1,389 @@
|
|||
--- a/arch/arm/Kconfig
|
||||
+++ b/arch/arm/Kconfig
|
||||
@@ -400,6 +400,7 @@ config ARCH_GEMINI
|
||||
select CLKSRC_MMIO
|
||||
select CPU_FA526
|
||||
select GENERIC_CLOCKEVENTS
|
||||
+ select MIGHT_HAVE_PCI
|
||||
help
|
||||
Support for the Cortina Systems Gemini family SoCs
|
||||
|
||||
--- a/arch/arm/mach-gemini/include/mach/hardware.h
|
||||
+++ b/arch/arm/mach-gemini/include/mach/hardware.h
|
||||
@@ -71,4 +71,9 @@
|
||||
*/
|
||||
#define IO_ADDRESS(x) IOMEM((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)
|
||||
|
||||
+/*
|
||||
+ * PCI subsystem macros
|
||||
+ */
|
||||
+#define pcibios_assign_all_busses() 1
|
||||
+
|
||||
#endif
|
||||
--- a/arch/arm/mach-gemini/include/mach/irqs.h
|
||||
+++ b/arch/arm/mach-gemini/include/mach/irqs.h
|
||||
@@ -43,11 +43,14 @@
|
||||
|
||||
#define NORMAL_IRQ_NUM 32
|
||||
|
||||
-#define GPIO_IRQ_BASE NORMAL_IRQ_NUM
|
||||
+#define PCI_IRQ_BASE NORMAL_IRQ_NUM
|
||||
+#define PCI_IRQ_NUM 4
|
||||
+
|
||||
+#define GPIO_IRQ_BASE (NORMAL_IRQ_NUM + PCI_IRQ_NUM)
|
||||
#define GPIO_IRQ_NUM (3 * 32)
|
||||
|
||||
#define ARCH_TIMER_IRQ IRQ_TIMER2
|
||||
|
||||
-#define NR_IRQS (NORMAL_IRQ_NUM + GPIO_IRQ_NUM)
|
||||
+#define NR_IRQS (NORMAL_IRQ_NUM + PCI_IRQ_NUM + GPIO_IRQ_NUM)
|
||||
|
||||
#endif /* __MACH_IRQS_H__ */
|
||||
--- a/arch/arm/mach-gemini/Makefile
|
||||
+++ b/arch/arm/mach-gemini/Makefile
|
||||
@@ -6,6 +6,8 @@
|
||||
|
||||
obj-y := irq.o mm.o time.o devices.o gpio.o idle.o reset.o
|
||||
|
||||
+obj-$(CONFIG_PCI) += pci.o
|
||||
+
|
||||
# Board-specific support
|
||||
obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o
|
||||
obj-$(CONFIG_MACH_RUT100) += board-rut1xx.o
|
||||
--- a/arch/arm/mach-gemini/mm.c
|
||||
+++ b/arch/arm/mach-gemini/mm.c
|
||||
@@ -59,6 +59,11 @@ static struct map_desc gemini_io_desc[]
|
||||
.length = SZ_512K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
+ .virtual = (unsigned long)IO_ADDRESS(GEMINI_PCI_IO_BASE),
|
||||
+ .pfn = __phys_to_pfn(GEMINI_PCI_IO_BASE),
|
||||
+ .length = SZ_512K,
|
||||
+ .type = MT_DEVICE,
|
||||
+ }, {
|
||||
.virtual = (unsigned long)IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
|
||||
.pfn = __phys_to_pfn(GEMINI_FLASH_CTRL_BASE),
|
||||
.length = SZ_512K,
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/mach-gemini/pci.c
|
||||
@@ -0,0 +1,320 @@
|
||||
+/*
|
||||
+ * Support for Gemini PCI Controller
|
||||
+ *
|
||||
+ * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
|
||||
+ * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
|
||||
+ *
|
||||
+ * based on SL2312 PCI controller code
|
||||
+ * Storlink (C) 2003
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License as published by
|
||||
+ * the Free Software Foundation; either version 2 of the License, or
|
||||
+ * (at your option) any later version.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/pci.h>
|
||||
+#include <linux/irq.h>
|
||||
+#include <linux/gpio.h>
|
||||
+
|
||||
+#include <asm/mach/pci.h>
|
||||
+
|
||||
+#include <mach/irqs.h>
|
||||
+#include <mach/hardware.h>
|
||||
+
|
||||
+#define GEMINI_PCI_IOSIZE_1M 0x0000
|
||||
+
|
||||
+#define GEMINI_PCI_PMC 0x40
|
||||
+#define GEMINI_PCI_PMCSR 0x44
|
||||
+#define GEMINI_PCI_CTRL1 0x48
|
||||
+#define GEMINI_PCI_CTRL2 0x4C
|
||||
+#define GEMINI_PCI_MEM1_BASE_SIZE 0x50
|
||||
+#define GEMINI_PCI_MEM2_BASE_SIZE 0x54
|
||||
+#define GEMINI_PCI_MEM3_BASE_SIZE 0x58
|
||||
+
|
||||
+#define PCI_CTRL2_INTSTS_OFFSET 28
|
||||
+#define PCI_CTRL2_INTMASK_OFFSET 22
|
||||
+
|
||||
+#define GEMINI_PCI_DMA_MASK 0xFFF00000
|
||||
+#define GEMINI_PCI_DMA_MEM1_BASE 0x00000000
|
||||
+#define GEMINI_PCI_DMA_MEM2_BASE 0x00000000
|
||||
+#define GEMINI_PCI_DMA_MEM3_BASE 0x00000000
|
||||
+#define GEMINI_PCI_DMA_MEM1_SIZE 7
|
||||
+#define GEMINI_PCI_DMA_MEM2_SIZE 6
|
||||
+#define GEMINI_PCI_DMA_MEM3_SIZE 6
|
||||
+
|
||||
+#define PCI_CONF_ENABLE (1 << 31)
|
||||
+#define PCI_CONF_WHERE(r) ((r) & 0xFC)
|
||||
+#define PCI_CONF_BUS(b) (((b) & 0xFF) << 16)
|
||||
+#define PCI_CONF_DEVICE(d) (((d) & 0x1F) << 11)
|
||||
+#define PCI_CONF_FUNCTION(f) (((f) & 0x07) << 8)
|
||||
+
|
||||
+#define PCI_IOSIZE_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE))
|
||||
+#define PCI_PROT_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x04)
|
||||
+#define PCI_CTRL_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x08)
|
||||
+#define PCI_SOFTRST_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x10)
|
||||
+#define PCI_CONFIG_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x28)
|
||||
+#define PCI_DATA_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x2C)
|
||||
+
|
||||
+
|
||||
+static DEFINE_SPINLOCK(gemini_pci_lock);
|
||||
+
|
||||
+static int gemini_pci_read_config(struct pci_bus* bus, unsigned int fn,
|
||||
+ int config, int size, u32* value)
|
||||
+{
|
||||
+ unsigned long irq_flags;
|
||||
+
|
||||
+ spin_lock_irqsave(&gemini_pci_lock, irq_flags);
|
||||
+
|
||||
+ __raw_writel(PCI_CONF_BUS(bus->number) |
|
||||
+ PCI_CONF_DEVICE(PCI_SLOT(fn)) |
|
||||
+ PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
|
||||
+ PCI_CONF_WHERE(config) |
|
||||
+ PCI_CONF_ENABLE,
|
||||
+ PCI_CONFIG_REG);
|
||||
+
|
||||
+ *value = __raw_readl(PCI_DATA_REG);
|
||||
+
|
||||
+ if (size == 1)
|
||||
+ *value = (*value >> (8 * (config & 3))) & 0xFF;
|
||||
+ else if (size == 2)
|
||||
+ *value = (*value >> (8 * (config & 3))) & 0xFFFF;
|
||||
+
|
||||
+ spin_unlock_irqrestore(&gemini_pci_lock, irq_flags);
|
||||
+
|
||||
+ dev_dbg(&bus->dev,
|
||||
+ "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
|
||||
+ PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
|
||||
+
|
||||
+ return PCIBIOS_SUCCESSFUL;
|
||||
+}
|
||||
+
|
||||
+static int gemini_pci_write_config(struct pci_bus* bus, unsigned int fn,
|
||||
+ int config, int size, u32 value)
|
||||
+{
|
||||
+ unsigned long irq_flags = 0;
|
||||
+ int ret = PCIBIOS_SUCCESSFUL;
|
||||
+
|
||||
+ dev_dbg(&bus->dev,
|
||||
+ "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
|
||||
+ PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
|
||||
+
|
||||
+ spin_lock_irqsave(&gemini_pci_lock, irq_flags);
|
||||
+
|
||||
+ __raw_writel(PCI_CONF_BUS(bus->number) |
|
||||
+ PCI_CONF_DEVICE(PCI_SLOT(fn)) |
|
||||
+ PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
|
||||
+ PCI_CONF_WHERE(config) |
|
||||
+ PCI_CONF_ENABLE,
|
||||
+ PCI_CONFIG_REG);
|
||||
+
|
||||
+ switch(size) {
|
||||
+ case 4:
|
||||
+ __raw_writel(value, PCI_DATA_REG);
|
||||
+ break;
|
||||
+ case 2:
|
||||
+ __raw_writew(value, PCI_DATA_REG + (config & 3));
|
||||
+ break;
|
||||
+ case 1:
|
||||
+ __raw_writeb(value, PCI_DATA_REG + (config & 3));
|
||||
+ break;
|
||||
+ default:
|
||||
+ ret = PCIBIOS_BAD_REGISTER_NUMBER;
|
||||
+ }
|
||||
+
|
||||
+ spin_unlock_irqrestore(&gemini_pci_lock, irq_flags);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static struct pci_ops gemini_pci_ops = {
|
||||
+ .read = gemini_pci_read_config,
|
||||
+ .write = gemini_pci_write_config,
|
||||
+};
|
||||
+
|
||||
+static struct resource gemini_pci_resource_io = {
|
||||
+ .name = "PCI I/O Space",
|
||||
+ .start = GEMINI_PCI_IO_BASE,
|
||||
+ .end = GEMINI_PCI_IO_BASE + SZ_1M - 1,
|
||||
+ .flags = IORESOURCE_IO,
|
||||
+};
|
||||
+
|
||||
+static struct resource gemini_pci_resource_mem = {
|
||||
+ .name = "PCI Memory Space",
|
||||
+ .start = GEMINI_PCI_MEM_BASE,
|
||||
+ .end = GEMINI_PCI_MEM_BASE + SZ_128M - 1,
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+};
|
||||
+
|
||||
+static int __init gemini_pci_request_resources(struct pci_sys_data *sys)
|
||||
+{
|
||||
+ if (request_resource(&ioport_resource, &gemini_pci_resource_io))
|
||||
+ goto bad_resources;
|
||||
+ if (request_resource(&iomem_resource, &gemini_pci_resource_mem))
|
||||
+ goto bad_resources;
|
||||
+
|
||||
+ pci_add_resource(&sys->resources, &gemini_pci_resource_io);
|
||||
+ pci_add_resource(&sys->resources, &gemini_pci_resource_mem);
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+bad_resources:
|
||||
+ pr_err("Gemini PCI: request_resource() failed. "
|
||||
+ "Abort PCI bus enumeration.\n");
|
||||
+ return -1;
|
||||
+}
|
||||
+
|
||||
+static int __init gemini_pci_setup(int nr, struct pci_sys_data *sys)
|
||||
+{
|
||||
+ unsigned int cmd;
|
||||
+
|
||||
+ pcibios_min_io = 0x100;
|
||||
+ pcibios_min_mem = 0;
|
||||
+
|
||||
+ if ((nr > 0) || gemini_pci_request_resources(sys))
|
||||
+ return 0;
|
||||
+
|
||||
+ /* setup I/O space to 1MB size */
|
||||
+ __raw_writel(GEMINI_PCI_IOSIZE_1M, PCI_IOSIZE_REG);
|
||||
+
|
||||
+ /* setup hostbridge */
|
||||
+ cmd = __raw_readl(PCI_CTRL_REG);
|
||||
+ cmd |= PCI_COMMAND_IO;
|
||||
+ cmd |= PCI_COMMAND_MEMORY;
|
||||
+ cmd |= PCI_COMMAND_MASTER;
|
||||
+ __raw_writel(cmd, PCI_CTRL_REG);
|
||||
+
|
||||
+ return 1;
|
||||
+}
|
||||
+
|
||||
+static struct pci_bus* __init gemini_pci_scan_bus(int nr, struct pci_sys_data* sys)
|
||||
+{
|
||||
+ unsigned int reg = 0;
|
||||
+ struct pci_bus* bus = 0;
|
||||
+
|
||||
+ bus = pci_scan_bus(nr, &gemini_pci_ops, sys);
|
||||
+ if (bus) {
|
||||
+ dev_dbg(&bus->dev, "setting up PCI DMA\n");
|
||||
+ reg = (GEMINI_PCI_DMA_MEM1_BASE & GEMINI_PCI_DMA_MASK)
|
||||
+ | (GEMINI_PCI_DMA_MEM1_SIZE << 16);
|
||||
+ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM1_BASE_SIZE, 4, reg);
|
||||
+ reg = (GEMINI_PCI_DMA_MEM2_BASE & GEMINI_PCI_DMA_MASK)
|
||||
+ | (GEMINI_PCI_DMA_MEM2_SIZE << 16);
|
||||
+ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM2_BASE_SIZE, 4, reg);
|
||||
+ reg = (GEMINI_PCI_DMA_MEM3_BASE & GEMINI_PCI_DMA_MASK)
|
||||
+ | (GEMINI_PCI_DMA_MEM3_SIZE << 16);
|
||||
+ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM3_BASE_SIZE, 4, reg);
|
||||
+ }
|
||||
+
|
||||
+ return bus;
|
||||
+}
|
||||
+
|
||||
+/* Should work with all boards based on original Storlink EVB */
|
||||
+static int __init gemini_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
+{
|
||||
+ if (slot < 9 || slot > 12)
|
||||
+ return -1;
|
||||
+
|
||||
+ return PCI_IRQ_BASE + (((slot - 9) + (pin - 1)) & 0x3);
|
||||
+}
|
||||
+
|
||||
+static struct hw_pci gemini_hw_pci __initdata = {
|
||||
+ .nr_controllers = 1,
|
||||
+ .setup = gemini_pci_setup,
|
||||
+ .scan = gemini_pci_scan_bus,
|
||||
+ .map_irq = gemini_pci_map_irq,
|
||||
+};
|
||||
+
|
||||
+/* we need this for muxed PCI interrupts handling */
|
||||
+static struct pci_bus bogus_pci_bus;
|
||||
+
|
||||
+static void gemini_pci_ack_irq(struct irq_data *d)
|
||||
+{
|
||||
+ unsigned int irq = d->irq;
|
||||
+ unsigned int reg;
|
||||
+
|
||||
+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®);
|
||||
+ reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET);
|
||||
+ reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTSTS_OFFSET);
|
||||
+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
|
||||
+}
|
||||
+
|
||||
+static void gemini_pci_mask_irq(struct irq_data *d)
|
||||
+{
|
||||
+ unsigned int irq = d->irq;
|
||||
+ unsigned int reg;
|
||||
+
|
||||
+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®);
|
||||
+ reg &= ~((0xF << PCI_CTRL2_INTSTS_OFFSET)
|
||||
+ | (1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET)));
|
||||
+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
|
||||
+}
|
||||
+
|
||||
+static void gemini_pci_unmask_irq(struct irq_data *d)
|
||||
+{
|
||||
+ unsigned int irq = d->irq;
|
||||
+ unsigned int reg;
|
||||
+
|
||||
+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®);
|
||||
+ reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET);
|
||||
+ reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET);
|
||||
+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
|
||||
+}
|
||||
+
|
||||
+static void gemini_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
+{
|
||||
+ unsigned int pci_irq_no, irq_stat, reg, i;
|
||||
+
|
||||
+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®);
|
||||
+ irq_stat = reg >> PCI_CTRL2_INTSTS_OFFSET;
|
||||
+
|
||||
+ for (i = 0; i < 4; i++) {
|
||||
+
|
||||
+ if ((irq_stat & (1 << i)) == 0)
|
||||
+ continue;
|
||||
+
|
||||
+ pci_irq_no = PCI_IRQ_BASE + i;
|
||||
+
|
||||
+ BUG_ON(!(irq_desc[pci_irq_no].handle_irq));
|
||||
+ irq_desc[pci_irq_no].handle_irq(pci_irq_no,
|
||||
+ &irq_desc[pci_irq_no]);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static struct irq_chip gemini_pci_irq_chip = {
|
||||
+ .name = "PCI",
|
||||
+ .irq_ack = gemini_pci_ack_irq,
|
||||
+ .irq_mask = gemini_pci_mask_irq,
|
||||
+ .irq_unmask = gemini_pci_unmask_irq,
|
||||
+};
|
||||
+
|
||||
+static int __init gemini_pci_init(void)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = 72; i <= 95; i++)
|
||||
+ gpio_request(i, "PCI");
|
||||
+
|
||||
+ /* initialize our bogus bus */
|
||||
+ dev_set_name(&bogus_pci_bus.dev, "PCI IRQ handler");
|
||||
+ bogus_pci_bus.number = 0;
|
||||
+
|
||||
+ /* mask and clear all interrupts */
|
||||
+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2 + 2, 2,
|
||||
+ 0xF000);
|
||||
+
|
||||
+ for (i = PCI_IRQ_BASE; i < PCI_IRQ_BASE + 4; i++) {
|
||||
+ irq_set_chip_and_handler(i, &gemini_pci_irq_chip,
|
||||
+ handle_level_irq);
|
||||
+ set_irq_flags(i, IRQF_VALID);
|
||||
+ }
|
||||
+
|
||||
+ irq_set_chained_handler(IRQ_PCI, gemini_pci_irq_handler);
|
||||
+
|
||||
+ pci_common_init(&gemini_hw_pci);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+subsys_initcall(gemini_pci_init);
|
||||
|
|
@ -0,0 +1,192 @@
|
|||
--- a/arch/arm/mach-gemini/include/mach/global_reg.h
|
||||
+++ b/arch/arm/mach-gemini/include/mach/global_reg.h
|
||||
@@ -227,7 +227,13 @@
|
||||
#define USB0_PLUG_MINIB (1 << 29)
|
||||
#define GMAC_GMII (1 << 28)
|
||||
#define GMAC_1_ENABLE (1 << 27)
|
||||
-/* TODO: define ATA/SATA bits */
|
||||
+/* 011 - ata0 <-> sata0, sata1; bring out ata1
|
||||
+ * 010 - ata1 <-> sata1, sata0; bring out ata0
|
||||
+ * 001 - ata0 <-> sata0, ata1 <-> sata1; bring out ata1
|
||||
+ * 000 - ata0 <-> sata0, ata1 <-> sata1; bring out ata0 */
|
||||
+#define IDE_IOMUX_MASK (7 << 24)
|
||||
+#define IDE_IOMUX_SATA1_SATA0 (2 << 24)
|
||||
+#define IDE_IOMUX_SATA0_SATA1 (3 << 24)
|
||||
#define USB1_VBUS_ON (1 << 23)
|
||||
#define USB0_VBUS_ON (1 << 22)
|
||||
#define APB_CLKOUT_ENABLE (1 << 21)
|
||||
--- a/arch/arm/mach-gemini/irq.c 2013-02-19 13:38:13.263948000 +0100
|
||||
+++ b/arch/arm/mach-gemini/irq.c 2013-02-19 18:24:02.912997292 +0100
|
||||
@@ -89,6 +89,9 @@
|
||||
irq_set_handler(i, handle_edge_irq);
|
||||
mode |= 1 << i;
|
||||
level |= 1 << i;
|
||||
+ } else if (i >= IRQ_IDE0 && i <= IRQ_IDE1) {
|
||||
+ irq_set_handler(i, handle_edge_irq);
|
||||
+ mode |= 1 << i;
|
||||
} else {
|
||||
irq_set_handler(i, handle_level_irq);
|
||||
}
|
||||
--- a/arch/arm/mach-gemini/common.h
|
||||
+++ b/arch/arm/mach-gemini/common.h
|
||||
@@ -29,6 +29,7 @@
|
||||
extern int platform_register_watchdog(void);
|
||||
extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata);
|
||||
extern int platform_register_usb(unsigned int id);
|
||||
+extern int platform_register_pata(unsigned int id);
|
||||
|
||||
extern void gemini_restart(enum reboot_mode mode, const char *cmd);
|
||||
|
||||
--- a/arch/arm/mach-gemini/devices.c
|
||||
+++ b/arch/arm/mach-gemini/devices.c
|
||||
@@ -249,3 +249,67 @@
|
||||
return platform_device_register(&usb_device[id]);
|
||||
}
|
||||
|
||||
+static u64 pata_gemini_dmamask0 = 0xffffffffUL;
|
||||
+static u64 pata_gemini_dmamask1 = 0xffffffffUL;
|
||||
+
|
||||
+static struct resource pata_gemini_resources0[] =
|
||||
+{
|
||||
+ [0] = {
|
||||
+ .start = GEMINI_IDE0_BASE,
|
||||
+ .end = GEMINI_IDE0_BASE + 0x40,
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+ },
|
||||
+ [1] = {
|
||||
+ .start = IRQ_IDE0,
|
||||
+ .end = IRQ_IDE0,
|
||||
+ .flags = IORESOURCE_IRQ,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static struct resource pata_gemini_resources1[] =
|
||||
+{
|
||||
+ [0] = {
|
||||
+ .start = GEMINI_IDE1_BASE,
|
||||
+ .end = GEMINI_IDE1_BASE + 0x40,
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+ },
|
||||
+ [1] = {
|
||||
+ .start = IRQ_IDE1,
|
||||
+ .end = IRQ_IDE1,
|
||||
+ .flags = IORESOURCE_IRQ,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static struct platform_device pata_gemini_devices[] =
|
||||
+{
|
||||
+ {
|
||||
+ .name = "pata-gemini",
|
||||
+ .id = 0,
|
||||
+ .dev =
|
||||
+ {
|
||||
+ .dma_mask = &pata_gemini_dmamask0,
|
||||
+ .coherent_dma_mask = 0xffffffff,
|
||||
+ },
|
||||
+ .num_resources = ARRAY_SIZE(pata_gemini_resources0),
|
||||
+ .resource = pata_gemini_resources0,
|
||||
+ },
|
||||
+ {
|
||||
+ .name = "pata-gemini",
|
||||
+ .id = 1,
|
||||
+ .dev =
|
||||
+ {
|
||||
+ .dma_mask = &pata_gemini_dmamask1,
|
||||
+ .coherent_dma_mask = 0xffffffff,
|
||||
+ },
|
||||
+ .num_resources = ARRAY_SIZE(pata_gemini_resources1),
|
||||
+ .resource = pata_gemini_resources1,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+int __init platform_register_pata(unsigned int id)
|
||||
+{
|
||||
+ if (id > 1)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ return platform_device_register(&pata_gemini_devices[id]);
|
||||
+}
|
||||
--- a/arch/arm/mach-gemini/mm.c
|
||||
+++ b/arch/arm/mach-gemini/mm.c
|
||||
@@ -24,6 +24,11 @@
|
||||
.length = SZ_512K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
+ .virtual = (unsigned long)IO_ADDRESS(GEMINI_SATA_BASE),
|
||||
+ .pfn = __phys_to_pfn(GEMINI_SATA_BASE),
|
||||
+ .length = SZ_512K,
|
||||
+ .type = MT_DEVICE,
|
||||
+ }, {
|
||||
.virtual = (unsigned long)IO_ADDRESS(GEMINI_UART_BASE),
|
||||
.pfn = __phys_to_pfn(GEMINI_UART_BASE),
|
||||
.length = SZ_512K,
|
||||
--- a/drivers/ata/Kconfig
|
||||
+++ b/drivers/ata/Kconfig
|
||||
@@ -536,6 +536,16 @@ config PATA_EFAR
|
||||
|
||||
If unsure, say N.
|
||||
|
||||
+config PATA_GEMINI
|
||||
+ tristate "Gemini PATA support (Experimental)"
|
||||
+ depends on ARCH_GEMINI
|
||||
+ help
|
||||
+ This option enables support for the Gemini PATA-Controller.
|
||||
+ Note that the Gemini SoC has no native SATA-Controller but an
|
||||
+ onboard PATA-SATA bridge.
|
||||
+
|
||||
+ If unsure, say N.
|
||||
+
|
||||
config PATA_HPT366
|
||||
tristate "HPT 366/368 PATA support"
|
||||
depends on PCI
|
||||
--- a/drivers/ata/Makefile
|
||||
+++ b/drivers/ata/Makefile
|
||||
@@ -53,6 +53,7 @@
|
||||
obj-$(CONFIG_PATA_CYPRESS) += pata_cypress.o
|
||||
obj-$(CONFIG_PATA_EFAR) += pata_efar.o
|
||||
obj-$(CONFIG_PATA_EP93XX) += pata_ep93xx.o
|
||||
+obj-$(CONFIG_PATA_GEMINI) += pata_gemini.o
|
||||
obj-$(CONFIG_PATA_HPT366) += pata_hpt366.o
|
||||
obj-$(CONFIG_PATA_HPT37X) += pata_hpt37x.o
|
||||
obj-$(CONFIG_PATA_HPT3X2N) += pata_hpt3x2n.o
|
||||
--- a/arch/arm/mach-gemini/board-nas4220b.c
|
||||
+++ b/arch/arm/mach-gemini/board-nas4220b.c
|
||||
@@ -146,11 +146,28 @@
|
||||
GLOBAL_MISC_CTRL));
|
||||
}
|
||||
|
||||
+static void __init sata_ib4220b_init(void)
|
||||
+{
|
||||
+ unsigned val;
|
||||
+
|
||||
+ val = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
|
||||
+ GLOBAL_MISC_CTRL));
|
||||
+ val &= ~(IDE_IOMUX_MASK | PFLASH_PADS_DISABLE);
|
||||
+ val |= IDE_PADS_ENABLE;
|
||||
+ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
|
||||
+ GLOBAL_MISC_CTRL));
|
||||
+
|
||||
+ /* enabling ports for presence detection, master only */
|
||||
+ writel(0x00000001, (void __iomem*)(IO_ADDRESS(GEMINI_SATA_BASE) + 0x18));
|
||||
+ writel(0x00000001, (void __iomem*)(IO_ADDRESS(GEMINI_SATA_BASE) + 0x1c));
|
||||
+}
|
||||
+
|
||||
static void __init ib4220b_init(void)
|
||||
{
|
||||
gemini_gpio_init();
|
||||
ib4220b_gmac_init();
|
||||
usb_ib4220b_init();
|
||||
+ sata_ib4220b_init();
|
||||
platform_register_uart();
|
||||
platform_register_pflash(SZ_16M, NULL, 0);
|
||||
platform_device_register(&ib4220b_led_device);
|
||||
@@ -161,6 +178,8 @@
|
||||
platform_register_ethernet(&ib4220b_gmac_data);
|
||||
platform_register_usb(0);
|
||||
platform_register_usb(1);
|
||||
+ platform_register_pata(0);
|
||||
+ platform_register_pata(1);
|
||||
}
|
||||
|
||||
MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
--- a/arch/arm/mach-gemini/time.c 2015-03-25 23:06:03.188317455 +0200
|
||||
+++ b/arch/arm/mach-gemini/time.c 2015-03-25 23:06:24.417315486 +0200
|
||||
@@ -15,15 +15,18 @@
|
||||
#include <asm/mach/time.h>
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/clocksource.h>
|
||||
+#include <linux/sched_clock.h>
|
||||
|
||||
/*
|
||||
* Register definitions for the timers
|
||||
*/
|
||||
-#define TIMER_COUNT(BASE_ADDR) (BASE_ADDR + 0x00)
|
||||
-#define TIMER_LOAD(BASE_ADDR) (BASE_ADDR + 0x04)
|
||||
-#define TIMER_MATCH1(BASE_ADDR) (BASE_ADDR + 0x08)
|
||||
-#define TIMER_MATCH2(BASE_ADDR) (BASE_ADDR + 0x0C)
|
||||
-#define TIMER_CR(BASE_ADDR) (BASE_ADDR + 0x30)
|
||||
+#define TIMER_COUNT(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x00)
|
||||
+#define TIMER_LOAD(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x04)
|
||||
+#define TIMER_MATCH1(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x08)
|
||||
+#define TIMER_MATCH2(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x0C)
|
||||
+#define TIMER_CR(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x30)
|
||||
+#define TIMER_INTR_STATE(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x34)
|
||||
+#define TIMER_INTR_MASK(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x38)
|
||||
|
||||
#define TIMER_1_CR_ENABLE (1 << 0)
|
||||
#define TIMER_1_CR_CLOCK (1 << 1)
|
||||
@@ -34,27 +37,38 @@
|
||||
#define TIMER_3_CR_ENABLE (1 << 6)
|
||||
#define TIMER_3_CR_CLOCK (1 << 7)
|
||||
#define TIMER_3_CR_INT (1 << 8)
|
||||
+#define TIMER_1_CR_UPDOWN (1 << 9)
|
||||
+#define TIMER_2_CR_UPDOWN (1 << 10)
|
||||
+#define TIMER_3_CR_UPDOWN (1 << 11)
|
||||
+
|
||||
+#define TIMER_1_INT_MATCH1 (1 << 0)
|
||||
+#define TIMER_1_INT_MATCH2 (1 << 1)
|
||||
+#define TIMER_1_INT_OVERFLOW (1 << 2)
|
||||
+#define TIMER_2_INT_MATCH1 (1 << 3)
|
||||
+#define TIMER_2_INT_MATCH2 (1 << 4)
|
||||
+#define TIMER_2_INT_OVERFLOW (1 << 5)
|
||||
+#define TIMER_3_INT_MATCH1 (1 << 6)
|
||||
+#define TIMER_3_INT_MATCH2 (1 << 7)
|
||||
+#define TIMER_3_INT_OVERFLOW (1 << 8)
|
||||
+#define TIMER_INT_ALL_MASK 0x1ff
|
||||
|
||||
static unsigned int tick_rate;
|
||||
|
||||
+static u64 notrace gemini_read_sched_clock(void)
|
||||
+{
|
||||
+ return readl(TIMER_COUNT(GEMINI_TIMER3_BASE));
|
||||
+}
|
||||
+
|
||||
static int gemini_timer_set_next_event(unsigned long cycles,
|
||||
struct clock_event_device *evt)
|
||||
{
|
||||
u32 cr;
|
||||
|
||||
- cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
|
||||
-
|
||||
- /* This may be overdoing it, feel free to test without this */
|
||||
- cr &= ~TIMER_2_CR_ENABLE;
|
||||
- cr &= ~TIMER_2_CR_INT;
|
||||
- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
|
||||
-
|
||||
- /* Set next event */
|
||||
- writel(cycles, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE)));
|
||||
- writel(cycles, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE)));
|
||||
- cr |= TIMER_2_CR_ENABLE;
|
||||
- cr |= TIMER_2_CR_INT;
|
||||
- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
|
||||
+ /* Setup the match register */
|
||||
+ cr = readl(TIMER_COUNT(GEMINI_TIMER1_BASE));
|
||||
+ writel(cr + cycles, TIMER_MATCH1(GEMINI_TIMER1_BASE));
|
||||
+ if (readl(TIMER_COUNT(GEMINI_TIMER1_BASE)) - cr > cycles)
|
||||
+ return -ETIME;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -66,48 +80,68 @@
|
||||
u32 cr;
|
||||
|
||||
switch (mode) {
|
||||
- case CLOCK_EVT_MODE_PERIODIC:
|
||||
- /* Start the timer */
|
||||
- writel(period,
|
||||
- TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE)));
|
||||
- writel(period,
|
||||
- TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE)));
|
||||
- cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
|
||||
- cr |= TIMER_2_CR_ENABLE;
|
||||
- cr |= TIMER_2_CR_INT;
|
||||
- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
|
||||
+ case CLOCK_EVT_MODE_PERIODIC:
|
||||
+ /* Stop timer and interrupt. */
|
||||
+ cr = readl(TIMER_CR(GEMINI_TIMER_BASE));
|
||||
+ cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
|
||||
+ writel(cr, TIMER_CR(GEMINI_TIMER_BASE));
|
||||
+
|
||||
+ /* Setup timer to fire at 1/HZ intervals. */
|
||||
+ cr = 0xffffffff - (period - 1);
|
||||
+ writel(cr, TIMER_COUNT(GEMINI_TIMER1_BASE));
|
||||
+ writel(cr, TIMER_LOAD(GEMINI_TIMER1_BASE));
|
||||
+
|
||||
+ /* enable interrupt on overflaw */
|
||||
+ cr = readl(TIMER_INTR_MASK(GEMINI_TIMER_BASE));
|
||||
+ cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
|
||||
+ cr |= TIMER_1_INT_OVERFLOW;
|
||||
+ writel(cr, TIMER_INTR_MASK(GEMINI_TIMER_BASE));
|
||||
+
|
||||
+ /* start the timer */
|
||||
+ cr = readl(TIMER_CR(GEMINI_TIMER_BASE));
|
||||
+ cr |= TIMER_1_CR_ENABLE | TIMER_1_CR_INT;
|
||||
+ writel(cr, TIMER_CR(GEMINI_TIMER_BASE));
|
||||
break;
|
||||
+
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
case CLOCK_EVT_MODE_UNUSED:
|
||||
- case CLOCK_EVT_MODE_SHUTDOWN:
|
||||
+ case CLOCK_EVT_MODE_SHUTDOWN:
|
||||
+ /* Stop timer and interrupt. */
|
||||
+ cr = readl(TIMER_CR(GEMINI_TIMER_BASE));
|
||||
+ cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
|
||||
+ writel(cr, TIMER_CR(GEMINI_TIMER_BASE));
|
||||
+
|
||||
+ /* Setup counter start from 0 */
|
||||
+ writel(0, TIMER_COUNT(GEMINI_TIMER1_BASE));
|
||||
+ writel(0, TIMER_LOAD(GEMINI_TIMER1_BASE));
|
||||
+
|
||||
+ /* enable interrupt */
|
||||
+ cr = readl(TIMER_INTR_MASK(GEMINI_TIMER_BASE));
|
||||
+ cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
|
||||
+ cr |= TIMER_1_INT_MATCH1;
|
||||
+ writel(cr, TIMER_INTR_MASK(GEMINI_TIMER_BASE));
|
||||
+
|
||||
+ /* start the timer */
|
||||
+ cr = readl(TIMER_CR(GEMINI_TIMER_BASE));
|
||||
+ cr |= TIMER_1_CR_ENABLE;
|
||||
+ writel(cr, TIMER_CR(GEMINI_TIMER_BASE));
|
||||
+ break;
|
||||
+
|
||||
case CLOCK_EVT_MODE_RESUME:
|
||||
- /*
|
||||
- * Disable also for oneshot: the set_next() call will
|
||||
- * arm the timer instead.
|
||||
- */
|
||||
- cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
|
||||
- cr &= ~TIMER_2_CR_ENABLE;
|
||||
- cr &= ~TIMER_2_CR_INT;
|
||||
- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
|
||||
break;
|
||||
- default:
|
||||
- break;
|
||||
}
|
||||
}
|
||||
|
||||
-/* Use TIMER2 as clock event */
|
||||
static struct clock_event_device gemini_clockevent = {
|
||||
- .name = "TIMER2",
|
||||
- .rating = 300, /* Reasonably fast and accurate clock event */
|
||||
- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
|
||||
- .set_next_event = gemini_timer_set_next_event,
|
||||
- .set_mode = gemini_timer_set_mode,
|
||||
+ .name = "gemini_timer_1",
|
||||
+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
|
||||
+ .shift = 32,
|
||||
+ .rating = 300,
|
||||
+ .set_next_event = gemini_timer_set_next_event,
|
||||
+ .set_mode = gemini_timer_set_mode,
|
||||
};
|
||||
|
||||
-/*
|
||||
- * IRQ handler for the timer
|
||||
- */
|
||||
-static irqreturn_t gemini_timer_interrupt(int irq, void *dev_id)
|
||||
+static irqreturn_t gemini_timer_intr(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *evt = &gemini_clockevent;
|
||||
|
||||
@@ -116,14 +150,11 @@
|
||||
}
|
||||
|
||||
static struct irqaction gemini_timer_irq = {
|
||||
- .name = "Gemini Timer Tick",
|
||||
- .flags = IRQF_TIMER,
|
||||
- .handler = gemini_timer_interrupt,
|
||||
+ .name = "gemini timer 1",
|
||||
+ .flags = IRQF_DISABLED | IRQF_TIMER,
|
||||
+ .handler = gemini_timer_intr,
|
||||
};
|
||||
|
||||
-/*
|
||||
- * Set up timer interrupt, and return the current time in seconds.
|
||||
- */
|
||||
void __init gemini_timer_init(void)
|
||||
{
|
||||
u32 reg_v;
|
||||
@@ -151,20 +182,35 @@
|
||||
}
|
||||
|
||||
/*
|
||||
- * Make irqs happen for the system timer
|
||||
+ * Reset the interrupt mask and status
|
||||
*/
|
||||
- setup_irq(IRQ_TIMER2, &gemini_timer_irq);
|
||||
+ writel(TIMER_INT_ALL_MASK, TIMER_INTR_MASK(GEMINI_TIMER_BASE));
|
||||
+ writel(0, TIMER_INTR_STATE(GEMINI_TIMER_BASE));
|
||||
+ writel(TIMER_1_CR_UPDOWN | TIMER_3_CR_ENABLE | TIMER_3_CR_UPDOWN,
|
||||
+ TIMER_CR(GEMINI_TIMER_BASE));
|
||||
|
||||
- /* Enable and use TIMER1 as clock source */
|
||||
- writel(0xffffffff, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)));
|
||||
- writel(0xffffffff, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER1_BASE)));
|
||||
- writel(TIMER_1_CR_ENABLE, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
|
||||
- if (clocksource_mmio_init(TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)),
|
||||
- "TIMER1", tick_rate, 300, 32,
|
||||
- clocksource_mmio_readl_up))
|
||||
- pr_err("timer: failed to initialize gemini clock source\n");
|
||||
+ /*
|
||||
+ * Setup free-running clocksource timer (interrupts
|
||||
+ * disabled.)
|
||||
+ */
|
||||
+ writel(0, TIMER_COUNT(GEMINI_TIMER3_BASE));
|
||||
+ writel(0, TIMER_LOAD(GEMINI_TIMER3_BASE));
|
||||
+ writel(0, TIMER_MATCH1(GEMINI_TIMER3_BASE));
|
||||
+ writel(0, TIMER_MATCH2(GEMINI_TIMER3_BASE));
|
||||
+ clocksource_mmio_init(TIMER_COUNT(GEMINI_TIMER3_BASE),
|
||||
+ "gemini_clocksource", tick_rate,
|
||||
+ 300, 32, clocksource_mmio_readl_up);
|
||||
+ sched_clock_register(gemini_read_sched_clock, 32, tick_rate);
|
||||
|
||||
- /* Configure and register the clockevent */
|
||||
+ /*
|
||||
+ * Setup clockevent timer (interrupt-driven.)
|
||||
+ */
|
||||
+ writel(0, TIMER_COUNT(GEMINI_TIMER1_BASE));
|
||||
+ writel(0, TIMER_LOAD(GEMINI_TIMER1_BASE));
|
||||
+ writel(0, TIMER_MATCH1(GEMINI_TIMER1_BASE));
|
||||
+ writel(0, TIMER_MATCH2(GEMINI_TIMER1_BASE));
|
||||
+ setup_irq(IRQ_TIMER1, &gemini_timer_irq);
|
||||
+ gemini_clockevent.cpumask = cpumask_of(0);
|
||||
clockevents_config_and_register(&gemini_clockevent, tick_rate,
|
||||
1, 0xffffffff);
|
||||
}
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
CONFIG_CMDLINE="rootfstype=squashfs,jffs2 noinitrd console=ttyS0,19200 mem=128M mtdparts=physmap-flash.0:128k(BOOT),3072k(Kern),6144k(Ramdisk),6144k(Application),128k(VCTL),640k(CurConf),128k(FIS-directory),12288k@0x320000(rootfs),15360k@0x20000(firmware) root=/dev/mtdblock7"
|
||||
CONFIG_MACH_NAS4220B=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_REDBOOT_PARTS is not set
|
||||
CONFIG_MTD_SPLIT_FIRMWARE=y
|
||||
Loading…
Reference in New Issue