mirror of https://github.com/hak5/openwrt-owl.git
mvebu: add Armada 385 DB AP support
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Imre Kaloz <kaloz@openwrt.org> SVN-Revision: 44266owl
Imre Kaloz
parent
3019f7ecbd
commit
9be491f084
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@ -128,6 +128,7 @@ endef
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# Boards with NAND, without subpages
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$(eval $(call NANDProfile,370-DB,armada-370-db,512KiB,4096))
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$(eval $(call NANDProfile,370-RD,armada-370-rd,512KiB,4096))
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$(eval $(call NANDProfile,385-DB-AP,armada-385-db-ap,256KiB,4096))
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$(eval $(call NANDProfile,Mirabox,armada-370-mirabox,512KiB,4096))
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$(eval $(call NANDProfile,XP-DB,armada-xp-db,512KiB,4096))
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$(eval $(call NANDProfile,XP-GP,armada-xp-gp,512KiB,4096))
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@ -0,0 +1,97 @@
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From 11aa9df4de06cc257327d783c5cb615989e87286 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime.ripard@free-electrons.com>
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Date: Fri, 23 Jan 2015 15:18:27 +0100
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Subject: [PATCH v2 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining
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The NDDB register holds the data that are needed by the read and write
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commands.
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However, during a read PIO access, the datasheet specifies that after each 32
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bits read in that register, when BCH is enabled, we have to make sure that the
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RDDREQ bit is set in the NDSR register.
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This fixes an issue that was seen on the Armada 385, and presumably other mvebu
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SoCs, when a read on a newly erased page would end up in the driver reporting a
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timeout from the NAND.
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Cc: <stable@vger.kernel.org> # v3.14
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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drivers/mtd/nand/pxa3xx_nand.c | 45 ++++++++++++++++++++++++++++++++++++------
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1 file changed, 39 insertions(+), 6 deletions(-)
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diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
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index 96b0b1d27df1..e6918befb951 100644
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--- a/drivers/mtd/nand/pxa3xx_nand.c
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+++ b/drivers/mtd/nand/pxa3xx_nand.c
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@@ -23,6 +23,7 @@
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#include <linux/mtd/partitions.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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+#include <linux/jiffies.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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@@ -480,6 +481,38 @@ static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
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nand_writel(info, NDCR, ndcr | int_mask);
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}
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+static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
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+{
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+ u32 *dst = (u32 *)data;
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+
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+ if (info->ecc_bch) {
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+ while (len--) {
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+ u32 timeout;
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+
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+ *dst++ = nand_readl(info, NDDB);
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+
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+ /*
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+ * According to the datasheet, when reading
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+ * from NDDB with BCH enabled, after each 32
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+ * bits reads, we have to make sure that the
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+ * NDSR.RDDREQ bit is set
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+ */
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+ timeout = jiffies + msecs_to_jiffies(5);
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+ while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) {
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+ if (!time_before(jiffies, timeout)) {
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+ dev_err(&info->pdev->dev,
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+ "Timeout on RDDREQ while draining the FIFO\n");
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+ return;
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+ }
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+
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+ cpu_relax();
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+ }
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+ }
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+ } else {
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+ __raw_readsl(info->mmio_base + NDDB, data, len);
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+ }
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+}
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+
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static void handle_data_pio(struct pxa3xx_nand_info *info)
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{
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unsigned int do_bytes = min(info->data_size, info->chunk_size);
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@@ -496,14 +529,14 @@ static void handle_data_pio(struct pxa3xx_nand_info *info)
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DIV_ROUND_UP(info->oob_size, 4));
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break;
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case STATE_PIO_READING:
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- __raw_readsl(info->mmio_base + NDDB,
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- info->data_buff + info->data_buff_pos,
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- DIV_ROUND_UP(do_bytes, 4));
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+ drain_fifo(info,
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+ info->data_buff + info->data_buff_pos,
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+ DIV_ROUND_UP(do_bytes, 4));
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if (info->oob_size > 0)
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- __raw_readsl(info->mmio_base + NDDB,
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- info->oob_buff + info->oob_buff_pos,
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- DIV_ROUND_UP(info->oob_size, 4));
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+ drain_fifo(info,
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+ info->oob_buff + info->oob_buff_pos,
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+ DIV_ROUND_UP(info->oob_size, 4));
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break;
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default:
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dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
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--
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2.2.2
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@ -0,0 +1,70 @@
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From 91b4c91f919abffa72cbf7545a944252f8e4f775 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime.ripard@free-electrons.com>
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Date: Thu, 8 Jan 2015 18:38:08 +0100
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Subject: [PATCH 3/4] ARM: mvebu: Add a number of pinctrl functions
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Some pinctrl functions can be shared with all DTS out there, since they are
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generic, SoC-wide muxing options. Add a number of these to the DTSI to avoid
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duplication.
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Signed-off-by: Andrew Lunn <andrew@lunn.ch>
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---
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arch/arm/boot/dts/armada-38x.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
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1 file changed, 39 insertions(+)
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diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
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index 40200084c6c8..98885c58be29 100644
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--- a/arch/arm/boot/dts/armada-38x.dtsi
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+++ b/arch/arm/boot/dts/armada-38x.dtsi
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@@ -195,6 +195,45 @@
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pinctrl@18000 {
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reg = <0x18000 0x20>;
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+
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+ ge0_rgmii_pins: ge-rgmii-pins-0 {
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+ marvell,pins = "mpp6", "mpp7", "mpp8",
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+ "mpp9", "mpp10", "mpp11",
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+ "mpp12", "mpp13", "mpp14",
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+ "mpp15", "mpp16", "mpp17";
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+ marvell,function = "ge0";
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+ };
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+
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+ i2c0_pins: i2c-pins-0 {
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+ marvell,pins = "mpp2", "mpp3";
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+ marvell,function = "i2c0";
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+ };
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+
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+ mdio_pins: mdio-pins {
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+ marvell,pins = "mpp4", "mpp5";
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+ marvell,function = "ge";
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+ };
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+
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+ ref_clk0_pins: ref-clk-pins-0 {
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+ marvell,pins = "mpp45";
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+ marvell,function = "ref";
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+ };
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+
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+ spi1_pins: spi-pins-1 {
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+ marvell,pins = "mpp56", "mpp57", "mpp58",
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+ "mpp59";
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+ marvell,function = "spi1";
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+ };
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+
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+ uart0_pins: uart-pins-0 {
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+ marvell,pins = "mpp0", "mpp1";
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+ marvell,function = "ua0";
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+ };
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+
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+ uart1_pins: uart-pins-1 {
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+ marvell,pins = "mpp19", "mpp20";
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+ marvell,function = "ua1";
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+ };
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};
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gpio0: gpio@18100 {
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--
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2.2.1
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@ -0,0 +1,220 @@
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From e5ee12817e9eac891c6b2a340f64d94d9abd355f Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime.ripard@free-electrons.com>
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Date: Thu, 8 Jan 2015 18:38:09 +0100
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Subject: [PATCH 4/4] ARM: mvebu: Add Armada 385 Access Point Development Board
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support
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The A385-AP is a board produced by Marvell that holds 3 mPCIe slot, a 16MB
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SPI-NOR, 3 Gigabit Ethernet ports, USB3 and NAND flash storage.
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[gregory.clement@free-electrons.com: switch the license to the dual
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X11/GPL with the agreement of the author]
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Signed-off-by: Andrew Lunn <andrew@lunn.ch>
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---
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arch/arm/boot/dts/Makefile | 1 +
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arch/arm/boot/dts/armada-385-db-ap.dts | 178 +++++++++++++++++++++++++++++++++
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2 files changed, 179 insertions(+)
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create mode 100644 arch/arm/boot/dts/armada-385-db-ap.dts
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diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
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index 6dc9c17f9ff5..d34837104949 100644
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -536,6 +536,7 @@ dtb-$(CONFIG_MACH_ARMADA_375) += \
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armada-375-db.dtb
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dtb-$(CONFIG_MACH_ARMADA_38X) += \
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armada-385-db.dtb \
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+ armada-385-db-ap.dtb \
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armada-385-rd.dtb
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dtb-$(CONFIG_MACH_ARMADA_XP) += \
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armada-xp-axpwifiap.dtb \
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diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts
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new file mode 100644
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index 000000000000..57b9119fb3e0
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--- /dev/null
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+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
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@@ -0,0 +1,178 @@
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+/*
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+ * Device Tree file for Marvell Armada 385 Access Point Development board
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+ * (DB-88F6820-AP)
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+ *
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+ * Copyright (C) 2014 Marvell
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+ *
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+ * Nadav Haklai <nadavh@marvell.com>
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+ *
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+ * This file is dual-licensed: you can use it either under the terms
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+ * of the GPL or the X11 license, at your option. Note that this dual
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+ * licensing only applies to this file, and not this project as a
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+ * whole.
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+ *
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+ * a) This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without
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+ * any warranty of any kind, whether express or implied.
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+ *
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+ * Or, alternatively,
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+ *
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+ * b) Permission is hereby granted, free of charge, to any person
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+ * obtaining a copy of this software and associated documentation
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+ * files (the "Software"), to deal in the Software without
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+ * restriction, including without limitation the rights to use,
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+ * copy, modify, merge, publish, distribute, sublicense, and/or
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+ * sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following
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+ * conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be
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+ * included in all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ */
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+
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+/dts-v1/;
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+#include "armada-385.dtsi"
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+
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+#include <dt-bindings/gpio/gpio.h>
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+
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+/ {
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+ model = "Marvell Armada 385 Access Point Development Board";
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+ compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x";
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+
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+ chosen {
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+ bootargs = "console=ttyS0,115200";
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+ stdout-path = &uart1;
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+ };
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+
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+ memory {
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+ device_type = "memory";
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+ reg = <0x00000000 0x80000000>; /* 2GB */
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+ };
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+
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+ soc {
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+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
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+
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+ internal-regs {
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+ spi1: spi@10680 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi1_pins>;
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+ status = "okay";
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+
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+ spi-flash@0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "st,m25p128";
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+ reg = <0>; /* Chip select 0 */
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+ spi-max-frequency = <54000000>;
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+ };
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+ };
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+
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+ i2c0: i2c@11000 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c0_pins>;
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+ status = "okay";
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+
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+ /*
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+ * This bus is wired to two EEPROM
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+ * sockets, one of which holding the
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+ * board ID used by the bootloader.
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+ * Erasing this EEPROM's content will
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+ * brick the board.
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+ * Use this bus with caution.
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+ */
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+ };
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+
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+ mdio@72004 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&mdio_pins>;
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+
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+ phy0: ethernet-phy@1 {
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+ reg = <1>;
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+ };
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+
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+ phy1: ethernet-phy@4 {
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+ reg = <4>;
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+ };
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+
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+ phy2: ethernet-phy@6 {
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+ reg = <6>;
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+ };
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+ };
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+
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+ /* UART0 is exposed through the JP8 connector */
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+ uart0: serial@12000 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart0_pins>;
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+ status = "okay";
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+ };
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+
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+ /*
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+ * UART1 is exposed through a FTDI chip
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+ * wired to the mini-USB connector
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+ */
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+ uart1: serial@12100 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart1_pins>;
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+ status = "okay";
|
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+ };
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+
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+ ethernet@30000 {
|
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+ status = "okay";
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+ phy = <&phy2>;
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+ phy-mode = "sgmii";
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+ };
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+
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+ ethernet@34000 {
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+ status = "okay";
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+ phy = <&phy1>;
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+ phy-mode = "sgmii";
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+ };
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+
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+ ethernet@70000 {
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+ pinctrl-names = "default";
|
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+
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+ /*
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+ * The Reference Clock 0 is used to
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+ * provide a clock to the PHY
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+ */
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+ pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
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+ status = "okay";
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+ phy = <&phy0>;
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+ phy-mode = "rgmii-id";
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+ };
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+ };
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+
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+ pcie-controller {
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+ status = "okay";
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+
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+ /*
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+ * The three PCIe units are accessible through
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+ * standard mini-PCIe slots on the board.
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+ */
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+ pcie@1,0 {
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+ /* Port 0, Lane 0 */
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+ status = "okay";
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+ };
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+
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+ pcie@2,0 {
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+ /* Port 1, Lane 0 */
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+ status = "okay";
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+ };
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+
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+ pcie@3,0 {
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+ /* Port 2, Lane 0 */
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+ status = "okay";
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+ };
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+ };
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+ };
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+};
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--
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2.2.1
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@ -0,0 +1,39 @@
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From 7eb1f09ec8e25aa2fc3f6fc5fc9405d9f917d503 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime.ripard@free-electrons.com>
|
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Date: Thu, 11 Dec 2014 14:14:58 +0100
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Subject: [PATCH 1/2] ARM: mvebu: A385-AP: Enable the NAND controller
|
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The A385 AP has a 1GB NAND chip. Enable it.
|
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|
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
---
|
||||
arch/arm/boot/dts/armada-385-db-ap.dts | 13 +++++++++++++
|
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1 file changed, 13 insertions(+)
|
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|
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diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts
|
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index 3a51531eb37b..02db04867d8f 100644
|
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--- a/arch/arm/boot/dts/armada-385-db-ap.dts
|
||||
+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
|
||||
@@ -122,6 +122,19 @@
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
+
|
||||
+ nfc: flash@d0000 {
|
||||
+ status = "okay";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ num-cs = <1>;
|
||||
+ nand-ecc-strength = <4>;
|
||||
+ nand-ecc-step-size = <512>;
|
||||
+ marvell,nand-keep-config;
|
||||
+ marvell,nand-enable-arbiter;
|
||||
+ nand-on-flash-bbt;
|
||||
+ };
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
--
|
||||
2.2.1
|
||||
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
From a95308d88c07e0093aedae7e64f92cb1e165f592 Mon Sep 17 00:00:00 2001
|
||||
From: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
Date: Fri, 5 Dec 2014 15:44:57 +0100
|
||||
Subject: [PATCH] pinctrl: mvebu: a38x: Add UART1 muxing options
|
||||
|
||||
The MPP19 and MMP20 pins also have the ability to be muxed to the uart1
|
||||
function.
|
||||
|
||||
Add this case to the pinctrl driver.
|
||||
|
||||
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
Acked-by: Jason Cooper <jason@lakedaemon.net>
|
||||
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
||||
---
|
||||
drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 6 ++++--
|
||||
1 file changed, 4 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c
|
||||
index 224c6cff6aa2..7302f66f4f19 100644
|
||||
--- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c
|
||||
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c
|
||||
@@ -145,14 +145,16 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {
|
||||
MPP_VAR_FUNCTION(2, "ptp", "event_req", V_88F6810_PLUS),
|
||||
MPP_VAR_FUNCTION(3, "pcie0", "clkreq", V_88F6810_PLUS),
|
||||
MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS),
|
||||
- MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS)),
|
||||
+ MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS),
|
||||
+ MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)),
|
||||
MPP_MODE(20,
|
||||
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
|
||||
MPP_VAR_FUNCTION(1, "ge0", "txclk", V_88F6810_PLUS),
|
||||
MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS),
|
||||
MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS),
|
||||
MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6810_PLUS),
|
||||
- MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS)),
|
||||
+ MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS),
|
||||
+ MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)),
|
||||
MPP_MODE(21,
|
||||
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
|
||||
MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6810_PLUS),
|
||||
--
|
||||
2.2.1
|
||||
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
From 4a25432b13090b57d257fa0ffb6712d8acf94523 Mon Sep 17 00:00:00 2001
|
||||
From: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
Date: Thu, 8 Jan 2015 18:38:05 +0100
|
||||
Subject: [PATCH 1/4] ARM: mvebu: a38x: Fix node names
|
||||
|
||||
Some nodes in the DTs have a reg property but no unit name in their node name.
|
||||
|
||||
This contradicts the way the ePAPR defines the node names. Fix this.
|
||||
|
||||
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
|
||||
---
|
||||
arch/arm/boot/dts/armada-380.dtsi | 2 +-
|
||||
arch/arm/boot/dts/armada-385-db.dts | 2 +-
|
||||
arch/arm/boot/dts/armada-385-rd.dts | 2 +-
|
||||
arch/arm/boot/dts/armada-385.dtsi | 2 +-
|
||||
arch/arm/boot/dts/armada-38x.dtsi | 4 ++--
|
||||
5 files changed, 6 insertions(+), 6 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi
|
||||
index 4173a8ab34e7..13400ce88c54 100644
|
||||
--- a/arch/arm/boot/dts/armada-380.dtsi
|
||||
+++ b/arch/arm/boot/dts/armada-380.dtsi
|
||||
@@ -32,7 +32,7 @@
|
||||
|
||||
soc {
|
||||
internal-regs {
|
||||
- pinctrl {
|
||||
+ pinctrl@18000 {
|
||||
compatible = "marvell,mv88f6810-pinctrl";
|
||||
reg = <0x18000 0x20>;
|
||||
};
|
||||
diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts
|
||||
index 2aaa9d2ac284..212605ccc7b6 100644
|
||||
--- a/arch/arm/boot/dts/armada-385-db.dts
|
||||
+++ b/arch/arm/boot/dts/armada-385-db.dts
|
||||
@@ -74,7 +74,7 @@
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
- mdio {
|
||||
+ mdio@72004 {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
diff --git a/arch/arm/boot/dts/armada-385-rd.dts b/arch/arm/boot/dts/armada-385-rd.dts
|
||||
index aaca2861dc87..74a3bfe6efd7 100644
|
||||
--- a/arch/arm/boot/dts/armada-385-rd.dts
|
||||
+++ b/arch/arm/boot/dts/armada-385-rd.dts
|
||||
@@ -67,7 +67,7 @@
|
||||
};
|
||||
|
||||
|
||||
- mdio {
|
||||
+ mdio@72004 {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
|
||||
index 6283d7912f71..5249a4d3c207 100644
|
||||
--- a/arch/arm/boot/dts/armada-385.dtsi
|
||||
+++ b/arch/arm/boot/dts/armada-385.dtsi
|
||||
@@ -37,7 +37,7 @@
|
||||
|
||||
soc {
|
||||
internal-regs {
|
||||
- pinctrl {
|
||||
+ pinctrl@18000 {
|
||||
compatible = "marvell,mv88f6820-pinctrl";
|
||||
reg = <0x18000 0x20>;
|
||||
};
|
||||
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
|
||||
index 74391dace9e7..ada1f206028b 100644
|
||||
--- a/arch/arm/boot/dts/armada-38x.dtsi
|
||||
+++ b/arch/arm/boot/dts/armada-38x.dtsi
|
||||
@@ -193,7 +193,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
- pinctrl {
|
||||
+ pinctrl@18000 {
|
||||
compatible = "marvell,mv88f6820-pinctrl";
|
||||
reg = <0x18000 0x20>;
|
||||
};
|
||||
@@ -373,7 +373,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
- mdio {
|
||||
+ mdio@72004 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,orion-mdio";
|
||||
--
|
||||
2.2.1
|
||||
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001
|
||||
From: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
Date: Tue, 13 Jan 2015 11:14:09 +0100
|
||||
Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions
|
||||
|
||||
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
---
|
||||
arch/arm/boot/dts/armada-385-db-ap.dts | 15 +++++++++++++++
|
||||
1 file changed, 15 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts
|
||||
index 02db04867d8f..2a58443e2504 100644
|
||||
--- a/arch/arm/boot/dts/armada-385-db-ap.dts
|
||||
+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
|
||||
@@ -134,6 +134,21 @@
|
||||
marvell,nand-keep-config;
|
||||
marvell,nand-enable-arbiter;
|
||||
nand-on-flash-bbt;
|
||||
+
|
||||
+ mtd0@00000000 {
|
||||
+ label = "u-boot";
|
||||
+ reg = <0x00000000 0x00800000>;
|
||||
+ };
|
||||
+
|
||||
+ mtd1@00800000 {
|
||||
+ label = "kernel";
|
||||
+ reg = <0x00800000 0x00800000>;
|
||||
+ };
|
||||
+
|
||||
+ mtd2@01000000 {
|
||||
+ label = "ubi";
|
||||
+ reg = <0x01000000 0x3f000000>;
|
||||
+ };
|
||||
};
|
||||
};
|
||||
|
||||
--
|
||||
2.2.1
|
||||
|
||||
Loading…
Reference in New Issue