mirror of https://github.com/hak5/openwrt-owl.git
mac80211: add pending brcmfmac patch fixing warm reboots
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> SVN-Revision: 46739owl
Rafał Miłecki
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92f679d3a3
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98531b425d
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@ -0,0 +1,193 @@
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From: Hante Meuleman <meuleman@broadcom.com>
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Date: Thu, 27 Aug 2015 16:14:06 +0200
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Subject: [PATCH] brcmfmac: Reset PCIE devices after recognition.
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When PCIE type devices are being FW reloaded without being properly
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reset then the device ends up in a locked state, requiring the
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device to be completely powered down. This patch adds a reset
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through watchdog at the moment the device (cores) has been
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recognized. This will solve warm reboot issues.
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Cc: Rafal Milecki <zajec5@gmail.com>
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Reviewed-by: Arend Van Spriel <arend@broadcom.com>
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Reviewed-by: Franky (Zhenhui) Lin <frankyl@broadcom.com>
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Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com>
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Signed-off-by: Hante Meuleman <meuleman@broadcom.com>
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Signed-off-by: Arend van Spriel <arend@broadcom.com>
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---
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--- a/drivers/net/wireless/brcm80211/brcmfmac/chip.c
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+++ b/drivers/net/wireless/brcm80211/brcmfmac/chip.c
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@@ -101,6 +101,9 @@
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/* ARM Cortex M3 core, ID 0x82a */
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#define BCM4329_CORE_ARM_BASE 0x18002000
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+/* Max possibly supported memory size (limited by IO mapped memory) */
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+#define BRCMF_CHIP_MAX_MEMSIZE (4 * 1024 * 1024)
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+
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#define CORE_SB(base, field) \
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(base + SBCONFIGOFF + offsetof(struct sbconfig, field))
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#define SBCOREREV(sbidh) \
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@@ -687,6 +690,12 @@ static int brcmf_chip_get_raminfo(struct
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brcmf_err("RAM size is undetermined\n");
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return -ENOMEM;
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}
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+
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+ if (ci->pub.ramsize > BRCMF_CHIP_MAX_MEMSIZE) {
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+ brcmf_err("RAM size is incorrect\n");
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+ return -ENOMEM;
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+ }
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+
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return 0;
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}
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@@ -899,6 +908,15 @@ static int brcmf_chip_recognition(struct
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/* assure chip is passive for core access */
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brcmf_chip_set_passive(&ci->pub);
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+
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+ /* Call bus specific reset function now. Cores have been determined
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+ * but further access may require a chip specific reset at this point.
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+ */
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+ if (ci->ops->reset) {
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+ ci->ops->reset(ci->ctx, &ci->pub);
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+ brcmf_chip_set_passive(&ci->pub);
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+ }
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+
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return brcmf_chip_get_raminfo(ci);
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}
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--- a/drivers/net/wireless/brcm80211/brcmfmac/chip.h
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+++ b/drivers/net/wireless/brcm80211/brcmfmac/chip.h
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@@ -73,6 +73,7 @@ struct brcmf_buscore_ops {
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u32 (*read32)(void *ctx, u32 addr);
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void (*write32)(void *ctx, u32 addr, u32 value);
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int (*prepare)(void *ctx);
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+ int (*reset)(void *ctx, struct brcmf_chip *chip);
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int (*setup)(void *ctx, struct brcmf_chip *chip);
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void (*activate)(void *ctx, struct brcmf_chip *chip, u32 rstvec);
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};
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--- a/drivers/net/wireless/brcm80211/brcmfmac/pcie.c
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+++ b/drivers/net/wireless/brcm80211/brcmfmac/pcie.c
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@@ -74,6 +74,8 @@ enum brcmf_pcie_state {
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#define BRCMF_PCIE_REG_INTMASK 0x94
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#define BRCMF_PCIE_REG_SBMBX 0x98
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+#define BRCMF_PCIE_REG_LINK_STATUS_CTRL 0xBC
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+
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#define BRCMF_PCIE_PCIE2REG_INTMASK 0x24
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#define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48
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#define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C
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@@ -466,6 +468,7 @@ brcmf_pcie_select_core(struct brcmf_pcie
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static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
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{
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+ struct brcmf_core *core;
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u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
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BRCMF_PCIE_CFGREG_PM_CSR,
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BRCMF_PCIE_CFGREG_MSI_CAP,
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@@ -484,32 +487,38 @@ static void brcmf_pcie_reset_device(stru
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if (!devinfo->ci)
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return;
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+ /* Disable ASPM */
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brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
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- brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
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- BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL);
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- lsc = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
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+ pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
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+ &lsc);
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val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
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- brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, val);
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+ pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
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+ val);
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+ /* Watchdog reset */
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brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
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WRITECC32(devinfo, watchdog, 4);
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msleep(100);
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+ /* Restore ASPM */
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brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
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- brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
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- BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL);
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- brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, lsc);
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+ pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
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+ lsc);
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- brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
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- for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
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- brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
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- cfg_offset[i]);
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- val = brcmf_pcie_read_reg32(devinfo,
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- BRCMF_PCIE_PCIE2REG_CONFIGDATA);
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- brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
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- cfg_offset[i], val);
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- brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA,
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- val);
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+ core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
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+ if (core->rev <= 13) {
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+ for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
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+ brcmf_pcie_write_reg32(devinfo,
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+ BRCMF_PCIE_PCIE2REG_CONFIGADDR,
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+ cfg_offset[i]);
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+ val = brcmf_pcie_read_reg32(devinfo,
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+ BRCMF_PCIE_PCIE2REG_CONFIGDATA);
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+ brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
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+ cfg_offset[i], val);
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+ brcmf_pcie_write_reg32(devinfo,
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+ BRCMF_PCIE_PCIE2REG_CONFIGDATA,
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+ val);
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+ }
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}
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}
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@@ -519,8 +528,6 @@ static void brcmf_pcie_attach(struct brc
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u32 config;
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brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
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- if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0)
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- brcmf_pcie_reset_device(devinfo);
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/* BAR1 window may not be sized properly */
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brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
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brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
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@@ -1636,6 +1643,23 @@ static int brcmf_pcie_buscoreprep(void *
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}
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+static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip)
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+{
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+ struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
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+ u32 val;
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+
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+ devinfo->ci = chip;
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+ brcmf_pcie_reset_device(devinfo);
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+
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+ val = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
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+ if (val != 0xffffffff)
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+ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
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+ val);
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+
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+ return 0;
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+}
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+
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+
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static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip,
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u32 rstvec)
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{
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@@ -1647,6 +1671,7 @@ static void brcmf_pcie_buscore_activate(
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static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
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.prepare = brcmf_pcie_buscoreprep,
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+ .reset = brcmf_pcie_buscore_reset,
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.activate = brcmf_pcie_buscore_activate,
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.read32 = brcmf_pcie_buscore_read32,
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.write32 = brcmf_pcie_buscore_write32,
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@@ -1814,7 +1839,6 @@ brcmf_pcie_remove(struct pci_dev *pdev)
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brcmf_pcie_intr_disable(devinfo);
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brcmf_detach(&pdev->dev);
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- brcmf_pcie_reset_device(devinfo);
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kfree(bus->bus_priv.pcie);
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kfree(bus->msgbuf->flowrings);
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