mirror of https://github.com/hak5/openwrt-owl.git
Alexandros C. Couloumbis
parent
9bc1e548a1
commit
93993b29e0
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@ -0,0 +1,57 @@
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -23,6 +23,21 @@ choice
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prompt "System type"
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default SGI_IP22
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+config ADM5120
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+ bool "Infineon/ADMtek ADM5120 SoC based machines"
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+ select CEVT_R4K
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+ select CSRC_R4K
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select SYS_HAS_EARLY_PRINTK
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+ select DMA_NONCOHERENT
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+ select IRQ_CPU
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+ select SYS_SUPPORTS_LITTLE_ENDIAN
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+ select SYS_SUPPORTS_BIG_ENDIAN
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+ select SYS_SUPPORTS_32BIT_KERNEL
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+ select ARCH_REQUIRE_GPIOLIB
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+ select SWAP_IO_SPACE if CPU_BIG_ENDIAN
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+ select MIPS_MACHINE
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+
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config MACH_ALCHEMY
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bool "Alchemy processor based machines"
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select SYS_SUPPORTS_ZBOOT
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@@ -681,6 +696,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
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endchoice
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+source "arch/mips/adm5120/Kconfig"
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source "arch/mips/alchemy/Kconfig"
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source "arch/mips/bcm63xx/Kconfig"
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source "arch/mips/jazz/Kconfig"
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--- a/arch/mips/Makefile
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+++ b/arch/mips/Makefile
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@@ -214,6 +214,22 @@ cflags-$(CONFIG_MACH_JAZZ) += -I$(srctre
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load-$(CONFIG_MACH_JAZZ) += 0xffffffff80080000
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#
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+# Infineon/ADMtek ADM5120
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+#
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+libs-$(CONFIG_ADM5120) += arch/mips/adm5120/prom/
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+core-$(CONFIG_ADM5120) += arch/mips/adm5120/common/
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+core-$(CONFIG_ADM5120_OEM_CELLVISION) += arch/mips/adm5120/cellvision/
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+core-$(CONFIG_ADM5120_OEM_COMPEX) += arch/mips/adm5120/compex/
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+core-$(CONFIG_ADM5120_OEM_EDIMAX) += arch/mips/adm5120/edimax/
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+core-$(CONFIG_ADM5120_OEM_INFINEON) += arch/mips/adm5120/infineon/
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+core-$(CONFIG_ADM5120_OEM_MIKROTIK) += arch/mips/adm5120/mikrotik/
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+core-$(CONFIG_ADM5120_OEM_MOTOROLA) += arch/mips/adm5120/motorola/
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+core-$(CONFIG_ADM5120_OEM_OSBRIDGE) += arch/mips/adm5120/osbridge/
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+core-$(CONFIG_ADM5120_OEM_ZYXEL) += arch/mips/adm5120/zyxel/
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+cflags-$(CONFIG_ADM5120) += -I$(srctree)/arch/mips/include/asm/mach-adm5120
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+load-$(CONFIG_ADM5120) += 0xffffffff80001000
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+
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+#
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# Common Alchemy Au1x00 stuff
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#
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core-$(CONFIG_SOC_AU1X00) += arch/mips/alchemy/common/
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@ -0,0 +1,21 @@
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--- a/drivers/mtd/maps/Kconfig
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+++ b/drivers/mtd/maps/Kconfig
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@@ -551,4 +551,8 @@ config MTD_PISMO
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When built as a module, it will be called pismo.ko
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+config MTD_ADM5120
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+ tristate "Map driver for ADM5120 based boards"
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+ depends on ADM5120
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+
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endmenu
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--- a/drivers/mtd/maps/Makefile
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+++ b/drivers/mtd/maps/Makefile
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@@ -40,6 +40,7 @@ obj-$(CONFIG_MTD_SCx200_DOCFLASH)+= scx2
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obj-$(CONFIG_MTD_DBOX2) += dbox2-flash.o
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obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o
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obj-$(CONFIG_MTD_PCI) += pci.o
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+obj-$(CONFIG_MTD_ADM5120) += adm5120-flash.o
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obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o
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obj-$(CONFIG_MTD_EDB7312) += edb7312.o
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obj-$(CONFIG_MTD_IMPA7) += impa7.o
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@ -0,0 +1,23 @@
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--- a/drivers/net/Kconfig
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+++ b/drivers/net/Kconfig
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@@ -614,6 +614,10 @@ config MIPS_AU1X00_ENET
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If you have an Alchemy Semi AU1X00 based system
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say Y. Otherwise, say N.
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+config ADM5120_ENET
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+ tristate "ADM5120 Ethernet switch support"
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+ depends on ADM5120
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+
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config SGI_IOC3_ETH
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bool "SGI IOC3 Ethernet"
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depends on PCI && SGI_IP27
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--- a/drivers/net/Makefile
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+++ b/drivers/net/Makefile
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@@ -213,6 +213,7 @@ obj-$(CONFIG_SC92031) += sc92031.o
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# This is also a 82596 and should probably be merged
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obj-$(CONFIG_LP486E) += lp486e.o
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+obj-$(CONFIG_ADM5120_ENET) += adm5120sw.o
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obj-$(CONFIG_ETH16I) += eth16i.o
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obj-$(CONFIG_ZORRO8390) += zorro8390.o 8390.o
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obj-$(CONFIG_HPLANCE) += hplance.o 7990.o
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@ -0,0 +1,33 @@
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--- a/drivers/usb/Makefile
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+++ b/drivers/usb/Makefile
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@@ -9,6 +9,7 @@ obj-$(CONFIG_USB) += core/
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obj-$(CONFIG_USB_MON) += mon/
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obj-$(CONFIG_PCI) += host/
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+obj-$(CONFIG_USB_ADM5120_HCD) += host/
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obj-$(CONFIG_USB_EHCI_HCD) += host/
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obj-$(CONFIG_USB_ISP116X_HCD) += host/
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obj-$(CONFIG_USB_OHCI_HCD) += host/
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--- a/drivers/usb/host/Kconfig
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+++ b/drivers/usb/host/Kconfig
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@@ -4,6 +4,10 @@
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comment "USB Host Controller Drivers"
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depends on USB
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+config USB_ADM5120_HCD
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+ tristate "ADM5120 HCD support (EXPERIMENTAL)"
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+ depends on USB && ADM5120 && EXPERIMENTAL
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+
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config USB_C67X00_HCD
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tristate "Cypress C67x00 HCD support"
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depends on USB
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--- a/drivers/usb/host/Makefile
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+++ b/drivers/usb/host/Makefile
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@@ -18,6 +18,7 @@ obj-$(CONFIG_USB_WHCI_HCD) += whci/
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obj-$(CONFIG_PCI) += pci-quirks.o
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+obj-$(CONFIG_USB_ADM5120_HCD) += adm5120-hcd.o
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obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
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obj-$(CONFIG_USB_OXU210HP_HCD) += oxu210hp-hcd.o
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obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
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@ -0,0 +1,22 @@
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--- a/arch/mips/pci/Makefile
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+++ b/arch/mips/pci/Makefile
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@@ -55,6 +55,7 @@ obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capc
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obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
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obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
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obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
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+obj-$(CONFIG_ADM5120) += pci-adm5120.o
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ifdef CONFIG_PCI_MSI
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obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
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--- a/include/linux/pci_ids.h
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+++ b/include/linux/pci_ids.h
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@@ -1752,6 +1752,9 @@
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#define PCI_VENDOR_ID_ESDGMBH 0x12fe
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#define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111
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+#define PCI_VENDOR_ID_ADMTEK 0x1317
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+#define PCI_DEVICE_ID_ADMTEK_ADM5120 0x5120
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+
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#define PCI_VENDOR_ID_SIIG 0x131f
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#define PCI_SUBVENDOR_ID_SIIG 0x131f
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#define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000
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@ -0,0 +1,22 @@
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--- a/drivers/leds/Kconfig
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+++ b/drivers/leds/Kconfig
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@@ -365,4 +365,12 @@ config LEDS_TRIGGER_NETDEV
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This allows LEDs to be controlled by network device activity.
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If unsure, say Y.
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+config LEDS_TRIGGER_ADM5120_SWITCH
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+ tristate "LED ADM5120 Switch Port Status Trigger"
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+ depends on LEDS_TRIGGERS && ADM5120
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+ help
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+ This allows LEDs to be controlled by the port states of
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+ the ADM5120 built-in Ethernet Switch
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+ If unsure, say N.
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+
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endif # NEW_LEDS
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--- a/drivers/leds/Makefile
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+++ b/drivers/leds/Makefile
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@@ -48,3 +48,4 @@ obj-$(CONFIG_LEDS_TRIGGER_GPIO) += ledt
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obj-$(CONFIG_LEDS_TRIGGER_DEFAULT_ON) += ledtrig-default-on.o
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obj-$(CONFIG_LEDS_TRIGGER_MORSE) += ledtrig-morse.o
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obj-$(CONFIG_LEDS_TRIGGER_NETDEV) += ledtrig-netdev.o
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+obj-$(CONFIG_LEDS_TRIGGER_ADM5120_SWITCH) += ledtrig-adm5120-switch.o
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@ -0,0 +1,84 @@
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--- a/drivers/mtd/chips/cfi_cmdset_0002.c
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+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
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@@ -53,6 +53,12 @@
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#define AT49BV6416 0x00d6
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#define MANUFACTURER_SAMSUNG 0x00ec
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+/* Macronix */
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+#define MX29LV160B 0x2249 /* MX29LV160 Bottom-boot chip */
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+#define MX29LV160T 0x22C4 /* MX29LV160 Top-boot chip */
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+#define MX29LV320B 0x22A8 /* MX29LV320 Bottom-boot chip */
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+#define MX29LV320T 0x22A7 /* MX29LV320 Top-boot chip */
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+
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static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
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static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
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static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
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@@ -283,6 +289,41 @@ static void fixup_s29gl032n_sectors(stru
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}
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}
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+#ifdef CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC
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+/*
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+ * Some Macronix chips has no/bad bootblock information in the CFI table
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+ */
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+static void fixup_macronix_bootloc(struct mtd_info *mtd, void* param)
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+{
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+ struct map_info *map = mtd->priv;
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+ struct cfi_private *cfi = map->fldrv_priv;
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+ struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
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+ __u8 t;
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+
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+ switch (cfi->id) {
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+ /* TODO: put affected chip ids here */
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+ case MX29LV160B:
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+ case MX29LV320B:
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+ t = 2; /* Bottom boot */
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+ break;
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+ case MX29LV160T:
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+ case MX29LV320T:
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+ t = 3; /* Top boot */
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+ break;
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+ default:
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+ return;
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+ }
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+
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+ if (extp->TopBottom == t)
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+ /* boot location detected by the CFI layer is correct */
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+ return;
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+
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+ extp->TopBottom = t;
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+ printk("%s: Macronix chip detected, id:0x%04X, boot location forced "
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+ "to %s\n", map->name, cfi->id, (t == 2) ? "bottom" : "top");
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+}
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+#endif /* CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC */
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+
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static struct cfi_fixup cfi_fixup_table[] = {
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{ CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
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#ifdef AMD_BOOTLOC_BUG
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@@ -319,6 +360,9 @@ static struct cfi_fixup fixup_table[] =
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*/
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{ CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip, NULL },
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{ CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock, NULL },
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+#ifdef CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC
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+ { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_macronix_bootloc, NULL, },
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+#endif
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{ 0, 0, NULL, NULL }
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};
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--- a/drivers/mtd/chips/Kconfig
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+++ b/drivers/mtd/chips/Kconfig
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@@ -196,6 +196,14 @@ config MTD_CFI_AMDSTD
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provides support for one of those command sets, used on chips
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including the AMD Am29LV320.
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+config MTD_CFI_FIXUP_MACRONIX_BOOTLOC
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+ bool "Fix boot-block location for Macronix flash chips"
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+ depends on MTD_CFI_AMDSTD
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+ help
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+ Some Macronix flash chips have no/wrong boot-block location in the
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+ CFI table, and the driver may detect the type incorrectly. Select
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+ this if your board has such chip.
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+
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config MTD_CFI_STAA
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tristate "Support for ST (Advanced Architecture) flash chips"
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depends on MTD_GEN_PROBE
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@ -0,0 +1,68 @@
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--- a/drivers/mtd/chips/jedec_probe.c
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+++ b/drivers/mtd/chips/jedec_probe.c
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@@ -133,6 +133,10 @@
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#define UPD29F064115 0x221C
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/* PMC */
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+#define PM39LV512 0x001B
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+#define PM39LV010 0x001C
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+#define PM39LV020 0x003D
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+#define PM39LV040 0x003E
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#define PM49FL002 0x006D
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#define PM49FL004 0x006E
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#define PM49FL008 0x006A
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@@ -1275,6 +1279,54 @@ static const struct amd_flash_info jedec
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ERASEINFO(0x02000,2),
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ERASEINFO(0x04000,1),
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}
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+ }, {
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+ .mfr_id = CFI_MFR_PMC,
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+ .dev_id = PM39LV512,
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+ .name = "PMC Pm39LV512",
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+ .devtypes = CFI_DEVICETYPE_X8,
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+ .uaddr = MTD_UADDR_0x0555_0x02AA,
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+ .dev_size = SIZE_64KiB,
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+ .cmd_set = P_ID_AMD_STD,
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+ .nr_regions = 1,
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+ .regions = {
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+ ERASEINFO(0x01000,16),
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+ }
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+ }, {
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+ .mfr_id = CFI_MFR_PMC,
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+ .dev_id = PM39LV010,
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+ .name = "PMC Pm39LV010",
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+ .devtypes = CFI_DEVICETYPE_X8,
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+ .uaddr = MTD_UADDR_0x0555_0x02AA,
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+ .dev_size = SIZE_128KiB,
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+ .cmd_set = P_ID_AMD_STD,
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+ .nr_regions = 1,
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+ .regions = {
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+ ERASEINFO(0x01000,32),
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+ }
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+ }, {
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+ .mfr_id = CFI_MFR_PMC,
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+ .dev_id = PM39LV020,
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+ .name = "PMC Pm39LV020",
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||||||
|
+ .devtypes = CFI_DEVICETYPE_X8,
|
||||||
|
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
|
||||||
|
+ .dev_size = SIZE_256KiB,
|
||||||
|
+ .cmd_set = P_ID_AMD_STD,
|
||||||
|
+ .nr_regions = 1,
|
||||||
|
+ .regions = {
|
||||||
|
+ ERASEINFO(0x01000,64),
|
||||||
|
+ }
|
||||||
|
+ }, {
|
||||||
|
+ .mfr_id = CFI_MFR_PMC,
|
||||||
|
+ .dev_id = PM39LV040,
|
||||||
|
+ .name = "PMC Pm39LV040",
|
||||||
|
+ .devtypes = CFI_DEVICETYPE_X8,
|
||||||
|
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
|
||||||
|
+ .dev_size = SIZE_512KiB,
|
||||||
|
+ .cmd_set = P_ID_AMD_STD,
|
||||||
|
+ .nr_regions = 1,
|
||||||
|
+ .regions = {
|
||||||
|
+ ERASEINFO(0x01000,128),
|
||||||
|
+ }
|
||||||
|
}, {
|
||||||
|
.mfr_id = CFI_MFR_PMC,
|
||||||
|
.dev_id = PM49FL002,
|
||||||
|
|
@ -0,0 +1,24 @@
|
||||||
|
--- a/drivers/mtd/Kconfig
|
||||||
|
+++ b/drivers/mtd/Kconfig
|
||||||
|
@@ -63,6 +63,11 @@ config MTD_ROOTFS_SPLIT
|
||||||
|
depends on MTD_PARTITIONS
|
||||||
|
default y
|
||||||
|
|
||||||
|
+config MTD_TRXSPLIT
|
||||||
|
+ bool "Automatically find and split TRX partitions"
|
||||||
|
+ depends on MTD_PARTITIONS
|
||||||
|
+ default n
|
||||||
|
+
|
||||||
|
config MTD_REDBOOT_PARTS
|
||||||
|
tristate "RedBoot partition table parsing"
|
||||||
|
depends on MTD_PARTITIONS
|
||||||
|
--- a/drivers/mtd/Makefile
|
||||||
|
+++ b/drivers/mtd/Makefile
|
||||||
|
@@ -8,6 +8,7 @@ mtd-y := mtdcore.o mtdsuper.o mtdbdi.
|
||||||
|
mtd-$(CONFIG_MTD_PARTITIONS) += mtdpart.o
|
||||||
|
|
||||||
|
obj-$(CONFIG_MTD_CONCAT) += mtdconcat.o
|
||||||
|
+obj-$(CONFIG_MTD_TRXSPLIT) += trxsplit.o
|
||||||
|
obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o
|
||||||
|
obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o
|
||||||
|
obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
|
||||||
|
|
@ -0,0 +1,28 @@
|
||||||
|
--- a/drivers/ata/Makefile
|
||||||
|
+++ b/drivers/ata/Makefile
|
||||||
|
@@ -88,6 +88,7 @@ obj-$(CONFIG_PATA_QDI) += pata_qdi.o
|
||||||
|
obj-$(CONFIG_PATA_RB532) += pata_rb532_cf.o
|
||||||
|
obj-$(CONFIG_PATA_RZ1000) += pata_rz1000.o
|
||||||
|
obj-$(CONFIG_PATA_WINBOND_VLB) += pata_winbond.o
|
||||||
|
+obj-$(CONFIG_PATA_RB153_CF) += pata_rb153_cf.o
|
||||||
|
|
||||||
|
# Should be last but two libata driver
|
||||||
|
obj-$(CONFIG_PATA_ACPI) += pata_acpi.o
|
||||||
|
--- a/drivers/ata/Kconfig
|
||||||
|
+++ b/drivers/ata/Kconfig
|
||||||
|
@@ -604,6 +604,15 @@ config PATA_RADISYS
|
||||||
|
|
||||||
|
If unsure, say N.
|
||||||
|
|
||||||
|
+config PATA_RB153_CF
|
||||||
|
+ tristate "RouterBOARD 153 Compact Flash support"
|
||||||
|
+ depends on ADM5120_MACH_RB_153
|
||||||
|
+ help
|
||||||
|
+ This option enables support for a Compact Flash connected on
|
||||||
|
+ the RouterBOARD 153.
|
||||||
|
+
|
||||||
|
+ If unsure, say N.
|
||||||
|
+
|
||||||
|
config PATA_RB532
|
||||||
|
tristate "RouterBoard 532 PATA CompactFlash support"
|
||||||
|
depends on MIKROTIK_RB532
|
||||||
|
|
@ -0,0 +1,378 @@
|
||||||
|
--- a/drivers/serial/amba-pl010.c
|
||||||
|
+++ b/drivers/serial/amba-pl010.c
|
||||||
|
@@ -51,11 +51,10 @@
|
||||||
|
|
||||||
|
#include <asm/io.h>
|
||||||
|
|
||||||
|
-#define UART_NR 8
|
||||||
|
-
|
||||||
|
#define SERIAL_AMBA_MAJOR 204
|
||||||
|
#define SERIAL_AMBA_MINOR 16
|
||||||
|
-#define SERIAL_AMBA_NR UART_NR
|
||||||
|
+#define SERIAL_AMBA_NR CONFIG_SERIAL_AMBA_PL010_NUMPORTS
|
||||||
|
+#define SERIAL_AMBA_NAME CONFIG_SERIAL_AMBA_PL010_PORTNAME
|
||||||
|
|
||||||
|
#define AMBA_ISR_PASS_LIMIT 256
|
||||||
|
|
||||||
|
@@ -81,9 +80,9 @@ static void pl010_stop_tx(struct uart_po
|
||||||
|
struct uart_amba_port *uap = (struct uart_amba_port *)port;
|
||||||
|
unsigned int cr;
|
||||||
|
|
||||||
|
- cr = readb(uap->port.membase + UART010_CR);
|
||||||
|
+ cr = __raw_readl(uap->port.membase + UART010_CR);
|
||||||
|
cr &= ~UART010_CR_TIE;
|
||||||
|
- writel(cr, uap->port.membase + UART010_CR);
|
||||||
|
+ __raw_writel(cr, uap->port.membase + UART010_CR);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void pl010_start_tx(struct uart_port *port)
|
||||||
|
@@ -91,9 +90,9 @@ static void pl010_start_tx(struct uart_p
|
||||||
|
struct uart_amba_port *uap = (struct uart_amba_port *)port;
|
||||||
|
unsigned int cr;
|
||||||
|
|
||||||
|
- cr = readb(uap->port.membase + UART010_CR);
|
||||||
|
+ cr = __raw_readl(uap->port.membase + UART010_CR);
|
||||||
|
cr |= UART010_CR_TIE;
|
||||||
|
- writel(cr, uap->port.membase + UART010_CR);
|
||||||
|
+ __raw_writel(cr, uap->port.membase + UART010_CR);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void pl010_stop_rx(struct uart_port *port)
|
||||||
|
@@ -101,9 +100,9 @@ static void pl010_stop_rx(struct uart_po
|
||||||
|
struct uart_amba_port *uap = (struct uart_amba_port *)port;
|
||||||
|
unsigned int cr;
|
||||||
|
|
||||||
|
- cr = readb(uap->port.membase + UART010_CR);
|
||||||
|
+ cr = __raw_readl(uap->port.membase + UART010_CR);
|
||||||
|
cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
|
||||||
|
- writel(cr, uap->port.membase + UART010_CR);
|
||||||
|
+ __raw_writel(cr, uap->port.membase + UART010_CR);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void pl010_enable_ms(struct uart_port *port)
|
||||||
|
@@ -111,9 +110,9 @@ static void pl010_enable_ms(struct uart_
|
||||||
|
struct uart_amba_port *uap = (struct uart_amba_port *)port;
|
||||||
|
unsigned int cr;
|
||||||
|
|
||||||
|
- cr = readb(uap->port.membase + UART010_CR);
|
||||||
|
+ cr = __raw_readl(uap->port.membase + UART010_CR);
|
||||||
|
cr |= UART010_CR_MSIE;
|
||||||
|
- writel(cr, uap->port.membase + UART010_CR);
|
||||||
|
+ __raw_writel(cr, uap->port.membase + UART010_CR);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void pl010_rx_chars(struct uart_amba_port *uap)
|
||||||
|
@@ -121,9 +120,9 @@ static void pl010_rx_chars(struct uart_a
|
||||||
|
struct tty_struct *tty = uap->port.state->port.tty;
|
||||||
|
unsigned int status, ch, flag, rsr, max_count = 256;
|
||||||
|
|
||||||
|
- status = readb(uap->port.membase + UART01x_FR);
|
||||||
|
+ status = __raw_readl(uap->port.membase + UART01x_FR);
|
||||||
|
while (UART_RX_DATA(status) && max_count--) {
|
||||||
|
- ch = readb(uap->port.membase + UART01x_DR);
|
||||||
|
+ ch = __raw_readl(uap->port.membase + UART01x_DR);
|
||||||
|
flag = TTY_NORMAL;
|
||||||
|
|
||||||
|
uap->port.icount.rx++;
|
||||||
|
@@ -132,9 +131,9 @@ static void pl010_rx_chars(struct uart_a
|
||||||
|
* Note that the error handling code is
|
||||||
|
* out of the main execution path
|
||||||
|
*/
|
||||||
|
- rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
|
||||||
|
+ rsr = __raw_readl(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
|
||||||
|
if (unlikely(rsr & UART01x_RSR_ANY)) {
|
||||||
|
- writel(0, uap->port.membase + UART01x_ECR);
|
||||||
|
+ __raw_writel(0, uap->port.membase + UART01x_ECR);
|
||||||
|
|
||||||
|
if (rsr & UART01x_RSR_BE) {
|
||||||
|
rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
|
||||||
|
@@ -164,7 +163,7 @@ static void pl010_rx_chars(struct uart_a
|
||||||
|
uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
|
||||||
|
|
||||||
|
ignore_char:
|
||||||
|
- status = readb(uap->port.membase + UART01x_FR);
|
||||||
|
+ status = __raw_readl(uap->port.membase + UART01x_FR);
|
||||||
|
}
|
||||||
|
spin_unlock(&uap->port.lock);
|
||||||
|
tty_flip_buffer_push(tty);
|
||||||
|
@@ -177,7 +176,7 @@ static void pl010_tx_chars(struct uart_a
|
||||||
|
int count;
|
||||||
|
|
||||||
|
if (uap->port.x_char) {
|
||||||
|
- writel(uap->port.x_char, uap->port.membase + UART01x_DR);
|
||||||
|
+ __raw_writel(uap->port.x_char, uap->port.membase + UART01x_DR);
|
||||||
|
uap->port.icount.tx++;
|
||||||
|
uap->port.x_char = 0;
|
||||||
|
return;
|
||||||
|
@@ -189,7 +188,7 @@ static void pl010_tx_chars(struct uart_a
|
||||||
|
|
||||||
|
count = uap->port.fifosize >> 1;
|
||||||
|
do {
|
||||||
|
- writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
|
||||||
|
+ __raw_writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
|
||||||
|
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
|
||||||
|
uap->port.icount.tx++;
|
||||||
|
if (uart_circ_empty(xmit))
|
||||||
|
@@ -207,9 +206,9 @@ static void pl010_modem_status(struct ua
|
||||||
|
{
|
||||||
|
unsigned int status, delta;
|
||||||
|
|
||||||
|
- writel(0, uap->port.membase + UART010_ICR);
|
||||||
|
+ __raw_writel(0, uap->port.membase + UART010_ICR);
|
||||||
|
|
||||||
|
- status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
|
||||||
|
+ status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
|
||||||
|
|
||||||
|
delta = status ^ uap->old_status;
|
||||||
|
uap->old_status = status;
|
||||||
|
@@ -237,7 +236,7 @@ static irqreturn_t pl010_int(int irq, vo
|
||||||
|
|
||||||
|
spin_lock(&uap->port.lock);
|
||||||
|
|
||||||
|
- status = readb(uap->port.membase + UART010_IIR);
|
||||||
|
+ status = __raw_readl(uap->port.membase + UART010_IIR);
|
||||||
|
if (status) {
|
||||||
|
do {
|
||||||
|
if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
|
||||||
|
@@ -250,7 +249,7 @@ static irqreturn_t pl010_int(int irq, vo
|
||||||
|
if (pass_counter-- == 0)
|
||||||
|
break;
|
||||||
|
|
||||||
|
- status = readb(uap->port.membase + UART010_IIR);
|
||||||
|
+ status = __raw_readl(uap->port.membase + UART010_IIR);
|
||||||
|
} while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
|
||||||
|
UART010_IIR_TIS));
|
||||||
|
handled = 1;
|
||||||
|
@@ -264,7 +263,7 @@ static irqreturn_t pl010_int(int irq, vo
|
||||||
|
static unsigned int pl010_tx_empty(struct uart_port *port)
|
||||||
|
{
|
||||||
|
struct uart_amba_port *uap = (struct uart_amba_port *)port;
|
||||||
|
- unsigned int status = readb(uap->port.membase + UART01x_FR);
|
||||||
|
+ unsigned int status = __raw_readl(uap->port.membase + UART01x_FR);
|
||||||
|
return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -274,7 +273,7 @@ static unsigned int pl010_get_mctrl(stru
|
||||||
|
unsigned int result = 0;
|
||||||
|
unsigned int status;
|
||||||
|
|
||||||
|
- status = readb(uap->port.membase + UART01x_FR);
|
||||||
|
+ status = __raw_readl(uap->port.membase + UART01x_FR);
|
||||||
|
if (status & UART01x_FR_DCD)
|
||||||
|
result |= TIOCM_CAR;
|
||||||
|
if (status & UART01x_FR_DSR)
|
||||||
|
@@ -300,12 +299,12 @@ static void pl010_break_ctl(struct uart_
|
||||||
|
unsigned int lcr_h;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&uap->port.lock, flags);
|
||||||
|
- lcr_h = readb(uap->port.membase + UART010_LCRH);
|
||||||
|
+ lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
|
||||||
|
if (break_state == -1)
|
||||||
|
lcr_h |= UART01x_LCRH_BRK;
|
||||||
|
else
|
||||||
|
lcr_h &= ~UART01x_LCRH_BRK;
|
||||||
|
- writel(lcr_h, uap->port.membase + UART010_LCRH);
|
||||||
|
+ __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
|
||||||
|
spin_unlock_irqrestore(&uap->port.lock, flags);
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -333,12 +332,12 @@ static int pl010_startup(struct uart_por
|
||||||
|
/*
|
||||||
|
* initialise the old status of the modem signals
|
||||||
|
*/
|
||||||
|
- uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
|
||||||
|
+ uap->old_status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Finally, enable interrupts
|
||||||
|
*/
|
||||||
|
- writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
|
||||||
|
+ __raw_writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
|
||||||
|
uap->port.membase + UART010_CR);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
@@ -361,10 +360,10 @@ static void pl010_shutdown(struct uart_p
|
||||||
|
/*
|
||||||
|
* disable all interrupts, disable the port
|
||||||
|
*/
|
||||||
|
- writel(0, uap->port.membase + UART010_CR);
|
||||||
|
+ __raw_writel(0, uap->port.membase + UART010_CR);
|
||||||
|
|
||||||
|
/* disable break condition and fifos */
|
||||||
|
- writel(readb(uap->port.membase + UART010_LCRH) &
|
||||||
|
+ __raw_writel(__raw_readl(uap->port.membase + UART010_LCRH) &
|
||||||
|
~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
|
||||||
|
uap->port.membase + UART010_LCRH);
|
||||||
|
|
||||||
|
@@ -386,7 +385,7 @@ pl010_set_termios(struct uart_port *port
|
||||||
|
/*
|
||||||
|
* Ask the core to calculate the divisor for us.
|
||||||
|
*/
|
||||||
|
- baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
|
||||||
|
+ baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
|
||||||
|
quot = uart_get_divisor(port, baud);
|
||||||
|
|
||||||
|
switch (termios->c_cflag & CSIZE) {
|
||||||
|
@@ -449,25 +448,25 @@ pl010_set_termios(struct uart_port *port
|
||||||
|
uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
|
||||||
|
|
||||||
|
/* first, disable everything */
|
||||||
|
- old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
|
||||||
|
+ old_cr = __raw_readl(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
|
||||||
|
|
||||||
|
if (UART_ENABLE_MS(port, termios->c_cflag))
|
||||||
|
old_cr |= UART010_CR_MSIE;
|
||||||
|
|
||||||
|
- writel(0, uap->port.membase + UART010_CR);
|
||||||
|
+ __raw_writel(0, uap->port.membase + UART010_CR);
|
||||||
|
|
||||||
|
/* Set baud rate */
|
||||||
|
quot -= 1;
|
||||||
|
- writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
|
||||||
|
- writel(quot & 0xff, uap->port.membase + UART010_LCRL);
|
||||||
|
+ __raw_writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
|
||||||
|
+ __raw_writel(quot & 0xff, uap->port.membase + UART010_LCRL);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ----------v----------v----------v----------v-----
|
||||||
|
* NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
|
||||||
|
* ----------^----------^----------^----------^-----
|
||||||
|
*/
|
||||||
|
- writel(lcr_h, uap->port.membase + UART010_LCRH);
|
||||||
|
- writel(old_cr, uap->port.membase + UART010_CR);
|
||||||
|
+ __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
|
||||||
|
+ __raw_writel(old_cr, uap->port.membase + UART010_CR);
|
||||||
|
|
||||||
|
spin_unlock_irqrestore(&uap->port.lock, flags);
|
||||||
|
}
|
||||||
|
@@ -554,7 +553,7 @@ static struct uart_ops amba_pl010_pops =
|
||||||
|
.verify_port = pl010_verify_port,
|
||||||
|
};
|
||||||
|
|
||||||
|
-static struct uart_amba_port *amba_ports[UART_NR];
|
||||||
|
+static struct uart_amba_port *amba_ports[SERIAL_AMBA_NR];
|
||||||
|
|
||||||
|
#ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
|
||||||
|
|
||||||
|
@@ -564,10 +563,10 @@ static void pl010_console_putchar(struct
|
||||||
|
unsigned int status;
|
||||||
|
|
||||||
|
do {
|
||||||
|
- status = readb(uap->port.membase + UART01x_FR);
|
||||||
|
+ status = __raw_readl(uap->port.membase + UART01x_FR);
|
||||||
|
barrier();
|
||||||
|
} while (!UART_TX_READY(status));
|
||||||
|
- writel(ch, uap->port.membase + UART01x_DR);
|
||||||
|
+ __raw_writel(ch, uap->port.membase + UART01x_DR);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
@@ -581,8 +580,8 @@ pl010_console_write(struct console *co,
|
||||||
|
/*
|
||||||
|
* First save the CR then disable the interrupts
|
||||||
|
*/
|
||||||
|
- old_cr = readb(uap->port.membase + UART010_CR);
|
||||||
|
- writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
|
||||||
|
+ old_cr = __raw_readl(uap->port.membase + UART010_CR);
|
||||||
|
+ __raw_writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
|
||||||
|
|
||||||
|
uart_console_write(&uap->port, s, count, pl010_console_putchar);
|
||||||
|
|
||||||
|
@@ -591,10 +590,10 @@ pl010_console_write(struct console *co,
|
||||||
|
* and restore the TCR
|
||||||
|
*/
|
||||||
|
do {
|
||||||
|
- status = readb(uap->port.membase + UART01x_FR);
|
||||||
|
+ status = __raw_readl(uap->port.membase + UART01x_FR);
|
||||||
|
barrier();
|
||||||
|
} while (status & UART01x_FR_BUSY);
|
||||||
|
- writel(old_cr, uap->port.membase + UART010_CR);
|
||||||
|
+ __raw_writel(old_cr, uap->port.membase + UART010_CR);
|
||||||
|
|
||||||
|
clk_disable(uap->clk);
|
||||||
|
}
|
||||||
|
@@ -603,9 +602,9 @@ static void __init
|
||||||
|
pl010_console_get_options(struct uart_amba_port *uap, int *baud,
|
||||||
|
int *parity, int *bits)
|
||||||
|
{
|
||||||
|
- if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
|
||||||
|
+ if (__raw_readl(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
|
||||||
|
unsigned int lcr_h, quot;
|
||||||
|
- lcr_h = readb(uap->port.membase + UART010_LCRH);
|
||||||
|
+ lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
|
||||||
|
|
||||||
|
*parity = 'n';
|
||||||
|
if (lcr_h & UART01x_LCRH_PEN) {
|
||||||
|
@@ -620,8 +619,8 @@ pl010_console_get_options(struct uart_am
|
||||||
|
else
|
||||||
|
*bits = 8;
|
||||||
|
|
||||||
|
- quot = readb(uap->port.membase + UART010_LCRL) |
|
||||||
|
- readb(uap->port.membase + UART010_LCRM) << 8;
|
||||||
|
+ quot = __raw_readl(uap->port.membase + UART010_LCRL) |
|
||||||
|
+ __raw_readl(uap->port.membase + UART010_LCRM) << 8;
|
||||||
|
*baud = uap->port.uartclk / (16 * (quot + 1));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
@@ -639,7 +638,7 @@ static int __init pl010_console_setup(st
|
||||||
|
* if so, search for the first available port that does have
|
||||||
|
* console support.
|
||||||
|
*/
|
||||||
|
- if (co->index >= UART_NR)
|
||||||
|
+ if (co->index >= SERIAL_AMBA_NR)
|
||||||
|
co->index = 0;
|
||||||
|
uap = amba_ports[co->index];
|
||||||
|
if (!uap)
|
||||||
|
@@ -657,7 +656,7 @@ static int __init pl010_console_setup(st
|
||||||
|
|
||||||
|
static struct uart_driver amba_reg;
|
||||||
|
static struct console amba_console = {
|
||||||
|
- .name = "ttyAM",
|
||||||
|
+ .name = SERIAL_AMBA_NAME,
|
||||||
|
.write = pl010_console_write,
|
||||||
|
.device = uart_console_device,
|
||||||
|
.setup = pl010_console_setup,
|
||||||
|
@@ -673,11 +672,11 @@ static struct console amba_console = {
|
||||||
|
|
||||||
|
static struct uart_driver amba_reg = {
|
||||||
|
.owner = THIS_MODULE,
|
||||||
|
- .driver_name = "ttyAM",
|
||||||
|
- .dev_name = "ttyAM",
|
||||||
|
+ .driver_name = SERIAL_AMBA_NAME,
|
||||||
|
+ .dev_name = SERIAL_AMBA_NAME,
|
||||||
|
.major = SERIAL_AMBA_MAJOR,
|
||||||
|
.minor = SERIAL_AMBA_MINOR,
|
||||||
|
- .nr = UART_NR,
|
||||||
|
+ .nr = SERIAL_AMBA_NR,
|
||||||
|
.cons = AMBA_CONSOLE,
|
||||||
|
};
|
||||||
|
|
||||||
|
--- a/drivers/serial/Kconfig
|
||||||
|
+++ b/drivers/serial/Kconfig
|
||||||
|
@@ -284,10 +284,25 @@ config SERIAL_AMBA_PL010
|
||||||
|
help
|
||||||
|
This selects the ARM(R) AMBA(R) PrimeCell PL010 UART. If you have
|
||||||
|
an Integrator/AP or Integrator/PP2 platform, or if you have a
|
||||||
|
- Cirrus Logic EP93xx CPU, say Y or M here.
|
||||||
|
+ Cirrus Logic EP93xx CPU or an Infineon ADM5120 SOC, say Y or M here.
|
||||||
|
|
||||||
|
If unsure, say N.
|
||||||
|
|
||||||
|
+config SERIAL_AMBA_PL010_NUMPORTS
|
||||||
|
+ int "Maximum number of AMBA PL010 serial ports"
|
||||||
|
+ depends on SERIAL_AMBA_PL010
|
||||||
|
+ default "8"
|
||||||
|
+ ---help---
|
||||||
|
+ Set this to the number of serial ports you want the AMBA PL010 driver
|
||||||
|
+ to support.
|
||||||
|
+
|
||||||
|
+config SERIAL_AMBA_PL010_PORTNAME
|
||||||
|
+ string "Name of the AMBA PL010 serial ports"
|
||||||
|
+ depends on SERIAL_AMBA_PL010
|
||||||
|
+ default "ttyAM"
|
||||||
|
+ ---help---
|
||||||
|
+ ::: To be written :::
|
||||||
|
+
|
||||||