mirror of https://github.com/hak5/openwrt-owl.git
John Crispin
parent
cce622bcb8
commit
880d600f71
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@ -46,6 +46,7 @@ CONFIG_DANUBE_GPIO=y
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CONFIG_DANUBE_LED=y
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CONFIG_DANUBE_LED=y
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CONFIG_DANUBE_MII0=y
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CONFIG_DANUBE_MII0=y
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CONFIG_DANUBE_MII1=y
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CONFIG_DANUBE_MII1=y
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CONFIG_DANUBE_SSC=y
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CONFIG_DANUBE_WDT=y
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CONFIG_DANUBE_WDT=y
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CONFIG_DEVPORT=y
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CONFIG_DEVPORT=y
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# CONFIG_DM9000 is not set
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# CONFIG_DM9000 is not set
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@ -24,6 +24,10 @@ config DANUBE_GPIO
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bool "Danube gpio"
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bool "Danube gpio"
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default y
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default y
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config DANUBE_SSC
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bool "Danube ssc"
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default y
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config DANUBE_EEPROM
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config DANUBE_EEPROM
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bool "Danube eeprom"
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bool "Danube eeprom"
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default y
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default y
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@ -1,38 +1,4 @@
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/******************************************************************************
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**
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** FILE NAME : danube_eeprom.c
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** PROJECT : Danube
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** MODULES : EEPROM
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**
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** DATE : 31 DEC 2004
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** AUTHOR : Liu Peng
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** DESCRIPTION : X25040 EEPROM Driver
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** COPYRIGHT : Copyright (c) 2006
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** Infineon Technologies AG
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** Am Campeon 1-12, 85579 Neubiberg, Germany
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**
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** This program is free software; you can redistribute it and/or modify
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** it under the terms of the GNU General Public License as published by
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** the Free Software Foundation; either version 2 of the License, or
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** (at your option) any later version.
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**
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** HISTORY
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** $Date $Author $Comment
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** 31 DEC 2004 Liu Peng Initiate Version
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** 25 OCT 2006 Xu Liang Add GPL header.
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*******************************************************************************/
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#define IFAP_EEPROM_DRV_VERSION "0.0.1"
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/*
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/*
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**************************************************
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*
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* This driver was originally based on the INCA-IP driver, but due to
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* fundamental conceptual drawbacks there has been changed a lot.
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*
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* Based on INCA-IP driver Copyright (c) 2003 Gary Jennejohn <gj@denx.de>
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* Based on the VxWorks drivers Copyright (c) 2002, Infineon Technologies.
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* the Free Software Foundation; either version 2 of the License, or
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@ -45,13 +11,21 @@
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*
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*
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* You should have received a copy of the GNU General Public License
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* This driver was originally based on the INCA-IP driver, but due to
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* fundamental conceptual drawbacks there has been changed a lot.
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*
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* Based on INCA-IP driver Copyright (c) 2003 Gary Jennejohn <gj@denx.de>
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* Based on the VxWorks drivers Copyright (c) 2002, Infineon Technologies.
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*
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* Copyright (C) 2006 infineon
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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*
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*
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*/
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*/
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#ifndef EXPORT_SYMTAB
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#define EXPORT_SYMTAB
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#define IFAP_EEPROM_DRV_VERSION "0.0.1"
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#endif
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/errno.h>
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#include <linux/signal.h>
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#include <linux/signal.h>
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@ -61,7 +35,6 @@
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#include <linux/major.h>
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#include <linux/major.h>
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#include <linux/string.h>
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#include <linux/string.h>
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#include <linux/fs.h>
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#include <linux/fs.h>
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#include <linux/proc_fs.h>
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#include <linux/fcntl.h>
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#include <linux/fcntl.h>
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#include <linux/ptrace.h>
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#include <linux/ptrace.h>
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#include <linux/mm.h>
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#include <linux/mm.h>
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@ -81,33 +54,15 @@
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#include <linux/version.h>
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#include <linux/version.h>
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#include <asm/danube/danube.h>
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#include <asm/danube/danube.h>
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#include <asm/danube/irq.h>
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#include <asm/danube/danube_irq.h>
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#include <asm/danube/ifx_ssc_defines.h>
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#include <asm/danube/ifx_ssc_defines.h>
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#include <asm/danube/ifx_ssc.h>
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#include <asm/danube/ifx_ssc.h>
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#if CONFIG_MODVERSIONS==1
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# include <linux/modversions.h>
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#endif
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#define AMAZON_EEPROM_EMSG(fmt,args...) printk("%s:" fmt, __FUNCTION__, ##args)
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#if 0
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#define AMAZON_EEPROM_DMSG(fmt,args...) printk("%s:" fmt, __FUNCTION__, ##args)
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#else
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#define AMAZON_EEPROM_DMSG(fmt,args...)
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#endif
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MODULE_LICENSE ("GPL");
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MODULE_AUTHOR ("Peng Liu");
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MODULE_DESCRIPTION ("IFAP EEPROM driver");
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MODULE_SUPPORTED_DEVICE ("danube_eeprom");
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MODULE_PARM (maj, "i");
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MODULE_PARM_DESC (maj, "Major device number");
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/* allow the user to set the major device number */
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/* allow the user to set the major device number */
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static int maj = 0;
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static int danube_eeprom_maj = 0;
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static ssize_t danube_eeprom_read (struct file *, char *, size_t, loff_t *);
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static ssize_t danube_eeprom_fops_read (struct file *, char *, size_t, loff_t *);
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static ssize_t danube_eeprom_write (struct file *, const char *, size_t,
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static ssize_t danube_eeprom_fops_write (struct file *, const char *, size_t,
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loff_t *);
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loff_t *);
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static int danube_eeprom_ioctl (struct inode *, struct file *, unsigned int,
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static int danube_eeprom_ioctl (struct inode *, struct file *, unsigned int,
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unsigned long);
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unsigned long);
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@ -124,284 +79,277 @@ extern int ifx_ssc_ioctl (struct inode *inode, struct file *filp,
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extern ssize_t ifx_ssc_kwrite (int port, const char *kbuf, size_t len);
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extern ssize_t ifx_ssc_kwrite (int port, const char *kbuf, size_t len);
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extern ssize_t ifx_ssc_kread (int port, char *kbuf, size_t len);
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extern ssize_t ifx_ssc_kread (int port, char *kbuf, size_t len);
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extern int ifx_ssc_cs_low (u32 pin);
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extern int ifx_ssc_cs_low (unsigned int pin);
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extern int ifx_ssc_cs_high (u32 pin);
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extern int ifx_ssc_cs_high (unsigned int pin);
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extern int ifx_ssc_txrx (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len);
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extern int ifx_ssc_txrx (char *tx_buf, unsigned int tx_len, char *rx_buf, unsigned int rx_len);
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extern int ifx_ssc_tx (char *tx_buf, u32 tx_len);
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extern int ifx_ssc_tx (char *tx_buf, unsigned int tx_len);
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extern int ifx_ssc_rx (char *rx_buf, u32 rx_len);
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extern int ifx_ssc_rx (char *rx_buf, unsigned int rx_len);
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/* CS: board dependant */
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#define EEPROM_CS IFX_SSC_WHBGPOSTAT_OUT0_POS
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#define EEPROM_CS IFX_SSC_WHBGPOSTAT_OUT0_POS
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/* commands for EEPROM, x25160, x25140 */
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/* commands for EEPROM, x25160, x25140 */
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#define EEPROM_WREN ((u8)0x06)
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#define EEPROM_WREN ((unsigned char)0x06)
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#define EEPROM_WRDI ((u8)0x04)
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#define EEPROM_WRDI ((unsigned char)0x04)
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#define EEPROM_RDSR ((u8)0x05)
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#define EEPROM_RDSR ((unsigned char)0x05)
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#define EEPROM_WRSR ((u8)0x01)
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#define EEPROM_WRSR ((unsigned char)0x01)
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#define EEPROM_READ ((u8)0x03)
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#define EEPROM_READ ((unsigned char)0x03)
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#define EEPROM_WRITE ((u8)0x02)
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#define EEPROM_WRITE ((unsigned char)0x02)
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#define EEPROM_PAGE_SIZE 4
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#define EEPROM_PAGE_SIZE 4
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#define EEPROM_SIZE 512
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#define EEPROM_SIZE 512
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/* Brief: EEPROM_RDSR command
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* Return: 0 OK
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* error code
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*/
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static int
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static int
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eeprom_rdsr (char *status)
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eeprom_rdsr (char *status)
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{
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{
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int ret = 0;
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int ret = 0;
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unsigned char cmd = EEPROM_RDSR;
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unsigned char cmd = EEPROM_RDSR;
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unsigned long flag;
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unsigned long flag;
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local_irq_save (flag);
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if ((ret = ifx_ssc_cs_low (EEPROM_CS))) {
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local_irq_save(flag);
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local_irq_restore (flag);
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return ret;
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if ((ret = ifx_ssc_cs_low (EEPROM_CS)))
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}
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{
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if ((ret = ifx_ssc_txrx (&cmd, 1, status, 1)) < 0) {
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local_irq_restore(flag);
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ifx_ssc_cs_high (EEPROM_CS);
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goto out;
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local_irq_restore (flag);
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return ret;
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}
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}
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if ((ret = ifx_ssc_cs_high (EEPROM_CS))) {
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if ((ret = ifx_ssc_txrx (&cmd, 1, status, 1)) < 0)
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local_irq_restore (flag);
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{
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return ret;
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ifx_ssc_cs_high(EEPROM_CS);
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local_irq_restore(flag);
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goto out;
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}
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}
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local_irq_restore (flag);
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if ((ret = ifx_ssc_cs_high(EEPROM_CS)))
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{
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local_irq_restore(flag);
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goto out;
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}
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local_irq_restore(flag);
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out:
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return ret;
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return ret;
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}
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}
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/* Brief: wait for WIP is over
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* Return:
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* 0 WIP is over
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* <0 Error code
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*/
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static inline int
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static inline int
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eeprom_wip_over (void)
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eeprom_wip_over (void)
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{
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{
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int ret = 0;
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int ret = 0;
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u8 status;
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unsigned char status;
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while (1) {
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ret = eeprom_rdsr (&status);
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while (1)
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AMAZON_EEPROM_DMSG ("status %x \n", status);
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{
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if (ret) {
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ret = eeprom_rdsr(&status);
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AMAZON_EEPROM_EMSG ("read back status fails %d\n",
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printk("status %x \n", status);
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ret);
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if (ret)
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{
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printk("read back status fails %d\n", ret);
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break;
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break;
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}
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}
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else if (((status) & 1) != 0) {
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AMAZON_EEPROM_DMSG ("read back status not zero %x\n",
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if (((status) & 1) != 0)
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status);
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printk("read back status not zero %x\n", status);
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}
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else
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else {
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break;
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break;
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}
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}
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}
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return ret;
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return ret;
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}
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}
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/* Brief: EEPROM_WREN command
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* Return: 0 OK
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* error code
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*/
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static int
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static int
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eeprom_wren (void)
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eeprom_wren (void)
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{
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{
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unsigned char cmd = EEPROM_WREN;
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unsigned char cmd = EEPROM_WREN;
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int ret = 0;
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int ret = 0;
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unsigned long flag;
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unsigned long flag;
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local_irq_save (flag);
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if ((ret = ifx_ssc_cs_low (EEPROM_CS))) {
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local_irq_save(flag);
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local_irq_restore (flag);
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if ((ret = ifx_ssc_cs_low(EEPROM_CS)))
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return ret;
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{
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local_irq_restore(flag);
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goto out;
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}
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}
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if ((ret = ifx_ssc_tx (&cmd, 1)) < 0) {
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if ((ret = ifx_ssc_tx(&cmd, 1)) < 0)
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ifx_ssc_cs_high (EEPROM_CS);
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{
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local_irq_restore (flag);
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ifx_ssc_cs_high(EEPROM_CS);
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return ret;
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local_irq_restore(flag);
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goto out;
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}
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}
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if ((ret = ifx_ssc_cs_high (EEPROM_CS))) {
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if ((ret = ifx_ssc_cs_high(EEPROM_CS)))
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local_irq_restore (flag);
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{
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return ret;
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local_irq_restore(flag);
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goto out;
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}
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}
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local_irq_restore (flag);
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eeprom_wip_over ();
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return ret;
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local_irq_restore(flag);
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eeprom_wip_over();
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out:
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return ret;
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}
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}
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/* Brief: EEPROM_WRSR command
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* Return: 0 OK
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* error code
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*/
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static int
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static int
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eeprom_wrsr (void)
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eeprom_wrsr (void)
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{
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{
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int ret = 0;
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int ret = 0;
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unsigned char cmd[2];
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unsigned char cmd[2];
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unsigned long flag;
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cmd[0] = EEPROM_WRSR;
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cmd[0] = EEPROM_WRSR;
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cmd[1] = 0;
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cmd[1] = 0;
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if ((ret = eeprom_wren ())) {
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AMAZON_EEPROM_EMSG ("eeprom_wren fails\n");
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if ((ret = eeprom_wren()))
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return ret;
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{
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}
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printk ("eeprom_wren fails\n");
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unsigned long flag;
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goto out1;
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local_irq_save (flag);
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if ((ret = ifx_ssc_cs_low (EEPROM_CS))) {
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goto eeprom_wrsr_err_out;
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}
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}
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if ((ret = ifx_ssc_tx (cmd, 2)) < 0) {
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local_irq_save(flag);
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ifx_ssc_cs_high (EEPROM_CS);
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goto eeprom_wrsr_err_out;
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if ((ret = ifx_ssc_cs_low(EEPROM_CS)))
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goto out;
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if ((ret = ifx_ssc_tx(cmd, 2)) < 0) {
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ifx_ssc_cs_high(EEPROM_CS);
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goto out;
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}
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}
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||||||
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if ((ret = ifx_ssc_cs_low (EEPROM_CS))) {
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if ((ret = ifx_ssc_cs_low(EEPROM_CS)))
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goto eeprom_wrsr_err_out;
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goto out;
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}
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local_irq_restore (flag);
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local_irq_restore(flag);
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eeprom_wip_over ();
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eeprom_wip_over();
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return ret;
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return ret;
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eeprom_wrsr_err_out:
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out:
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local_irq_restore (flag);
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local_irq_restore (flag);
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eeprom_wip_over ();
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eeprom_wip_over ();
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out1:
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return ret;
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return ret;
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}
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}
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|
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/* Brief: read EEPROM
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|
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* Parameter:
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* addr
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* len
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* buf
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* Return: ok
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* -EFAULT
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*/
|
|
||||||
static int
|
static int
|
||||||
eeprom_read (u32 addr, unsigned char *buf, u32 len)
|
eeprom_read (unsigned int addr, unsigned char *buf, unsigned int len)
|
||||||
{
|
{
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
unsigned char write_buf[2];
|
unsigned char write_buf[2];
|
||||||
u32 eff = 0;
|
unsigned int eff = 0;
|
||||||
|
|
||||||
unsigned long flag;
|
unsigned long flag;
|
||||||
|
|
||||||
while (1) {
|
while (1)
|
||||||
eeprom_wip_over ();
|
{
|
||||||
|
eeprom_wip_over();
|
||||||
eff = EEPROM_PAGE_SIZE - (addr % EEPROM_PAGE_SIZE);
|
eff = EEPROM_PAGE_SIZE - (addr % EEPROM_PAGE_SIZE);
|
||||||
eff = (eff < len) ? eff : len;
|
eff = (eff < len) ? eff : len;
|
||||||
//Format:
|
local_irq_save(flag);
|
||||||
//CMD + ADDR
|
|
||||||
local_irq_save (flag);
|
|
||||||
if ((ret = ifx_ssc_cs_low (EEPROM_CS)) < 0) {
|
|
||||||
goto eeprom_read_err_out;
|
|
||||||
}
|
|
||||||
|
|
||||||
write_buf[0] = EEPROM_READ | ((u8) ((addr & 0x100) >> 5));
|
if ((ret = ifx_ssc_cs_low(EEPROM_CS)) < 0)
|
||||||
|
goto out;
|
||||||
|
|
||||||
|
write_buf[0] = EEPROM_READ | ((unsigned char) ((addr & 0x100) >> 5));
|
||||||
write_buf[1] = (addr & 0xff);
|
write_buf[1] = (addr & 0xff);
|
||||||
|
|
||||||
if ((ret = ifx_ssc_txrx (write_buf, 2, buf, eff)) != eff) {
|
if ((ret = ifx_ssc_txrx (write_buf, 2, buf, eff)) != eff)
|
||||||
AMAZON_EEPROM_EMSG ("ssc_txrx fails %d\n", ret);
|
{
|
||||||
|
printk("ssc_txrx fails %d\n", ret);
|
||||||
ifx_ssc_cs_high (EEPROM_CS);
|
ifx_ssc_cs_high (EEPROM_CS);
|
||||||
goto eeprom_read_err_out;
|
goto out;
|
||||||
}
|
}
|
||||||
|
|
||||||
buf += ret;
|
buf += ret;
|
||||||
len -= ret;
|
len -= ret;
|
||||||
addr += ret;
|
addr += ret;
|
||||||
if ((ret = ifx_ssc_cs_high (EEPROM_CS))) {
|
|
||||||
goto eeprom_read_err_out;
|
if ((ret = ifx_ssc_cs_high(EEPROM_CS)))
|
||||||
}
|
goto out;
|
||||||
local_irq_restore (flag);
|
|
||||||
if (len <= 0) {
|
local_irq_restore(flag);
|
||||||
break;
|
|
||||||
}
|
if (len <= 0)
|
||||||
|
goto out2;
|
||||||
}
|
}
|
||||||
|
|
||||||
return ret;
|
out:
|
||||||
eeprom_read_err_out:
|
|
||||||
local_irq_restore (flag);
|
local_irq_restore (flag);
|
||||||
|
out2:
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Brief: write EEPROm
|
|
||||||
* Parameter:
|
|
||||||
* addr
|
|
||||||
* len
|
|
||||||
* buf
|
|
||||||
* Return: 0 ok
|
|
||||||
* -EFAULT
|
|
||||||
*/
|
|
||||||
static int
|
static int
|
||||||
eeprom_write (u32 addr, unsigned char *buf, u32 len)
|
eeprom_write (unsigned int addr, unsigned char *buf, unsigned int len)
|
||||||
{
|
{
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
u32 eff = 0;
|
unsigned int eff = 0;
|
||||||
unsigned char write_buf[2];
|
unsigned char write_buf[2];
|
||||||
|
|
||||||
//unsigned char rx_buf[EEPROM_PAGE_SIZE];
|
|
||||||
//Format:
|
|
||||||
//CMD + ADDR + DATA (up to EEPROM_PAGE_SIZE)
|
|
||||||
while (1) {
|
|
||||||
eeprom_wip_over ();
|
|
||||||
if ((ret = eeprom_wren ())) {
|
|
||||||
AMAZON_EEPROM_EMSG ("eeprom_wren fails\n");
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
write_buf[0] = EEPROM_WRITE | ((u8) ((addr & 0x100) >> 5));
|
|
||||||
write_buf[1] = (addr & 0xff);
|
|
||||||
|
|
||||||
eff = EEPROM_PAGE_SIZE - (addr % EEPROM_PAGE_SIZE);
|
|
||||||
eff = (eff < len) ? eff : len;
|
|
||||||
AMAZON_EEPROM_DMSG ("EEPROM Write:\n");
|
|
||||||
#if 0
|
|
||||||
int i;
|
int i;
|
||||||
|
unsigned char rx_buf[EEPROM_PAGE_SIZE];
|
||||||
|
|
||||||
|
while (1)
|
||||||
|
{
|
||||||
|
eeprom_wip_over();
|
||||||
|
|
||||||
|
if ((ret = eeprom_wren()))
|
||||||
|
{
|
||||||
|
printk("eeprom_wren fails\n");
|
||||||
|
goto out;
|
||||||
|
}
|
||||||
|
|
||||||
|
write_buf[0] = EEPROM_WRITE | ((unsigned char) ((addr & 0x100) >> 5));
|
||||||
|
write_buf[1] = (addr & 0xff);
|
||||||
|
|
||||||
|
eff = EEPROM_PAGE_SIZE - (addr % EEPROM_PAGE_SIZE);
|
||||||
|
eff = (eff < len) ? eff : len;
|
||||||
|
|
||||||
|
printk("EEPROM Write:\n");
|
||||||
for (i = 0; i < eff; i++) {
|
for (i = 0; i < eff; i++) {
|
||||||
printk ("%2x ", buf[i]);
|
printk("%2x ", buf[i]);
|
||||||
if (i % 16 == 15)
|
if ((i % 16) == 15)
|
||||||
printk ("\n");
|
printk("\n");
|
||||||
}
|
}
|
||||||
printk ("\n");
|
printk("\n");
|
||||||
#endif
|
|
||||||
|
|
||||||
if ((ret = ifx_ssc_cs_low (EEPROM_CS))) {
|
if ((ret = ifx_ssc_cs_low(EEPROM_CS)))
|
||||||
return ret;
|
goto out;
|
||||||
|
|
||||||
|
if ((ret = ifx_ssc_tx (write_buf, 2)) < 0)
|
||||||
|
{
|
||||||
|
printk("ssc_tx fails %d\n", ret);
|
||||||
|
ifx_ssc_cs_high(EEPROM_CS);
|
||||||
|
goto out;
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((ret = ifx_ssc_tx (write_buf, 2)) < 0) {
|
if ((ret = ifx_ssc_tx (buf, eff)) != eff)
|
||||||
AMAZON_EEPROM_EMSG ("ssc_tx fails %d\n", ret);
|
{
|
||||||
ifx_ssc_cs_high (EEPROM_CS);
|
printk("ssc_tx fails %d\n", ret);
|
||||||
return ret;
|
ifx_ssc_cs_high(EEPROM_CS);
|
||||||
}
|
goto out;
|
||||||
|
|
||||||
if ((ret = ifx_ssc_tx (buf, eff)) != eff) {
|
|
||||||
AMAZON_EEPROM_EMSG ("ssc_tx fails %d\n", ret);
|
|
||||||
ifx_ssc_cs_high (EEPROM_CS);
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
buf += ret;
|
buf += ret;
|
||||||
len -= ret;
|
len -= ret;
|
||||||
addr += ret;
|
addr += ret;
|
||||||
|
|
||||||
if ((ret = ifx_ssc_cs_high (EEPROM_CS))) {
|
if ((ret = ifx_ssc_cs_high (EEPROM_CS)))
|
||||||
return ret;
|
goto out;
|
||||||
}
|
|
||||||
#if 0
|
|
||||||
printk ("<==");
|
printk ("<==");
|
||||||
eeprom_read ((addr - eff), rx_buf, eff);
|
eeprom_read((addr - eff), rx_buf, eff);
|
||||||
for (i = 0; i < eff; i++) {
|
for (i = 0; i < eff; i++)
|
||||||
|
{
|
||||||
printk ("[%x]", rx_buf[i]);
|
printk ("[%x]", rx_buf[i]);
|
||||||
}
|
}
|
||||||
printk ("\n");
|
printk ("\n");
|
||||||
#endif
|
|
||||||
if (len <= 0)
|
if (len <= 0)
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
out:
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -419,139 +367,156 @@ danube_eeprom_close (struct inode *inode, struct file *filp)
|
||||||
}
|
}
|
||||||
|
|
||||||
int
|
int
|
||||||
danube_eeprom_ioctl (struct inode *inode, struct file *filp, unsigned int cmd,
|
danube_eeprom_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data)
|
||||||
unsigned long data)
|
|
||||||
{
|
{
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
ssize_t
|
ssize_t
|
||||||
danube_eeprom_kread (char *buf, size_t len, u32 addr)
|
danube_eeprom_read (char *buf, size_t len, unsigned int addr)
|
||||||
{
|
{
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
u32 data;
|
unsigned int data;
|
||||||
printk ("addr:=%d\n", addr);
|
|
||||||
printk ("len:=%d\n", len);
|
printk("addr:=%d\n", addr);
|
||||||
if ((addr + len) > EEPROM_SIZE) {
|
printk("len:=%d\n", len);
|
||||||
AMAZON_EEPROM_EMSG ("invalid len\n");
|
|
||||||
|
if ((addr + len) > EEPROM_SIZE)
|
||||||
|
{
|
||||||
|
printk("invalid len\n");
|
||||||
addr = 0;
|
addr = 0;
|
||||||
len = EEPROM_SIZE / 2;
|
len = EEPROM_SIZE / 2;
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((ret = ifx_ssc_open ((struct inode *) 0, NULL))) {
|
if ((ret = ifx_ssc_open ((struct inode *) 0, NULL)))
|
||||||
AMAZON_EEPROM_EMSG ("danube_eeprom_open fails\n");
|
{
|
||||||
goto read_err_out;
|
printk("danube_eeprom_open fails\n");
|
||||||
|
goto out;
|
||||||
}
|
}
|
||||||
|
|
||||||
data = (u32) IFX_SSC_MODE_RXTX;
|
data = (unsigned int)IFX_SSC_MODE_RXTX;
|
||||||
if ((ret =
|
|
||||||
ifx_ssc_ioctl ((struct inode *) 0, NULL, IFX_SSC_RXTX_MODE_SET,
|
if ((ret = ifx_ssc_ioctl ((struct inode *) 0, NULL, IFX_SSC_RXTX_MODE_SET, (unsigned long) &data)))
|
||||||
(unsigned long) &data))) {
|
{
|
||||||
AMAZON_EEPROM_EMSG ("set RXTX mode fails\n");
|
printk("set RXTX mode fails\n");
|
||||||
goto read_err_out;
|
goto out;
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((ret = eeprom_wrsr ())) {
|
if ((ret = eeprom_wrsr ()))
|
||||||
AMAZON_EEPROM_EMSG ("EEPROM reset fails\n");
|
{
|
||||||
goto read_err_out;
|
printk("EEPROM reset fails\n");
|
||||||
|
goto out;
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((ret = eeprom_read (addr, buf, len))) {
|
if ((ret = eeprom_read (addr, buf, len)))
|
||||||
AMAZON_EEPROM_EMSG ("eeprom read fails\n");
|
{
|
||||||
goto read_err_out;
|
printk("eeprom read fails\n");
|
||||||
|
goto out;
|
||||||
}
|
}
|
||||||
|
|
||||||
read_err_out:
|
out:
|
||||||
if (ifx_ssc_close ((struct inode *) 0, NULL)) {
|
if (ifx_ssc_close ((struct inode *) 0, NULL))
|
||||||
AMAZON_EEPROM_EMSG ("danube_eeprom_close fails\n");
|
printk("danube_eeprom_close fails\n");
|
||||||
}
|
|
||||||
return len;
|
return len;
|
||||||
|
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL(danube_eeprom_read);
|
||||||
EXPORT_SYMBOL (danube_eeprom_kread);
|
|
||||||
|
|
||||||
static ssize_t
|
static ssize_t
|
||||||
danube_eeprom_read (struct file *filp, char *ubuf, size_t len, loff_t * off)
|
danube_eeprom_fops_read (struct file *filp, char *ubuf, size_t len, loff_t * off)
|
||||||
{
|
{
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
unsigned char ssc_rx_buf[EEPROM_SIZE];
|
unsigned char ssc_rx_buf[EEPROM_SIZE];
|
||||||
long flag;
|
long flag;
|
||||||
|
|
||||||
if (*off >= EEPROM_SIZE)
|
if (*off >= EEPROM_SIZE)
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
if (*off + len > EEPROM_SIZE)
|
if (*off + len > EEPROM_SIZE)
|
||||||
len = EEPROM_SIZE - *off;
|
len = EEPROM_SIZE - *off;
|
||||||
|
|
||||||
if (len == 0)
|
if (len == 0)
|
||||||
return 0;
|
return 0;
|
||||||
local_irq_save (flag);
|
|
||||||
if ((ret = danube_eeprom_kread (ssc_rx_buf, len, *off)) < 0) {
|
local_irq_save(flag);
|
||||||
AMAZON_EEPROM_EMSG ("read fails, err=%x\n", ret);
|
|
||||||
local_irq_restore (flag);
|
if ((ret = danube_eeprom_read(ssc_rx_buf, len, *off)) < 0)
|
||||||
|
{
|
||||||
|
printk("read fails, err=%x\n", ret);
|
||||||
|
local_irq_restore(flag);
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
if (copy_to_user ((void *) ubuf, ssc_rx_buf, ret) != 0) {
|
|
||||||
local_irq_restore (flag);
|
if (copy_to_user((void*)ubuf, ssc_rx_buf, ret) != 0)
|
||||||
|
{
|
||||||
|
local_irq_restore(flag);
|
||||||
ret = -EFAULT;
|
ret = -EFAULT;
|
||||||
}
|
}
|
||||||
local_irq_restore (flag);
|
|
||||||
|
local_irq_restore(flag);
|
||||||
*off += len;
|
*off += len;
|
||||||
|
|
||||||
return len;
|
return len;
|
||||||
}
|
}
|
||||||
|
|
||||||
ssize_t
|
ssize_t
|
||||||
danube_eeprom_kwrite (char *buf, size_t len, u32 addr)
|
danube_eeprom_write (char *buf, size_t len, unsigned int addr)
|
||||||
{
|
{
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
u32 data;
|
unsigned int data;
|
||||||
if ((ret = ifx_ssc_open ((struct inode *) 0, NULL))) {
|
|
||||||
AMAZON_EEPROM_EMSG ("danube_eeprom_open fails\n");
|
if ((ret = ifx_ssc_open ((struct inode *) 0, NULL)))
|
||||||
goto write_err_out;
|
{
|
||||||
|
printk ("danube_eeprom_open fails\n");
|
||||||
|
goto out;
|
||||||
}
|
}
|
||||||
|
|
||||||
data = (u32) IFX_SSC_MODE_RXTX;
|
data = (unsigned int) IFX_SSC_MODE_RXTX;
|
||||||
if ((ret =
|
|
||||||
ifx_ssc_ioctl ((struct inode *) 0, NULL, IFX_SSC_RXTX_MODE_SET,
|
if ((ret = ifx_ssc_ioctl ((struct inode *) 0, NULL, IFX_SSC_RXTX_MODE_SET, (unsigned long) &data)))
|
||||||
(unsigned long) &data))) {
|
{
|
||||||
AMAZON_EEPROM_EMSG ("set RXTX mode fails\n");
|
printk ("set RXTX mode fails\n");
|
||||||
goto write_err_out;
|
goto out;
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((ret = eeprom_wrsr ())) {
|
if ((ret = eeprom_wrsr ())) {
|
||||||
AMAZON_EEPROM_EMSG ("EEPROM reset fails\n");
|
printk ("EEPROM reset fails\n");
|
||||||
goto write_err_out;
|
goto out;
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((ret = eeprom_write (addr, buf, len))) {
|
if ((ret = eeprom_write (addr, buf, len))) {
|
||||||
AMAZON_EEPROM_EMSG ("eeprom write fails\n");
|
printk ("eeprom write fails\n");
|
||||||
goto write_err_out;
|
goto out;
|
||||||
}
|
}
|
||||||
|
|
||||||
write_err_out:
|
out:
|
||||||
if (ifx_ssc_close ((struct inode *) 0, NULL)) {
|
if (ifx_ssc_close ((struct inode *) 0, NULL))
|
||||||
AMAZON_EEPROM_EMSG ("danube_eeprom_close fails\n");
|
printk ("danube_eeprom_close fails\n");
|
||||||
}
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL(danube_eeprom_write);
|
||||||
EXPORT_SYMBOL (danube_eeprom_kwrite);
|
|
||||||
|
|
||||||
static ssize_t
|
static ssize_t
|
||||||
danube_eeprom_write (struct file *filp, const char *ubuf, size_t len,
|
danube_eeprom_fops_write (struct file *filp, const char *ubuf, size_t len, loff_t * off)
|
||||||
loff_t * off)
|
|
||||||
{
|
{
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
unsigned char ssc_tx_buf[EEPROM_SIZE];
|
unsigned char ssc_tx_buf[EEPROM_SIZE];
|
||||||
|
|
||||||
if (*off >= EEPROM_SIZE)
|
if (*off >= EEPROM_SIZE)
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
if (len + *off > EEPROM_SIZE)
|
if (len + *off > EEPROM_SIZE)
|
||||||
len = EEPROM_SIZE - *off;
|
len = EEPROM_SIZE - *off;
|
||||||
if ((ret = copy_from_user (ssc_tx_buf, ubuf, len))) {
|
|
||||||
|
if ((ret = copy_from_user (ssc_tx_buf, ubuf, len)))
|
||||||
return EFAULT;
|
return EFAULT;
|
||||||
}
|
|
||||||
ret = danube_eeprom_kwrite (ssc_tx_buf, len, *off);
|
ret = danube_eeprom_write (ssc_tx_buf, len, *off);
|
||||||
if (ret > 0) {
|
|
||||||
|
if (ret > 0)
|
||||||
*off = ret;
|
*off = ret;
|
||||||
}
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -560,33 +525,34 @@ danube_eeprom_llseek (struct file * filp, loff_t off, int whence)
|
||||||
{
|
{
|
||||||
loff_t newpos;
|
loff_t newpos;
|
||||||
switch (whence) {
|
switch (whence) {
|
||||||
case 0: /*SEEK_SET */
|
case SEEK_SET:
|
||||||
newpos = off;
|
newpos = off;
|
||||||
break;
|
break;
|
||||||
case 1: /*SEEK_CUR */
|
|
||||||
|
case SEEK_CUR:
|
||||||
newpos = filp->f_pos + off;
|
newpos = filp->f_pos + off;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (newpos < 0)
|
if (newpos < 0)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
filp->f_pos = newpos;
|
filp->f_pos = newpos;
|
||||||
|
|
||||||
return newpos;
|
return newpos;
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct file_operations danube_eeprom_fops = {
|
static struct file_operations danube_eeprom_fops = {
|
||||||
owner:THIS_MODULE,
|
owner:THIS_MODULE,
|
||||||
llseek:danube_eeprom_llseek,
|
llseek:danube_eeprom_llseek,
|
||||||
/* llseek */
|
read:danube_eeprom_fops_read,
|
||||||
read:danube_eeprom_read, /* read */
|
write:danube_eeprom_fops_write,
|
||||||
write:danube_eeprom_write,
|
|
||||||
/* write */
|
|
||||||
ioctl:danube_eeprom_ioctl,
|
ioctl:danube_eeprom_ioctl,
|
||||||
/* ioctl */
|
open:danube_eeprom_open,
|
||||||
open:danube_eeprom_open, /* open */
|
|
||||||
release:danube_eeprom_close,
|
release:danube_eeprom_close,
|
||||||
/* release */
|
|
||||||
};
|
};
|
||||||
|
|
||||||
int __init
|
int __init
|
||||||
|
|
@ -594,46 +560,37 @@ danube_eeprom_init (void)
|
||||||
{
|
{
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
|
|
||||||
if ((ret = register_chrdev (maj, "eeprom", &danube_eeprom_fops)) < 0) {
|
danube_eeprom_maj = register_chrdev(0, "eeprom", &danube_eeprom_fops);
|
||||||
printk ("Unable to register major %d for the Infineon Amazon EEPROM\n", maj);
|
|
||||||
if (maj == 0) {
|
if (danube_eeprom_maj < 0)
|
||||||
goto errout;
|
{
|
||||||
|
printk("failed to register eeprom device\n");
|
||||||
|
ret = -EINVAL;
|
||||||
|
|
||||||
|
goto out;
|
||||||
}
|
}
|
||||||
else {
|
|
||||||
maj = 0;
|
printk("danube_eeprom : /dev/eeprom mayor %d\n", danube_eeprom_maj);
|
||||||
if ((ret =
|
|
||||||
register_chrdev (maj, "ssc",
|
out:
|
||||||
&danube_eeprom_fops)) < 0) {
|
|
||||||
printk ("Unable to register major 0 for the Infineon Amazon EEPROM\n");
|
|
||||||
goto errout;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (maj == 0)
|
|
||||||
maj = ret;
|
|
||||||
errout:
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
void __exit
|
void __exit
|
||||||
danube_eeprom_cleanup_module (void)
|
danube_eeprom_cleanup_module (void)
|
||||||
{
|
{
|
||||||
if (unregister_chrdev (maj, "eeprom")) {
|
/*if (unregister_chrdev (danube_eeprom_maj, "eeprom")) {
|
||||||
printk ("Unable to unregister major %d for the EEPROM\n",
|
printk ("Unable to unregister major %d for the EEPROM\n",
|
||||||
maj);
|
maj);
|
||||||
}
|
}*/
|
||||||
}
|
}
|
||||||
|
|
||||||
module_exit (danube_eeprom_cleanup_module);
|
module_exit (danube_eeprom_cleanup_module);
|
||||||
module_init (danube_eeprom_init);
|
module_init (danube_eeprom_init);
|
||||||
|
|
||||||
#ifndef MODULE
|
MODULE_LICENSE ("GPL");
|
||||||
static int __init
|
MODULE_AUTHOR ("Peng Liu");
|
||||||
danube_eeprom_set_maj (char *str)
|
MODULE_DESCRIPTION ("IFAP EEPROM driver");
|
||||||
{
|
MODULE_SUPPORTED_DEVICE ("danube_eeprom");
|
||||||
maj = simple_strtol (str, NULL, 0);
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
__setup ("eeprom_maj=", danube_eeprom_set_maj);
|
|
||||||
#endif /* !MODULE */
|
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -322,7 +322,6 @@
|
||||||
#define DANUBE_LED_EDGE_MASK (1 << 26)
|
#define DANUBE_LED_EDGE_MASK (1 << 26)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/*------------ GPIO */
|
/*------------ GPIO */
|
||||||
|
|
||||||
#define DANUBE_GPIO_BASE_ADDR (0xBE100B00)
|
#define DANUBE_GPIO_BASE_ADDR (0xBE100B00)
|
||||||
|
|
@ -346,4 +345,14 @@
|
||||||
#define DANUBE_GPIO_P0_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0030))
|
#define DANUBE_GPIO_P0_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0030))
|
||||||
#define DANUBE_GPIO_P1_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0060))
|
#define DANUBE_GPIO_P1_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0060))
|
||||||
|
|
||||||
|
|
||||||
|
/*------------ SSC */
|
||||||
|
|
||||||
|
#define DANUBE_SSC1_BASE_ADDR (KSEG1 + 0x1e100800)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -32,6 +32,10 @@
|
||||||
#define DANUBEASC1_RIR (INT_NUM_IM3_IRL0 + 9)
|
#define DANUBEASC1_RIR (INT_NUM_IM3_IRL0 + 9)
|
||||||
#define DANUBEASC1_EIR (INT_NUM_IM3_IRL0 + 10)
|
#define DANUBEASC1_EIR (INT_NUM_IM3_IRL0 + 10)
|
||||||
|
|
||||||
|
#define DANUBE_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
|
||||||
|
#define DANUBE_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
|
||||||
|
#define DANUBE_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
|
||||||
|
|
||||||
#define DANUBE_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
|
#define DANUBE_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
|
||||||
|
|
||||||
#define MIPS_CPU_TIMER_IRQ 7
|
#define MIPS_CPU_TIMER_IRQ 7
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,119 @@
|
||||||
|
//*************************************************************************
|
||||||
|
//* Summary of definitions which are used in each peripheral *
|
||||||
|
//*************************************************************************
|
||||||
|
|
||||||
|
#ifndef peripheral_definitions_h
|
||||||
|
#define peripheral_definitions_h
|
||||||
|
|
||||||
|
////#include "cpu.h"
|
||||||
|
//
|
||||||
|
///* These files have to be included by each peripheral */
|
||||||
|
//#include <sysdefs.h>
|
||||||
|
//#include <excep.h>
|
||||||
|
//#include <cpusubsys.h>
|
||||||
|
//#include <sys_api.h>
|
||||||
|
//#include <mips.h>
|
||||||
|
//#include "SRAM_address_map.h"
|
||||||
|
//
|
||||||
|
///* common header files for all CPU's */
|
||||||
|
//#include "iiu.h"
|
||||||
|
//#include "bcu.h"
|
||||||
|
//#include "FPI_address_map.h"
|
||||||
|
//#include "direct_interrupts.h"
|
||||||
|
|
||||||
|
/////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
//extern int _clz();
|
||||||
|
//extern void _nop();
|
||||||
|
//extern void _sleep();
|
||||||
|
//extern void sys_enable_int();
|
||||||
|
|
||||||
|
typedef unsigned char UINT8;
|
||||||
|
typedef signed char INT8;
|
||||||
|
typedef unsigned short UINT16;
|
||||||
|
typedef signed short INT16;
|
||||||
|
typedef unsigned int UINT32;
|
||||||
|
typedef signed int INT32;
|
||||||
|
typedef unsigned long long UINT64;
|
||||||
|
typedef signed long long INT64;
|
||||||
|
|
||||||
|
#define REG8( addr ) (*(volatile UINT8 *) (addr))
|
||||||
|
#define REG16( addr ) (*(volatile UINT16 *)(addr))
|
||||||
|
#define REG32( addr ) (*(volatile UINT32 *)(addr))
|
||||||
|
#define REG64( addr ) (*(volatile UINT64 *)(addr))
|
||||||
|
|
||||||
|
/* define routine to set FPI access in Supervisor Mode */
|
||||||
|
#define IFX_SUPERVISOR_ON() REG32(FB0_CFG) = 0x01
|
||||||
|
/* Supervisor mode ends, following functions will be done in User mode */
|
||||||
|
#define IFX_SUPERVISOR_OFF() REG32(FB0_CFG) = 0x00
|
||||||
|
/* Supervisor mode ends, following functions will be done in User mode */
|
||||||
|
#define IFX_SUPERVISOR_MODE() REG32(FB0_CFG)
|
||||||
|
/* Supervisor mode ends, following functions will be done in User mode */
|
||||||
|
#define IFX_SUPERVISOR_SET(svm) REG32(FB0_CFG) = svm
|
||||||
|
/* enable all Interrupts in IIU */
|
||||||
|
//#define IFX_ENABLE_IRQ(irq_mask, im_base) REG32(im_base | IIU_MASK) = irq_mask
|
||||||
|
///* get all high priority interrupt bits in IIU */
|
||||||
|
//#define IFX_GET_IRQ_MASKED(im_base) REG32(im_base | IIU_IRMASKED)
|
||||||
|
///* signal ends of interrupt to IIU */
|
||||||
|
//#define IFX_CLEAR_DIRECT_IRQ(irq_bit, im_base) REG32(im_base | IIU_IR) = irq_bit
|
||||||
|
///* force IIU interrupt register */
|
||||||
|
//#define IFX_FORCE_IIU_REGISTER(data, im_base) REG32(im_base | IIU_IRDEBUG) = data
|
||||||
|
///* get all bits of interrupt register */
|
||||||
|
//#define IFX_GET_IRQ_UNMASKED(im_base) REG32(im_base | IIU_IR)
|
||||||
|
/* insert a NOP instruction */
|
||||||
|
#define NOP _nop()
|
||||||
|
/* CPU goes to power down mode until interrupt occurs */
|
||||||
|
#define IFX_CPU_SLEEP _sleep()
|
||||||
|
/* enable all interrupts to CPU */
|
||||||
|
#define IFX_CPU_ENABLE_ALL_INTERRUPT sys_enable_int()
|
||||||
|
/* get all low priority interrupt bits in peripheral */
|
||||||
|
#define IFX_GET_LOW_PRIO_IRQ(int_reg) REG32(int_reg)
|
||||||
|
/* clear low priority interrupt bit in peripheral */
|
||||||
|
#define IFX_CLEAR_LOW_PRIO_IRQ(irq_bit, int_reg) REG32(int_reg) = irq_bit
|
||||||
|
/* write FPI bus */
|
||||||
|
#define WRITE_FPI_BYTE(data, addr) REG8(addr) = data
|
||||||
|
#define WRITE_FPI_16BIT(data, addr) REG16(addr) = data
|
||||||
|
#define WRITE_FPI_32BIT(data, addr) REG32(addr) = data
|
||||||
|
/* read FPI bus */
|
||||||
|
#define READ_FPI_BYTE(addr) REG8(addr)
|
||||||
|
#define READ_FPI_16BIT(addr) REG16(addr)
|
||||||
|
#define READ_FPI_32BIT(addr) REG32(addr)
|
||||||
|
/* write peripheral register */
|
||||||
|
#define WRITE_PERIPHERAL_REGISTER(data, addr) REG32(addr) = data
|
||||||
|
|
||||||
|
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||||||
|
#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr) = data
|
||||||
|
#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr) = data
|
||||||
|
#else //not CONFIG_CPU_LITTLE_ENDIAN
|
||||||
|
#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr+2) = data
|
||||||
|
#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr+3) = data
|
||||||
|
#endif //CONFIG_CPU_LITTLE_ENDIAN
|
||||||
|
|
||||||
|
/* read peripheral register */
|
||||||
|
#define READ_PERIPHERAL_REGISTER(addr) REG32(addr)
|
||||||
|
|
||||||
|
/* read/modify(or)/write peripheral register */
|
||||||
|
#define RMW_OR_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) | data
|
||||||
|
/* read/modify(and)/write peripheral register */
|
||||||
|
#define RMW_AND_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) & (UINT32)data
|
||||||
|
|
||||||
|
/* CPU-independent mnemonic constants */
|
||||||
|
/* CLC register bits */
|
||||||
|
#define IFX_CLC_ENABLE 0x00000000
|
||||||
|
#define IFX_CLC_DISABLE 0x00000001
|
||||||
|
#define IFX_CLC_DISABLE_STATUS 0x00000002
|
||||||
|
#define IFX_CLC_SUSPEND_ENABLE 0x00000004
|
||||||
|
#define IFX_CLC_CLOCK_OFF_DISABLE 0x00000008
|
||||||
|
#define IFX_CLC_OVERWRITE_SPEN_FSOE 0x00000010
|
||||||
|
#define IFX_CLC_FAST_CLOCK_SWITCH_OFF 0x00000020
|
||||||
|
#define IFX_CLC_RUN_DIVIDER_MASK 0x0000FF00
|
||||||
|
#define IFX_CLC_RUN_DIVIDER_OFFSET 8
|
||||||
|
#define IFX_CLC_SLEEP_DIVIDER_MASK 0x00FF0000
|
||||||
|
#define IFX_CLC_SLEEP_DIVIDER_OFFSET 16
|
||||||
|
#define IFX_CLC_SPECIFIC_DIVIDER_MASK 0x00FF0000
|
||||||
|
#define IFX_CLC_SPECIFIC_DIVIDER_OFFSET 24
|
||||||
|
|
||||||
|
/* number of cycles to wait for interrupt service routine to be called */
|
||||||
|
#define WAIT_CYCLES 50
|
||||||
|
|
||||||
|
#endif /* PERIPHERAL_DEFINITIONS_H not yet defined */
|
||||||
|
|
@ -0,0 +1,258 @@
|
||||||
|
/*
|
||||||
|
* ifx_ssc.h defines some data sructures used in ifx_ssc.c
|
||||||
|
*
|
||||||
|
* Copyright (C) 2004 Michael Schoenenborn (IFX COM TI BT)
|
||||||
|
*
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __IFX_SSC_H
|
||||||
|
#define __IFX_SSC_H
|
||||||
|
#ifdef __KERNEL__
|
||||||
|
#include <asm/danube/ifx_ssc_defines.h>
|
||||||
|
#endif //__KERNEL__
|
||||||
|
|
||||||
|
#define PORT_CNT 1 // assume default value
|
||||||
|
|
||||||
|
/* symbolic constants to be used in SSC routines */
|
||||||
|
|
||||||
|
// ### TO DO: bad performance
|
||||||
|
#define IFX_SSC_TXFIFO_ITL 1
|
||||||
|
#define IFX_SSC_RXFIFO_ITL 1
|
||||||
|
|
||||||
|
struct ifx_ssc_statistics {
|
||||||
|
unsigned int abortErr; /* abort error */
|
||||||
|
unsigned int modeErr; /* master/slave mode error */
|
||||||
|
unsigned int txOvErr; /* TX Overflow error */
|
||||||
|
unsigned int txUnErr; /* TX Underrun error */
|
||||||
|
unsigned int rxOvErr; /* RX Overflow error */
|
||||||
|
unsigned int rxUnErr; /* RX Underrun error */
|
||||||
|
unsigned int rxBytes;
|
||||||
|
unsigned int txBytes;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ifx_ssc_hwopts {
|
||||||
|
unsigned int AbortErrDetect:1; /* Abort Error detection (in slave mode) */
|
||||||
|
unsigned int rxOvErrDetect:1; /* Receive Overflow Error detection */
|
||||||
|
unsigned int rxUndErrDetect:1; /* Receive Underflow Error detection */
|
||||||
|
unsigned int txOvErrDetect:1; /* Transmit Overflow Error detection */
|
||||||
|
unsigned int txUndErrDetect:1; /* Transmit Underflow Error detection */
|
||||||
|
unsigned int echoMode:1; /* Echo mode */
|
||||||
|
unsigned int loopBack:1; /* Loopback mode */
|
||||||
|
unsigned int idleValue:1; /* Idle value */
|
||||||
|
unsigned int clockPolarity:1; /* Idle clock is high or low */
|
||||||
|
unsigned int clockPhase:1; /* Tx on trailing or leading edge */
|
||||||
|
unsigned int headingControl:1; /* LSB first or MSB first */
|
||||||
|
unsigned int dataWidth:6; /* from 2 up to 32 bits */
|
||||||
|
unsigned int masterSelect:1; /* Master or Slave mode */
|
||||||
|
unsigned int modeRxTx:2; /* rx/tx mode */
|
||||||
|
unsigned int gpoCs:8; /* choose outputs to use for chip select */
|
||||||
|
unsigned int gpoInv:8; /* invert GPO outputs */
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ifx_ssc_frm_opts {
|
||||||
|
bool FrameEnable; // SFCON.SFEN
|
||||||
|
unsigned int DataLength; // SFCON.DLEN
|
||||||
|
unsigned int PauseLength; // SFCON.PLEN
|
||||||
|
unsigned int IdleData; // SFCON.IDAT
|
||||||
|
unsigned int IdleClock; // SFCON.ICLK
|
||||||
|
bool StopAfterPause; // SFCON.STOP
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ifx_ssc_frm_status {
|
||||||
|
bool DataBusy; // SFSTAT.DBSY
|
||||||
|
bool PauseBusy; // SFSTAT.PBSY
|
||||||
|
unsigned int DataCount; // SFSTAT.DCNT
|
||||||
|
unsigned int PauseCount; // SFSTAT.PCNT
|
||||||
|
bool EnIntAfterData; // SFCON.IBEN
|
||||||
|
bool EnIntAfterPause; // SFCON.IAEN
|
||||||
|
};
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
char *buf;
|
||||||
|
size_t len;
|
||||||
|
} ifx_ssc_buf_item_t;
|
||||||
|
|
||||||
|
// data structures for batch execution
|
||||||
|
typedef union {
|
||||||
|
struct {
|
||||||
|
bool save_options;
|
||||||
|
} init;
|
||||||
|
ifx_ssc_buf_item_t read;
|
||||||
|
ifx_ssc_buf_item_t write;
|
||||||
|
ifx_ssc_buf_item_t rd_wr;
|
||||||
|
unsigned int set_baudrate;
|
||||||
|
struct ifx_ssc_frm_opts set_frm;
|
||||||
|
unsigned int set_gpo;
|
||||||
|
struct ifx_ssc_hwopts set_hwopts;
|
||||||
|
} ifx_ssc_batch_cmd_param;
|
||||||
|
|
||||||
|
struct ifx_ssc_batch_list {
|
||||||
|
unsigned int cmd;
|
||||||
|
ifx_ssc_batch_cmd_param cmd_param;
|
||||||
|
struct ifx_ssc_batch_list *next;
|
||||||
|
};
|
||||||
|
|
||||||
|
#ifdef __KERNEL__
|
||||||
|
#define IFX_SSC_IS_MASTER(p) ((p)->opts.masterSelect == SSC_MASTER_MODE)
|
||||||
|
|
||||||
|
struct ifx_ssc_port {
|
||||||
|
unsigned long mapbase;
|
||||||
|
struct ifx_ssc_hwopts opts;
|
||||||
|
struct ifx_ssc_statistics stats;
|
||||||
|
struct ifx_ssc_frm_status frm_status;
|
||||||
|
struct ifx_ssc_frm_opts frm_opts;
|
||||||
|
/* wait queue for ifx_ssc_read() */
|
||||||
|
wait_queue_head_t rwait, pwait;
|
||||||
|
int port_nr;
|
||||||
|
char port_is_open; /* exclusive open - boolean */
|
||||||
|
// int no_of_bits; /* number of _valid_ bits */
|
||||||
|
// int elem_size; /* shift for element (no of bytes)*/
|
||||||
|
/* buffer and pointers to the read/write position */
|
||||||
|
char *rxbuf; /* buffer for RX */
|
||||||
|
char *rxbuf_end; /* buffer end pointer for RX */
|
||||||
|
volatile char *rxbuf_ptr; /* buffer write pointer for RX */
|
||||||
|
char *txbuf; /* buffer for TX */
|
||||||
|
char *txbuf_end; /* buffer end pointer for TX */
|
||||||
|
volatile char *txbuf_ptr; /* buffer read pointer for TX */
|
||||||
|
unsigned int baud;
|
||||||
|
/* each channel has its own interrupts */
|
||||||
|
/* (transmit/receive/error/frame) */
|
||||||
|
unsigned int txirq, rxirq, errirq, frmirq;
|
||||||
|
};
|
||||||
|
/* default values for SSC configuration */
|
||||||
|
// values of CON
|
||||||
|
#define IFX_SSC_DEF_IDLE_DATA 1 /* enable */
|
||||||
|
#define IFX_SSC_DEF_BYTE_VALID_CTL 1 /* enable */
|
||||||
|
#define IFX_SSC_DEF_DATA_WIDTH 32 /* bits */
|
||||||
|
#define IFX_SSC_DEF_ABRT_ERR_DETECT 0 /* disable */
|
||||||
|
#define IFX_SSC_DEF_RO_ERR_DETECT 1 /* enable */
|
||||||
|
#define IFX_SSC_DEF_RU_ERR_DETECT 0 /* disable */
|
||||||
|
#define IFX_SSC_DEF_TO_ERR_DETECT 0 /* disable */
|
||||||
|
#define IFX_SSC_DEF_TU_ERR_DETECT 0 /* disable */
|
||||||
|
#define IFX_SSC_DEF_LOOP_BACK 0 /* disable */
|
||||||
|
#define IFX_SSC_DEF_ECHO_MODE 0 /* disable */
|
||||||
|
#define IFX_SSC_DEF_CLOCK_POLARITY 0 /* low */
|
||||||
|
#define IFX_SSC_DEF_CLOCK_PHASE 1 /* 0: shift on leading edge, latch on trailling edge, 1, otherwise */
|
||||||
|
#define IFX_SSC_DEF_HEADING_CONTROL IFX_SSC_MSB_FIRST
|
||||||
|
#define IFX_SSC_DEF_MODE_RXTX IFX_SSC_MODE_RXTX
|
||||||
|
// other values
|
||||||
|
#define IFX_SSC_DEF_MASTERSLAVE IFX_SSC_MASTER_MODE /* master */
|
||||||
|
#ifdef CONFIG_USE_EMULATOR
|
||||||
|
#define IFX_SSC_DEF_BAUDRATE 10000
|
||||||
|
#else
|
||||||
|
#define IFX_SSC_DEF_BAUDRATE 2000000
|
||||||
|
#endif
|
||||||
|
#define IFX_SSC_DEF_RMC 0x10
|
||||||
|
|
||||||
|
#define IFX_SSC_DEF_TXFIFO_FL 8
|
||||||
|
#define IFX_SSC_DEF_RXFIFO_FL 1
|
||||||
|
|
||||||
|
#if 1 //TODO
|
||||||
|
#define IFX_SSC_DEF_GPO_CS 0x3 /* no chip select */
|
||||||
|
#define IFX_SSC_DEF_GPO_INV 0 /* no chip select */
|
||||||
|
#else
|
||||||
|
#error "what is ur Chip Select???"
|
||||||
|
#endif
|
||||||
|
#define IFX_SSC_DEF_SFCON 0 /* no serial framing */
|
||||||
|
#if 0
|
||||||
|
#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\
|
||||||
|
IFX_SSC_R_BIT | IFX_SSC_E_BIT | IFX_SSC_F_BIT
|
||||||
|
#endif
|
||||||
|
#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\
|
||||||
|
IFX_SSC_R_BIT | IFX_SSC_E_BIT
|
||||||
|
#endif /* __KERNEL__ */
|
||||||
|
|
||||||
|
// batch execution commands
|
||||||
|
#define IFX_SSC_BATCH_CMD_INIT 1
|
||||||
|
#define IFX_SSC_BATCH_CMD_READ 2
|
||||||
|
#define IFX_SSC_BATCH_CMD_WRITE 3
|
||||||
|
#define IFX_SSC_BATCH_CMD_RD_WR 4
|
||||||
|
#define IFX_SSC_BATCH_CMD_SET_BAUDRATE 5
|
||||||
|
#define IFX_SSC_BATCH_CMD_SET_HWOPTS 6
|
||||||
|
#define IFX_SSC_BATCH_CMD_SET_FRM 7
|
||||||
|
#define IFX_SSC_BATCH_CMD_SET_GPO 8
|
||||||
|
#define IFX_SSC_BATCH_CMD_FIFO_FLUSH 9
|
||||||
|
//#define IFX_SSC_BATCH_CMD_
|
||||||
|
//#define IFX_SSC_BATCH_CMD_
|
||||||
|
#define IFX_SSC_BATCH_CMD_END_EXEC 0
|
||||||
|
|
||||||
|
/* Macros to configure SSC hardware */
|
||||||
|
/* headingControl: */
|
||||||
|
#define IFX_SSC_LSB_FIRST 0
|
||||||
|
#define IFX_SSC_MSB_FIRST 1
|
||||||
|
/* dataWidth: */
|
||||||
|
#define IFX_SSC_MIN_DATA_WIDTH 2
|
||||||
|
#define IFX_SSC_MAX_DATA_WIDTH 32
|
||||||
|
/* master/slave mode select */
|
||||||
|
#define IFX_SSC_MASTER_MODE 1
|
||||||
|
#define IFX_SSC_SLAVE_MODE 0
|
||||||
|
/* rx/tx mode */
|
||||||
|
// ### TO DO: !!! ATTENTION! Hardware dependency => move to ifx_ssc_defines.h
|
||||||
|
#define IFX_SSC_MODE_RXTX 0
|
||||||
|
#define IFX_SSC_MODE_RX 1
|
||||||
|
#define IFX_SSC_MODE_TX 2
|
||||||
|
#define IFX_SSC_MODE_OFF 3
|
||||||
|
#define IFX_SSC_MODE_MASK IFX_SSC_MODE_RX | IFX_SSC_MODE_TX
|
||||||
|
|
||||||
|
/* GPO values */
|
||||||
|
#define IFX_SSC_MAX_GPO_OUT 7
|
||||||
|
|
||||||
|
#define IFX_SSC_RXREQ_BLOCK_SIZE 32768
|
||||||
|
|
||||||
|
/***********************/
|
||||||
|
/* defines for ioctl's */
|
||||||
|
/***********************/
|
||||||
|
#define IFX_SSC_IOCTL_MAGIC 'S'
|
||||||
|
/* read out the statistics */
|
||||||
|
#define IFX_SSC_STATS_READ _IOR(IFX_SSC_IOCTL_MAGIC, 1, struct ifx_ssc_statistics)
|
||||||
|
/* clear the statistics */
|
||||||
|
#define IFX_SSC_STATS_RESET _IO(IFX_SSC_IOCTL_MAGIC, 2)
|
||||||
|
/* set the baudrate */
|
||||||
|
#define IFX_SSC_BAUD_SET _IOW(IFX_SSC_IOCTL_MAGIC, 3, unsigned int)
|
||||||
|
/* get the current baudrate */
|
||||||
|
#define IFX_SSC_BAUD_GET _IOR(IFX_SSC_IOCTL_MAGIC, 4, unsigned int)
|
||||||
|
/* set hardware options */
|
||||||
|
#define IFX_SSC_HWOPTS_SET _IOW(IFX_SSC_IOCTL_MAGIC, 5, struct ifx_ssc_hwopts)
|
||||||
|
/* get the current hardware options */
|
||||||
|
#define IFX_SSC_HWOPTS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 6, struct ifx_ssc_hwopts)
|
||||||
|
/* set transmission mode */
|
||||||
|
#define IFX_SSC_RXTX_MODE_SET _IOW(IFX_SSC_IOCTL_MAGIC, 7, unsigned int)
|
||||||
|
/* get the current transmission mode */
|
||||||
|
#define IFX_SSC_RXTX_MODE_GET _IOR(IFX_SSC_IOCTL_MAGIC, 8, unsigned int)
|
||||||
|
/* abort transmission */
|
||||||
|
#define IFX_SSC_ABORT _IO(IFX_SSC_IOCTL_MAGIC, 9)
|
||||||
|
#define IFX_SSC_FIFO_FLUSH _IO(IFX_SSC_IOCTL_MAGIC, 9)
|
||||||
|
|
||||||
|
/* set general purpose outputs */
|
||||||
|
#define IFX_SSC_GPO_OUT_SET _IOW(IFX_SSC_IOCTL_MAGIC, 32, unsigned int)
|
||||||
|
/* clear general purpose outputs */
|
||||||
|
#define IFX_SSC_GPO_OUT_CLR _IOW(IFX_SSC_IOCTL_MAGIC, 33, unsigned int)
|
||||||
|
/* get general purpose outputs */
|
||||||
|
#define IFX_SSC_GPO_OUT_GET _IOR(IFX_SSC_IOCTL_MAGIC, 34, unsigned int)
|
||||||
|
|
||||||
|
/*** serial framing ***/
|
||||||
|
/* get status of serial framing */
|
||||||
|
#define IFX_SSC_FRM_STATUS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 48, struct ifx_ssc_frm_status)
|
||||||
|
/* get counter reload values and control bits */
|
||||||
|
#define IFX_SSC_FRM_CONTROL_GET _IOR(IFX_SSC_IOCTL_MAGIC, 49, struct ifx_ssc_frm_opts)
|
||||||
|
/* set counter reload values and control bits */
|
||||||
|
#define IFX_SSC_FRM_CONTROL_SET _IOW(IFX_SSC_IOCTL_MAGIC, 50, struct ifx_ssc_frm_opts)
|
||||||
|
|
||||||
|
/*** batch execution ***/
|
||||||
|
/* do batch execution */
|
||||||
|
#define IFX_SSC_BATCH_EXEC _IOW(IFX_SSC_IOCTL_MAGIC, 64, struct ifx_ssc_batch_list)
|
||||||
|
|
||||||
|
#ifdef __KERNEL__
|
||||||
|
// routines from ifx_ssc.c
|
||||||
|
// ### TO DO
|
||||||
|
/* kernel interface for read and write */
|
||||||
|
ssize_t ifx_ssc_kread (int, char *, size_t);
|
||||||
|
ssize_t ifx_ssc_kwrite (int, const char *, size_t);
|
||||||
|
|
||||||
|
#ifdef CONFIG_IFX_VP_KERNEL_TEST
|
||||||
|
void ifx_ssc_tc (void);
|
||||||
|
#endif // CONFIG_IFX_VP_KERNEL_TEST
|
||||||
|
|
||||||
|
#endif //__KERNEL__
|
||||||
|
#endif // __IFX_SSC_H
|
||||||
|
|
@ -0,0 +1,547 @@
|
||||||
|
#ifndef IFX_SSC_DEFINES_H
|
||||||
|
#define IFX_SSC_DEFINES_H
|
||||||
|
|
||||||
|
#include "ifx_peripheral_definitions.h"
|
||||||
|
|
||||||
|
/* maximum SSC FIFO size */
|
||||||
|
#define IFX_SSC_MAX_FIFO_SIZE 32
|
||||||
|
|
||||||
|
/* register map of SSC */
|
||||||
|
|
||||||
|
/* address of the Clock Control Register of the SSC */
|
||||||
|
#define IFX_SSC_CLC 0x00000000
|
||||||
|
/* IFX_SSC_CLC register is significant in bits 23 downto 8 and in bits 5, 3, 2, 0
|
||||||
|
bit 1 is hardware modified*/
|
||||||
|
#define IFX_SSC_CLC_readmask 0x00FFFFEF
|
||||||
|
#define IFX_SSC_CLC_writemask 0x00FFFF3D
|
||||||
|
#define IFX_SSC_CLC_hwmask 0x00000002
|
||||||
|
#define IFX_SSC_CLC_dontcare (IFX_SSC_CLC_readmask & IFX_SSC_CLC_writemask & ~IFX_SSC_CLC_hwmask)
|
||||||
|
|
||||||
|
/* address of Port Input Select Register of the SSC */
|
||||||
|
#define IFX_SSC_PISEL 0x00000004
|
||||||
|
/* IFX_SSC_PISEL register is significant in lowest three bits only */
|
||||||
|
#define IFX_SSC_PISEL_readmask 0x00000007
|
||||||
|
#define IFX_SSC_PISEL_writemask 0x00000007
|
||||||
|
#define IFX_SSC_PISEL_hwmask 0x00000000
|
||||||
|
#define IFX_SSC_PISEL_dontcare (IFX_SSC_PISEL_readmask & IFX_SSC_PISEL_writemask & ~IFX_SSC_PISEL_hwmask)
|
||||||
|
|
||||||
|
/* address of Identification Register of the SSC */
|
||||||
|
#define IFX_SSC_ID 0x00000008
|
||||||
|
/* IFX_SSC_ID register is significant in no bit */
|
||||||
|
#define IFX_SSC_ID_readmask 0x0000FF3F
|
||||||
|
#define IFX_SSC_ID_writemask 0x00000000
|
||||||
|
#define IFX_SSC_ID_hwmask 0x00000000
|
||||||
|
#define IFX_SSC_ID_dontcare (IFX_SSC_ID_readmask & IFX_SSC_ID_writemask & ~IFX_SSC_ID_hwmask)
|
||||||
|
|
||||||
|
/* address of the Control Register of the SSC */
|
||||||
|
#define IFX_SSC_CON 0x00000010
|
||||||
|
/* IFX_SSC_CON register is significant in bits 23:22, 20:16 and 12:0 */
|
||||||
|
#define IFX_SSC_CON_readmask 0x01DF1FFF
|
||||||
|
#define IFX_SSC_CON_writemask 0x01DF1FFF
|
||||||
|
#define IFX_SSC_CON_hwmask 0x00000000
|
||||||
|
#define IFX_SSC_CON_dontcare (IFX_SSC_CON_readmask & IFX_SSC_CON_writemask & ~IFX_SSC_CON_hwmask)
|
||||||
|
|
||||||
|
/* address of the Status Register of the SSC */
|
||||||
|
#define IFX_SSC_STATE 0x00000014
|
||||||
|
/* IFX_SSC_STATE register is readable in bits 30:28, 26:24, 20:16, 12:7 and 2:0
|
||||||
|
all bits except 1:0 are hardware modified */
|
||||||
|
#define IFX_SSC_STATE_readmask 0x771F3F87
|
||||||
|
#define IFX_SSC_STATE_writemask 0x00000000
|
||||||
|
#define IFX_SSC_STATE_hwmask 0x771F3F84
|
||||||
|
#define IFX_SSC_STATE_dontcare (IFX_SSC_STATE_readmask & IFX_SSC_STATE_writemask & ~IFX_SSC_STATE_hwmask)
|
||||||
|
|
||||||
|
/* address of the Write Hardware Modified Control Register Bits of the SSC */
|
||||||
|
#define IFX_SSC_WHBSTATE 0x00000018
|
||||||
|
/* IFX_SSC_WHBSTATE register is write only */
|
||||||
|
#define IFX_SSC_WHBSTATE_readmask 0x00000000
|
||||||
|
#define IFX_SSC_WHBSTATE_writemask 0x0000FFFF
|
||||||
|
#define IFX_SSC_WHBSTATE_hwmask 0x00000000
|
||||||
|
#define IFX_SSC_WHBSTATE_dontcare (IFX_SSC_WHBSTATE_readmask & IFX_SSC_WHBSTATE_writemask & ~IFX_SSC_WHBSTATE_hwmask)
|
||||||
|
|
||||||
|
/* address of the Baudrate Timer Reload Register of the SSC */
|
||||||
|
#define IFX_SSC_BR 0x00000040
|
||||||
|
/* IFX_SSC_BR register is significant in bit 15 downto 0*/
|
||||||
|
#define IFX_SSC_BR_readmask 0x0000FFFF
|
||||||
|
#define IFX_SSC_BR_writemask 0x0000FFFF
|
||||||
|
#define IFX_SSC_BR_hwmask 0x00000000
|
||||||
|
#define IFX_SSC_BR_dontcare (IFX_SSC_BR_readmask & IFX_SSC_BR_writemask & ~IFX_SSC_BR_hwmask)
|
||||||
|
|
||||||
|
/* address of the Baudrate Timer Status Register of the SSC */
|
||||||
|
#define IFX_SSC_BRSTAT 0x00000044
|
||||||
|
/* IFX_SSC_BRSTAT register is significant in bit 15 downto 0*/
|
||||||
|
#define IFX_SSC_BRSTAT_readmask 0x0000FFFF
|
||||||
|
#define IFX_SSC_BRSTAT_writemask 0x00000000
|
||||||
|
#define IFX_SSC_BRSTAT_hwmask 0x0000FFFF
|
||||||
|
#define IFX_SSC_BRSTAT_dontcare (IFX_SSC_BRSTAT_readmask & IFX_SSC_BRSTAT_writemask & ~IFX_SSC_BRSTAT_hwmask)
|
||||||
|
|
||||||
|
/* address of the Transmitter Buffer Register of the SSC */
|
||||||
|
#define IFX_SSC_TB 0x00000020
|
||||||
|
/* IFX_SSC_TB register is significant in bit 31 downto 0*/
|
||||||
|
#define IFX_SSC_TB_readmask 0xFFFFFFFF
|
||||||
|
#define IFX_SSC_TB_writemask 0xFFFFFFFF
|
||||||
|
#define IFX_SSC_TB_hwmask 0x00000000
|
||||||
|
#define IFX_SSC_TB_dontcare (IFX_SSC_TB_readmask & IFX_SSC_TB_writemask & ~IFX_SSC_TB_hwmask)
|
||||||
|
|
||||||
|
/* address of the Reciver Buffer Register of the SSC */
|
||||||
|
#define IFX_SSC_RB 0x00000024
|
||||||
|
/* IFX_SSC_RB register is significant in no bits*/
|
||||||
|
#define IFX_SSC_RB_readmask 0xFFFFFFFF
|
||||||
|
#define IFX_SSC_RB_writemask 0x00000000
|
||||||
|
#define IFX_SSC_RB_hwmask 0xFFFFFFFF
|
||||||
|
#define IFX_SSC_RB_dontcare (IFX_SSC_RB_readmask & IFX_SSC_RB_writemask & ~IFX_SSC_RB_hwmask)
|
||||||
|
|
||||||
|
/* address of the Receive FIFO Control Register of the SSC */
|
||||||
|
#define IFX_SSC_RXFCON 0x00000030
|
||||||
|
/* IFX_SSC_RXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */
|
||||||
|
#define IFX_SSC_RXFCON_readmask 0x00003F03
|
||||||
|
#define IFX_SSC_RXFCON_writemask 0x00003F03
|
||||||
|
#define IFX_SSC_RXFCON_hwmask 0x00000000
|
||||||
|
#define IFX_SSC_RXFCON_dontcare (IFX_SSC_RXFCON_readmask & IFX_SSC_RXFCON_writemask & ~IFX_SSC_RXFCON_hwmask)
|
||||||
|
|
||||||
|
/* address of the Transmit FIFO Control Register of the SSC */
|
||||||
|
#define IFX_SSC_TXFCON 0x00000034
|
||||||
|
/* IFX_SSC_TXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */
|
||||||
|
#define IFX_SSC_TXFCON_readmask 0x00003F03
|
||||||
|
#define IFX_SSC_TXFCON_writemask 0x00003F03
|
||||||
|
#define IFX_SSC_TXFCON_hwmask 0x00000000
|
||||||
|
#define IFX_SSC_TXFCON_dontcare (IFX_SSC_TXFCON_readmask & IFX_SSC_TXFCON_writemask & ~IFX_SSC_TXFCON_hwmask)
|
||||||
|
|
||||||
|
/* address of the FIFO Status Register of the SSC */
|
||||||
|
#define IFX_SSC_FSTAT 0x00000038
|
||||||
|
/* IFX_SSC_FSTAT register is significant in no bit*/
|
||||||
|
#define IFX_SSC_FSTAT_readmask 0x00003F3F
|
||||||
|
#define IFX_SSC_FSTAT_writemask 0x00000000
|
||||||
|
#define IFX_SSC_FSTAT_hwmask 0x00003F3F
|
||||||
|
#define IFX_SSC_FSTAT_dontcare (IFX_SSC_FSTAT_readmask & IFX_SSC_FSTAT_writemask & ~IFX_SSC_FSTAT_hwmask)
|
||||||
|
|
||||||
|
/* address of the Data Frame Control register of the SSC */
|
||||||
|
#define IFX_SSC_SFCON 0x00000060
|
||||||
|
#define IFX_SSC_SFCON_readmask 0xFFDFFFFD
|
||||||
|
#define IFX_SSC_SFCON_writemask 0xFFDFFFFD
|
||||||
|
#define IFX_SSC_SFCON_hwmask 0x00000000
|
||||||
|
#define IFX_SSC_SFCON_dontcare (IFX_SSC_SFCON_readmask & IFX_SSC_SFCON_writemask & ~IFX_SSC_SFCON_hwmask)
|
||||||
|
|
||||||
|
/* address of the Data Frame Status register of the SSC */
|
||||||
|
#define IFX_SSC_SFSTAT 0x00000064
|
||||||
|
#define IFX_SSC_SFSTAT_readmask 0xFFC0FFF3
|
||||||
|
#define IFX_SSC_SFSTAT_writemask 0x00000000
|
||||||
|
#define IFX_SSC_SFSTAT_hwmask 0xFFC0FFF3
|
||||||
|
#define IFX_SSC_SFSTAT_dontcare (IFX_SSC_SFSTAT_readmask & IFX_SSC_SFSTAT_writemask & ~IFX_SSC_SFSTAT_hwmask)
|
||||||
|
|
||||||
|
/* address of the General Purpose Output Control register of the SSC */
|
||||||
|
#define IFX_SSC_GPOCON 0x00000070
|
||||||
|
#define IFX_SSC_GPOCON_readmask 0x0000FFFF
|
||||||
|
#define IFX_SSC_GPOCON_writemask 0x0000FFFF
|
||||||
|
#define IFX_SSC_GPOCON_hwmask 0x00000000
|
||||||
|
#define IFX_SSC_GPOCON_dontcare (IFX_SSC_GPOCON_readmask & IFX_SSC_GPOCON_writemask & ~IFX_SSC_GPOCON_hwmask)
|
||||||
|
|
||||||
|
/* address of the General Purpose Output Status register of the SSC */
|
||||||
|
#define IFX_SSC_GPOSTAT 0x00000074
|
||||||
|
#define IFX_SSC_GPOSTAT_readmask 0x000000FF
|
||||||
|
#define IFX_SSC_GPOSTAT_writemask 0x00000000
|
||||||
|
#define IFX_SSC_GPOSTAT_hwmask 0x00000000
|
||||||
|
#define IFX_SSC_GPOSTAT_dontcare (IFX_SSC_GPOSTAT_readmask & IFX_SSC_GPOSTAT_writemask & ~IFX_SSC_GPOSTAT_hwmask)
|
||||||
|
|
||||||
|
/* address of the Force GPO Status register of the SSC */
|
||||||
|
#define IFX_SSC_WHBGPOSTAT 0x00000078
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_readmask 0x00000000
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_writemask 0x0000FFFF
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_hwmask 0x00000000
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_dontcare (IFX_SSC_WHBGPOSTAT_readmask & IFX_SSC_WHBGPOSTAT_writemask & ~IFX_SSC_WHBGPOSTAT_hwmask)
|
||||||
|
|
||||||
|
/* address of the Receive Request Register of the SSC */
|
||||||
|
#define IFX_SSC_RXREQ 0x00000080
|
||||||
|
#define IFX_SSC_RXREQ_readmask 0x0000FFFF
|
||||||
|
#define IFX_SSC_RXREQ_writemask 0x0000FFFF
|
||||||
|
#define IFX_SSC_RXREQ_hwmask 0x00000000
|
||||||
|
#define IFX_SSC_RXREQ_dontcare (IFX_SSC_RXREQ_readmask & IFX_SSC_RXREQ_writemask & ~IFX_SSC_RXREQ_hwmask)
|
||||||
|
|
||||||
|
/* address of the Receive Count Register of the SSC */
|
||||||
|
#define IFX_SSC_RXCNT 0x00000084
|
||||||
|
#define IFX_SSC_RXCNT_readmask 0x0000FFFF
|
||||||
|
#define IFX_SSC_RXCNT_writemask 0x00000000
|
||||||
|
#define IFX_SSC_RXCNT_hwmask 0x0000FFFF
|
||||||
|
#define IFX_SSC_RXCNT_dontcare (IFX_SSC_RXCNT_readmask & IFX_SSC_RXCNT_writemask & ~IFX_SSC_RXCNT_hwmask)
|
||||||
|
|
||||||
|
/* address of the DMA Configuration Register of the SSC */
|
||||||
|
#define IFX_SSC_DMACON 0x000000EC
|
||||||
|
#define IFX_SSC_DMACON_readmask 0x0000FFFF
|
||||||
|
#define IFX_SSC_DMACON_writemask 0x00000000
|
||||||
|
#define IFX_SSC_DMACON_hwmask 0x0000FFFF
|
||||||
|
#define IFX_SSC_DMACON_dontcare (IFX_SSC_DMACON_readmask & IFX_SSC_DMACON_writemask & ~IFX_SSC_DMACON_hwmask)
|
||||||
|
|
||||||
|
//------------------------------------------------------
|
||||||
|
// interrupt register for enabling interrupts, mask register of irq_reg
|
||||||
|
#define IFX_SSC_IRN_EN 0xF4
|
||||||
|
// read/write
|
||||||
|
#define IFX_SSC_IRN_EN_readmask 0x0000000F
|
||||||
|
#define IFX_SSC_IRN_EN_writemask 0x0000000F
|
||||||
|
#define IFX_SSC_IRN_EN_hwmask 0x00000000
|
||||||
|
#define IFX_SSC_IRN_EN_dontcare (IFX_SSC_IRN_EN_readmask & IFX_SSC_IRN_EN_writemask & ~IFX_SSC_IRN_EN_hwmask)
|
||||||
|
|
||||||
|
// interrupt register for accessing interrupts
|
||||||
|
#define IFX_SSC_IRN_CR 0xF8
|
||||||
|
// read/write
|
||||||
|
#define IFX_SSC_IRN_CR_readmask 0x0000000F
|
||||||
|
#define IFX_SSC_IRN_CR_writemask 0x0000000F
|
||||||
|
#define IFX_SSC_IRN_CR_hwmask 0x0000000F
|
||||||
|
#define IFX_SSC_IRN_CR_dontcare (IFX_SSC_IRN_CR_readmask & IFX_SSC_IRN_CR_writemask & ~IFX_SSC_IRN_CR_hwmask)
|
||||||
|
|
||||||
|
// interrupt register for stimulating interrupts
|
||||||
|
#define IFX_SSC_IRN_ICR 0xFC
|
||||||
|
// read/write
|
||||||
|
#define IFX_SSC_IRN_ICR_readmask 0x0000000F
|
||||||
|
#define IFX_SSC_IRN_ICR_writemask 0x0000000F
|
||||||
|
#define IFX_SSC_IRN_ICR_hwmask 0x00000000
|
||||||
|
#define IFX_SSC_IRN_ICR_dontcare (IFX_SSC_IRN_ICR_readmask & IFX_SSC_IRN_ICR_writemask & ~IFX_SSC_IRN_ICR_hwmask)
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------
|
||||||
|
// Number of IRQs and bitposition of IRQ
|
||||||
|
#define IFX_SSC_NUM_IRQ 4
|
||||||
|
#define IFX_SSC_T_BIT 0x00000001
|
||||||
|
#define IFX_SSC_R_BIT 0x00000002
|
||||||
|
#define IFX_SSC_E_BIT 0x00000004
|
||||||
|
#define IFX_SSC_F_BIT 0x00000008
|
||||||
|
|
||||||
|
/* bit masks for SSC registers */
|
||||||
|
|
||||||
|
/* ID register */
|
||||||
|
#define IFX_SSC_PERID_REV_MASK 0x0000001F
|
||||||
|
#define IFX_SSC_PERID_CFG_MASK 0x00000020
|
||||||
|
#define IFX_SSC_PERID_ID_MASK 0x0000FF00
|
||||||
|
#define IFX_SSC_PERID_REV_OFFSET 0
|
||||||
|
#define IFX_SSC_PERID_CFG_OFFSET 5
|
||||||
|
#define IFX_SSC_PERID_ID_OFFSET 8
|
||||||
|
#define IFX_SSC_PERID_ID 0x45
|
||||||
|
#define IFX_SSC_PERID_DMA_ON 0x00000020
|
||||||
|
#define IFX_SSC_PERID_RXFS_MASK 0x003F0000
|
||||||
|
#define IFX_SSC_PERID_RXFS_OFFSET 16
|
||||||
|
#define IFX_SSC_PERID_TXFS_MASK 0x3F000000
|
||||||
|
#define IFX_SSC_PERID_TXFS_OFFSET 24
|
||||||
|
|
||||||
|
/* PISEL register */
|
||||||
|
#define IFX_SSC_PISEL_MASTER_IN_A 0x0000
|
||||||
|
#define IFX_SSC_PISEL_MASTER_IN_B 0x0001
|
||||||
|
#define IFX_SSC_PISEL_SLAVE_IN_A 0x0000
|
||||||
|
#define IFX_SSC_PISEL_SLAVE_IN_B 0x0002
|
||||||
|
#define IFX_SSC_PISEL_CLOCK_IN_A 0x0000
|
||||||
|
#define IFX_SSC_PISEL_CLOCK_IN_B 0x0004
|
||||||
|
|
||||||
|
/* IFX_SSC_CON register */
|
||||||
|
#define IFX_SSC_CON_ECHO_MODE_ON 0x01000000
|
||||||
|
#define IFX_SSC_CON_ECHO_MODE_OFF 0x00000000
|
||||||
|
#define IFX_SSC_CON_IDLE_HIGH 0x00800000
|
||||||
|
#define IFX_SSC_CON_IDLE_LOW 0x00000000
|
||||||
|
#define IFX_SSC_CON_ENABLE_BYTE_VALID 0x00400000
|
||||||
|
#define IFX_SSC_CON_DISABLE_BYTE_VALID 0x00000000
|
||||||
|
#define IFX_SSC_CON_DATA_WIDTH_OFFSET 16
|
||||||
|
#define IFX_SSC_CON_DATA_WIDTH_MASK 0x001F0000
|
||||||
|
#define IFX_SSC_ENCODE_DATA_WIDTH(width) (((width - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET) & IFX_SSC_CON_DATA_WIDTH_MASK)
|
||||||
|
|
||||||
|
#define IFX_SSC_CON_RESET_ON_BAUDERR 0x00002000
|
||||||
|
#define IFX_SSC_CON_GO_ON_ON_BAUDERR 0x00000000
|
||||||
|
|
||||||
|
#define IFX_SSC_CON_RX_UFL_CHECK 0x00001000
|
||||||
|
#define IFX_SSC_CON_RX_UFL_IGNORE 0x00000000
|
||||||
|
#define IFX_SSC_CON_TX_UFL_CHECK 0x00000800
|
||||||
|
#define IFX_SSC_CON_TX_UFL_IGNORE 0x00000000
|
||||||
|
#define IFX_SSC_CON_ABORT_ERR_CHECK 0x00000400
|
||||||
|
#define IFX_SSC_CON_ABORT_ERR_IGNORE 0x00000000
|
||||||
|
#define IFX_SSC_CON_RX_OFL_CHECK 0x00000200
|
||||||
|
#define IFX_SSC_CON_RX_OFL_IGNORE 0x00000000
|
||||||
|
#define IFX_SSC_CON_TX_OFL_CHECK 0x00000100
|
||||||
|
#define IFX_SSC_CON_TX_OFL_IGNORE 0x00000000
|
||||||
|
#define IFX_SSC_CON_ALL_ERR_CHECK 0x00001F00
|
||||||
|
#define IFX_SSC_CON_ALL_ERR_IGNORE 0x00000000
|
||||||
|
|
||||||
|
#define IFX_SSC_CON_LOOPBACK_MODE 0x00000080
|
||||||
|
#define IFX_SSC_CON_NO_LOOPBACK 0x00000000
|
||||||
|
#define IFX_SSC_CON_HALF_DUPLEX 0x00000080
|
||||||
|
#define IFX_SSC_CON_FULL_DUPLEX 0x00000000
|
||||||
|
#define IFX_SSC_CON_CLOCK_FALL 0x00000040
|
||||||
|
#define IFX_SSC_CON_CLOCK_RISE 0x00000000
|
||||||
|
#define IFX_SSC_CON_SHIFT_THEN_LATCH 0x00000000
|
||||||
|
#define IFX_SSC_CON_LATCH_THEN_SHIFT 0x00000020
|
||||||
|
#define IFX_SSC_CON_MSB_FIRST 0x00000010
|
||||||
|
#define IFX_SSC_CON_LSB_FIRST 0x00000000
|
||||||
|
#define IFX_SSC_CON_ENABLE_CSB 0x00000008
|
||||||
|
#define IFX_SSC_CON_DISABLE_CSB 0x00000000
|
||||||
|
#define IFX_SSC_CON_INVERT_CSB 0x00000004
|
||||||
|
#define IFX_SSC_CON_TRUE_CSB 0x00000000
|
||||||
|
#define IFX_SSC_CON_RX_OFF 0x00000002
|
||||||
|
#define IFX_SSC_CON_RX_ON 0x00000000
|
||||||
|
#define IFX_SSC_CON_TX_OFF 0x00000001
|
||||||
|
#define IFX_SSC_CON_TX_ON 0x00000000
|
||||||
|
|
||||||
|
/* IFX_SSC_STATE register */
|
||||||
|
#define IFX_SSC_STATE_RX_BYTE_VALID_OFFSET 28
|
||||||
|
#define IFX_SSC_STATE_RX_BYTE_VALID_MASK 0x70000000
|
||||||
|
#define IFX_SSC_DECODE_RX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET)
|
||||||
|
#define IFX_SSC_STATE_TX_BYTE_VALID_OFFSET 24
|
||||||
|
#define IFX_SSC_STATE_TX_BYTE_VALID_MASK 0x07000000
|
||||||
|
#define IFX_SSC_DECODE_TX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_TX_BYTE_VALID_MASK) >> IFX_SSC_STATE_TX_BYTE_VALID_OFFSET)
|
||||||
|
#define IFX_SSC_STATE_BIT_COUNT_OFFSET 16
|
||||||
|
#define IFX_SSC_STATE_BIT_COUNT_MASK 0x001F0000
|
||||||
|
#define IFX_SSC_DECODE_DATA_WIDTH(con_state) (((con_state & IFX_SSC_STATE_BIT_COUNT_MASK) >> IFX_SSC_STATE_BIT_COUNT_OFFSET) + 1)
|
||||||
|
#define IFX_SSC_STATE_BUSY 0x00002000
|
||||||
|
#define IFX_SSC_STATE_RX_UFL 0x00001000
|
||||||
|
#define IFX_SSC_STATE_TX_UFL 0x00000800
|
||||||
|
#define IFX_SSC_STATE_ABORT_ERR 0x00000400
|
||||||
|
#define IFX_SSC_STATE_RX_OFL 0x00000200
|
||||||
|
#define IFX_SSC_STATE_TX_OFL 0x00000100
|
||||||
|
#define IFX_SSC_STATE_MODE_ERR 0x00000080
|
||||||
|
#define IFX_SSC_STATE_SLAVE_IS_SELECTED 0x00000004
|
||||||
|
#define IFX_SSC_STATE_IS_MASTER 0x00000002
|
||||||
|
#define IFX_SSC_STATE_IS_ENABLED 0x00000001
|
||||||
|
|
||||||
|
/* WHBSTATE register */
|
||||||
|
#define IFX_SSC_WHBSTATE_DISABLE_SSC 0x0001
|
||||||
|
#define IFX_SSC_WHBSTATE_CONFIGURATION_MODE 0x0001
|
||||||
|
#define IFX_SSC_WHBSTATE_CLR_ENABLE 0x0001
|
||||||
|
|
||||||
|
#define IFX_SSC_WHBSTATE_ENABLE_SSC 0x0002
|
||||||
|
#define IFX_SSC_WHBSTATE_RUN_MODE 0x0002
|
||||||
|
#define IFX_SSC_WHBSTATE_SET_ENABLE 0x0002
|
||||||
|
|
||||||
|
#define IFX_SSC_WHBSTATE_SLAVE_MODE 0x0004
|
||||||
|
#define IFX_SSC_WHBSTATE_CLR_MASTER_SELECT 0x0004
|
||||||
|
|
||||||
|
#define IFX_SSC_WHBSTATE_MASTER_MODE 0x0008
|
||||||
|
#define IFX_SSC_WHBSTATE_SET_MASTER_SELECT 0x0008
|
||||||
|
|
||||||
|
#define IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR 0x0010
|
||||||
|
#define IFX_SSC_WHBSTATE_SET_RX_UFL_ERROR 0x0020
|
||||||
|
|
||||||
|
#define IFX_SSC_WHBSTATE_CLR_MODE_ERROR 0x0040
|
||||||
|
#define IFX_SSC_WHBSTATE_SET_MODE_ERROR 0x0080
|
||||||
|
|
||||||
|
#define IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR 0x0100
|
||||||
|
#define IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR 0x0200
|
||||||
|
#define IFX_SSC_WHBSTATE_CLR_ABORT_ERROR 0x0400
|
||||||
|
#define IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR 0x0800
|
||||||
|
#define IFX_SSC_WHBSTATE_SET_TX_OFL_ERROR 0x1000
|
||||||
|
#define IFX_SSC_WHBSTATE_SET_RX_OFL_ERROR 0x2000
|
||||||
|
#define IFX_SSC_WHBSTATE_SET_ABORT_ERROR 0x4000
|
||||||
|
#define IFX_SSC_WHBSTATE_SET_TX_UFL_ERROR 0x8000
|
||||||
|
#define IFX_SSC_WHBSTATE_CLR_ALL_ERROR 0x0F50
|
||||||
|
#define IFX_SSC_WHBSTATE_SET_ALL_ERROR 0xF0A0
|
||||||
|
|
||||||
|
/* BR register */
|
||||||
|
#define IFX_SSC_BR_BAUDRATE_OFFSET 0
|
||||||
|
#define IFX_SSC_BR_BAUDRATE_MASK 0xFFFF
|
||||||
|
|
||||||
|
/* BR_STAT register */
|
||||||
|
#define IFX_SSC_BRSTAT_BAUDTIMER_OFFSET 0
|
||||||
|
#define IFX_SSC_BRSTAT_BAUDTIMER_MASK 0xFFFF
|
||||||
|
|
||||||
|
/* TB register */
|
||||||
|
#define IFX_SSC_TB_DATA_OFFSET 0
|
||||||
|
#define IFX_SSC_TB_DATA_MASK 0xFFFFFFFF
|
||||||
|
|
||||||
|
/* RB register */
|
||||||
|
#define IFX_SSC_RB_DATA_OFFSET 0
|
||||||
|
#define IFX_SSC_RB_DATA_MASK 0xFFFFFFFF
|
||||||
|
|
||||||
|
/* RXFCON and TXFCON registers */
|
||||||
|
#define IFX_SSC_XFCON_FIFO_DISABLE 0x0000
|
||||||
|
#define IFX_SSC_XFCON_FIFO_ENABLE 0x0001
|
||||||
|
#define IFX_SSC_XFCON_FIFO_FLUSH 0x0002
|
||||||
|
#define IFX_SSC_XFCON_ITL_MASK 0x00003F00
|
||||||
|
#define IFX_SSC_XFCON_ITL_OFFSET 8
|
||||||
|
|
||||||
|
/* FSTAT register */
|
||||||
|
#define IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET 0
|
||||||
|
#define IFX_SSC_FSTAT_RECEIVED_WORDS_MASK 0x003F
|
||||||
|
#define IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET 8
|
||||||
|
#define IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK 0x3F00
|
||||||
|
|
||||||
|
/* GPOCON register */
|
||||||
|
#define IFX_SSC_GPOCON_INVOUT0_POS 0
|
||||||
|
#define IFX_SSC_GPOCON_INV_OUT0 0x00000001
|
||||||
|
#define IFX_SSC_GPOCON_TRUE_OUT0 0x00000000
|
||||||
|
#define IFX_SSC_GPOCON_INVOUT1_POS 1
|
||||||
|
#define IFX_SSC_GPOCON_INV_OUT1 0x00000002
|
||||||
|
#define IFX_SSC_GPOCON_TRUE_OUT1 0x00000000
|
||||||
|
#define IFX_SSC_GPOCON_INVOUT2_POS 2
|
||||||
|
#define IFX_SSC_GPOCON_INV_OUT2 0x00000003
|
||||||
|
#define IFX_SSC_GPOCON_TRUE_OUT2 0x00000000
|
||||||
|
#define IFX_SSC_GPOCON_INVOUT3_POS 3
|
||||||
|
#define IFX_SSC_GPOCON_INV_OUT3 0x00000008
|
||||||
|
#define IFX_SSC_GPOCON_TRUE_OUT3 0x00000000
|
||||||
|
#define IFX_SSC_GPOCON_INVOUT4_POS 4
|
||||||
|
#define IFX_SSC_GPOCON_INV_OUT4 0x00000010
|
||||||
|
#define IFX_SSC_GPOCON_TRUE_OUT4 0x00000000
|
||||||
|
#define IFX_SSC_GPOCON_INVOUT5_POS 5
|
||||||
|
#define IFX_SSC_GPOCON_INV_OUT5 0x00000020
|
||||||
|
#define IFX_SSC_GPOCON_TRUE_OUT5 0x00000000
|
||||||
|
#define IFX_SSC_GPOCON_INVOUT6_POS 6
|
||||||
|
#define IFX_SSC_GPOCON_INV_OUT6 0x00000040
|
||||||
|
#define IFX_SSC_GPOCON_TRUE_OUT6 0x00000000
|
||||||
|
#define IFX_SSC_GPOCON_INVOUT7_POS 7
|
||||||
|
#define IFX_SSC_GPOCON_INV_OUT7 0x00000080
|
||||||
|
#define IFX_SSC_GPOCON_TRUE_OUT7 0x00000000
|
||||||
|
#define IFX_SSC_GPOCON_INV_OUT_ALL 0x000000FF
|
||||||
|
#define IFX_SSC_GPOCON_TRUE_OUT_ALL 0x00000000
|
||||||
|
|
||||||
|
#define IFX_SSC_GPOCON_ISCSB0_POS 8
|
||||||
|
#define IFX_SSC_GPOCON_IS_CSB0 0x00000100
|
||||||
|
#define IFX_SSC_GPOCON_IS_GPO0 0x00000000
|
||||||
|
#define IFX_SSC_GPOCON_ISCSB1_POS 9
|
||||||
|
#define IFX_SSC_GPOCON_IS_CSB1 0x00000200
|
||||||
|
#define IFX_SSC_GPOCON_IS_GPO1 0x00000000
|
||||||
|
#define IFX_SSC_GPOCON_ISCSB2_POS 10
|
||||||
|
#define IFX_SSC_GPOCON_IS_CSB2 0x00000400
|
||||||
|
#define IFX_SSC_GPOCON_IS_GPO2 0x00000000
|
||||||
|
#define IFX_SSC_GPOCON_ISCSB3_POS 11
|
||||||
|
#define IFX_SSC_GPOCON_IS_CSB3 0x00000800
|
||||||
|
#define IFX_SSC_GPOCON_IS_GPO3 0x00000000
|
||||||
|
#define IFX_SSC_GPOCON_ISCSB4_POS 12
|
||||||
|
#define IFX_SSC_GPOCON_IS_CSB4 0x00001000
|
||||||
|
#define IFX_SSC_GPOCON_IS_GPO4 0x00000000
|
||||||
|
#define IFX_SSC_GPOCON_ISCSB5_POS 13
|
||||||
|
#define IFX_SSC_GPOCON_IS_CSB5 0x00002000
|
||||||
|
#define IFX_SSC_GPOCON_IS_GPO5 0x00000000
|
||||||
|
#define IFX_SSC_GPOCON_ISCSB6_POS 14
|
||||||
|
#define IFX_SSC_GPOCON_IS_CSB6 0x00004000
|
||||||
|
#define IFX_SSC_GPOCON_IS_GPO6 0x00000000
|
||||||
|
#define IFX_SSC_GPOCON_ISCSB7_POS 15
|
||||||
|
#define IFX_SSC_GPOCON_IS_CSB7 0x00008000
|
||||||
|
#define IFX_SSC_GPOCON_IS_GPO7 0x00000000
|
||||||
|
#define IFX_SSC_GPOCON_IS_CSB_ALL 0x0000FF00
|
||||||
|
#define IFX_SSC_GPOCON_IS_GPO_ALL 0x00000000
|
||||||
|
|
||||||
|
/* GPOSTAT register */
|
||||||
|
#define IFX_SSC_GPOSTAT_OUT0 0x00000001
|
||||||
|
#define IFX_SSC_GPOSTAT_OUT1 0x00000002
|
||||||
|
#define IFX_SSC_GPOSTAT_OUT2 0x00000004
|
||||||
|
#define IFX_SSC_GPOSTAT_OUT3 0x00000008
|
||||||
|
#define IFX_SSC_GPOSTAT_OUT4 0x00000010
|
||||||
|
#define IFX_SSC_GPOSTAT_OUT5 0x00000020
|
||||||
|
#define IFX_SSC_GPOSTAT_OUT6 0x00000040
|
||||||
|
#define IFX_SSC_GPOSTAT_OUT7 0x00000080
|
||||||
|
#define IFX_SSC_GPOSTAT_OUT_ALL 0x000000FF
|
||||||
|
|
||||||
|
/* WHBGPOSTAT register */
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_CLROUT0_POS 0
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_CLR_OUT0 0x00000001
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_CLROUT1_POS 1
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_CLR_OUT1 0x00000002
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_CLROUT2_POS 2
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_CLR_OUT2 0x00000004
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_CLROUT3_POS 3
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_CLR_OUT3 0x00000008
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_CLROUT4_POS 4
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_CLR_OUT4 0x00000010
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_CLROUT5_POS 5
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_CLR_OUT5 0x00000020
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_CLROUT6_POS 6
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_CLR_OUT6 0x00000040
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_CLROUT7_POS 7
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_CLR_OUT7 0x00000080
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_CLR_OUT_ALL 0x000000FF
|
||||||
|
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_OUT0_POS 0
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_OUT1_POS 1
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_OUT2_POS 2
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_OUT3_POS 3
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_OUT4_POS 4
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_OUT5_POS 5
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_OUT6_POS 6
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_OUT7_POS 7
|
||||||
|
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_SETOUT0_POS 8
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_SET_OUT0 0x00000100
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_SETOUT1_POS 9
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_SET_OUT1 0x00000200
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_SETOUT2_POS 10
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_SET_OUT2 0x00000400
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_SETOUT3_POS 11
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_SET_OUT3 0x00000800
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_SETOUT4_POS 12
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_SET_OUT4 0x00001000
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_SETOUT5_POS 13
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_SET_OUT5 0x00002000
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_SETOUT6_POS 14
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_SET_OUT6 0x00004000
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_SETOUT7_POS 15
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_SET_OUT7 0x00008000
|
||||||
|
#define IFX_SSC_WHBGPOSTAT_SET_OUT_ALL 0x0000FF00
|
||||||
|
|
||||||
|
/* SFCON register */
|
||||||
|
#define IFX_SSC_SFCON_SF_ENABLE 0x00000001
|
||||||
|
#define IFX_SSC_SFCON_SF_DISABLE 0x00000000
|
||||||
|
#define IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE 0x00000004
|
||||||
|
#define IFX_SSC_SFCON_FIR_DISABLE_BEFORE_PAUSE 0x00000000
|
||||||
|
#define IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE 0x00000008
|
||||||
|
#define IFX_SSC_SFCON_FIR_DISABLE_AFTER_PAUSE 0x00000000
|
||||||
|
#define IFX_SSC_SFCON_DATA_LENGTH_MASK 0x0000FFF0
|
||||||
|
#define IFX_SSC_SFCON_DATA_LENGTH_OFFSET 4
|
||||||
|
#define IFX_SSC_SFCON_PAUSE_DATA_MASK 0x00030000
|
||||||
|
#define IFX_SSC_SFCON_PAUSE_DATA_OFFSET 16
|
||||||
|
#define IFX_SSC_SFCON_PAUSE_DATA_0 0x00000000
|
||||||
|
#define IFX_SSC_SFCON_PAUSE_DATA_1 0x00010000
|
||||||
|
#define IFX_SSC_SFCON_PAUSE_DATA_IDLE 0x00020000
|
||||||
|
#define IFX_SSC_SFCON_PAUSE_CLOCK_MASK 0x000C0000
|
||||||
|
#define IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET 18
|
||||||
|
#define IFX_SSC_SFCON_PAUSE_CLOCK_0 0x00000000
|
||||||
|
#define IFX_SSC_SFCON_PAUSE_CLOCK_1 0x00040000
|
||||||
|
#define IFX_SSC_SFCON_PAUSE_CLOCK_IDLE 0x00080000
|
||||||
|
#define IFX_SSC_SFCON_PAUSE_CLOCK_RUN 0x000C0000
|
||||||
|
#define IFX_SSC_SFCON_STOP_AFTER_PAUSE 0x00100000
|
||||||
|
#define IFX_SSC_SFCON_CONTINUE_AFTER_PAUSE 0x00000000
|
||||||
|
#define IFX_SSC_SFCON_PAUSE_LENGTH_MASK 0xFFC00000
|
||||||
|
#define IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET 22
|
||||||
|
#define IFX_SSC_SFCON_DATA_LENGTH_MAX 4096
|
||||||
|
#define IFX_SSC_SFCON_PAUSE_LENGTH_MAX 1024
|
||||||
|
|
||||||
|
#define IFX_SSC_SFCON_EXTRACT_DATA_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET)
|
||||||
|
#define IFX_SSC_SFCON_EXTRACT_PAUSE_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET)
|
||||||
|
#define IFX_SSC_SFCON_SET_DATA_LENGTH(value) ((value << IFX_SSC_SFCON_DATA_LENGTH_OFFSET) & IFX_SSC_SFCON_DATA_LENGTH_MASK)
|
||||||
|
#define IFX_SSC_SFCON_SET_PAUSE_LENGTH(value) ((value << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) & IFX_SSC_SFCON_PAUSE_LENGTH_MASK)
|
||||||
|
|
||||||
|
/* SFSTAT register */
|
||||||
|
#define IFX_SSC_SFSTAT_IN_DATA 0x00000001
|
||||||
|
#define IFX_SSC_SFSTAT_IN_PAUSE 0x00000002
|
||||||
|
#define IFX_SSC_SFSTAT_DATA_COUNT_MASK 0x0000FFF0
|
||||||
|
#define IFX_SSC_SFSTAT_DATA_COUNT_OFFSET 4
|
||||||
|
#define IFX_SSC_SFSTAT_PAUSE_COUNT_MASK 0xFFF00000
|
||||||
|
#define IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET 20
|
||||||
|
|
||||||
|
#define IFX_SSC_SFSTAT_EXTRACT_DATA_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET)
|
||||||
|
#define IFX_SSC_SFSTAT_EXTRACT_PAUSE_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET)
|
||||||
|
|
||||||
|
/* RXREQ register */
|
||||||
|
#define IFX_SSC_RXREQ_RXCOUNT_MASK 0x0000FFFF
|
||||||
|
#define IFX_SSC_RXREQ_RXCOUNT_OFFSET 0
|
||||||
|
|
||||||
|
/* RXCNT register */
|
||||||
|
#define IFX_SSC_RXCNT_TODO_MASK 0x0000FFFF
|
||||||
|
#define IFX_SSC_RXCNT_TODO_OFFSET 0
|
||||||
|
|
||||||
|
/* DMACON register */
|
||||||
|
#define IFX_SSC_DMACON_RXON 0x00000001
|
||||||
|
#define IFX_SSC_DMACON_RXOFF 0x00000000
|
||||||
|
#define IFX_SSC_DMACON_TXON 0x00000002
|
||||||
|
#define IFX_SSC_DMACON_TXOFF 0x00000000
|
||||||
|
#define IFX_SSC_DMACON_DMAON 0x00000003
|
||||||
|
#define IFX_SSC_DMACON_DMAOFF 0x00000000
|
||||||
|
#define IFX_SSC_DMACON_CLASS_MASK 0x0000000C
|
||||||
|
#define IFX_SSC_DMACON_CLASS_OFFSET 2
|
||||||
|
|
||||||
|
/* register access macros */
|
||||||
|
#define ifx_ssc_fstat_received_words(status) (status & 0x003F)
|
||||||
|
#define ifx_ssc_fstat_words_to_transmit(status) ((status & 0x3F00) >> 8)
|
||||||
|
|
||||||
|
#define ifx_ssc_change_status(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_WHBSTATE))
|
||||||
|
#define ifx_ssc_set_config(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_CON))
|
||||||
|
#define ifx_ssc_get_config(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_CON))
|
||||||
|
#define ifx_ssc_get_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_STATE))
|
||||||
|
#define ifx_ssc_receive(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_RB))
|
||||||
|
#define ifx_ssc_transmit(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_TB))
|
||||||
|
#define ifx_ssc_fifo_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_FSTAT))
|
||||||
|
#define ifx_ssc_set_baudrate(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_BR))
|
||||||
|
|
||||||
|
#define ifx_ssc_extract_rx_fifo_size(id) ((id & IFX_SSC_PERID_RXFS_MASK) >> IFX_SSC_PERID_RXFS_OFFSET)
|
||||||
|
#define ifx_ssc_extract_tx_fifo_size(id) ((id & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -81,12 +81,13 @@ Index: linux-2.6.23/drivers/char/watchdog/Makefile
|
||||||
Index: linux-2.6.23/drivers/char/Makefile
|
Index: linux-2.6.23/drivers/char/Makefile
|
||||||
===================================================================
|
===================================================================
|
||||||
--- linux-2.6.23.orig/drivers/char/Makefile 2007-12-13 20:41:42.000000000 +0100
|
--- linux-2.6.23.orig/drivers/char/Makefile 2007-12-13 20:41:42.000000000 +0100
|
||||||
+++ linux-2.6.23/drivers/char/Makefile 2007-12-14 22:30:59.000000000 +0100
|
+++ linux-2.6.23/drivers/char/Makefile 2007-12-14 22:41:07.000000000 +0100
|
||||||
@@ -135,3 +135,7 @@
|
@@ -135,3 +135,8 @@
|
||||||
rm $@.tmp
|
rm $@.tmp
|
||||||
|
|
||||||
endif
|
endif
|
||||||
+
|
+
|
||||||
+obj-$(CONFIG_DANUBE_LED) += danube_led.o
|
+obj-$(CONFIG_DANUBE_LED) += danube_led.o
|
||||||
+obj-$(CONFIG_DANUBE_GPIO) += danube_gpio.o
|
+obj-$(CONFIG_DANUBE_GPIO) += danube_gpio.o
|
||||||
|
+obj-$(CONFIG_DANUBE_SSC) += danube_ssc.o
|
||||||
+obj-$(CONFIG_DANUBE_EEPROM) += danube_eeprom.o
|
+obj-$(CONFIG_DANUBE_EEPROM) += danube_eeprom.o
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue