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Serial patches for .21 

SVN-Revision: 7375
owl
Hamish Guthrie 2007-05-28 14:47:05 +00:00
parent c2b3f561a8
commit 77fc5bb1da
2 changed files with 91 additions and 104 deletions
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30
target/linux/at91-2.6/patches/008-fdl-serial.patch
View File

@ -1,6 +1,6 @@
--- linux-2.6.19.2.old/drivers/serial/atmel_serial.c 2007-05-01 13:08:03.000000000 +0200
+++ linux-2.6.19.2/drivers/serial/atmel_serial.c 2007-05-09 17:13:34.000000000 +0200
@@ -173,6 +173,34 @@
--- linux-2.6.21.1.orig/drivers/serial/atmel_serial.c 2007-05-28 12:22:29.000000000 +0200
+++ linux-2.6.21.1/drivers/serial/atmel_serial.c 2007-05-28 16:39:09.000000000 +0200
@@ -174,7 +174,35 @@
at91_set_gpio_value(AT91_PIN_PA21, 0);
else
at91_set_gpio_value(AT91_PIN_PA21, 1);
@ -17,7 +17,7 @@
+ at91_set_gpio_value(AT91_PIN_PB7, 0);
+ else
+ at91_set_gpio_value(AT91_PIN_PB7, 1);
+ }
}
+
+ /*
+ * FDL VersaLink adds GPIOS to provide full modem control on
@ -32,27 +32,24 @@
+ at91_set_gpio_value(AT91_PIN_PB2, 0);
+ else
+ at91_set_gpio_value(AT91_PIN_PB2, 1);
}
+ }
}
#endif
@@ -210,8 +238,14 @@
@@ -211,8 +239,10 @@
/*
* The control signals are active low.
*/
- if (!(status & ATMEL_US_DCD))
- ret |= TIOCM_CD;
+
+ /*
+ * Ignore DCD reister for USARTS 0 and 3 as FDL Versalink uses
+ * GPIO's for these signals
+ */
+ if (!(port->mapbase == AT91RM9200_BASE_US0 || port->mapbase == AT91RM9200_BASE_US3))
+ if (!(status & ATMEL_US_DCD))
+ ret |= TIOCM_CD;
if (!(status & ATMEL_US_CTS))
ret |= TIOCM_CTS;
if (!(status & ATMEL_US_DSR))
@@ -219,6 +253,16 @@
@@ -220,6 +250,16 @@
if (!(status & ATMEL_US_RI))
ret |= TIOCM_RI;
@ -69,7 +66,7 @@
return ret;
}
@@ -510,6 +554,34 @@
@@ -511,6 +551,34 @@
}
/*
@ -104,7 +101,7 @@
* Interrupt handler
*/
static irqreturn_t atmel_interrupt(int irq, void *dev_id)
@@ -586,6 +658,24 @@
@@ -587,6 +655,23 @@
return retval;
}
@ -124,12 +121,11 @@
+ return retval;
+ }
+ }
+
+
/*
* Initialize DMA (if necessary)
*/
@@ -602,6 +692,10 @@
@@ -603,6 +688,10 @@
kfree(atmel_port->pdc_rx[0].buf);
}
free_irq(port->irq, port);
@ -140,7 +136,7 @@
return -ENOMEM;
}
pdc->dma_addr = dma_map_single(port->dev, pdc->buf, PDC_BUFFER_SIZE, DMA_FROM_DEVICE);
@@ -635,6 +729,10 @@
@@ -636,6 +725,10 @@
retval = atmel_open_hook(port);
if (retval) {
free_irq(port->irq, port);
@ -151,7 +147,7 @@
return retval;
}
}
@@ -694,6 +792,10 @@
@@ -701,6 +794,10 @@
* Free the interrupt
*/
free_irq(port->irq, port);

33
target/linux/at91-2.6/patches/009-fdl-uartinit.patch
View File

@ -1,7 +1,14 @@
diff -urN linux-2.6.19.2.old/arch/arm/mach-at91rm9200/at91rm9200_devices.c linux-2.6.19.2/arch/arm/mach-at91rm9200/at91rm9200_devices.c
--- linux-2.6.19.2.old/arch/arm/mach-at91rm9200/at91rm9200_devices.c 2007-05-01 13:08:02.000000000 +0200
+++ linux-2.6.19.2/arch/arm/mach-at91rm9200/at91rm9200_devices.c 2007-05-09 12:59:58.000000000 +0200
@@ -709,6 +709,10 @@
--- linux-2.6.21.1.orig/arch/arm/mach-at91/at91rm9200_devices.c 2007-05-28 12:22:29.000000000 +0200
+++ linux-2.6.21.1/arch/arm/mach-at91/at91rm9200_devices.c 2007-05-28 16:44:36.000000000 +0200
@@ -618,7 +618,6 @@
#if defined(CONFIG_NEW_LEDS)
-
static struct platform_device at91_leds = {
.name = "at91_leds",
.id = -1,
@@ -724,6 +723,10 @@
* We need to drive the pin manually. Default is off (RTS is active low).
*/
at91_set_gpio_output(AT91_PIN_PA21, 1);
@ -12,7 +19,7 @@ diff -urN linux-2.6.19.2.old/arch/arm/mach-at91rm9200/at91rm9200_devices.c linux
}
static struct resource uart1_resources[] = {
@@ -820,6 +824,12 @@
@@ -835,6 +838,12 @@
{
at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */
at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */
@ -25,19 +32,3 @@ diff -urN linux-2.6.19.2.old/arch/arm/mach-at91rm9200/at91rm9200_devices.c linux
}
struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
diff -urN linux-2.6.19.2.old/arch/arm/mach-at91rm9200/vlink_leds.c linux-2.6.19.2/arch/arm/mach-at91rm9200/vlink_leds.c
--- linux-2.6.19.2.old/arch/arm/mach-at91rm9200/vlink_leds.c 2007-05-01 13:08:03.000000000 +0200
+++ linux-2.6.19.2/arch/arm/mach-at91rm9200/vlink_leds.c 2007-05-09 12:58:42.000000000 +0200
@@ -114,12 +114,6 @@
at91_set_gpio_input(AT91_PIN_PB8, 1); // JIGPRESENT
at91_set_gpio_input(AT91_PIN_PB22, 1); // PWR_IND
- at91_set_gpio_input(AT91_PIN_PA19, 1); // P1DTR
- at91_set_gpio_input(AT91_PIN_PA24, 1); // P2DTR
- at91_set_gpio_output(AT91_PIN_PB29, 1); // P2DCD
- at91_set_gpio_output(AT91_PIN_PB2, 1); // P2RI
- at91_set_gpio_output(AT91_PIN_PB6, 1); // P1DCD
- at91_set_gpio_output(AT91_PIN_PB7, 1); // P1RI
at91_set_gpio_input(AT91_PIN_PB27, 1); // UDB_CNX
at91_set_gpio_output(AT91_PIN_PB28, 1); // UDB_PUP