mirror of https://github.com/hak5/openwrt-owl.git
parent
046c32e6bf
commit
7524480b82
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@ -98,7 +98,7 @@
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/* Workaround for unstable PLL clock */
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- if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
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- (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
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+ if ((tp->phy_id & PHY_ID_MASK != PHY_ID_BCM5750_2) &&
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+ if ((tp->phy_id & PHY_ID_MASK) != PHY_ID_BCM5750_2 &&
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+ /* !!! FIXME !!! */
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+ ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
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+ (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
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@ -252,14 +252,6 @@
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if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
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~GRC_LCLCTRL_GPIO_OUTPUT1);
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@@ -12063,7 +12133,6 @@ static int __devinit tg3_get_invariants(
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tp->write32 = tg3_write_flush_reg32;
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}
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-
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if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
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(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
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tp->write32_tx_mbox = tg3_write32_tx_mbox;
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@@ -12099,6 +12168,11 @@ static int __devinit tg3_get_invariants(
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
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tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
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@ -98,7 +98,7 @@
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/* Workaround for unstable PLL clock */
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- if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
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- (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
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+ if ((tp->phy_id & PHY_ID_MASK != PHY_ID_BCM5750_2) &&
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+ if ((tp->phy_id & PHY_ID_MASK) != PHY_ID_BCM5750_2 &&
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+ /* !!! FIXME !!! */
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+ ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
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+ (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
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@ -252,14 +252,6 @@
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if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
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~GRC_LCLCTRL_GPIO_OUTPUT1);
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@@ -12100,7 +12170,6 @@ static int __devinit tg3_get_invariants(
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tp->write32 = tg3_write_flush_reg32;
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}
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-
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if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
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(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
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tp->write32_tx_mbox = tg3_write32_tx_mbox;
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@@ -12136,6 +12205,11 @@ static int __devinit tg3_get_invariants(
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
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tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
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@ -8,7 +8,7 @@
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int err = -ENOMEM;
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u32 tmp, flags = 0;
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+ if (ssb_dma_set_mask(dev, DMA_32BIT_MASK))
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+ if (ssb_dma_set_mask(dev, DMA_BIT_MASK(32)))
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+ return -EOPNOTSUPP;
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+
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if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) {
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@ -80,7 +80,7 @@
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/* Workaround for unstable PLL clock */
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- if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
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- (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
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+ if ((tp->phy_id & PHY_ID_MASK != PHY_ID_BCM5750_2) &&
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+ if ((tp->phy_id & PHY_ID_MASK) != PHY_ID_BCM5750_2 &&
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+ /* !!! FIXME !!! */
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+ ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
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+ (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
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