mirror of https://github.com/hak5/openwrt-owl.git
Revert "ramips: mt7621-spi: replace the driver with upstream staging one"
This reverts commit a44f000077.
This breaks some mt7621 devices.
Signed-off-by: John Crispin <john@phrozen.org>
master
John Crispin
parent
48a7a2a75d
commit
749a29f76c
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@ -5,8 +5,6 @@ Subject: [PATCH 43/53] spi: add mt7621 support
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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Note: This patch contains upstream mt7621-spi at 9c562d8411a54f6731cdc587c29968d9e8610c85
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drivers/spi/Kconfig | 6 +
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drivers/spi/Makefile | 1 +
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drivers/spi/spi-mt7621.c | 480 ++++++++++++++++++++++++++++++++++++++++++++++
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@ -40,7 +38,7 @@ Note: This patch contains upstream mt7621-spi at 9c562d8411a54f6731cdc587c29968d
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obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
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--- /dev/null
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+++ b/drivers/spi/spi-mt7621.c
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@@ -0,0 +1,515 @@
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@@ -0,0 +1,494 @@
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+/*
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+ * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
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+ *
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@ -98,8 +96,7 @@ Note: This patch contains upstream mt7621-spi at 9c562d8411a54f6731cdc587c29968d
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+#define MT7621_CPOL BIT(4)
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+#define MT7621_LSB_FIRST BIT(3)
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+
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+#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | \
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+ SPI_LSB_FIRST | SPI_CS_HIGH)
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+#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
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+
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+struct mt7621_spi;
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+
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@ -109,7 +106,6 @@ Note: This patch contains upstream mt7621-spi at 9c562d8411a54f6731cdc587c29968d
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+ unsigned int sys_freq;
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+ unsigned int speed;
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+ struct clk *clk;
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+ int pending_write;
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+
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+ struct mt7621_spi_ops *ops;
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+};
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@ -135,13 +131,14 @@ Note: This patch contains upstream mt7621-spi at 9c562d8411a54f6731cdc587c29968d
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+
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+ master |= 7 << 29;
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+ master |= 1 << 2;
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+#ifdef CONFIG_SOC_MT7620
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+ if (duplex)
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+ master |= 1 << 10;
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+ else
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+#endif
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+ master &= ~(1 << 10);
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+
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+ mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
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+ rs->pending_write = 0;
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+}
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+
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+static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
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@ -150,7 +147,7 @@ Note: This patch contains upstream mt7621-spi at 9c562d8411a54f6731cdc587c29968d
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+ int cs = spi->chip_select;
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+ u32 polar = 0;
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+
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+ mt7621_spi_reset(rs, cs);
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+ mt7621_spi_reset(rs, cs);
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+ if (enable)
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+ polar = BIT(cs);
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+ mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
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@ -183,34 +180,36 @@ Note: This patch contains upstream mt7621-spi at 9c562d8411a54f6731cdc587c29968d
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+ reg |= MT7621_LSB_FIRST;
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+
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+ reg &= ~(MT7621_CPHA | MT7621_CPOL);
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+ switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
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+ case SPI_MODE_0:
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+ break;
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+ case SPI_MODE_1:
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+ reg |= MT7621_CPHA;
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+ break;
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+ case SPI_MODE_2:
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+ reg |= MT7621_CPOL;
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+ break;
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+ case SPI_MODE_3:
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+ reg |= MT7621_CPOL | MT7621_CPHA;
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+ break;
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+ switch(spi->mode & (SPI_CPOL | SPI_CPHA)) {
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+ case SPI_MODE_0:
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+ break;
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+ case SPI_MODE_1:
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+ reg |= MT7621_CPHA;
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+ break;
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+ case SPI_MODE_2:
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+ reg |= MT7621_CPOL;
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+ break;
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+ case SPI_MODE_3:
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+ reg |= MT7621_CPOL | MT7621_CPHA;
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+ break;
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+ }
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+ mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
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+
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+ return 0;
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+}
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+
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+static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
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+static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
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+{
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+ struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
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+ int i;
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+
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+ for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
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+ u32 status;
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+
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+ status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
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+ if ((status & SPITRANS_BUSY) == 0)
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+ if ((status & SPITRANS_BUSY) == 0) {
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+ return 0;
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+ }
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+ cpu_relax();
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+ udelay(1);
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+ }
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@ -218,92 +217,6 @@ Note: This patch contains upstream mt7621-spi at 9c562d8411a54f6731cdc587c29968d
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+ return -ETIMEDOUT;
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+}
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+
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+static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs,
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+ int rx_len, u8 *buf)
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+{
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+ /* Combine with any pending write, and perform one or
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+ * more half-duplex transactions reading 'len' bytes.
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+ * Data to be written is already in MT7621_SPI_DATA*
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+ */
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+ int tx_len = rs->pending_write;
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+
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+ rs->pending_write = 0;
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+
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+ while (rx_len || tx_len) {
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+ int i;
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+ u32 val = (min(tx_len, 4) * 8) << 24;
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+ int rx = min(rx_len, 32);
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+
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+ if (tx_len > 4)
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+ val |= (tx_len - 4) * 8;
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+ val |= (rx * 8) << 12;
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+ mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
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+
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+ tx_len = 0;
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+
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+ val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
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+ val |= SPI_CTL_START;
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+ mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
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+
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+ mt7621_spi_wait_till_ready(rs);
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+
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+ for (i = 0; i < rx; i++) {
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+ if ((i % 4) == 0)
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+ val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
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+ *buf++ = val & 0xff;
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+ val >>= 8;
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+ }
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+ rx_len -= i;
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+ }
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+}
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+
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+static inline void mt7621_spi_flush(struct mt7621_spi *rs)
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+{
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+ mt7621_spi_read_half_duplex(rs, 0, NULL);
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+}
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+
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+static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs,
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+ int tx_len, const u8 *buf)
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+{
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+ int val = 0;
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+ int len = rs->pending_write;
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+
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+ if (len & 3) {
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+ val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3));
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+ if (len < 4) {
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+ val <<= (4 - len) * 8;
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+ val = swab32(val);
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+ }
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+ }
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+
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+ while (tx_len > 0) {
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+ if (len >= 36) {
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+ rs->pending_write = len;
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+ mt7621_spi_flush(rs);
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+ len = 0;
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+ }
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+
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+ val |= *buf++ << (8 * (len & 3));
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+ len++;
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+ if ((len & 3) == 0) {
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+ if (len == 4)
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+ /* The byte-order of the opcode is weird! */
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+ val = swab32(val);
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+ mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val);
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+ val = 0;
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+ }
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+ tx_len -= 1;
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+ }
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+ if (len & 3) {
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+ if (len < 4) {
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+ val = swab32(val);
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+ val >>= (4 - len) * 8;
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+ }
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+ mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val);
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+ }
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+ rs->pending_write = len;
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+}
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+
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+static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
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+ struct spi_message *m)
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+{
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@ -312,30 +225,84 @@ Note: This patch contains upstream mt7621-spi at 9c562d8411a54f6731cdc587c29968d
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+ unsigned int speed = spi->max_speed_hz;
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+ struct spi_transfer *t = NULL;
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+ int status = 0;
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+ int i, len = 0;
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+ int rx_len = 0;
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+ u32 data[9] = { 0 };
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+ u32 val;
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+
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+ mt7621_spi_wait_till_ready(rs);
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+ mt7621_spi_wait_till_ready(spi);
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+
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+ list_for_each_entry(t, &m->transfers, transfer_list) {
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+ const u8 *buf = t->tx_buf;
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+
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+ if (t->rx_buf)
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+ rx_len += t->len;
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+
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+ if (!buf)
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+ continue;
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+
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+ list_for_each_entry(t, &m->transfers, transfer_list)
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+ if (t->speed_hz < speed)
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+ speed = t->speed_hz;
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+
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+ /*
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+ * m25p80 might attempt to write more data than we can handle.
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+ * truncate the message to what we can fit into the registers
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+ */
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+ if (len + t->len > 36)
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+ t->len = 36 - len;
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+
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+ for (i = 0; i < t->len; i++, len++)
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+ data[len / 4] |= buf[i] << (8 * (len & 3));
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+ }
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+
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+ if (WARN_ON(rx_len > 32)) {
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+ status = -EIO;
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+ goto msg_done;
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+ }
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+
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+ if (mt7621_spi_prepare(spi, speed)) {
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+ status = -EIO;
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+ goto msg_done;
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+ }
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+ data[0] = swab32(data[0]);
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+ if (len < 4)
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+ data[0] >>= (4 - len) * 8;
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+
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+ for (i = 0; i < len; i += 4)
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+ mt7621_spi_write(rs, MT7621_SPI_OPCODE + i, data[i / 4]);
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+
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+ val = (min_t(int, len, 4) * 8) << 24;
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+ if (len > 4)
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+ val |= (len - 4) * 8;
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+ val |= (rx_len * 8) << 12;
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+ mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
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+
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+ mt7621_spi_set_cs(spi, 1);
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+ m->actual_length = 0;
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+ list_for_each_entry(t, &m->transfers, transfer_list) {
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+ if (t->rx_buf)
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+ mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf);
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+ else if (t->tx_buf)
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+ mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf);
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+ m->actual_length += t->len;
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+ }
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+ mt7621_spi_flush(rs);
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+
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+ val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
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+ val |= SPI_CTL_START;
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+ mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
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+
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+ mt7621_spi_wait_till_ready(spi);
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+
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+ mt7621_spi_set_cs(spi, 0);
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+
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+ for (i = 0; i < rx_len; i += 4)
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+ data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
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+
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+ m->actual_length = len + rx_len;
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+
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+ len = 0;
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+ list_for_each_entry(t, &m->transfers, transfer_list) {
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+ u8 *buf = t->rx_buf;
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+
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+ if (!buf)
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+ continue;
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+
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+ for (i = 0; i < t->len; i++, len++)
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+ buf[i] = data[len / 4] >> (8 * (len & 3));
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+ }
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+
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+msg_done:
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+ m->status = status;
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+ spi_finalize_current_message(master);
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@ -343,6 +310,7 @@ Note: This patch contains upstream mt7621-spi at 9c562d8411a54f6731cdc587c29968d
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+ return 0;
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+}
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+
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+#ifdef CONFIG_SOC_MT7620
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+static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
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+ struct spi_message *m)
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+{
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@ -356,7 +324,7 @@ Note: This patch contains upstream mt7621-spi at 9c562d8411a54f6731cdc587c29968d
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+ u32 data[9] = { 0 };
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+ u32 val = 0;
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+
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+ mt7621_spi_wait_till_ready(rs);
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+ mt7621_spi_wait_till_ready(spi);
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+
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+ list_for_each_entry(t, &m->transfers, transfer_list) {
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+ const u8 *buf = t->tx_buf;
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@ -401,7 +369,7 @@ Note: This patch contains upstream mt7621-spi at 9c562d8411a54f6731cdc587c29968d
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+ val |= SPI_CTL_START;
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+ mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
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+
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+ mt7621_spi_wait_till_ready(rs);
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+ mt7621_spi_wait_till_ready(spi);
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+
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+ mt7621_spi_set_cs(spi, 0);
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+
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@ -427,15 +395,18 @@ Note: This patch contains upstream mt7621-spi at 9c562d8411a54f6731cdc587c29968d
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+
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+ return 0;
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+}
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+#endif
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+
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+static int mt7621_spi_transfer_one_message(struct spi_master *master,
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+ struct spi_message *m)
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+{
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+ struct spi_device *spi = m->spi;
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+#ifdef CONFIG_SOC_MT7620
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+ int cs = spi->chip_select;
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+
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+ if (cs)
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+ return mt7621_spi_transfer_full_duplex(master, m);
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+#endif
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+ return mt7621_spi_transfer_half_duplex(master, m);
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+}
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+
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@ -462,6 +433,11 @@ Note: This patch contains upstream mt7621-spi at 9c562d8411a54f6731cdc587c29968d
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+};
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+MODULE_DEVICE_TABLE(of, mt7621_spi_match);
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+
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+static size_t mt7621_max_transfer_size(struct spi_device *spi)
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+{
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+ return 32;
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+}
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+
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+static int mt7621_spi_probe(struct platform_device *pdev)
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+{
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+ const struct of_device_id *match;
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@ -507,6 +483,7 @@ Note: This patch contains upstream mt7621-spi at 9c562d8411a54f6731cdc587c29968d
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+ master->bits_per_word_mask = SPI_BPW_MASK(8);
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+ master->dev.of_node = pdev->dev.of_node;
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+ master->num_chipselect = 2;
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+ master->max_transfer_size = mt7621_max_transfer_size;
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+
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+ dev_set_drvdata(&pdev->dev, master);
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+
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@ -516,7 +493,6 @@ Note: This patch contains upstream mt7621-spi at 9c562d8411a54f6731cdc587c29968d
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+ rs->master = master;
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+ rs->sys_freq = clk_get_rate(rs->clk);
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+ rs->ops = ops;
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+ rs->pending_write = 0;
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+ dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
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+
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+ device_reset(&pdev->dev);
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@ -545,6 +521,7 @@ Note: This patch contains upstream mt7621-spi at 9c562d8411a54f6731cdc587c29968d
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+static struct platform_driver mt7621_spi_driver = {
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+ .driver = {
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+ .name = DRIVER_NAME,
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+ .owner = THIS_MODULE,
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+ .of_match_table = mt7621_spi_match,
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+ },
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+ .probe = mt7621_spi_probe,
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