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initial merge of infineon code for amazon, pci is still broken a bit. a big thank you goes to infineon for providing info and reference code 

SVN-Revision: 8137
owl
John Crispin 2007-07-23 22:10:11 +00:00
parent bee2897419
commit 7470547083
47 changed files with 26109 additions and 0 deletions
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25
target/linux/amazon-2.6/Makefile Normal file
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#
# Copyright (C) 2006 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
ARCH:=mips
BOARD:=amazon
BOARDNAME:=Infineon Amazon
FEATURES:=squashfs jffs2 broken
define Target/Description
Build firmware images for Infineon Amazon boards
endef
KERNELNAME:="uImage"
include $(INCLUDE_DIR)/kernel-build.mk
# include the profiles
-include profiles/*.mk
$(eval $(call BuildKernel))

14
target/linux/amazon-2.6/base-files/default/etc/config/network Normal file
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# Copyright (C) 2006 OpenWrt.org
config interface loopback
option ifname lo
option proto static
option ipaddr 127.0.0.1
option netmask 255.0.0.0
config interface lan
option ifname eth1
option type bridge
option proto static
option ipaddr 192.168.1.1
option netmask 255.255.255.0

211
target/linux/amazon-2.6/config/default Normal file
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CONFIG_32BIT=y
# CONFIG_64BIT is not set
# CONFIG_64BIT_PHYS_ADDR is not set
CONFIG_AMAZON=y
CONFIG_AMAZON_ASC_UART=y
CONFIG_AMAZON_MTD=y
CONFIG_AMAZON_NET_SW=y
CONFIG_AMAZON_PCI=y
CONFIG_AMAZON_WDT=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
# CONFIG_ATM is not set
# CONFIG_ATMEL is not set
CONFIG_BASE_SMALL=0
# CONFIG_BCM43XX is not set
CONFIG_BITREVERSE=y
# CONFIG_BT is not set
CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/bin/sh"
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_SYNC=y
# CONFIG_CPU_LITTLE_ENDIAN is not set
CONFIG_CPU_MIPS32=y
CONFIG_CPU_MIPS32_R1=y
# CONFIG_CPU_MIPS32_R2 is not set
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
CONFIG_CPU_MIPSR1=y
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_DDB5477 is not set
# CONFIG_DM9000 is not set
CONFIG_DMA_NEED_PCI_MAP_STATE=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_EARLY_PRINTK=y
CONFIG_FS_POSIX_ACL=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
# CONFIG_GENERIC_GPIO is not set
# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
# CONFIG_GEN_RTC is not set
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAVE_STD_PC_SERIAL_PORT=y
# CONFIG_HERMES is not set
# CONFIG_HOSTAP is not set
CONFIG_HW_HAS_PCI=y
CONFIG_HW_RANDOM=y
# CONFIG_I2C is not set
# CONFIG_IDE is not set
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_IPW2100 is not set
# CONFIG_IPW2200 is not set
CONFIG_IRQ_CPU=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
# CONFIG_MACH_VR41XX is not set
CONFIG_MIPS=y
# CONFIG_MIPS_ATLAS is not set
# CONFIG_MIPS_BOSPORUS is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MIPS_DB1000 is not set
# CONFIG_MIPS_DB1100 is not set
# CONFIG_MIPS_DB1200 is not set
# CONFIG_MIPS_DB1500 is not set
# CONFIG_MIPS_DB1550 is not set
# CONFIG_MIPS_EV64120 is not set
CONFIG_MIPS_L1_CACHE_SHIFT=5
# CONFIG_MIPS_MALTA is not set
# CONFIG_MIPS_MIRAGE is not set
# CONFIG_MIPS_MTX1 is not set
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_PB1000 is not set
# CONFIG_MIPS_PB1100 is not set
# CONFIG_MIPS_PB1200 is not set
# CONFIG_MIPS_PB1500 is not set
# CONFIG_MIPS_PB1550 is not set
# CONFIG_MIPS_SEAD is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MIPS_VPE_LOADER is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_MOMENCO_OCELOT_G is not set
CONFIG_MTD=y
# CONFIG_MTD_ABSENT is not set
CONFIG_MTD_AMAZON_BUS_WIDTH_16=y
# CONFIG_MTD_AMAZON_BUS_WIDTH_32 is not set
# CONFIG_MTD_AMAZON_BUS_WIDTH_8 is not set
# CONFIG_MTD_AMAZON_FLASH_SIZE_16 is not set
# CONFIG_MTD_AMAZON_FLASH_SIZE_2 is not set
CONFIG_MTD_AMAZON_FLASH_SIZE_4=y
# CONFIG_MTD_AMAZON_FLASH_SIZE_8 is not set
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_MTD_BLOCK2MTD is not set
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_AMDSTD=y
# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
# CONFIG_MTD_CFI_GEOMETRY is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
CONFIG_MTD_CFI_NOSWAP=y
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_CHAR=y
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_CONCAT is not set
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
CONFIG_MTD_MAP_BANK_WIDTH_2=y
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_OBSOLETE_CHIPS is not set
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_OTP is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_PCI is not set
# CONFIG_MTD_PHRAM is not set
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_BANKWIDTH=0
CONFIG_MTD_PHYSMAP_LEN=0x0
CONFIG_MTD_PHYSMAP_START=0x0
# CONFIG_MTD_PLATRAM is not set
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_RAM is not set
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_REDBOOT_PARTS_READONLY=y
# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_NET_PCI is not set
CONFIG_NET_SCH_FIFO=y
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_PAGE_SIZE_16KB is not set
CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_64KB is not set
# CONFIG_PAGE_SIZE_8KB is not set
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_PNPACPI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PRISM54 is not set
# CONFIG_RTC is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
# CONFIG_SERIAL_8250 is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_PTSWARM is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
# CONFIG_TOSHIBA_JMR3927 is not set
# CONFIG_TOSHIBA_RBTX4927 is not set
# CONFIG_TOSHIBA_RBTX4938 is not set
CONFIG_TRAD_SIGNALS=y
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_USB is not set

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target/linux/amazon-2.6/files/arch/mips/amazon/Kconfig Normal file
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# copyright 2007 john crispin <blogic@openwrt.org>
menu "Amazon built-in"
config AMAZON_ASC_UART
bool "Amazon asc uart"
select SERIAL_CORE
select SERIAL_CORE_CONSOLE
default y
config AMAZON_PCI
bool "Amazon PCI support"
default y
select HW_HAS_PCI
select PCI
config AMAZON_NET_SW
bool "Amazon network"
default y
config AMAZON_WDT
bool "Amazon watchdog timer"
default y
config AMAZON_MTD
bool "Amazon MTD map"
default y
choice
prompt "Flash Size"
depends on AMAZON_MTD
config MTD_AMAZON_FLASH_SIZE_2
bool "2MB"
config MTD_AMAZON_FLASH_SIZE_4
bool "4MB"
config MTD_AMAZON_FLASH_SIZE_8
bool "8MB"
config MTD_AMAZON_FLASH_SIZE_16
bool "16MB"
endchoice
choice
prompt "Bus Width"
depends on AMAZON_MTD
config MTD_AMAZON_BUS_WIDTH_8
bool "8-bit"
config MTD_AMAZON_BUS_WIDTH_16
bool "16-bit"
config MTD_AMAZON_BUS_WIDTH_32
bool "32-bit"
endchoice
endmenu

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target/linux/amazon-2.6/files/arch/mips/amazon/Makefile Normal file
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#
# Copyright 2007 openwrt.org
# John Crispin <blogic@openwrt.org>
#
# Makefile for Infineon Amazon
#
obj-y := dma-core.o interrupt.o prom.o setup.o
obj-$(CONFIG_PCI) += pci.o

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target/linux/amazon-2.6/files/arch/mips/amazon/dma-core.c Normal file
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69
target/linux/amazon-2.6/files/arch/mips/amazon/dma-core.h Normal file
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#ifndef DMA_CORE_H
#define DMA_CORE_H
#define AMAZON_DMA_REG32(reg_num) *((volatile u32*)(reg_num))
#define AMAZON_DMA_CH_STEP 4
#define COMB_ISR_RX_MASK 0xfe000000
#define COMB_ISR_TX_MASK 0x01f00000
#define DMA_OWN 1
#define CPU_OWN 0
#define DMA_MAJOR 250
//Descriptors
#define DMA_DESC_OWN_CPU 0x0
#define DMA_DESC_OWN_DMA 0x80000000
#define DMA_DESC_CPT_SET 0x40000000
#define DMA_DESC_SOP_SET 0x20000000
#define DMA_DESC_EOP_SET 0x10000000
#define switch_rx_chan_base 0
#define switch_tx_chan_base 7
#define switch2_rx_chan_base 2
#define switch2_tx_chan_base 8
#define TPE_rx_chan_base 4
#define TPE_tx_chan_base 9
#define DPLus2FPI_rx_chan_base 6
#define DPLus2FPI_tx_chan_base 11
#define RX_CHAN_NUM 7
#define TX_CHAN_NUM 5
#define CHAN_TOTAL_NUM (RX_CHAN_NUM+TX_CHAN_NUM)
#define DEFAULT_OFFSET 20
#define DESCRIPTOR_SIZE 8
typedef struct dev_list{
struct dma_device_info* dev;
int weight;
struct dev_list* prev;
struct dev_list* next;
}dev_list;
typedef struct channel_info{
char device_name[16];
int occupied;
enum attr_t attr;
int current_desc;
int weight;
int default_weight;
int desc_num;
int burst_len;
int desc_len;
int desc_ofst;
int packet_size;
int offset_from_base;
int control;
void* opt[DEFAULT_OFFSET];
u8* (*buffer_alloc)(int len,int* offset, void** opt);
int (*buffer_free)(u8* dataptr,void* opt);
int (*intr_handler)(struct dma_device_info* info,int status);
struct dma_device_info* dma_dev;
}channel_info;
#endif

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/*
* Gary Jennejohn (C) 2003 <gj@denx.de>
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* Routines for generic manipulation of the interrupts found on the
* AMAZON boards.
*/
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <asm/amazon/amazon.h>
#include <asm/amazon/irq.h>
#include <asm/bootinfo.h>
#include <asm/irq_cpu.h>
#include <asm/irq.h>
#include <asm/time.h>
static void amazon_disable_irq(unsigned int irq_nr)
{
/* have to access the correct register here */
if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0)
/* access IM0 DMA channels */
*AMAZON_ICU_IM0_IER &= (~(AMAZON_DMA_H_MASK));
else if (irq_nr <= INT_NUM_IM0_IRL31 && irq_nr >= INT_NUM_IM0_IRL12)
/* access IM0 except DMA*/
*AMAZON_ICU_IM0_IER &= (~AMAZON_ICU_IM0_IER_IR(irq_nr));
else if (irq_nr <= INT_NUM_IM1_IRL31 && irq_nr >= INT_NUM_IM1_IRL0)
/* access IM1 */
*AMAZON_ICU_IM1_IER &= (~AMAZON_ICU_IM1_IER_IR(irq_nr - INT_NUM_IM1_IRL0));
else if (irq_nr <= INT_NUM_IM2_IRL31 && irq_nr >= INT_NUM_IM2_IRL0)
/* access IM2 */
*AMAZON_ICU_IM2_IER &= (~AMAZON_ICU_IM2_IER_IR(irq_nr - INT_NUM_IM2_IRL0));
else if (irq_nr <= INT_NUM_IM3_IRL31 && irq_nr >= INT_NUM_IM3_IRL0)
/* access IM3 */
*AMAZON_ICU_IM3_IER &= (~AMAZON_ICU_IM3_IER_IR((irq_nr - INT_NUM_IM3_IRL0)));
else if (irq_nr <= INT_NUM_IM4_IRL31 && irq_nr >= INT_NUM_IM4_IRL0)
/* access IM4 */
*AMAZON_ICU_IM4_IER &= (~AMAZON_ICU_IM4_IER_IR((irq_nr - INT_NUM_IM4_IRL0)));
}
static void amazon_mask_and_ack_irq(unsigned int irq_nr)
{
/* have to access the correct register here */
if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0) {
/* access IM0 DMA channels */
*AMAZON_ICU_IM0_IER &= (~(AMAZON_DMA_H_MASK)); /* mask */
*AMAZON_ICU_IM0_ISR = AMAZON_DMA_H_MASK; /* ack */
} else if (irq_nr <= INT_NUM_IM0_IRL31 && irq_nr >= INT_NUM_IM0_IRL12) {
/* access IM0 except DMA */
*AMAZON_ICU_IM0_IER &= ~AMAZON_ICU_IM0_IER_IR(irq_nr - INT_NUM_IM0_IRL0); /* mask */
*AMAZON_ICU_IM0_ISR = AMAZON_ICU_IM0_ISR_IR(irq_nr - INT_NUM_IM0_IRL0); /* ack */
} else if (irq_nr <= INT_NUM_IM1_IRL31 && irq_nr >= INT_NUM_IM1_IRL0) {
/* access IM1 */
*AMAZON_ICU_IM1_IER &= ~AMAZON_ICU_IM1_IER_IR(irq_nr - INT_NUM_IM1_IRL0); /* mask */
*AMAZON_ICU_IM1_ISR = AMAZON_ICU_IM1_ISR_IR(irq_nr - INT_NUM_IM1_IRL0); /* ack */
} else if (irq_nr <= INT_NUM_IM2_IRL31 && irq_nr >= INT_NUM_IM2_IRL0) {
/* access IM2 */
*AMAZON_ICU_IM2_IER &= ~AMAZON_ICU_IM2_IER_IR(irq_nr - INT_NUM_IM2_IRL0); /* mask */
*AMAZON_ICU_IM2_ISR = AMAZON_ICU_IM2_ISR_IR(irq_nr - INT_NUM_IM2_IRL0); /* ack */
} else if (irq_nr <= INT_NUM_IM3_IRL31 && irq_nr >= INT_NUM_IM3_IRL0) {
/* access IM3 */
*AMAZON_ICU_IM3_IER &= ~AMAZON_ICU_IM3_IER_IR(irq_nr - INT_NUM_IM3_IRL0); /* mask */
*AMAZON_ICU_IM3_ISR = AMAZON_ICU_IM3_ISR_IR(irq_nr - INT_NUM_IM3_IRL0); /* ack */
} else if (irq_nr <= INT_NUM_IM4_IRL31 && irq_nr >= INT_NUM_IM4_IRL0) {
*AMAZON_ICU_IM4_IER &= ~AMAZON_ICU_IM4_IER_IR(irq_nr - INT_NUM_IM4_IRL0); /* mask */
*AMAZON_ICU_IM4_ISR = AMAZON_ICU_IM4_ISR_IR(irq_nr - INT_NUM_IM4_IRL0); /* ack */
}
}
static void amazon_enable_irq(unsigned int irq_nr)
{
/* have to access the correct register here */
if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0)
/* access IM0 DMA*/
*AMAZON_ICU_IM0_IER |= AMAZON_DMA_H_MASK;
else if (irq_nr <= INT_NUM_IM0_IRL31 && irq_nr >= INT_NUM_IM0_IRL12)
/* access IM0 except DMA*/
*AMAZON_ICU_IM0_IER |= AMAZON_ICU_IM0_IER_IR(irq_nr - INT_NUM_IM0_IRL0);
else if (irq_nr <= INT_NUM_IM1_IRL31 && irq_nr >= INT_NUM_IM1_IRL0)
/* access IM1 */
*AMAZON_ICU_IM1_IER |= AMAZON_ICU_IM1_IER_IR(irq_nr - INT_NUM_IM1_IRL0);
else if (irq_nr <= INT_NUM_IM2_IRL31 && irq_nr >= INT_NUM_IM2_IRL0)
/* access IM2 */
*AMAZON_ICU_IM2_IER |= AMAZON_ICU_IM2_IER_IR(irq_nr - INT_NUM_IM2_IRL0);
else if (irq_nr <= INT_NUM_IM3_IRL31 && irq_nr >= INT_NUM_IM3_IRL0)
/* access IM3 */
*AMAZON_ICU_IM3_IER |= AMAZON_ICU_IM3_IER_IR((irq_nr - INT_NUM_IM3_IRL0));
else if (irq_nr <= INT_NUM_IM4_IRL31 && irq_nr >= INT_NUM_IM4_IRL0)
/* access IM4 */
*AMAZON_ICU_IM4_IER |= AMAZON_ICU_IM4_IER_IR((irq_nr - INT_NUM_IM4_IRL0));
}
static unsigned int amazon_startup_irq(unsigned int irq)
{
amazon_enable_irq(irq);
return 0;
}
static void amazon_end_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
amazon_enable_irq(irq);
}
}
static struct hw_interrupt_type amazon_irq_type = {
"AMAZON",
.startup = amazon_startup_irq,
.enable = amazon_enable_irq,
.disable = amazon_disable_irq,
.unmask = amazon_enable_irq,
.ack = amazon_mask_and_ack_irq,
.mask = amazon_disable_irq,
.mask_ack = amazon_mask_and_ack_irq,
.end = amazon_end_irq
};
/* Cascaded interrupts from IM0 */
static inline void amazon_hw0_irqdispatch(void)
{
u32 irq;
irq = (*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM0_VEC_MASK;
if (irq <= 11 && irq >= 0) {
//DMA fixed to IM0_IRL0
irq = 0;
}
do_IRQ(irq + INT_NUM_IM0_IRL0);
}
/* Cascaded interrupts from IM1 */
static inline void amazon_hw1_irqdispatch(void)
{
u32 irq;
irq = ((*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM1_VEC_MASK) >> 5;
do_IRQ(irq + INT_NUM_IM1_IRL0);
}
/* Cascaded interrupts from IM2 */
static inline void amazon_hw2_irqdispatch(void)
{
u32 irq;
irq = ((*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM2_VEC_MASK) >> 10;
do_IRQ(irq + INT_NUM_IM2_IRL0);
}
/* Cascaded interrupts from IM3 */
static inline void amazon_hw3_irqdispatch(void)
{
u32 irq;
irq = ((*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM3_VEC_MASK) >> 15;
do_IRQ(irq + INT_NUM_IM3_IRL0);
}
/* Cascaded interrupts from IM4 */
static inline void amazon_hw4_irqdispatch(void)
{
u32 irq;
irq = ((*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM4_VEC_MASK) >> 20;
do_IRQ(irq + INT_NUM_IM4_IRL0);
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & CAUSEF_IP7){
do_IRQ(MIPS_CPU_TIMER_IRQ);
}
else if (pending & CAUSEF_IP2)
amazon_hw0_irqdispatch();
else if (pending & CAUSEF_IP3)
amazon_hw1_irqdispatch();
else if (pending & CAUSEF_IP4)
amazon_hw2_irqdispatch();
else if (pending & CAUSEF_IP5)
amazon_hw3_irqdispatch();
else if (pending & CAUSEF_IP6)
amazon_hw4_irqdispatch();
else
printk("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
}
static struct irqaction cascade = {
.handler = no_action,
.flags = SA_INTERRUPT,
.name = "cascade",
};
/* Function for careful CP0 interrupt mask access */
void __init arch_init_irq(void)
{
int i;
/* mask all interrupt sources */
*AMAZON_ICU_IM0_IER = 0;
*AMAZON_ICU_IM1_IER = 0;
*AMAZON_ICU_IM2_IER = 0;
*AMAZON_ICU_IM3_IER = 0;
*AMAZON_ICU_IM4_IER = 0;
mips_cpu_irq_init();
/* set up irq cascade */
for (i = 2; i <= 6; i++) {
setup_irq(i, &cascade);
}
for (i = INT_NUM_IRQ0; i <= INT_NUM_IM4_IRL31; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
set_irq_chip(i, &amazon_irq_type);
}
}

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/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
/* FIXME: convert nasty volatile register derefs to readl/writel calls */
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/paccess.h>
#include <asm/amazon/irq.h>
#include <asm/amazon/amazon.h>
#define AMAZON_PCI_REG32( addr ) (*(volatile u32 *)(addr))
#ifndef AMAZON_PCI_MEM_BASE
#define AMAZON_PCI_MEM_BASE 0xb2000000
#endif
#define AMAZON_PCI_MEM_SIZE 0x00400000
#define AMAZON_PCI_IO_BASE 0xb2400000
#define AMAZON_PCI_IO_SIZE 0x00002000
#define AMAZON_PCI_CFG_BUSNUM_SHF 16
#define AMAZON_PCI_CFG_DEVNUM_SHF 11
#define AMAZON_PCI_CFG_FUNNUM_SHF 8
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
static inline u32 amazon_r32(u32 addr)
{
u32 *ptr = (u32 *) addr;
return __raw_readl(ptr);
}
static inline void amazon_w32(u32 addr, u32 val)
{
u32 *ptr = (u32 *) addr;
__raw_writel(val, ptr);
}
static struct resource pci_io_resource = {
.name = "io pci IO space",
#if 0
.start = AMAZON_PCI_IO_BASE,
.end = AMAZON_PCI_IO_BASE + AMAZON_PCI_IO_SIZE - 1,
#endif
.start = 0,
.end = AMAZON_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
};
static struct resource pci_mem_resource = {
.name = "ext pci memory space",
.start = AMAZON_PCI_MEM_BASE,
.end = AMAZON_PCI_MEM_BASE + AMAZON_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM
};
static inline u32 amazon_pci_swap(u32 val)
{
#ifdef CONFIG_AMAZON_PCI_HW_SWAP
return swab32(val);
#else
return val;
#endif
}
static int amazon_pci_config_access(unsigned char access_type,
struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
{
unsigned long flags;
u32 pci_addr;
u32 val;
int ret;
/* Amazon support slot from 0 to 15 */
/* devfn 0 & 0x20 is itself */
if ((bus != 0) || (devfn == 0) || (devfn == 0x20))
return 1;
pci_addr=AMAZON_PCI_CFG_BASE |
bus->number << AMAZON_PCI_CFG_BUSNUM_SHF |
devfn << AMAZON_PCI_CFG_FUNNUM_SHF |
(where & ~0x3);
local_irq_save(flags);
if (access_type == PCI_ACCESS_WRITE) {
val = amazon_pci_swap(*data);
ret = put_dbe(val, (u32 *)pci_addr);
} else {
ret = get_dbe(val, (u32 *)pci_addr);
*data = amazon_pci_swap(val);
}
amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)));
amazon_w32(STATUS_COMMAND_ADDR, amazon_r32(STATUS_COMMAND_ADDR));
amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)));
local_irq_restore(flags);
return ret;
}
static int amazon_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
{
u32 data = 0;
int ret = PCIBIOS_SUCCESSFUL;
if (amazon_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) {
data = ~0;
ret = -1;
}
switch (size) {
case 1:
*((u8 *) val) = (data >> ((where & 3) << 3)) & 0xff;
break;
case 2:
*((u16 *) val) = (data >> ((where & 3) << 3)) & 0xffff;
break;
case 4:
*val = data;
break;
default:
return -1;
}
return ret;
}
static int amazon_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
{
if (size != 4) {
u32 data;
if (amazon_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
return -1;
if (size == 1)
val = (data & ~(0xff << ((where & 3) << 3))) | (val << ((where & 3) << 3));
else if (size == 2)
val = (data & ~(0xffff << ((where & 3) << 3))) | (val << ((where & 3) << 3));
else
return -1;
}
if (amazon_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
return -1;
return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops amazon_pci_ops = {
amazon_pci_read,
amazon_pci_write
};
static struct pci_controller amazon_pci_controller = {
.pci_ops = &amazon_pci_ops,
.mem_resource = &pci_mem_resource,
.io_resource = &pci_io_resource
};
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
switch (slot) {
case 13:
/* IDSEL = AD29 --> USB Host Controller */
return INT_NUM_IM2_IRL15;
case 14:
/* IDSEL = AD30 --> mini PCI connector */
return INT_NUM_IM2_IRL14;
default:
printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin);
return 0;
}
}
int pcibios_plat_dev_init(struct pci_dev *dev)
{
switch(dev->irq) {
case INT_NUM_IM2_IRL15:
/*
* IDSEL = AD29 --> USB Host Controller
* PCI_INTA/B/C--GPIO Port0.2--EXIN3
* IN/ALT0:1 ALT1:0
* PULL UP
*/
(*AMAZON_GPIO_P0_DIR) = (*AMAZON_GPIO_P0_DIR) & 0xfffffffb;
(*AMAZON_GPIO_P0_ALTSEL0) = (*AMAZON_GPIO_P0_ALTSEL0)| 4;
(*AMAZON_GPIO_P0_ALTSEL1) = (*AMAZON_GPIO_P0_ALTSEL1)& 0xfffffffb;
(*AMAZON_GPIO_P0_PUDSEL) = (*AMAZON_GPIO_P0_PUDSEL) | 4;
(*AMAZON_GPIO_P0_PUDEN) = (*AMAZON_GPIO_P0_PUDEN) | 4;
//External Interrupt Node
(*AMAZON_ICU_EXTINTCR) = (*AMAZON_ICU_EXTINTCR)|0x6000; /* Low Level triggered */
(*AMAZON_ICU_IRNEN) = (*AMAZON_ICU_IRNEN)|0x8;
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
break;
case INT_NUM_IM2_IRL14:
/*
* IDSEL = AD30 --> mini PCI connector
* PCI_INTA--GPIO Port0.1--EXIN2
* IN/ALT0:1 ALT1:0
* PULL UP
*/
(*AMAZON_GPIO_P0_DIR) = (*AMAZON_GPIO_P0_DIR) & 0xfffffffd;
(*AMAZON_GPIO_P0_ALTSEL0) = (*AMAZON_GPIO_P0_ALTSEL0)| 2;
(*AMAZON_GPIO_P0_ALTSEL1) = (*AMAZON_GPIO_P0_ALTSEL1)& 0xfffffffd;
(*AMAZON_GPIO_P0_PUDSEL) = (*AMAZON_GPIO_P0_PUDSEL) | 2;
(*AMAZON_GPIO_P0_PUDEN) = (*AMAZON_GPIO_P0_PUDEN) | 2;
//External Interrupt Node
(*AMAZON_ICU_EXTINTCR) = (*AMAZON_ICU_EXTINTCR)|0x600;
(*AMAZON_ICU_IRNEN) = (*AMAZON_ICU_IRNEN)|0x4;
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
break;
default:
return 1;
}
return 0;
}
int amazon_pci_init(void)
{
u32 temp_buffer;
#ifdef CONFIG_AMAZON_PCI_HW_SWAP
AMAZON_PCI_REG32(IRM) = AMAZON_PCI_REG32(IRM) | (1<<27) | (1<<28);
wmb();
#endif
AMAZON_PCI_REG32(CLOCK_CONTROL) = AMAZON_PCI_REG32(CLOCK_CONTROL) | (1<<ARB_CTRL_bit);
amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)));
AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) = AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) | (1<<BUS_MASTER_ENABLE_BIT) |(1<<MEM_SPACE_ENABLE_BIT);
temp_buffer = AMAZON_PCI_REG32(PCI_ARB_CTRL_STATUS_ADDR);
temp_buffer = temp_buffer | (1<< INTERNAL_ARB_ENABLE_BIT);
temp_buffer = temp_buffer & ~(3<< PCI_MASTER0_REQ_MASK_2BITS);
temp_buffer = temp_buffer & ~(3<< PCI_MASTER0_GNT_MASK_2BITS);
/* flash */
temp_buffer = temp_buffer & ~(3<< PCI_MASTER1_REQ_MASK_2BITS);
temp_buffer = temp_buffer & ~(3<< PCI_MASTER1_GNT_MASK_2BITS);
/* external master */
temp_buffer = temp_buffer & ~(3<< PCI_MASTER2_REQ_MASK_2BITS);
temp_buffer = temp_buffer & ~(3<< PCI_MASTER2_GNT_MASK_2BITS);
AMAZON_PCI_REG32(PCI_ARB_CTRL_STATUS_ADDR) = temp_buffer;
wmb();
AMAZON_PCI_REG32(FPI_ADDRESS_MAP_0) = 0xb2000000;
AMAZON_PCI_REG32(FPI_ADDRESS_MAP_1) = 0xb2100000;
AMAZON_PCI_REG32(FPI_ADDRESS_MAP_2) = 0xb2200000;
AMAZON_PCI_REG32(FPI_ADDRESS_MAP_3) = 0xb2300000;
AMAZON_PCI_REG32(FPI_ADDRESS_MAP_4) = 0xb2400000;
AMAZON_PCI_REG32(FPI_ADDRESS_MAP_5) = 0xb2500000;
AMAZON_PCI_REG32(FPI_ADDRESS_MAP_6) = 0xb2600000;
AMAZON_PCI_REG32(FPI_ADDRESS_MAP_7) = 0xb2700000;
AMAZON_PCI_REG32(BAR11_MASK) = 0x0f000008;
AMAZON_PCI_REG32(PCI_ADDRESS_MAP_11) = 0x0;
AMAZON_PCI_REG32(BAR1_ADDR) = 0x0;
amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)));
//use 8 dw burse length
AMAZON_PCI_REG32(FPI_BURST_LENGTH) = 0x303;
set_io_port_base(ioremap(AMAZON_PCI_IO_BASE, AMAZON_PCI_IO_SIZE));
register_pci_controller(&amazon_pci_controller);
return 0;
}
arch_initcall(amazon_pci_init);

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/*
* copyright 2007 john crispin <blogic@openwrt.org>
*/
#include <linux/init.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <linux/ioport.h>
#include <asm/bootinfo.h>
#include <asm/amazon/amazon.h>
#include <asm/amazon/irq.h>
#include <asm/amazon/model.h>
#include <asm/cpu.h>
void prom_putchar(char c)
{
/* Wait for FIFO to empty */
while (((*AMAZON_ASC_FSTAT) >> 8) != 0x00) ;
/* Crude cr/nl handling is better than none */
if(c == '\n')
*AMAZON_ASC_TBUF=('\r');
*AMAZON_ASC_TBUF=(c);
}
void prom_printf(const char * fmt, ...)
{
va_list args;
int l;
char *p, *buf_end;
char buf[1024];
va_start(args, fmt);
l = vsprintf(buf, fmt, args); /* hopefully i < sizeof(buf) */
va_end(args);
buf_end = buf + l;
for (p = buf; p < buf_end; p++)
prom_putchar(*p);
}
void __init prom_init(void)
{
mips_machgroup = MACH_GROUP_INFINEON;
mips_machtype = MACH_INFINEON_AMAZON;
strcpy(&(arcs_cmdline[0]), "console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit");
add_memory_region(0x00000000, 0x1000000, BOOT_MEM_RAM);
}
void prom_free_prom_memory(void)
{
}
const char *get_system_type(void)
{
return BOARD_SYSTEM_TYPE;
}

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/*
* Copyright (C) 2004 Peng Liu <peng.liu@infineon.com>
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
*/
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <asm/reboot.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/cpu.h>
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/amazon/amazon.h>
#include <asm/amazon/irq.h>
#include <asm/amazon/model.h>
extern void prom_printf(const char * fmt, ...);
static void amazon_reboot_setup(void);
/* the CPU clock rate - lifted from u-boot */
unsigned int amazon_get_cpu_hz(void)
{
/*-----------------------------------*/
/**CGU CPU Clock Reduction Register***/
/*-----------------------------------*/
switch((*AMAZON_CGU_CPUCRD) & 0x3){
case 0:
/*divider ration 1/1, 235 MHz clock */
return 235000000;
case 1:
/*divider ration 2/3, 235 MHz clock, clock not accurate, here */
return 150000000;
case 2:
/*divider ration 1/2, 235 MHz clock */
return 117500000;
default:
/*divider ration 1/4, 235 MHz clock */
return 58750000;
}
}
/* the FPI clock rate - lifted from u-boot */
unsigned int amazon_get_fpi_hz(void)
{
unsigned int clkCPU;
clkCPU = amazon_get_cpu_hz();
/*-------------------------------------*/
/***CGU Clock Divider Select Register***/
/*-------------------------------------*/
switch ((*AMAZON_CGU_DIV) & 0x3)
{
case 1:
return clkCPU >> 1;
case 2:
return clkCPU >> 2;
default:
return clkCPU;
/* '11' is reserved */
}
}
/* get the CPU version number - based on sysLib.c from VxWorks sources */
/* this doesn't really belong here, but it's a convenient location */
unsigned int amazon_get_cpu_ver(void)
{
static unsigned int cpu_ver = 0;
if (cpu_ver == 0)
cpu_ver = *AMAZON_MCD_CHIPID & 0xFFFFF000;
return cpu_ver;
}
void amazon_time_init(void)
{
mips_hpt_frequency = amazon_get_cpu_hz()/2;
printk("mips_hpt_frequency:%d\n",mips_hpt_frequency);
}
extern int hr_time_resolution;
/* ISR GPTU Timer 6 for high resolution timer */
static void amazon_timer6_interrupt(int irq, void *dev_id)
{
timer_interrupt(AMAZON_TIMER6_INT, NULL);
}
static struct irqaction hrt_irqaction = {
.handler = amazon_timer6_interrupt,
.flags = SA_INTERRUPT,
.name = "hrt",
};
/*
* THe CPU counter for System timer, set to HZ
* GPTU Timer 6 for high resolution timer, set to hr_time_resolution
* Also misuse this routine to print out the CPU type and clock.
*/
void __init plat_timer_setup(struct irqaction *irq)
{
/* cpu counter for timer interrupts */
setup_irq(MIPS_CPU_TIMER_IRQ, irq);
#if 0
/* to generate the first CPU timer interrupt */
write_c0_compare(read_c0_count() + amazon_get_cpu_hz()/(2*HZ));
#endif
/* enable the timer in the PMU */
*(AMAZON_PMU_PWDCR) = (*(AMAZON_PMU_PWDCR))| AMAZON_PMU_PWDCR_GPT|AMAZON_PMU_PWDCR_FPI;
/* setup the GPTU for timer tick f_fpi == f_gptu*/
*(AMAZON_GPTU_CLC) = 0x100;
*(AMAZON_GPTU_CAPREL) = 0xffff;
*(AMAZON_GPTU_T6CON) = 0x80C0;
//setup_irq(AMAZON_TIMER6_INT,&hrt_irqaction);
#if 0
#ifdef CONFIG_HIGH_RES_TIMERS
/* GPTU timer 6 */
int retval;
if ( hr_time_resolution > 200000000 || hr_time_resolution < 40) {
prom_printf("hr_time_resolution is out of range, HIGH_RES_TIMER is diabled.\n");
return;
}
/* enable the timer in the PMU */
*(AMAZON_PMU_PWDCR) = (*(AMAZON_PMU_PWDCR))| AMAZON_PMU_PWDCR_GPT|AMAZON_PMU_PWDCR_FPI;
/* setup the GPTU for timer tick f_fpi == f_gptu*/
*(AMAZON_GPTU_CLC) = 0x100;
*(AMAZON_GPTU_CAPREL) = 0xffff;
*(AMAZON_GPTU_T6CON) = 0x80C0;
retval = setup_irq(AMAZON_TIMER6_INT,&hrt_irqaction);
if (retval){
prom_printf("reqeust_irq failed %d. HIGH_RES_TIMER is diabled\n",AMAZON_TIMER6_INT);
}
#endif //CONFIG_HIGH_RES_TIMERS
#endif
}
void __init plat_mem_setup(void)
{
u32 chipid = 0;
u32 part_no = 0;
chipid = *(AMAZON_MCD_CHIPID);
part_no = AMAZON_MCD_CHIPID_PART_NUMBER_GET(chipid);
if(part_no == AMAZON_CHIPID_YANGTSE){
prom_printf("Yangtse Version\n");
} else if (part_no == AMAZON_CHIPID_STANDARD) {
prom_printf(SYSTEM_MODEL_NAME "\n");
} else {
prom_printf("unknown version %8x\n",part_no);
}
amazon_reboot_setup();
board_time_init = amazon_time_init;
//stop reset TPE and DFE
*(AMAZON_RST_REQ) = 0x0;
//clock
*(AMAZON_PMU_PWDCR) = 0x3fff;
//reenable trace capability
part_no = *(AMAZON_BCU_ECON);
}
static void amazon_machine_restart(char *command)
{
local_irq_disable();
*AMAZON_RST_REQ = AMAZON_RST_ALL;
for (;;) ;
}
static void amazon_machine_halt(void)
{
printk(KERN_NOTICE "System halted.\n");
local_irq_disable();
for (;;) ;
}
static void amazon_machine_power_off(void)
{
printk(KERN_NOTICE "Please turn off the power now.\n");
local_irq_disable();
for (;;) ;
}
static void amazon_reboot_setup(void)
{
_machine_restart = amazon_machine_restart;
_machine_halt = amazon_machine_halt;
pm_power_off = amazon_machine_power_off;
}

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/*
* Infineon AP DC COM Amazon WDT driver
* Copyright 2004 Wu Qi Ming <gokimi@msn.com>
* All rights reserved
*/
#if defined(MODVERSIONS)
#include <linux/modversions.h>
#endif
#include <linux/module.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/fs.h>
#include <linux/errno.h>
#include <linux/proc_fs.h>
#include <linux/stat.h>
#include <linux/tty.h>
#include <linux/selection.h>
#include <linux/kmod.h>
#include <linux/vmalloc.h>
#include <linux/kdev_t.h>
#include <linux/ioctl.h>
#include <asm/uaccess.h>
#include <asm/system.h>
#include <asm/amazon/amazon.h>
#include <asm/amazon/amazon_wdt.h>
#define AMAZON_WDT_EMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args)
extern unsigned int amazon_get_fpi_hz(void);
/* forward declarations for _fops */
static ssize_t wdt_read(struct file *file, char *buf, size_t count, loff_t *offset);
static ssize_t wdt_write(struct file *file, const char *buf, size_t count, loff_t *offset);
static int wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg);
static int wdt_open(struct inode *inode, struct file *file);
static int wdt_release(struct inode *inode, struct file *file);
static int wdt_proc_read(char *buf, char **start, off_t offset,int count, int *eof, void *data);
static struct file_operations wdt_fops = {
read:wdt_read,
write:wdt_write,
ioctl:wdt_ioctl,
open:wdt_open,
release:wdt_release,
};
/* data */
static struct wdt_dev *amazon_wdt_dev;
static struct proc_dir_entry* amazon_wdt_dir;
static int occupied=0;
/* Brief: enable WDT
* Parameter:
timeout: time interval for WDT
* Return:
0 OK
EINVAL
* Describes:
1. Password Access
2. Modify Access (change ENDINIT => 0)
3. Change WDT_CON1 (enable WDT)
4. Password Access again
5. Modify Access (change ENDINIT => 1)
*/
int wdt_enable(int timeout)
{
u32 hard_psw,ffpi;
int reload_value, divider=0;
ffpi = amazon_get_fpi_hz();
divider = 1;
if((reload_value=65536-timeout*ffpi/256)<0){
divider = 0;
reload_value=65536-timeout*ffpi/16384;
}
if (reload_value < 0){
AMAZON_WDT_EMSG("timeout too large %d\n", timeout);
return -EINVAL;
}
AMAZON_WDT_EMSG("timeout:%d reload_value: %8x\n", timeout, reload_value);
hard_psw=(AMAZON_WDT_REG32(AMAZON_WDT_CON0)&0xffffff01)+(AMAZON_WDT_REG32(AMAZON_WDT_CON1)&0xc)+ 0xf0;
AMAZON_WDT_REG32(AMAZON_WDT_CON0)=hard_psw;
wmb();
AMAZON_WDT_REG32(AMAZON_WDT_CON0)=(hard_psw&0xff00)+(reload_value<<16)+0xf2;
wmb();
AMAZON_WDT_REG32(AMAZON_WDT_CON1)=divider<<2;
wmb();
hard_psw=(AMAZON_WDT_REG32(AMAZON_WDT_CON0)&0xffffff01)+(AMAZON_WDT_REG32(AMAZON_WDT_CON1)&0xc)+ 0xf0;
AMAZON_WDT_REG32(AMAZON_WDT_CON0)=hard_psw;
wmb();
AMAZON_WDT_REG32(AMAZON_WDT_CON0)=(AMAZON_WDT_REG32(AMAZON_WDT_CON0)&0xffffff00)+0xf3;
wmb();
return 0;
}
/* Brief: Disable/stop WDT
*/
void wdt_disable(void)
{
u32 hard_psw=0;
hard_psw=(AMAZON_WDT_REG32(AMAZON_WDT_CON0)&0xffffff01)+(AMAZON_WDT_REG32(AMAZON_WDT_CON1)&0xc)+ 0xf0;
AMAZON_WDT_REG32(AMAZON_WDT_CON0)=hard_psw;
wmb();
AMAZON_WDT_REG32(AMAZON_WDT_CON0)=(AMAZON_WDT_REG32(AMAZON_WDT_CON0)&0xffffff00)+0xf2;
wmb();
AMAZON_WDT_REG32(AMAZON_WDT_CON1)|=8;
wmb();
hard_psw=(AMAZON_WDT_REG32(AMAZON_WDT_CON0)&0xffffff01)+(AMAZON_WDT_REG32(AMAZON_WDT_CON1)&0xc)+ 0xf0;
AMAZON_WDT_REG32(AMAZON_WDT_CON0)=hard_psw;
wmb();
AMAZON_WDT_REG32(AMAZON_WDT_CON0)=(AMAZON_WDT_REG32(AMAZON_WDT_CON0)&0xffffff00)+0xf3;
wmb();
return;
}
static int wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
{
int result=0;
static int timeout=-1;
switch(cmd){
case AMAZON_WDT_IOC_START:
AMAZON_WDT_DMSG("enable watch dog timer!\n");
if ( copy_from_user((void*)&timeout, (void*)arg, sizeof (int)) ){
AMAZON_WDT_EMSG("invalid argument\n");
result=-EINVAL;
}else{
if ((result = wdt_enable(timeout)) < 0){
timeout = -1;
}
}
break;
case AMAZON_WDT_IOC_STOP:
AMAZON_WDT_DMSG("disable watch dog timer\n");
timeout = -1;
wdt_disable();
break;
case AMAZON_WDT_IOC_PING:
if (timeout <0 ){
result = -EIO;
}else{
result = wdt_enable(timeout);
}
}
return result;
}
static ssize_t wdt_read(struct file *file, char *buf, size_t count, loff_t *offset)
{
return 0;
}
static ssize_t wdt_write(struct file *file, const char *buf, size_t count, loff_t *offset)
{
return count;
}
static int wdt_open(struct inode *inode, struct file *file)
{
AMAZON_WDT_DMSG("wdt_open\n");
if (occupied == 1) return -EBUSY;
occupied = 1;
return 0;
}
static int wdt_release(struct inode *inode, struct file *file)
{
AMAZON_WDT_DMSG("wdt_release\n");
occupied = 0;
return 0;
}
int wdt_register_proc_read(char *buf, char **start, off_t offset,
int count, int *eof, void *data)
{
int len=0;
printk("wdt_registers:\n");
len+=sprintf(buf+len,"NMISR: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_WDT_NMISR));
len+=sprintf(buf+len,"RST_REQ: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_RST_REQ));
len+=sprintf(buf+len,"RST_SR: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_RST_SR));
len+=sprintf(buf+len,"WDT_CON0: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_WDT_CON0));
len+=sprintf(buf+len,"WDT_CON1: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_WDT_CON1));
len+=sprintf(buf+len,"WDT_SR: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_WDT_SR));
*eof = 1;
return len;
}
int __init amazon_wdt_init_module(void)
{
int result=0;
amazon_wdt_dev = (wdt_dev*)kmalloc(sizeof(wdt_dev),GFP_KERNEL);
if (amazon_wdt_dev == NULL){
return -ENOMEM;
}
memset(amazon_wdt_dev,0,sizeof(wdt_dev));
amazon_wdt_dev->major=result;
strcpy(amazon_wdt_dev->name,"wdt");
result = register_chrdev(0,amazon_wdt_dev->name,&wdt_fops);
if (result < 0) {
AMAZON_WDT_EMSG("cannot register device\n");
kfree(amazon_wdt_dev);
return result;
}
amazon_wdt_dir=proc_mkdir("amazon_wdt",NULL);
create_proc_read_entry("wdt_register",
0,
amazon_wdt_dir,
wdt_register_proc_read,
NULL);
occupied=0;
return 0;
}
void amazon_wdt_cleanup_module(void)
{
unregister_chrdev(amazon_wdt_dev->major,amazon_wdt_dev->name);
kfree(amazon_wdt_dev);
remove_proc_entry("wdt_register",amazon_wdt_dir);
remove_proc_entry("amazon_wdt",NULL);
AMAZON_WDT_DMSG("unloaded\n");
return;
}
MODULE_LICENSE ("GPL");
MODULE_AUTHOR("Infineon IFAP DC COM");
MODULE_DESCRIPTION("AMAZON WDT driver");
module_init(amazon_wdt_init_module);
module_exit(amazon_wdt_cleanup_module);

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target/linux/amazon-2.6/files/drivers/char/ifx_ssc.c Normal file
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target/linux/amazon-2.6/files/drivers/mtd/maps/amazon.c Normal file
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/*
* Handle mapping of the flash memory access routines
* on Amazon based devices.
*
* Copyright(C) 2004 peng.liu@infineon.com
*
* This code is GPLed
*
*/
// 000005:fchang 2005/6/2 Modified by Bingtao to double check if the EBU is enabled/disabled
// 506231:tc.chen 2005/06/23 increase firmware partition size form 192KB to 256KB
// 050701:linmars 2005/07/01 fix flash size wrong alignment after increase firmware partition
// 165001:henryhsu 2005/8/18 Remove the support for Intel flash because of 2.1 not enough rootfs partition size
// 165001:henryhsu 2005/9/7 Rolback to support INtel flash
// 509071:tc.chen 2005/09/07 Reduced flash writing time
// 511046:linmars 2005/11/04 change bootloader size from 128 into 64
// 511241:linmars 2005/11/24 merge TaiChen's IRM patch
// copyright 2005 infineon
// copyright 2007 john crispin <blogic@openwrt.org>
// copyright 2007 felix fietkau <nbd@openwrt.org>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <asm/io.h>
#include <linux/init.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/cfi.h>
#include <linux/mutex.h>
#include <asm/amazon/amazon.h>
#define AMAZON_PCI_ARB_CTL_ALT 0xb100205c
#define AMAZON_MTD_REG32( addr ) (*(volatile u32 *)(addr))
static struct map_info amazon_map = {
.name = "AMAZON_FLASH",
.bankwidth = 2,
.size = 0x400000,
};
static map_word amazon_read16(struct map_info * map, unsigned long ofs)
{
map_word temp;
ofs ^= 2;
temp.x[0] = *((__u16 *) (map->virt + ofs));
return temp;
}
static void amazon_write16(struct map_info *map, map_word d, unsigned long adr)
{
adr ^= 2;
*((__u16 *) (map->virt + adr)) = d.x[0];
}
void amazon_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
{
u8 *p;
u8 *to_8;
ssize_t l = len;
from = (unsigned long) (from + map->virt);
p = (u8 *) from;
to_8 = (u8 *) to;
while(len--){
*to_8++ = *p++;
}
}
void amazon_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
{
u8 *p = (u8*) from;
u8 *to_8;
to += (unsigned long) map->virt;
to_8 = (u8*)to;
while(len--){
*p++ = *to_8++;
}
}
#define UBOOT_SIZE 0x40000
static struct mtd_partition amazon_partitions[3] = {
{
name:"U-Boot", /* U-Boot firmware */
offset:0x00000000,
size:UBOOT_SIZE , /* 128k */
},
{
name:"kernel", /* firmware */
offset:UBOOT_SIZE,
size:0x00100000, /* 192K */
},
{
name:"rootfs", /* default partition */
offset:0x00200000,
size:0x00200000,
},
};
unsigned long flash_start = 0x13000000;
unsigned long flash_size = 0x800000;
unsigned long uImage_size = 0x10000d;
int find_uImage_size(unsigned long start_offset){
unsigned long temp;
printk("trying to find uImage and its size\n");
amazon_copy_from(&amazon_map, &temp, start_offset + 12, 4);
printk("kernel size is %d \n", temp + 0x40);
return temp + 0x40;
}
int __init init_amazon_mtd(void)
{
int ret = 0;
struct mtd_info *mymtd = NULL;
struct mtd_partition *parts = NULL;
*AMAZON_EBU_BUSCON0 = 0x1d7ff;
amazon_map.read = amazon_read16;
amazon_map.write = amazon_write16;
amazon_map.copy_from = amazon_copy_from;
amazon_map.copy_to = amazon_copy_to;
amazon_map.phys = flash_start;
amazon_map.virt = ioremap_nocache(flash_start, flash_size);
if (!amazon_map.virt) {
printk(KERN_WARNING "Failed to ioremap!\n");
return -EIO;
}
mymtd = (struct mtd_info *) do_map_probe("cfi_probe", &amazon_map);
if (!mymtd) {
iounmap(amazon_map.virt);
printk("probing failed\n");
return -ENXIO;
}
mymtd->owner = THIS_MODULE;
parts = &amazon_partitions[0];
amazon_partitions[2].offset = UBOOT_SIZE + find_uImage_size(amazon_partitions[1].offset);
amazon_partitions[1].size = mymtd->size - amazon_partitions[1].offset - (2 * mymtd->erasesize);
amazon_partitions[2].size = mymtd->size - amazon_partitions[2].offset - (2 * mymtd->erasesize);
add_mtd_partitions(mymtd, parts, 3);
return 0;
}
static void __exit cleanup_amazon_mtd(void)
{
/* FIXME! */
}
module_init(init_amazon_mtd);
module_exit(cleanup_amazon_mtd);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("john crispin blogic@openwrt.org");
MODULE_DESCRIPTION("MTD map driver for AMAZON boards");

876
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/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*/
//-----------------------------------------------------------------------
/*
* Description:
* Driver for Infineon Amazon 3 port switch
*/
//-----------------------------------------------------------------------
/* Author: Wu Qi Ming[Qi-Ming.Wu@infineon.com]
* Created: 7-April-2004
*/
//-----------------------------------------------------------------------
/* History
* Changed on: Jun 28, 2004
* Changed by: peng.liu@infineon.com
* Reason: add hardware flow control (HFC) (CONFIG_NET_HW_FLOWCONTROL)
*
* Changed on: Apr 6, 2005
* Changed by: mars.lin@infineon.com
* Reason : supoort port identification
*/
// copyright 2004-2005 infineon.com
// copyright 2007 john crispin <blogic@openwrt.org>
// copyright 2007 felix fietkau <nbd@openwrt.org>
// TODO
// port vlan code from bcrm target... the tawainese code was scrapped due to crappyness
// check all the mmi reg settings and possibly document them better
// verify the ethtool code
// remove the while(1) stuff
// further clean up and rework ... but it works for now
// check the mode[]=bridge stuff
// verify that the ethaddr can be set from u-boot
#ifndef __KERNEL__
#define __KERNEL__
#endif
#if defined(CONFIG_MODVERSIONS) && !defined(MODVERSIONS)
#define MODVERSIONS
#endif
#if defined(MODVERSIONS) && !defined(__GENKSYMS__)
#include <linux/modversions.h>
#endif
#include <linux/module.h>
#include <linux/string.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/mii.h>
#include <asm/uaccess.h>
#include <linux/in.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/skbuff.h>
#include <linux/in6.h>
#include <linux/proc_fs.h>
#include <linux/mm.h>
#include <linux/ethtool.h>
#include <asm/checksum.h>
#include <linux/init.h>
#include <asm/amazon/amazon.h>
#include <asm/amazon/amazon_dma.h>
#include <asm/amazon/amazon_sw.h>
// how many mii ports are there ?
#define AMAZON_SW_INT_NO 2
#define ETHERNET_PACKET_DMA_BUFFER_SIZE 1536
/***************************************** Module Parameters *************************************/
char mode[] = "bridge";
module_param_array(mode, charp, NULL, 0);
static int timeout = 1 * HZ;
module_param(timeout, int, 0);
int switch_init(struct net_device *dev);
void switch_tx_timeout(struct net_device *dev);
struct net_device switch_devs[2] = {
{init:switch_init,},
{init:switch_init,}
};
int add_mac_table_entry(u64 entry_value)
{
int i;
u32 data1, data2;
AMAZON_SW_REG32(AMAZON_SW_ARL_CTL) = ~7;
for (i = 0; i < 32; i++) {
AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) = 0x80000000 | 0x20 | i;
while (AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) & (0x80000000)) {};
data1 = AMAZON_SW_REG32(AMAZON_SW_DATA1);
data2 = AMAZON_SW_REG32(AMAZON_SW_DATA2);
if ((data1 & (0x00700000)) != 0x00700000)
continue;
AMAZON_SW_REG32(AMAZON_SW_DATA1) = (u32) (entry_value >> 32);
AMAZON_SW_REG32(AMAZON_SW_DATA2) = (u32) entry_value & 0xffffffff;
AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) = 0xc0000020 | i;
while (AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) & (0x80000000)) {};
break;
}
AMAZON_SW_REG32(AMAZON_SW_ARL_CTL) |= 7;
if (i >= 32)
return -1;
return OK;
}
u64 read_mac_table_entry(int index)
{
u32 data1, data2;
u64 value;
AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) = 0x80000000 | 0x20 | index;
while (AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) & (0x80000000)) {};
data1 = AMAZON_SW_REG32(AMAZON_SW_DATA1) & 0xffffff;
data2 = AMAZON_SW_REG32(AMAZON_SW_DATA2);
value = (u64) data1 << 32 | (u64) data2;
return value;
}
int write_mac_table_entry(int index, u64 value)
{
u32 data1, data2;
data1 = (u32) (value >> 32);
data2 = (u32) value & 0xffffffff;
AMAZON_SW_REG32(AMAZON_SW_DATA1) = data1;
AMAZON_SW_REG32(AMAZON_SW_DATA2) = data2;
AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) = 0xc0000020 | index;
while (AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) & (0x80000000)) {};
return OK;
}
u32 get_mdio_reg(int phy_addr, int reg_num)
{
u32 value;
AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) = (3 << 30) | ((phy_addr & 0x1f) << 21) | ((reg_num & 0x1f) << 16);
while (AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) & (1 << 31)) {};
value = AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) & 0xffff;
return value;
}
int set_mdio_reg(int phy_addr, int reg_num, u32 value)
{
AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) = (2 << 30) | ((phy_addr & 0x1f) << 21) | ((reg_num & 0x1f) << 16) | (value & 0xffff);
while (AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) & (1 << 31)) {};
return OK;
}
int auto_negotiate(int phy_addr)
{
u32 value = 0;
value = get_mdio_reg(phy_addr, MDIO_BASE_CONTROL_REG);
set_mdio_reg(phy_addr, MDIO_BASE_CONTROL_REG, (value | RESTART_AUTO_NEGOTIATION | AUTO_NEGOTIATION_ENABLE | PHY_RESET));
return OK;
}
/*
In this version of switch driver, we split the dma channels for the switch.
2 for port0 and 2 for port1. So that we can do internal bridging if necessary.
In switch mode, packets coming in from port0 or port1 is able to do Destination
address lookup. Packets coming from port0 with destination address of port1 should
not go to pmac again. The switch hardware should be able to do the switch in the hard
ware level. Packets coming from the pmac should not do the DA look up in that the
desination is already known for the kernel. It only needs to go to the correct NIC to
find its way out.
*/
int amazon_sw_chip_init(void)
{
u32 tmp1;
int i = 0;
/* Aging tick select: 5mins */
tmp1 = 0xa0;
if (strcmp(mode, "bridge") == 0) {
// bridge mode, set militarised mode to 1, no learning!
tmp1 |= 0xC00;
} else {
// enable learning for P0 and P1,
tmp1 |= 3;
}
/* unknown broadcast/multicast/unicast to all ports */
AMAZON_SW_REG32(AMAZON_SW_UN_DEST) = 0x1ff;
AMAZON_SW_REG32(AMAZON_SW_ARL_CTL) = tmp1;
/* OCS:1 set OCS bit, split the two NIC in rx direction EDL:1 (enable DA lookup) */
#if defined(CONFIG_IFX_NFEXT_AMAZON_SWITCH_PHYPORT) || defined(CONFIG_IFX_NFEXT_AMAZON_SWITCH_PHYPORT_MODULE)
AMAZON_SW_REG32(AMAZON_SW_P2_PCTL) = 0x700;
#else
AMAZON_SW_REG32(AMAZON_SW_P2_PCTL) = 0x401;
#endif
/* EPC: 1 split the two NIC in tx direction CRC is generated */
AMAZON_SW_REG32(AMAZON_SW_P2_CTL) = 0x6;
// for bi-directional
AMAZON_SW_REG32(AMAZON_SW_P0_WM) = 0x14141412;
AMAZON_SW_REG32(AMAZON_SW_P1_WM) = 0x14141412;
AMAZON_SW_REG32(AMAZON_SW_P2_WM) = 0x28282826;
AMAZON_SW_REG32(AMAZON_SW_GBL_WM) = 0x0;
AMAZON_SW_REG32(AMAZON_CGU_PLL0SR) = (AMAZON_SW_REG32(AMAZON_CGU_PLL0SR)) | 0x58000000;
// clock for PHY
AMAZON_SW_REG32(AMAZON_CGU_IFCCR) = (AMAZON_SW_REG32(AMAZON_CGU_IFCCR)) | 0x80000004;
// enable power for PHY
AMAZON_SW_REG32(AMAZON_PMU_PWDCR) = (AMAZON_SW_REG32(AMAZON_PMU_PWDCR)) | AMAZON_PMU_PWDCR_EPHY;
// set reverse MII, enable MDIO statemachine
AMAZON_SW_REG32(AMAZON_SW_MDIO_CFG) = 0x800027bf;
while (1)
if (((AMAZON_SW_REG32(AMAZON_SW_MDIO_CFG)) & 0x80000000) == 0)
break;
AMAZON_SW_REG32(AMAZON_SW_EPHY) = 0xff;
// auto negotiation
AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) = 0x83e08000;
auto_negotiate(0x1f);
/* enable all ports */
AMAZON_SW_REG32(AMAZON_SW_PS_CTL) = 0x7;
for (i = 0; i < 32; i++)
write_mac_table_entry(i, 1 << 50);
return 0;
}
static unsigned char my_ethaddr[MAX_ADDR_LEN];
/* need to get the ether addr from u-boot */
static int __init ethaddr_setup(char *line)
{
char *ep;
int i;
memset(my_ethaddr, 0, MAX_ADDR_LEN);
for (i = 0; i < 6; i++) {
my_ethaddr[i] = line ? simple_strtoul(line, &ep, 16) : 0;
if (line)
line = (*ep) ? ep + 1 : ep;
}
printk("mac address %2x-%2x-%2x-%2x-%2x-%2x \n", my_ethaddr[0], my_ethaddr[1], my_ethaddr[2], my_ethaddr[3], my_ethaddr[4], my_ethaddr[5]);
return 0;
}
__setup("ethaddr=", ethaddr_setup);
static void open_rx_dma(struct net_device *dev)
{
struct switch_priv *priv = (struct switch_priv *) dev->priv;
struct dma_device_info *dma_dev = priv->dma_device;
int i;
for (i = 0; i < dma_dev->num_rx_chan; i++)
dma_dev->rx_chan[i].control = 1;
dma_device_update_rx(dma_dev);
}
#ifdef CONFIG_NET_HW_FLOWCONTROL
static void close_rx_dma(struct net_device *dev)
{
struct switch_priv *priv = (struct switch_priv *) dev->priv;
struct dma_device_info *dma_dev = priv->dma_device;
int i;
for (i = 0; i < dma_dev->num_rx_chan; i++)
dma_dev->rx_chan[i].control = 0;
dma_device_update_rx(dma_dev);
}
void amazon_xon(struct net_device *dev)
{
unsigned long flag;
local_irq_save(flag);
open_rx_dma(dev);
local_irq_restore(flag);
}
#endif
int switch_open(struct net_device *dev)
{
struct switch_priv *priv = (struct switch_priv *) dev->priv;
if (!strcmp(dev->name, "eth1")) {
priv->mdio_phy_addr = PHY0_ADDR;
}
open_rx_dma(dev);
#ifdef CONFIG_NET_HW_FLOWCONTROL
if ((priv->fc_bit = netdev_register_fc(dev, amazon_xon)) == 0) {
printk("Hardware Flow Control register fails\n");
}
#endif
netif_start_queue(dev);
return OK;
}
int switch_release(struct net_device *dev)
{
int i;
struct switch_priv *priv = (struct switch_priv *) dev->priv;
struct dma_device_info *dma_dev = priv->dma_device;
for (i = 0; i < dma_dev->num_tx_chan; i++)
dma_dev->tx_chan[i].control = 0;
for (i = 0; i < dma_dev->num_rx_chan; i++)
dma_dev->rx_chan[i].control = 0;
dma_device_update(dma_dev);
#ifdef CONFIG_NET_HW_FLOWCONTROL
if (priv->fc_bit) {
netdev_unregister_fc(priv->fc_bit);
}
#endif
netif_stop_queue(dev);
return OK;
}
void switch_rx(struct net_device *dev, int len, struct sk_buff *skb)
{
struct switch_priv *priv = (struct switch_priv *) dev->priv;
#ifdef CONFIG_NET_HW_FLOWCONTROL
int mit_sel = 0;
#endif
skb->dev = dev;
skb->protocol = eth_type_trans(skb, dev);
#ifdef CONFIG_NET_HW_FLOWCONTROL
mit_sel = netif_rx(skb);
switch (mit_sel) {
case NET_RX_SUCCESS:
case NET_RX_CN_LOW:
case NET_RX_CN_MOD:
break;
case NET_RX_CN_HIGH:
break;
case NET_RX_DROP:
if ((priv->fc_bit)
&& (!test_and_set_bit(priv->fc_bit, &netdev_fc_xoff))) {
close_rx_dma(dev);
}
break;
}
#else
netif_rx(skb);
#endif
priv->stats.rx_packets++;
priv->stats.rx_bytes += len;
return;
}
int asmlinkage switch_hw_tx(char *buf, int len, struct net_device *dev)
{
struct switch_priv *priv = dev->priv;
struct dma_device_info *dma_dev = priv->dma_device;
dma_dev->current_tx_chan = 0;
return dma_device_write(dma_dev, buf, len, priv->skb);
}
int asmlinkage switch_tx(struct sk_buff *skb, struct net_device *dev)
{
int len;
char *data;
struct switch_priv *priv = (struct switch_priv *) dev->priv;
len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
data = skb->data;
priv->skb = skb;
dev->trans_start = jiffies;
if (switch_hw_tx(data, len, dev) != len) {
dev_kfree_skb_any(skb);
return OK;
}
priv->stats.tx_packets++;
priv->stats.tx_bytes += len;
return OK;
}
void switch_tx_timeout(struct net_device *dev)
{
struct switch_priv *priv = (struct switch_priv *) dev->priv;
priv->stats.tx_errors++;
netif_wake_queue(dev);
return;
}
void negotiate(struct net_device *dev)
{
struct switch_priv *priv = (struct switch_priv *) dev->priv;
unsigned short data = get_mdio_reg(priv->mdio_phy_addr, MDIO_ADVERTISMENT_REG);
data &= ~(MDIO_ADVERT_100_HD | MDIO_ADVERT_100_FD | MDIO_ADVERT_10_FD | MDIO_ADVERT_10_HD);
switch (priv->current_speed_selection) {
case 10:
if (priv->current_duplex == full)
data |= MDIO_ADVERT_10_FD;
else if (priv->current_duplex == half)
data |= MDIO_ADVERT_10_HD;
else
data |= MDIO_ADVERT_10_HD | MDIO_ADVERT_10_FD;
break;
case 100:
if (priv->current_duplex == full)
data |= MDIO_ADVERT_100_FD;
else if (priv->current_duplex == half)
data |= MDIO_ADVERT_100_HD;
else
data |= MDIO_ADVERT_100_HD | MDIO_ADVERT_100_FD;
break;
case 0: /* Auto */
if (priv->current_duplex == full)
data |= MDIO_ADVERT_100_FD | MDIO_ADVERT_10_FD;
else if (priv->current_duplex == half)
data |= MDIO_ADVERT_100_HD | MDIO_ADVERT_10_HD;
else
data |= MDIO_ADVERT_100_HD | MDIO_ADVERT_100_FD | MDIO_ADVERT_10_FD | MDIO_ADVERT_10_HD;
break;
default: /* assume autoneg speed and duplex */
data |= MDIO_ADVERT_100_HD | MDIO_ADVERT_100_FD | MDIO_ADVERT_10_FD | MDIO_ADVERT_10_HD;
}
set_mdio_reg(priv->mdio_phy_addr, MDIO_ADVERTISMENT_REG, data);
/* Renegotiate with link partner */
data = get_mdio_reg(priv->mdio_phy_addr, MDIO_BASE_CONTROL_REG);
data |= MDIO_BC_NEGOTIATE;
set_mdio_reg(priv->mdio_phy_addr, MDIO_BASE_CONTROL_REG, data);
}
void set_duplex(struct net_device *dev, enum duplex new_duplex)
{
struct switch_priv *priv = (struct switch_priv *) dev->priv;
if (new_duplex != priv->current_duplex) {
priv->current_duplex = new_duplex;
negotiate(dev);
}
}
void set_speed(struct net_device *dev, unsigned long speed)
{
struct switch_priv *priv = (struct switch_priv *) dev->priv;
priv->current_speed_selection = speed;
negotiate(dev);
}
static int switch_ethtool_ioctl(struct net_device *dev, struct ifreq *ifr)
{
struct switch_priv *priv = (struct switch_priv *) dev->priv;
struct ethtool_cmd ecmd;
if (copy_from_user(&ecmd, ifr->ifr_data, sizeof(ecmd)))
return -EFAULT;
switch (ecmd.cmd) {
case ETHTOOL_GSET:
memset((void *) &ecmd, 0, sizeof(ecmd));
ecmd.supported = SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
ecmd.port = PORT_TP;
ecmd.transceiver = XCVR_EXTERNAL;
ecmd.phy_address = priv->mdio_phy_addr;
ecmd.speed = priv->current_speed;
ecmd.duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
ecmd.advertising = ADVERTISED_TP;
if (priv->current_duplex == autoneg && priv->current_speed_selection == 0)
ecmd.advertising |= ADVERTISED_Autoneg;
else {
ecmd.advertising |= ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
if (priv->current_speed_selection == 10)
ecmd.advertising &= ~(ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full);
else if (priv->current_speed_selection == 100)
ecmd.advertising &= ~(ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full);
if (priv->current_duplex == half)
ecmd.advertising &= ~(ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Full);
else if (priv->current_duplex == full)
ecmd.advertising &= ~(ADVERTISED_10baseT_Half | ADVERTISED_100baseT_Half);
}
ecmd.autoneg = AUTONEG_ENABLE;
if (copy_to_user(ifr->ifr_data, &ecmd, sizeof(ecmd)))
return -EFAULT;
break;
case ETHTOOL_SSET:
if (!capable(CAP_NET_ADMIN)) {
return -EPERM;
}
if (ecmd.autoneg == AUTONEG_ENABLE) {
set_duplex(dev, autoneg);
set_speed(dev, 0);
} else {
set_duplex(dev, ecmd.duplex == DUPLEX_HALF ? half : full);
set_speed(dev, ecmd.speed == SPEED_10 ? 10 : 100);
}
break;
case ETHTOOL_GDRVINFO:
{
struct ethtool_drvinfo info;
memset((void *) &info, 0, sizeof(info));
strncpy(info.driver, "AMAZONE", sizeof(info.driver) - 1);
strncpy(info.fw_version, "N/A", sizeof(info.fw_version) - 1);
strncpy(info.bus_info, "N/A", sizeof(info.bus_info) - 1);
info.regdump_len = 0;
info.eedump_len = 0;
info.testinfo_len = 0;
if (copy_to_user(ifr->ifr_data, &info, sizeof(info)))
return -EFAULT;
}
break;
case ETHTOOL_NWAY_RST:
if (priv->current_duplex == autoneg && priv->current_speed_selection == 0)
negotiate(dev);
break;
default:
return -EOPNOTSUPP;
break;
}
return 0;
}
int mac_table_tools_ioctl(struct net_device *dev, struct mac_table_req *req)
{
int cmd;
int i;
cmd = req->cmd;
switch (cmd) {
case RESET_MAC_TABLE:
for (i = 0; i < 32; i++) {
write_mac_table_entry(i, 0);
}
break;
case READ_MAC_ENTRY:
req->entry_value = read_mac_table_entry(req->index);
break;
case WRITE_MAC_ENTRY:
write_mac_table_entry(req->index, req->entry_value);
break;
case ADD_MAC_ENTRY:
add_mac_table_entry(req->entry_value);
break;
default:
return -EINVAL;
}
return 0;
}
/*
the ioctl for the switch driver is developed in the conventional way
the control type falls into some basic categories, among them, the
SIOCETHTOOL is the traditional eth interface. VLAN_TOOLS and
MAC_TABLE_TOOLS are designed specifically for amazon chip. User
should be aware of the data structures used in these interfaces.
*/
int switch_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
struct data_req *switch_data_req = (struct data_req *) ifr->ifr_data;
struct mac_table_req *switch_mac_table_req;
switch (cmd) {
case SIOCETHTOOL:
switch_ethtool_ioctl(dev, ifr);
break;
case SIOCGMIIPHY: /* Get PHY address */
break;
case SIOCGMIIREG: /* Read MII register */
break;
case SIOCSMIIREG: /* Write MII register */
break;
case SET_ETH_SPEED_10: /* 10 Mbps */
break;
case SET_ETH_SPEED_100: /* 100 Mbps */
break;
case SET_ETH_SPEED_AUTO: /* Auto negotiate speed */
break;
case SET_ETH_DUPLEX_HALF: /* Half duplex. */
break;
case SET_ETH_DUPLEX_FULL: /* Full duplex. */
break;
case SET_ETH_DUPLEX_AUTO: /* Autonegotiate duplex */
break;
case SET_ETH_REG:
AMAZON_SW_REG32(switch_data_req->index) = switch_data_req->value;
break;
case MAC_TABLE_TOOLS:
switch_mac_table_req = (struct mac_table_req *) ifr->ifr_data;
mac_table_tools_ioctl(dev, switch_mac_table_req);
break;
default:
return -EINVAL;
}
return 0;
}
struct net_device_stats *switch_stats(struct net_device *dev)
{
struct switch_priv *priv = (struct switch_priv *) dev->priv;
return &priv->stats;
}
int switch_change_mtu(struct net_device *dev, int new_mtu)
{
if (new_mtu >= 1516)
new_mtu = 1516;
dev->mtu = new_mtu;
return 0;
}
int switch_hw_receive(struct net_device *dev, struct dma_device_info *dma_dev)
{
u8 *buf = NULL;
int len = 0;
struct sk_buff *skb = NULL;
len = dma_device_read(dma_dev, &buf, (void **) &skb);
if (len >= 0x600) {
printk("packet too large %d\n", len);
goto switch_hw_receive_err_exit;
}
/* remove CRC */
len -= 4;
if (skb == NULL) {
printk("cannot restore pointer\n");
goto switch_hw_receive_err_exit;
}
if (len > (skb->end - skb->tail)) {
printk("BUG, len:%d end:%p tail:%p\n", (len + 4), skb->end, skb->tail);
goto switch_hw_receive_err_exit;
}
skb_put(skb, len);
skb->dev = dev;
switch_rx(dev, len, skb);
return OK;
switch_hw_receive_err_exit:
if (skb)
dev_kfree_skb_any(skb);
return -EIO;
}
int dma_intr_handler(struct dma_device_info *dma_dev, int status)
{
struct net_device *dev;
dev = switch_devs + (u32) dma_dev->priv;
switch (status) {
case RCV_INT:
switch_hw_receive(dev, dma_dev);
break;
case TX_BUF_FULL_INT:
netif_stop_queue(dev);
break;
case TRANSMIT_CPT_INT:
netif_wake_queue(dev);
break;
}
return OK;
}
/* reserve 2 bytes in front of data pointer*/
u8 *dma_buffer_alloc(int len, int *byte_offset, void **opt)
{
u8 *buffer = NULL;
struct sk_buff *skb = NULL;
skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE);
if (skb == NULL) {
return NULL;
}
buffer = (u8 *) (skb->data);
skb_reserve(skb, 2);
*(int *) opt = (int) skb;
*byte_offset = 2;
return buffer;
}
int dma_buffer_free(u8 * dataptr, void *opt)
{
struct sk_buff *skb = NULL;
if (opt == NULL) {
kfree(dataptr);
} else {
skb = (struct sk_buff *) opt;
dev_kfree_skb_any(skb);
}
return OK;
}
int init_dma_device(_dma_device_info * dma_dev)
{
int i;
int num_tx_chan, num_rx_chan;
if (strcmp(dma_dev->device_name, "switch1") == 0) {
num_tx_chan = 1;
num_rx_chan = 2;
dma_dev->priv = (void *) 0;
} else {
num_tx_chan = 1;
num_rx_chan = 2;
dma_dev->priv = (void *) 1;
}
dma_dev->weight = 1;
dma_dev->num_tx_chan = num_tx_chan;
dma_dev->num_rx_chan = num_rx_chan;
dma_dev->ack = 1;
dma_dev->tx_burst_len = 4;
dma_dev->rx_burst_len = 4;
for (i = 0; i < dma_dev->num_tx_chan; i++) {
dma_dev->tx_chan[i].weight = QOS_DEFAULT_WGT;
dma_dev->tx_chan[i].desc_num = 10;
dma_dev->tx_chan[i].packet_size = 0;
dma_dev->tx_chan[i].control = 0;
}
for (i = 0; i < num_rx_chan; i++) {
dma_dev->rx_chan[i].weight = QOS_DEFAULT_WGT;
dma_dev->rx_chan[i].desc_num = 10;
dma_dev->rx_chan[i].packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE;
dma_dev->rx_chan[i].control = 0;
}
dma_dev->intr_handler = dma_intr_handler;
dma_dev->buffer_alloc = dma_buffer_alloc;
dma_dev->buffer_free = dma_buffer_free;
return 0;
}
int switch_set_mac_address(struct net_device *dev, void *p)
{
struct sockaddr *addr = p;
memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
return OK;
}
int switch_init(struct net_device *dev)
{
u64 retval = 0;
int i;
int result;
struct switch_priv *priv;
ether_setup(dev); /* assign some of the fields */
printk("%s up using ", dev->name);
dev->open = switch_open;
dev->stop = switch_release;
dev->hard_start_xmit = switch_tx;
dev->do_ioctl = switch_ioctl;
dev->get_stats = switch_stats;
dev->change_mtu = switch_change_mtu;
dev->set_mac_address = switch_set_mac_address;
dev->tx_timeout = switch_tx_timeout;
dev->watchdog_timeo = timeout;
SET_MODULE_OWNER(dev);
dev->priv = kmalloc(sizeof(struct switch_priv), GFP_KERNEL);
if (dev->priv == NULL)
return -ENOMEM;
memset(dev->priv, 0, sizeof(struct switch_priv));
priv = dev->priv;
priv->dma_device = (struct dma_device_info *) kmalloc(sizeof(struct dma_device_info), GFP_KERNEL);
if ((dev - switch_devs) == 0) {
sprintf(priv->dma_device->device_name, "switch1");
} else if ((dev - switch_devs) == 1) {
sprintf(priv->dma_device->device_name, "switch2");
}
printk("\"%s\"\n", priv->dma_device->device_name);
init_dma_device(priv->dma_device);
result = dma_device_register(priv->dma_device);
/* read the mac address from the mac table and put them into the mac table. */
for (i = 0; i < 6; i++) {
retval += my_ethaddr[i];
}
/* ethaddr not set in u-boot ? */
if (retval == 0) {
dev->dev_addr[0] = 0x00;
dev->dev_addr[1] = 0x20;
dev->dev_addr[2] = 0xda;
dev->dev_addr[3] = 0x86;
dev->dev_addr[4] = 0x23;
dev->dev_addr[5] = 0x74 + (unsigned char) (dev - switch_devs);
} else {
for (i = 0; i < 6; i++) {
dev->dev_addr[i] = my_ethaddr[i];
}
dev->dev_addr[5] += +(unsigned char) (dev - switch_devs);
}
return OK;
}
int switch_init_module(void)
{
int i = 0, result, device_present = 0;
for (i = 0; i < AMAZON_SW_INT_NO; i++) {
sprintf(switch_devs[i].name, "eth%d", i);
if ((result = register_netdev(switch_devs + i)))
printk("error %i registering device \"%s\"\n", result, switch_devs[i].name);
else
device_present++;
}
amazon_sw_chip_init();
return device_present ? 0 : -ENODEV;
}
void switch_cleanup(void)
{
int i;
struct switch_priv *priv;
for (i = 0; i < AMAZON_SW_INT_NO; i++) {
priv = switch_devs[i].priv;
if (priv->dma_device) {
dma_device_unregister(priv->dma_device);
kfree(priv->dma_device);
}
kfree(switch_devs[i].priv);
unregister_netdev(switch_devs + i);
}
return;
}
module_init(switch_init_module);
module_exit(switch_cleanup);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Wu Qi Ming");

755
target/linux/amazon-2.6/files/drivers/serial/amazon_asc.c Normal file
View File

@ -0,0 +1,755 @@
/*
* linux/drivers/char/amazon_asc.c
*
* Driver for AMAZONASC serial ports
*
* Copyright (C) 2004 Infineon IFAP DC COM CPE
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
* Based on drivers/serial/serial_s3c2400.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* $Id: amazon_asc.c,v 1.2 2005/04/01 02:40:48 pliu Exp $
*
* This is a generic driver for AMAZONASC-type serial ports.
*/
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/major.h>
#include <linux/string.h>
#include <linux/fcntl.h>
#include <linux/ptrace.h>
#include <linux/ioport.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/circ_buf.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/irq.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/bitops.h>
#include <asm/amazon/amazon.h>
#include <asm/amazon/irq.h>
#include <asm/amazon/serial.h>
#define PORT_AMAZONASC 111
#if defined(CONFIG_SERIAL_AMAZONASC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
#define SUPPORT_SYSRQ
#endif
#include <linux/serial_core.h>
#define UART_NR 1
#define SERIAL_AMAZONASC_MAJOR TTY_MAJOR
#define CALLOUT_AMAZONASC_MAJOR TTYAUX_MAJOR
#define SERIAL_AMAZONASC_MINOR 64
#define SERIAL_AMAZONASC_NR UART_NR
extern void prom_printf(const char * fmt, ...);
static struct uart_port amazonasc_ports[UART_NR];
static struct uart_driver amazonasc_reg;
#ifdef CONFIG_SERIAL_AMAZONASC_CONSOLE /*SUPPORT_SYSRQ*/
static struct console amazonasc_console;
#endif
static unsigned int uartclk = 0;
#define SET_BIT(reg, mask) *reg |= (mask)
#define CLEAR_BIT(reg, mask) *reg &= (~mask)
#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
#define SET_BITS(reg, mask) SET_BIT(reg, mask)
#define SET_BITFIELD(reg, mask, off, val) \
{*reg &= (~mask); *reg |= (val << off);}
static void amazonasc_tx_chars(struct uart_port *port);
/* fake flag to indicate CREAD was not set -> throw away all bytes */
#define UART_DUMMY_UER_RX 1
/* macro to set the bit corresponding to an interrupt number */
#define BIT_NO(irq) (1 << (irq - 64))
#define SERIAL_DEBUG
extern unsigned int amazon_get_fpi_hz(void);
static int tx_enabled = 0;
static void amazonasc_stop_tx(struct uart_port *port)
{
/* fifo underrun shuts up after firing once */
return;
}
static void amazonasc_start_tx(struct uart_port *port)
{
unsigned long flags;
local_irq_save(flags);
amazonasc_tx_chars(port);
local_irq_restore(flags);
return;
}
static void amazonasc_stop_rx(struct uart_port *port)
{
/* clear the RX enable bit */
*AMAZON_ASC_WHBCON = ASCWHBCON_CLRREN;
}
static void amazonasc_enable_ms(struct uart_port *port)
{
/* no modem signals */
return;
}
static void
amazonasc_rx_chars(struct uart_port *port)
{
struct tty_struct *tty = port->info->tty;
unsigned int ch = 0, rsr = 0, fifocnt;
unsigned long flags;
fifocnt = *AMAZON_ASC_FSTAT & ASCFSTAT_RXFFLMASK;
while (fifocnt--)
{
u8 flag = TTY_NORMAL;
ch = *AMAZON_ASC_RBUF;
rsr = (*AMAZON_ASC_CON & ASCCON_ANY) | UART_DUMMY_UER_RX;
tty_flip_buffer_push(tty);
port->icount.rx++;
/*
* Note that the error handling code is
* out of the main execution path
*/
if (rsr & ASCCON_ANY) {
if (rsr & ASCCON_PE) {
port->icount.parity++;
SET_BIT(AMAZON_ASC_WHBCON, ASCWHBCON_CLRPE);
} else if (rsr & ASCCON_FE) {
port->icount.frame++;
SET_BIT(AMAZON_ASC_WHBCON, ASCWHBCON_CLRFE);
}
if (rsr & ASCCON_OE) {
port->icount.overrun++;
SET_BIT(AMAZON_ASC_WHBCON, ASCWHBCON_CLROE);
}
rsr &= port->read_status_mask;
if (rsr & ASCCON_PE)
flag = TTY_PARITY;
else if (rsr & ASCCON_FE)
flag = TTY_FRAME;
}
if ((rsr & port->ignore_status_mask) == 0)
tty_insert_flip_char(tty, ch, flag);
if (rsr & ASCCON_OE)
/*
* Overrun is special, since it's reported
* immediately, and doesn't affect the current
* character
*/
tty_insert_flip_char(tty, 0, TTY_OVERRUN);
}
if (ch != 0)
tty_flip_buffer_push(tty);
return;
}
static void amazonasc_tx_chars(struct uart_port *port)
{
struct circ_buf *xmit = &port->info->xmit;
if (uart_tx_stopped(port)) {
amazonasc_stop_tx(port);
return;
}
while (((*AMAZON_ASC_FSTAT & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF) != AMAZONASC_TXFIFO_FULL)
{
if (port->x_char) {
*AMAZON_ASC_TBUF = port->x_char;
port->icount.tx++;
port->x_char = 0;
continue;
}
if (uart_circ_empty(xmit))
break;
*AMAZON_ASC_TBUF = xmit->buf[xmit->tail];
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
}
static irqreturn_t amazonasc_tx_int(int irq, void *port)
{
*(AMAZON_ASC_IRNCR1) = ASC_IRNCR_TIR;
amazonasc_start_tx(port);
/* clear any pending interrupts */
SET_BIT(AMAZON_ASC_WHBCON, ASCWHBCON_CLRPE);
SET_BIT(AMAZON_ASC_WHBCON, ASCWHBCON_CLRFE);
SET_BIT(AMAZON_ASC_WHBCON, ASCWHBCON_CLROE);
return IRQ_HANDLED;
}
static irqreturn_t amazonasc_er_int(int irq, void *port)
{
/* clear any pending interrupts */
SET_BIT(AMAZON_ASC_WHBCON, ASCWHBCON_CLRPE);
SET_BIT(AMAZON_ASC_WHBCON, ASCWHBCON_CLRFE);
SET_BIT(AMAZON_ASC_WHBCON, ASCWHBCON_CLROE);
return IRQ_HANDLED;
}
static irqreturn_t amazonasc_rx_int(int irq, void *port)
{
*(AMAZON_ASC_IRNCR1) = ASC_IRNCR_RIR;
amazonasc_rx_chars((struct uart_port *) port);
return IRQ_HANDLED;
}
static u_int amazonasc_tx_empty(struct uart_port *port)
{
int status;
/*
* FSTAT tells exactly how many bytes are in the FIFO.
* The question is whether we really need to wait for all
* 16 bytes to be transmitted before reporting that the
* transmitter is empty.
*/
status = *AMAZON_ASC_FSTAT & ASCFSTAT_TXFFLMASK;
return status ? 0 : TIOCSER_TEMT;
}
static u_int amazonasc_get_mctrl(struct uart_port *port)
{
/* no modem control signals - the readme says to pretend all are set */
return TIOCM_CTS|TIOCM_CAR|TIOCM_DSR;
}
static void amazonasc_set_mctrl(struct uart_port *port, u_int mctrl)
{
/* no modem control - just return */
return;
}
static void amazonasc_break_ctl(struct uart_port *port, int break_state)
{
/* no way to send a break */
return;
}
static int amazonasc_startup(struct uart_port *port)
{
unsigned int con = 0;
unsigned long flags;
int retval;
/* this assumes: CON.BRS = CON.FDE = 0 */
if (uartclk == 0)
uartclk = amazon_get_fpi_hz();
amazonasc_ports[0].uartclk = uartclk;
/* block the IRQs */
local_irq_save(flags);
/* this setup was probably already done in u-boot */
/* ASC and GPIO Port 1 bits 3 and 4 share the same pins
* P1.3 (RX) in, Alternate 10
* P1.4 (TX) in, Alternate 10
*/
SET_BITFIELD((AMAZON_GPIO_P1_DIR), 0x8, 4, 1); //P1.4 output, P1.3 input
SET_BIT((AMAZON_GPIO_P1_ALTSEL0), 0x18); //ALTSETL0 11
CLEAR_BIT((AMAZON_GPIO_P1_ALTSEL1), 0x18); //ALTSETL1 00
SET_BITFIELD((AMAZON_GPIO_P1_OD), 0x8, 4, 1);
/* set up the CLC */
CLEAR_BIT(AMAZON_ASC_CLC, AMAZON_ASC_CLC_DISS);
SET_BITFIELD(AMAZON_ASC_CLC, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 1);
/* asynchronous mode */
con = ASCCON_M_8ASYNC;
/* set error signals - framing and overrun */
con |= ASCCON_FEN;
con |= ASCCON_OEN;
con |= ASCCON_PEN;
/* choose the line - there's only one */
*AMAZON_ASC_PISEL = 0;
#if 1
*AMAZON_ASC_TXFCON = (((AMAZONASC_TXFIFO_FL<<ASCTXFCON_TXFITLOFF)&ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN |ASCTXFCON_TXFFLU);
*AMAZON_ASC_RXFCON = (((AMAZONASC_RXFIFO_FL<<ASCRXFCON_RXFITLOFF)&ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN |ASCRXFCON_RXFFLU);
wmb();
#else
/* TXFIFO's fill level */
SET_BITFIELD(AMAZON_ASC_TXFCON, ASCTXFCON_TXFITLMASK,
ASCTXFCON_TXFITLOFF, AMAZONASC_TXFIFO_FL);
/* enable TXFIFO */
SET_BIT(AMAZON_ASC_TXFCON, ASCTXFCON_TXFEN);
/* RXFIFO's fill level */
SET_BITFIELD(AMAZON_ASC_RXFCON, ASCRXFCON_RXFITLMASK,
ASCRXFCON_RXFITLOFF, AMAZONASC_RXFIFO_FL);
/* enable RXFIFO */
SET_BIT(AMAZON_ASC_RXFCON, ASCRXFCON_RXFEN);
/* now really set CON */
#endif
SET_BIT(AMAZON_ASC_CON,con);
/*
* Allocate the IRQs
*/
retval = request_irq(AMAZONASC_RIR, amazonasc_rx_int, 0, "asc_rx", port);
if (retval){
printk("-------req1 failed\n");
return retval;
}
retval = request_irq(AMAZONASC_TIR, amazonasc_tx_int, 0, "asc_tx", port);
if (retval){
printk("----------req2 failed\n");
goto err1;
}
retval = request_irq(AMAZONASC_EIR, amazonasc_er_int, 0, "asc_er", port);
if (retval){
printk("---------req3 failed\n");
goto err2;
}
/* unblock the IRQs */
local_irq_restore(flags);
return 0;
err2:
free_irq(AMAZONASC_TIR, port);
err1:
free_irq(AMAZONASC_RIR, port);
local_irq_restore(flags);
return retval;
}
static void amazonasc_shutdown(struct uart_port *port)
{
/*
* Free the interrupts
*/
free_irq(AMAZONASC_RIR, port);
free_irq(AMAZONASC_TIR, port);
free_irq(AMAZONASC_EIR, port);
/*
* disable the baudrate generator to disable the ASC
*/
*AMAZON_ASC_CON = 0;
/* flush and then disable the fifos */
SET_BIT(AMAZON_ASC_RXFCON, ASCRXFCON_RXFFLU);
CLEAR_BIT(AMAZON_ASC_RXFCON, ASCRXFCON_RXFEN);
SET_BIT(AMAZON_ASC_TXFCON, ASCTXFCON_TXFFLU);
CLEAR_BIT(AMAZON_ASC_TXFCON, ASCTXFCON_TXFEN);
}
static void amazonasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
{
unsigned int cflag;
unsigned int iflag;
unsigned int baud, quot;
unsigned int con = 0;
unsigned long flags;
cflag = new->c_cflag;
iflag = new->c_iflag;
/* byte size and parity */
switch (cflag & CSIZE) {
/* 7 bits are always with parity */
case CS7: con = ASCCON_M_7ASYNCPAR; break;
/* the ASC only suports 7 and 8 bits */
case CS5:
case CS6:
default:
if (cflag & PARENB)
con = ASCCON_M_8ASYNCPAR;
else
con = ASCCON_M_8ASYNC;
break;
}
if (cflag & CSTOPB)
con |= ASCCON_STP;
if (cflag & PARENB) {
if (!(cflag & PARODD))
con &= ~ASCCON_ODD;
else
con |= ASCCON_ODD;
}
port->read_status_mask = ASCCON_OE;
if (iflag & INPCK)
port->read_status_mask |= ASCCON_FE | ASCCON_PE;
/* the ASC can't really detect or generate a BREAK */
#if 0
if (iflag & (BRKINT | PARMRK))
port->read_status_mask |= UERSTAT_BREAK;
#endif
/*
* Characters to ignore
*/
port->ignore_status_mask = 0;
if (iflag & IGNPAR)
port->ignore_status_mask |= ASCCON_FE | ASCCON_PE;
#if 0
/* always ignore breaks - the ASC can't handle them XXXX */
port->ignore_status_mask |= UERSTAT_BREAK;
#endif
if (iflag & IGNBRK) {
/*port->ignore_status_mask |= UERSTAT_BREAK;*/
/*
* If we're ignoring parity and break indicators,
* ignore overruns too (for real raw support).
*/
if (iflag & IGNPAR)
port->ignore_status_mask |= ASCCON_OE;
}
/*
* Ignore all characters if CREAD is not set.
*/
if ((cflag & CREAD) == 0)
port->ignore_status_mask |= UART_DUMMY_UER_RX;
/* set error signals - framing, parity and overrun */
con |= ASCCON_FEN;
con |= ASCCON_OEN;
con |= ASCCON_PEN;
/* enable the receiver */
con |= ASCCON_REN;
/* block the IRQs */
local_irq_save(flags);
/* set up CON */
*AMAZON_ASC_CON = con;
/* Set baud rate - take a divider of 2 into account */
baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16);
quot = uart_get_divisor(port, baud);
quot = quot/2 - 1;
/* the next 3 probably already happened when we set CON above */
/* disable the baudrate generator */
CLEAR_BIT(AMAZON_ASC_CON, ASCCON_R);
/* make sure the fractional divider is off */
CLEAR_BIT(AMAZON_ASC_CON, ASCCON_FDE);
/* set up to use divisor of 2 */
CLEAR_BIT(AMAZON_ASC_CON, ASCCON_BRS);
/* now we can write the new baudrate into the register */
*AMAZON_ASC_BTR = quot;
/* turn the baudrate generator back on */
SET_BIT(AMAZON_ASC_CON, ASCCON_R);
/* unblock the IRQs */
local_irq_restore(flags);
}
static const char *amazonasc_type(struct uart_port *port)
{
return port->type == PORT_AMAZONASC ? "AMAZONASC" : NULL;
}
/*
* Release the memory region(s) being used by 'port'
*/
static void amazonasc_release_port(struct uart_port *port)
{
return;
}
/*
* Request the memory region(s) being used by 'port'
*/
static int amazonasc_request_port(struct uart_port *port)
{
return 0;
}
/*
* Configure/autoconfigure the port.
*/
static void amazonasc_config_port(struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE) {
port->type = PORT_AMAZONASC;
amazonasc_request_port(port);
}
}
/*
* verify the new serial_struct (for TIOCSSERIAL).
*/
static int amazonasc_verify_port(struct uart_port *port, struct serial_struct *ser)
{
int ret = 0;
if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMAZONASC)
ret = -EINVAL;
if (ser->irq < 0 || ser->irq >= NR_IRQS)
ret = -EINVAL;
if (ser->baud_base < 9600)
ret = -EINVAL;
return ret;
}
static struct uart_ops amazonasc_pops = {
.tx_empty = amazonasc_tx_empty,
.set_mctrl = amazonasc_set_mctrl,
.get_mctrl = amazonasc_get_mctrl,
.stop_tx = amazonasc_stop_tx,
.start_tx = amazonasc_start_tx,
.stop_rx = amazonasc_stop_rx,
.enable_ms = amazonasc_enable_ms,
.break_ctl = amazonasc_break_ctl,
.startup = amazonasc_startup,
.shutdown = amazonasc_shutdown,
.set_termios = amazonasc_set_termios,
.type = amazonasc_type,
.release_port = amazonasc_release_port,
.request_port = amazonasc_request_port,
.config_port = amazonasc_config_port,
.verify_port = amazonasc_verify_port,
};
static struct uart_port amazonasc_ports[UART_NR] = {
{
membase: (void *)AMAZON_ASC,
mapbase: AMAZON_ASC,
iotype: SERIAL_IO_MEM,
irq: AMAZONASC_RIR, /* RIR */
uartclk: 0, /* filled in dynamically */
fifosize: 16,
unused: { AMAZONASC_TIR, AMAZONASC_EIR}, /* xmit/error/xmit-buffer-empty IRQ */
type: PORT_AMAZONASC,
ops: &amazonasc_pops,
flags: ASYNC_BOOT_AUTOCONF,
},
};
static void amazonasc_console_write(struct console *co, const char *s, u_int count)
{
int i, fifocnt;
unsigned long flags;
/* block the IRQ */
local_irq_save(flags);
/*
* Now, do each character
*/
for (i = 0; i < count;)
{
/* wait until the FIFO is not full */
do
{
fifocnt = (*AMAZON_ASC_FSTAT & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF;
} while (fifocnt == AMAZONASC_TXFIFO_FULL);
#if 1
if (s[i] == '\0')
{
break;
}
#endif
if (s[i] == '\n')
{
*AMAZON_ASC_TBUF = '\r';
do
{
fifocnt = (*AMAZON_ASC_FSTAT &
ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF;
} while (fifocnt == AMAZONASC_TXFIFO_FULL);
}
*AMAZON_ASC_TBUF = s[i];
i++;
} /* for */
/* restore the IRQ */
local_irq_restore(flags);
}
static void __init
amazonasc_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits)
{
u_int lcr_h;
lcr_h = *AMAZON_ASC_CON;
/* do this only if the ASC is turned on */
if (lcr_h & ASCCON_R) {
u_int quot, div, fdiv, frac;
*parity = 'n';
if ((lcr_h & ASCCON_MODEMASK) == ASCCON_M_7ASYNCPAR ||
(lcr_h & ASCCON_MODEMASK) == ASCCON_M_8ASYNCPAR) {
if (lcr_h & ASCCON_ODD)
*parity = 'o';
else
*parity = 'e';
}
if ((lcr_h & ASCCON_MODEMASK) == ASCCON_M_7ASYNCPAR)
*bits = 7;
else
*bits = 8;
quot = *AMAZON_ASC_BTR + 1;
/* this gets hairy if the fractional divider is used */
if (lcr_h & ASCCON_FDE)
{
div = 1;
fdiv = *AMAZON_ASC_FDV;
if (fdiv == 0)
fdiv = 512;
frac = 512;
}
else
{
div = lcr_h & ASCCON_BRS ? 3 : 2;
fdiv = frac = 1;
}
/*
* This doesn't work exactly because we use integer
* math to calculate baud which results in rounding
* errors when we try to go from quot -> baud !!
* Try to make this work for both the fractional divider
* and the simple divider. Also try to avoid rounding
* errors using integer math.
*/
*baud = frac * (port->uartclk / (div * 512 * 16 * quot));
if (*baud > 1100 && *baud < 2400)
*baud = 1200;
if (*baud > 2300 && *baud < 4800)
*baud = 2400;
if (*baud > 4700 && *baud < 9600)
*baud = 4800;
if (*baud > 9500 && *baud < 19200)
*baud = 9600;
if (*baud > 19000 && *baud < 38400)
*baud = 19200;
if (*baud > 38400 && *baud < 57600)
*baud = 38400;
if (*baud > 57600 && *baud < 115200)
*baud = 57600;
if (*baud > 115200 && *baud < 230400)
*baud = 115200;
}
}
static int __init amazonasc_console_setup(struct console *co, char *options)
{
struct uart_port *port;
int baud = 115200;
int bits = 8;
int parity = 'n';
int flow = 'n';
/* this assumes: CON.BRS = CON.FDE = 0 */
if (uartclk == 0)
uartclk = amazon_get_fpi_hz();
co->index = 0;
port = &amazonasc_ports[0];
amazonasc_ports[0].uartclk = uartclk;
amazonasc_ports[0].type = PORT_AMAZONASC;
if (options){
uart_parse_options(options, &baud, &parity, &bits, &flow);
}
return uart_set_options(port, co, baud, parity, bits, flow);
}
static struct uart_driver amazonasc_reg;
static struct console amazonasc_console = {
name: "ttyS",
write: amazonasc_console_write,
device: uart_console_device,
setup: amazonasc_console_setup,
flags: CON_PRINTBUFFER,
index: -1,
data: &amazonasc_reg,
};
static int __init amazonasc_console_init(void)
{
register_console(&amazonasc_console);
return 0;
}
console_initcall(amazonasc_console_init);
static struct uart_driver amazonasc_reg = {
.owner = THIS_MODULE,
.driver_name = "serial",
.dev_name = "ttyS",
.major = TTY_MAJOR,
.minor = 64,
.nr = UART_NR,
.cons = &amazonasc_console,
};
static int __init amazonasc_init(void)
{
unsigned char res;
uart_register_driver(&amazonasc_reg);
res = uart_add_one_port(&amazonasc_reg, &amazonasc_ports[0]);
return res;
}
static void __exit amazonasc_exit(void)
{
uart_unregister_driver(&amazonasc_reg);
}
module_init(amazonasc_init);
module_exit(amazonasc_exit);
MODULE_AUTHOR("Gary Jennejohn, Felix Fietkau, John Crispin");
MODULE_DESCRIPTION("MIPS AMAZONASC serial port driver");
MODULE_LICENSE("GPL");

232
target/linux/amazon-2.6/files/include/asm-mips/amazon/adm6996.h Normal file
View File

@ -0,0 +1,232 @@
/******************************************************************************
Copyright (c) 2004, Infineon Technologies. All rights reserved.
No Warranty
Because the program is licensed free of charge, there is no warranty for
the program, to the extent permitted by applicable law. Except when
otherwise stated in writing the copyright holders and/or other parties
provide the program "as is" without warranty of any kind, either
expressed or implied, including, but not limited to, the implied
warranties of merchantability and fitness for a particular purpose. The
entire risk as to the quality and performance of the program is with
you. should the program prove defective, you assume the cost of all
necessary servicing, repair or correction.
In no event unless required by applicable law or agreed to in writing
will any copyright holder, or any other party who may modify and/or
redistribute the program as permitted above, be liable to you for
damages, including any general, special, incidental or consequential
damages arising out of the use or inability to use the program
(including but not limited to loss of data or data being rendered
inaccurate or losses sustained by you or third parties or a failure of
the program to operate with any other programs), even if such holder or
other party has been advised of the possibility of such damages.
******************************************************************************
Module : ifx_swdrv.h
Date : 2004-09-01
Description : JoeLin
Remarks:
*****************************************************************************/
#ifndef _ADM_6996_MODULE_H_
#define _ADM_6996_MODULE_H_
#include <asm/amazon/amazon.h>
#define ifx_printf(x) printk x
/* command codes */
#define ADM_SW_SMI_READ 0x02
#define ADM_SW_SMI_WRITE 0x01
#define ADM_SW_SMI_START 0x01
#define ADM_SW_EEPROM_WRITE 0x01
#define ADM_SW_EEPROM_WRITE_ENABLE 0x03
#define ADM_SW_EEPROM_WRITE_DISABLE 0x00
#define EEPROM_TYPE 8 /* for 93C66 */
/* bit masks */
#define ADM_SW_BIT_MASK_1 0x00000001
#define ADM_SW_BIT_MASK_2 0x00000002
#define ADM_SW_BIT_MASK_4 0x00000008
#define ADM_SW_BIT_MASK_10 0x00000200
#define ADM_SW_BIT_MASK_16 0x00008000
#define ADM_SW_BIT_MASK_32 0x80000000
/* delay timers */
#define ADM_SW_MDC_DOWN_DELAY 5
#define ADM_SW_MDC_UP_DELAY 5
#define ADM_SW_CS_DELAY 5
/* MDIO modes */
#define ADM_SW_MDIO_OUTPUT 1
#define ADM_SW_MDIO_INPUT 0
#define ADM_SW_MAX_PORT_NUM 5
#define ADM_SW_MAX_VLAN_NUM 15
/* registers */
#define ADM_SW_PORT0_CONF 0x1
#define ADM_SW_PORT1_CONF 0x3
#define ADM_SW_PORT2_CONF 0x5
#define ADM_SW_PORT3_CONF 0x7
#define ADM_SW_PORT4_CONF 0x8
#define ADM_SW_PORT5_CONF 0x9
#define ADM_SW_VLAN_MODE 0x11
#define ADM_SW_MAC_LOCK 0x12
#define ADM_SW_VLAN0_CONF 0x13
#define ADM_SW_PORT0_PVID 0x28
#define ADM_SW_PORT1_PVID 0x29
#define ADM_SW_PORT2_PVID 0x2a
#define ADM_SW_PORT34_PVID 0x2b
#define ADM_SW_PORT5_PVID 0x2c
#define ADM_SW_PHY_RESET 0x2f
#define ADM_SW_MISC_CONF 0x30
#define ADM_SW_BNDWDH_CTL0 0x31
#define ADM_SW_BNDWDH_CTL1 0x32
#define ADM_SW_BNDWDH_CTL_ENA 0x33
/* port modes */
#define ADM_SW_PORT_FLOWCTL 0x1 /* 802.3x flow control */
#define ADM_SW_PORT_AN 0x2 /* auto negotiation */
#define ADM_SW_PORT_100M 0x4 /* 100M */
#define ADM_SW_PORT_FULL 0x8 /* full duplex */
#define ADM_SW_PORT_TAG 0x10 /* output tag on */
#define ADM_SW_PORT_DISABLE 0x20 /* disable port */
#define ADM_SW_PORT_TOS 0x40 /* TOS first */
#define ADM_SW_PORT_PPRI 0x80 /* port based priority first */
#define ADM_SW_PORT_MDIX 0x8000 /* auto MDIX on */
#define ADM_SW_PORT_PVID_SHIFT 10
#define ADM_SW_PORT_PVID_BITS 4
/* VLAN */
#define ADM_SW_VLAN_PORT0 0x1
#define ADM_SW_VLAN_PORT1 0x2
#define ADM_SW_VLAN_PORT2 0x10
#define ADM_SW_VLAN_PORT3 0x40
#define ADM_SW_VLAN_PORT4 0x80
#define ADM_SW_VLAN_PORT5 0x100
/* GPIO 012 enabled, output mode */
#define GPIO_ENABLEBITS 0x000700f8
/*
define AMAZON GPIO port to ADM6996 EEPROM interface
MDIO -> EEDI GPIO 16, AMAZON GPIO P1.0, bi-direction
MDC -> EESK GPIO 17, AMAZON GPIO P1.1, output only
MDCS -> EECS GPIO 18, AMAZON GPIO P1.2, output only
EEDO GPIO 15, AMAZON GPIO P0.15, do not need this one! */
#define GPIO_MDIO 1 //P1.0
#define GPIO_MDC 2 //P1.1
#define GPIO_MDCS 4 //P1.2
//joelin #define GPIO_MDIO 0
//joelin #define GPIO_MDC 5 /* PORT 0 GPIO5 */
//joelin #define GPIO_MDCS 6 /* PORT 0 GPIO6 */
#define MDIO_INPUT 0x00000001
#define MDIO_OUTPUT_EN 0x00010000
/* type definitions */
typedef unsigned char U8;
typedef unsigned short U16;
typedef unsigned int U32;
typedef struct _REGRW_
{
unsigned int addr;
unsigned int value;
unsigned int mode;
}REGRW, *PREGRW;
//joelin adm6996i
typedef struct _MACENTRY_
{
unsigned char mac_addr[6];
unsigned long fid:4;
unsigned long portmap:6;
union {
unsigned long age_timer:9;
unsigned long info_ctrl:9;
} ctrl;
unsigned long occupy:1;
unsigned long info_type:1;
unsigned long bad:1;
unsigned long result:3;//000:command ok ,001:all entry used,010:Entry Not found ,011:try next entry ,101:command error
}MACENTRY, *PMACENTRY;
typedef struct _PROTOCOLFILTER_
{
int protocol_filter_num;//[0~7]
int ip_p; //Value Compared with Protocol in IP Heade[7:0]
char action:2;//Action for protocol Filter .
//00 = Protocol Portmap is Default Output Ports.
//01 = Protocol Portmap is 6'b0.
//10 = Protocol Portmap is the CPU port if the incoming port
//is not the CPU port. But if the incoming port is the CPU port, then Type Portmap contains Default Output Ports, excluding the CPU port.
}PROTOCOLFILTER, *PPROTOCOLFILTER;
//joelin adm6996i
/* Santosh: for IGMP proxy/snooping */
//050614:fchang int adm_process_mac_table_request (unsigned int cmd, struct _MACENTRY_ *mac);
//050614:fchang int adm_process_protocol_filter_request (unsigned int cmd, struct _PROTOCOLFILTER_ *filter);
/* IOCTL keys */
#define KEY_IOCTL_ADM_REGRW 0x01
#define KEY_IOCTL_ADM_SW_REGRW 0x02
#define KEY_IOCTL_ADM_SW_PORTSTS 0x03
#define KEY_IOCTL_ADM_SW_INIT 0x04
//for adm6996i-start
#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD 0x05
#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL 0x06
#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT 0x07
#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE 0x08
#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD 0x09
#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL 0x0a
#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET 0x0b
//adm6996i #define KEY_IOCTL_MAX_KEY 0x05
#define KEY_IOCTL_MAX_KEY 0x0c
//for adm6996i-end
/* IOCTL MAGIC */
#define ADM_MAGIC ('a'|'d'|'m'|'t'|'e'|'k')
/* IOCTL parameters */
#define ADM_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_REGRW, REGRW)
#define ADM_SW_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_REGRW, REGRW)
#define ADM_SW_IOCTL_PORTSTS _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_PORTSTS, NULL)
#define ADM_SW_IOCTL_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_INIT, NULL)
//6996i-stat
#define ADM_SW_IOCTL_MACENTRY_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD,MACENTRY)
#define ADM_SW_IOCTL_MACENTRY_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL,MACENTRY)
#define ADM_SW_IOCTL_MACENTRY_GET_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT,MACENTRY)
#define ADM_SW_IOCTL_MACENTRY_GET_MORE _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE,MACENTRY)
#define ADM_SW_IOCTL_FILTER_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD,PROTOCOLFILTER)
#define ADM_SW_IOCTL_FILTER_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL,PROTOCOLFILTER)
#define ADM_SW_IOCTL_FILTER_GET _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET,PROTOCOLFILTER)
//6996i-end
#define REG_READ 0x0
#define REG_WRITE 0x1
/* undefine symbol */
#define AMAZON_SW_REG(reg) *((volatile U32*)(reg))
//#define GPIO0_INPUT_MASK 0
//#define GPIO_conf0_REG 0x12345678
//#define GPIO_SET_HI
//#define GPIO_SET_LOW
#endif
/* _ADM_6996_MODULE_H_ */

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#ifndef AMAZON_DMA_H
#define AMAZON_DMA_H
#define RCV_INT 1
#define TX_BUF_FULL_INT 2
#define TRANSMIT_CPT_INT 4
#define QOS_DEFAULT_WGT 0x7fffffffUL;
enum attr_t{
TX=0,
RX=1,
RESERVED=2,
DEFAULT=3,
};
#ifdef CONFIG_CPU_LITTLE_ENDIAN
typedef struct rx_desc{
u32 data_length:16;
volatile u32 reserved:7;
volatile u32 byte_offset:2;
volatile u32 Burst_length_offset:3;
volatile u32 EoP:1;
volatile u32 Res:1;
volatile u32 C:1;
volatile u32 OWN:1;
volatile u32 Data_Pointer;
/*fix me:should be 28 bits here, 32 bits just for host simulatiuon purpose*/
}_rx_desc;
typedef struct tx_desc{
volatile u32 data_length:16;
volatile u32 reserved1:7;
volatile u32 byte_offset:5;
volatile u32 EoP:1;
volatile u32 SoP:1;
volatile u32 C:1;
volatile u32 OWN:1;
volatile u32 Data_Pointer;//fix me:should be 28 bits here
}_tx_desc;
#else //BIG
typedef struct rx_desc{
union
{
struct
{
volatile u32 OWN :1;
volatile u32 C :1;
volatile u32 SoP :1;
volatile u32 EoP :1;
volatile u32 Burst_length_offset :3;
volatile u32 byte_offset :2;
volatile u32 reserve :7;
volatile u32 data_length :16;
}field;
volatile u32 word;
}status;
volatile u32 Data_Pointer;
}_rx_desc;
typedef struct tx_desc{
union
{
struct
{
volatile u32 OWN :1;
volatile u32 C :1;
volatile u32 SoP :1;
volatile u32 EoP :1;
volatile u32 byte_offset :5;
volatile u32 reserved :7;
volatile u32 data_length :16;
}field;
volatile u32 word;
}status;
volatile u32 Data_Pointer;
}_tx_desc;
#endif //ENDIAN
struct dma_channel_info{
/*filled by driver, optional*/
enum attr_t attr;/*TX or RX*/
int weight;
int desc_num;
int packet_size;
int control;/*on or off*/
int desc_base;
int status;
};
typedef struct dma_channel_info _dma_channel_info;
struct dma_device_info{
/*variables*/
/*filled by driver, compulsary*/
char device_name[15];
enum attr_t attr;/*default or else*/
int tx_burst_len;
int rx_burst_len;
int logic_rx_chan_base;
int logic_tx_chan_base;
u8 on_ch_bit;
/*filled by driver, optional*/
int weight;
int current_tx_chan;
int current_rx_chan;
int num_tx_chan;
int num_rx_chan;
struct dma_channel_info tx_chan[2];
struct dma_channel_info rx_chan[4];
/*functions, optional*/
u8* (*buffer_alloc)(int len,int* offset, void** opt);
int (*buffer_free)(u8* dataptr, void* opt);
int (*intr_handler)(struct dma_device_info* info, int status);
/*set by device, clear by dma*/
int ack;
void * priv; /* used by peripheral driver only */
};
typedef struct dma_device_info _dma_device_info;
int dma_device_register(struct dma_device_info* info);
int dma_device_unregister(struct dma_device_info* info);
int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt);
int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt);
int dma_device_update(struct dma_device_info* info);
void dma_device_update_rx(struct dma_device_info* dma_dev);
void dma_device_update_tx(struct dma_device_info* dma_dev);
void register_handler_sim(int (*handler)(int));
#endif /* AMAZON_DMA_H */

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#ifndef _AMAZON_MEI_H
#define _AMAZON_MEI_H
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
#include "amazon_mei_app.h"
#define AMAZON_MEI_DEBUG_ON
#define AMAZON_MEI_CMV_EXTRA
#define AMAZON_MEI_MAJOR 106
/*
** Define where in ME Processor's memory map the Stratify chip lives
*/
#define MEI_SPACE_ACCESS 0xB0100C00
#define MAXSWAPSIZE 8 * 1024 //8k *(32bits)
//#define AMAZON_ADSL_IMAGESIZE 16*1024 // 16k * (32bits)
// Mailboxes
#define MSG_LENGTH 16 // x16 bits
#define YES_REPLY 1
#define NO_REPLY 0
#define CMV_TIMEOUT 100 //jiffies
#define MIB_INTERVAL 10000 //msec
/*** Bit definitions ***/
#define FALSE 0
#define TRUE 1
#define BIT0 1<<0
#define BIT1 1<<1
#define BIT2 1<<2
#define BIT3 1<<3
#define BIT4 1<<4
#define BIT5 1<<5
#define BIT6 1<<6
#define BIT7 1<<7
#define BIT8 1<<8
#define BIT9 1<<9
#define BIT10 1<<10
#define BIT11 1<<11
#define BIT12 1<<12
#define BIT13 1<<13
#define BIT14 1<<14
#define BIT15 1<<15
#define BIT16 1<<16
#define BIT17 1<<17
#define BIT18 1<<18
#define BIT19 1<<19
#define BIT20 1<<20
#define BIT21 1<<21
#define BIT22 1<<22
#define BIT23 1<<23
#define BIT24 1<<24
#define BIT25 1<<25
#define BIT26 1<<26
#define BIT27 1<<27
#define BIT28 1<<28
#define BIT29 1<<29
#define BIT30 1<<30
#define BIT31 1<<31
/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/
#define MEI_DATA_XFR (0x0000 + MEI_SPACE_ACCESS)
#define MEI_VERSION (0x0200 + MEI_SPACE_ACCESS)
#define ARC_GP_STAT (0x0204 + MEI_SPACE_ACCESS)
#define MEI_XFR_ADDR (0x020C + MEI_SPACE_ACCESS)
#define MEI_TO_ARC_INT (0x021C + MEI_SPACE_ACCESS)
#define ARC_TO_MEI_INT (0x0220 + MEI_SPACE_ACCESS)
#define ARC_TO_MEI_INT_MASK (0x0224 + MEI_SPACE_ACCESS)
#define MEI_DEBUG_WAD (0x0228 + MEI_SPACE_ACCESS)
#define MEI_DEBUG_RAD (0x022C + MEI_SPACE_ACCESS)
#define MEI_DEBUG_DATA (0x0230 + MEI_SPACE_ACCESS)
#define MEI_DEBUG_DEC (0x0234 + MEI_SPACE_ACCESS)
#define MEI_CONTROL (0x0238 + MEI_SPACE_ACCESS)
#define AT_CELLRDY_BC0 (0x023C + MEI_SPACE_ACCESS)
#define AT_CELLRDY_BC1 (0x0240 + MEI_SPACE_ACCESS)
#define AR_CELLRDY_BC0 (0x0244 + MEI_SPACE_ACCESS)
#define AR_CELLRDY_BC1 (0x0248 + MEI_SPACE_ACCESS)
#define AAI_ACCESS (0x024C + MEI_SPACE_ACCESS)
#define AAITXCB0 (0x0300 + MEI_SPACE_ACCESS)
#define AAITXCB1 (0x0304 + MEI_SPACE_ACCESS)
#define AAIRXCB0 (0x0308 + MEI_SPACE_ACCESS)
#define AAIRXCB1 (0x030C + MEI_SPACE_ACCESS)
// MEI_TO_ARC_INTERRUPT Register definitions
#define MEI_TO_ARC_INT1 BIT3
#define MEI_TO_ARC_INT0 BIT2
#define MEI_TO_ARC_CS_DONE BIT1
#define MEI_TO_ARC_MSGAV BIT0
// ARC_TO_MEI_INTERRUPT Register definitions
#define ARC_TO_MEI_INT1 BIT8
#define ARC_TO_MEI_INT0 BIT7
#define ARC_TO_MEI_CS_REQ BIT6
#define ARC_TO_MEI_DBG_DONE BIT5
#define ARC_TO_MEI_MSGACK BIT4
#define ARC_TO_MEI_NO_ACCESS BIT3
#define ARC_TO_MEI_CHECK_AAITX BIT2
#define ARC_TO_MEI_CHECK_AAIRX BIT1
#define ARC_TO_MEI_MSGAV BIT0
// ARC_TO_MEI_INTERRUPT_MASK Register definitions
#define GP_INT1_EN BIT8
#define GP_INT0_EN BIT7
#define CS_REQ_EN BIT6
#define DBG_DONE_EN BIT5
#define MSGACK_EN BIT4
#define NO_ACC_EN BIT3
#define AAITX_EN BIT2
#define AAIRX_EN BIT1
#define MSGAV_EN BIT0
// MEI_CONTROL Register definitions
#define INT_LEVEL BIT2
#define SOFT_RESET BIT1
#define HOST_MSTR BIT0
// MEI_DEBUG_DECODE Register definitions
#define MEI_DEBUG_DEC_MASK (0x3)
#define MEI_DEBUG_DEC_AUX_MASK (0x0)
#define MEI_DEBUG_DEC_DMP1_MASK (0x1)
#define MEI_DEBUG_DEC_DMP2_MASK (0x2)
#define MEI_DEBUG_DEC_CORE_MASK (0x3)
// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
// page swap requests.
#define MEI_TO_ARC_MAILBOX (0x15FC0)
#define MEI_TO_ARC_MAILBOXR (0x15FEC)
#define ARC_TO_MEI_MAILBOX (0x15F90)
#define ARC_MEI_MAILBOXR (0x15FBC)
// Codeswap request messages are indicated by setting BIT31
#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000)
/*
** Swap page header
*/
// Page must be loaded at boot time if size field has BIT31 set
#define BOOT_FLAG (BIT31)
#define BOOT_FLAG_MASK ~BOOT_FLAG
// Swap page header describes size in 32-bit words, load location, and image offset
// for program and/or data segments
typedef struct _arc_swp_page_hdr
{
u32 p_offset; // Offset bytes of progseg from beginning of image
u32 p_dest; // Destination addr of progseg on processor
u32 p_size; // Size in 32-bitwords of program segment
u32 d_offset; // Offset bytes of dataseg from beginning of image
u32 d_dest; // Destination addr of dataseg on processor
u32 d_size; // Size in 32-bitwords of data segment
}ARC_SWP_PAGE_HDR;
/*
** Swap image header
*/
#define GET_PROG 0 // Flag used for program mem segment
#define GET_DATA 1 // Flag used for data mem segment
// Image header contains size of image, checksum for image, and count of
// page headers. Following that are 'count' page headers followed by
// the code and/or data segments to be loaded
typedef struct _arc_img_hdr
{
u32 size; // Size of binary image in bytes
u32 checksum; // Checksum for image
u32 count; // Count of swp pages in image
ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy
}ARC_IMG_HDR;
/*
** Native size for the Stratiphy interface is 32-bits. All reads and writes
** MUST be aligned on 32-bit boundaries. Trickery must be invoked to read word and/or
** byte data. Read routines are provided. Write routines are probably a bad idea, as the
** Arc has unrestrained, unseen access to the same memory, so a read-modify-write cycle
** could very well have unintended results.
*/
MEI_ERROR meiCMV(u16 *, int); // first arg is CMV to ARC, second to indicate whether need reply
void meiLongwordWrite(u32 ul_address, u32 ul_data);
void meiLongwordRead(u32 ul_address, u32 *pul_data);
MEI_ERROR meiDMAWrite(u32 destaddr, u32 *databuff, u32 databuffsize);
MEI_ERROR meiDebugWrite(u32 destaddr, u32 *databuff, u32 databuffsize);
MEI_ERROR meiDMARead(u32 srcaddr, u32 *databuff, u32 databuffsize);
MEI_ERROR meiDebugRead(u32 srcaddr, u32 *databuff, u32 databuffsize);
void meiPollForDbgDone(void);
void meiMailboxInterruptsDisable(void);
void meiMailboxInterruptsEnable(void);
MEI_ERROR meiMailboxWrite(u16 *msgsrcbuffer, u16 msgsize);
MEI_ERROR meiMailboxRead(u16 *msgdestbuffer, u16 msgsize);
int meiGetPage( u32 Page, u32 data, u32 MaxSize, u32 *Buffer, u32 *Dest);
MEI_ERROR meiHaltArc(void);
MEI_ERROR meiRunArc(void);
MEI_ERROR meiDownloadBootCode(void);
MEI_ERROR meiForceRebootAdslModem(void);
void makeCMV(u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data);
#endif

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//509221:tc.chen 2005/09/22 Reset DFE added when MEI_TO_ARC_CS_DONE not cleared by ARC and Added AMAZON_MEI_DEBUG_MODE ioctl
#ifndef _AMAZON_MEI_APP_H
#define _AMAZON_MEI_APP_H
/////////////////////////////////////////////////////////////////////////////////////////////////////
// ioctl control
#define AMAZON_MEI_START 300
#define AMAZON_MEI_REPLY 301
#define AMAZON_MEI_NOREPLY 302
#define AMAZON_MEI_RESET 303
#define AMAZON_MEI_REBOOT 304
#define AMAZON_MEI_HALT 305
#define AMAZON_MEI_CMV_WINHOST 306
#define AMAZON_MEI_CMV_READ 307
#define AMAZON_MEI_CMV_WRITE 308
#define AMAZON_MEI_MIB_DAEMON 309
#define AMAZON_MEI_SHOWTIME 310
#define AMAZON_MEI_REMOTE 311
#define AMAZON_MEI_READDEBUG 312
#define AMAZON_MEI_WRITEDEBUG 313
#define AMAZON_MEI_LOP 314
#define AMAZON_MEI_PCM_SETUP 315
#define AMAZON_MEI_PCM_START_TIMER 316
#define AMAZON_MEI_PCM_STOP_TIMER 317
#define AMAZON_MEI_PCM_CHECK 318
#define AMAZON_MEI_GET_EOC_LEN 319
#define AMAZON_MEI_GET_EOC_DATA 320
#define AMAZON_MEI_PCM_GETDATA 321
#define AMAZON_MEI_PCM_GPIO 322
#define AMAZON_MEI_EOC_SEND 323
//MIB
#define AMAZON_MIB_LO_ATUC 324
#define AMAZON_MIB_LO_ATUR 325
#define AMAZON_MEI_DOWNLOAD 326
#define AMAZON_MEI_DEBUG_MODE 327 //509221:tc.chen
#define LOOP_DIAGNOSTIC_MODE_COMPLETE 328
/*** Enums ***/
typedef enum mei_error
{
MEI_SUCCESS = 0,
MEI_FAILURE = -1,
MEI_MAILBOX_FULL = -2,
MEI_MAILBOX_EMPTY = -3,
MEI_MAILBOX_TIMEOUT = -4,
}MEI_ERROR;
#endif

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//509221:tc.chen 2005/09/22 Reset DFE added when MEI_TO_ARC_CS_DONE not cleared by ARC and Added AMAZON_MEI_DEBUG_MODE ioctl
#ifndef _AMAZON_MEI_IOCTL_H
#define _AMAZON_MEI_IOCTL_H
/////////////////////////////////////////////////////////////////////////////////////////////////////
#define PCM_BUFF_SIZE 1024 //bytes
// interrupt numbers
#ifndef _AMAZON_ADSL_APP
typedef struct pcm_data_struct{
u16 S;
u16 temp;
u16 LSW;
u16 MSW;
u16 len;
u16 rdindex;
u16 wrindex;
u16 flow;
int finish;
u8 buff[PCM_BUFF_SIZE];
int point;
}pcm_data_struct;
typedef struct amazon_clreoc_pkt{
struct list_head list;
u8 * command; //point to clreoc command data
int len; //command length
}amazon_clreoc_pkt;
// Number of intervals
#define INTERVAL_NUM 192 //two days
typedef struct amazon_mei_mib{
struct list_head list;
struct timeval start_time; //start of current interval
int AtucPerfLof;
int AtucPerfLos;
int AtucPerfEs;
int AtucPerfInit;
int AturPerfLof;
int AturPerfLos;
int AturPerfLpr;
int AturPerfEs;
int AturChanPerfRxBlk;
int AturChanPerfTxBlk;
int AturChanPerfCorrBlk;
int AturChanPerfUncorrBlk;
//RFC-3440
int AtucPerfStatFastR;
int AtucPerfStatFailedFastR;
int AtucPerfStatSesL;
int AtucPerfStatUasL;
int AturPerfStatSesL;
int AturPerfStatUasL;
}amazon_mei_mib;
typedef struct adslChanPrevTxRate{
u32 adslAtucChanPrevTxRate;
u32 adslAturChanPrevTxRate;
}adslChanPrevTxRate;
typedef struct adslPhysCurrStatus{
u32 adslAtucCurrStatus;
u32 adslAturCurrStatus;
}adslPhysCurrStatus;
typedef struct ChanType{
int interleave;
int fast;
// 603221:tc.chen start
int bearchannel0;
int bearchannel1;
// 603221:tc.chen end
}ChanType;
typedef struct mib_previous_read{
u16 ATUC_PERF_ESS;
u16 ATUR_PERF_ESS;
u32 ATUR_CHAN_RECV_BLK;
u16 ATUR_CHAN_CORR_BLK_INTL;
u16 ATUR_CHAN_CORR_BLK_FAST;
u16 ATUR_CHAN_UNCORR_BLK_INTL;
u16 ATUR_CHAN_UNCORR_BLK_FAST;
u16 ATUC_PERF_STAT_FASTR;
u16 ATUC_PERF_STAT_FAILED_FASTR;
u16 ATUC_PERF_STAT_SESL;
u16 ATUC_PERF_STAT_UASL;
u16 ATUR_PERF_STAT_SESL;
}mib_previous_read;
typedef struct mib_flags_pretime{
struct timeval ATUC_PERF_LOSS_PTIME;
struct timeval ATUC_PERF_LOFS_PTIME;
struct timeval ATUR_PERF_LOSS_PTIME;
struct timeval ATUR_PERF_LOFS_PTIME;
struct timeval ATUR_PERF_LPR_PTIME;
}mib_flags_pretime;
// cmv message structures
#define MP_PAYLOAD_SIZE 12
typedef struct mpmessage{
u16 iFunction;
u16 iGroup;
u16 iAddress;
u16 iIndex;
u16 iPayload[MP_PAYLOAD_SIZE];
}MPMessage;
#endif
typedef struct meireg{
u32 iAddress;
u32 iData;
}meireg;
#define MEIDEBUG_BUFFER_SIZES 50
typedef struct meidebug{
u32 iAddress;
u32 iCount;
u32 buffer[MEIDEBUG_BUFFER_SIZES];
}meidebug;
//==============================================================================
// Group definitions
//==============================================================================
#define OPTN 5
#define CNFG 8
#define CNTL 1
#define STAT 2
#define RATE 6
#define PLAM 7
#define INFO 3
#define TEST 4
//==============================================================================
// Opcode definitions
//==============================================================================
#define H2D_CMV_READ 0x00
#define H2D_CMV_WRITE 0x04
#define H2D_CMV_INDICATE_REPLY 0x10
#define H2D_ERROR_OPCODE_UNKNOWN 0x20
#define H2D_ERROR_CMV_UNKNOWN 0x30
#define D2H_CMV_READ_REPLY 0x01
#define D2H_CMV_WRITE_REPLY 0x05
#define D2H_CMV_INDICATE 0x11
#define D2H_ERROR_OPCODE_UNKNOWN 0x21
#define D2H_ERROR_CMV_UNKNOWN 0x31
#define D2H_ERROR_CMV_READ_NOT_AVAILABLE 0x41
#define D2H_ERROR_CMV_WRITE_ONLY 0x51
#define D2H_ERROR_CMV_READ_ONLY 0x61
#define H2D_DEBUG_READ_DM 0x02
#define H2D_DEBUG_READ_PM 0x06
#define H2D_DEBUG_WRITE_DM 0x0a
#define H2D_DEBUG_WRITE_PM 0x0e
#define D2H_DEBUG_READ_DM_REPLY 0x03
#define D2H_DEBUG_READ_FM_REPLY 0x07
#define D2H_DEBUG_WRITE_DM_REPLY 0x0b
#define D2H_DEBUG_WRITE_FM_REPLY 0x0f
#define D2H_ERROR_ADDR_UNKNOWN 0x33
#define D2H_AUTONOMOUS_MODEM_READY_MSG 0xf1
//==============================================================================
// INFO register address field definitions
//==============================================================================
#define INFO_TxState 0
#define INFO_RxState 1
#define INFO_TxNextState 2
#define INFO_RxNextState 3
#define INFO_TxStateJumpFrom 4
#define INFO_RxStateJumpFrom 5
#define INFO_ReverbSnrBuf 8
#define INFO_ReverbEchoSnrBuf 9
#define INFO_MedleySnrBuf 10
#define INFO_RxShowtimeSnrBuf 11
#define INFO_DECdelay 12
#define INFO_DECExponent 13
#define INFO_DECTaps 14
#define INFO_AECdelay 15
#define INFO_AECExponent 16
#define INFO_AECTaps 17
#define INFO_TDQExponent 18
#define INFO_TDQTaps 19
#define INFO_FDQExponent 20
#define INFO_FDQTaps 21
#define INFO_USBat 22
#define INFO_DSBat 23
#define INFO_USFineGains 24
#define INFO_DSFineGains 25
#define INFO_BitloadFirstChannel 26
#define INFO_BitloadLastChannel 27
#define INFO_PollEOCData 28 // CO specific
#define INFO_CSNRMargin 29 // CO specific
#define INFO_RCMsgs1 30
#define INFO_RMsgs1 31
#define INFO_RMsgRA 32
#define INFO_RCMsgRA 33
#define INFO_RMsg2 34
#define INFO_RCMsg2 35
#define INFO_BitLoadOK 36
#define INFO_RCRates1 37
#define INFO_RRates1Tab 38
#define INFO_RMsgs1Tab 39
#define INFO_RMsgRATab 40
#define INFO_RRatesRA 41
#define INFO_RCRatesRA 42
#define INFO_RRates2 43
#define INFO_RCRates2 44
#define INFO_PackedRMsg2 45
#define INFO_RxBitSwapFlag 46
#define INFO_TxBitSwapFlag 47
#define INFO_ShowtimeSNRUpdateCount 48
#define INFO_ShowtimeFDQUpdateCount 49
#define INFO_ShowtimeDECUpdateCount 50
#define INFO_CopyRxBuffer 51
#define INFO_RxToneBuf 52
#define INFO_TxToneBuf 53
#define INFO_Version 54
#define INFO_TimeStamp 55
#define INFO_feVendorID 56
#define INFO_feSerialNum 57
#define INFO_feVersionNum 58
#define INFO_BulkMemory 59 //Points to start of bulk memory
#define INFO_neVendorID 60
#define INFO_neVersionNum 61
#define INFO_neSerialNum 62
//==============================================================================
// RATE register address field definitions
//==============================================================================
#define RATE_UsRate 0
#define RATE_DsRate 1
//==============================================================================
// PLAM (Physical Layer Management) register address field definitions
// (See G997.1 for reference)
//==============================================================================
// ///
// Failure Flags ///
// ///
#define PLAM_NearEndFailureFlags 0
#define PLAM_FarEndFailureFlags 1
// ///
// Near End Failure Flags Bit Definitions ///
// ///
// ADSL Failures ///
#define PLAM_LOS_FailureBit 0x0001
#define PLAM_LOF_FailureBit 0x0002
#define PLAM_LPR_FailureBit 0x0004
#define PLAM_RFI_FailureBit 0x0008
// ATM Failures ///
#define PLAM_NCD_LP0_FailureBit 0x0010
#define PLAM_NCD_LP1_FailureBit 0x0020
#define PLAM_LCD_LP0_FailureBit 0x0040
#define PLAM_LCD_LP1_FailureBit 0x0080
#define PLAM_NCD_BC0_FailureBit 0x0100
#define PLAM_NCD_BC1_FailureBit 0x0200
#define PLAM_LCD_BC0_FailureBit 0x0400
#define PLAM_LCD_BC1_FailureBit 0x0800
// ///
// Performance Counts ///
// ///
#define PLAM_NearEndCrcCnt 2
#define PLAM_CorrectedRSErrors 3
#define PLAM_NearEndECSCnt 6
#define PLAM_NearEndESCnt 7
#define PLAM_NearEndSESCnt 8
#define PLAM_NearEndLOSSCnt 9
#define PLAM_NearEndUASLCnt 10
#define PLAM_NearEndHECErrCnt 11
#define PLAM_NearEndHECTotCnt 16
#define PLAM_NearEndCellTotCnt 18
#define PLAM_NearEndSfCntLSW 20
#define PLAM_NearEndSfCntMSW 21
#define PLAM_FarEndFebeCnt 24
#define PLAM_FarEndFecCnt 28
#define PLAM_FarEndFECSCnt 32
#define PLAM_FarEndESCnt 33
#define PLAM_FarEndSESCnt 34
#define PLAM_FarEndLOSSCnt 35
#define PLAM_FarEndUASLCnt 36
#define PLAM_FarEndHECErrCnt 37
#define PLAM_FarEndHECTotCnt 41
#define PLAM_FarEndCellTotCnt 43
#define PLAM_LineAttn 45
#define PLAM_SNRMargin 46
//==============================================================================
// CNTL register address and bit field definitions
//==============================================================================
#define CNTL_ModemControl 0
#define CNTL_ModemReset 0x0
#define CNTL_ModemStart 0x2
//==============================================================================
// STAT register address and bit field definitions
//==============================================================================
#define STAT_MacroState 0
#define STAT_Mode 1
#define STAT_DMTFramingMode 2
#define STAT_SleepState 3
#define STAT_Misc 4
#define STAT_FailureState 5
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// STAT_OLRStatus provides status of OLR
//16-bit STAT_OLRStatus_DS
// [1:0] : OLR status 00=IDLE, 01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted
// [3:2]: Reserved
// [5:4]: OLR_Type (1:bitswap; 2: DRR; 3: SRA)
// [7:6]: Reserved
// [10:8]: >0=Request. 0=not. For DS, # of request transmissions/retransmissions (3 bits).
// [11]: 1=Receive Response, 0=not
// [15:12]: Reserved
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///
#define STAT_OLRStatus_DS 6
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// STAT_OLRStatus provides status of OLR
// 16-bit STAT_OLRStatus_US CMV
// [1:0] : OLR status 00=IDLE, 01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted
// [3:2]: Reserved
// [5:4]: OLR_Type (1:bitswap; 2: DRR; 3: SRA)
// [7:6]: Reserved
// [8]: 1=Request Received. 0=not.
// [10:9]: Reserved
// [11]: 1=Response Sent, 0=not
// [15:12]: Reserved
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///
#define STAT_OLRStatus_US 7
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// STAT_PMStatus provides status of PM
// 16-bit STAT_PMStatus CMV
// [1:0] : PM Status 00=IDLE, 01=PM_IN_PROGRESS, 10=PM_Completed, 11=PM_Aborted
// [2] : 0=ATU_R initiated PM; 1 = ATU_C initiated PM
// [3]: Reserved
// [5:4]: PM_Type (1:Simple Request; 2: L2 request; 3: L2 trim)
// [7:6]: Reserved
// [10:8]: >0=Request. 0=not. # of request transmissions/retransmissions (3 bits).
// [11]: 1=Response, 0=not
// [15:12]: Reserved
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///
#define STAT_PMStatus 8
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// 16-bit STAT_OLRError_DS, STAT_OLRError_US, STAT_PMError
// [3:0]: OLR/PM response reason code
// [7:4]: OLR/PM Internal error code
// [15:8]: OLR/PM Reserved for future
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///
#define STAT_OLRError_DS 9
#define STAT_OLRError_US 10
#define STAT_PMError 11
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// STAT_MacroState
// MacroState reflects the high level state of the modem
#define STAT_InitState 0x0000
#define STAT_ReadyState 0x0001
#define STAT_FailState 0x0002
#define STAT_IdleState 0x0003
#define STAT_QuietState 0x0004
#define STAT_GhsState 0x0005
#define STAT_FullInitState 0x0006
#define STAT_ShowTimeState 0x0007
#define STAT_FastRetrainState 0x0008
#define STAT_LoopDiagMode 0x0009
#define STAT_ShortInit 0x000A // Bis short initialization ///
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// STAT_Mode
// ConfigurationMode indicates the mode of the current ADSL Link. In general, a modem may use
// G.Hs or some other mechanism to negotiate the specific mode of operation.
// The OPTN_modeControl CMV is used to select a set of desired modes.
// The STAT_Mode CMV indicates which mode was actually selected.
#define STAT_ConfigMode_T1413 0x0001
#define STAT_ConfigMode_G992_2_AB 0x0002
#define STAT_ConfigMode_G992_1_A 0x0004
#define STAT_ConfigMode_G992_1_B 0x0008
#define STAT_ConfigMode_G992_1_C 0x0010
#define STAT_ConfigMode_G992_2_C 0x0020
#define STAT_ConfigMode_G992_3_A 0x0100
#define STAT_ConfigMode_G992_3_B 0x0200
#define STAT_ConfigMode_G992_3_I 0x0400
#define STAT_ConfigMode_G992_3_J 0x0800
#define STAT_ConfigMode_G992_3_L 0x1000
#define STAT_ConfigMode_G992_4_A 0x2000
#define STAT_ConfigMode_G992_4_I 0x4000
#define STAT_ConfigMode_G992_5 0x8000
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// STAT_DMTFramingMode
// FramingMode indicates the DMT framing mde negotiated during initialization. The framing mode
// status is not applicable in BIS mode and its value is undefined
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#define STAT_FramingModeMask 0x0003
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// STAT_Misc
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#define STAT_OverlappedSpectrum 0x0008
#define STAT_TCM 0x0010
#define STAT_TDQ_at_1104 0x0020
#define STAT_T1413_Signal_Detected 0x0040
#define STAT_AnnexL_US_Mask1_PSD 0x1000 //indicate we actually selected G992.3 AnnexL US PSD mask1
#define STAT_AnnexL_US_Mask2_PSD 0x2000 //indicate we actually selected G992.3 AnnexL US PSD mask2
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// STAT_FailureState
// when the MacroSTate indicates the fail state, FailureState provides a failure code
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#define E_CODE_NO_ERROR 0
#define E_CODE_BAT_TX 1 // TX BAT table is incorrect */
#define E_CODE_BAT_RX 2 // RX BAT table is incorrect */
#define E_CODE_PROFILE 3 // profile is not selected in fast retrain */
#define E_CODE_TX_AOC_FIFO_OVERFLOW 4
#define E_CODE_TRUNCATE_FR 5 //Fast Retrain truncated due to no stored profiles*/
#define E_CODE_BITLOAD 6 // bit loading fails */
#define E_CODE_ST_ERROR 7 // showtime CRC error */
#define E_CODE_RESERVED 8 // using parameters reserved by the ITU-T */
#define E_CODE_C_TONES 9 // detected C_TONES */
#define E_CODE_CODESWAP_ERR 10 // codeswap not finished in time */
#define E_CODE_FIFO_OVERFLOW 11 // we have run out of fifo space */
#define E_CODE_C_BG_DECODE_ERR 12 // error in decoding C-BG message */
#define E_CODE_C_RATES2_DECODE_ERR 13 // error in decoding C-MSGS2 and C-RATES2 */
#define E_CODE_RCMedleyRx_C_SEGUE2_Failure 14 // Timeout after RCMedleyRx waiting for C_SEGUE2 */
#define E_CODE_RReverbRATx_C_SEGUE2_Failure 15 // Timeout after RReverbRATx waiting for C_SEGUE2 */
#define E_CODE_RReverb3Tx_C_SEGUE1_Failure 16 // Timeout after RReverb3Tx waiting for C_SEGUE1 */
#define E_CODE_RCCRC2Rx_C_RATES1_DECOD_ERR 17 // Received CRC not equal to computed CRC */
#define E_CODE_RCCRC1Rx_C_RATES1_DECOD_ERR 18 // Received CRC not equal to computed CRC */
#define E_CODE_RReverb5Tx_C_SEGUE2_Failure 19 // Timeout after RReverb5Tx waiting for C_SEGUE2 */
#define E_CODE_RReverb6Tx_C_SEGUE3_Failure 20 // Timeout after RReverb6Tx waiting for C_SEGUE3 */
#define E_CODE_RSegue5Tx_C_SEGUE3_Failure 21 // Timeout after RSegue5Tx waiting for C_SEGUE3 */
#define E_CODE_RCReverb5Rx_C_SEGUE_Failure 22 // Timeout after RCReverb5Rx waiting for C_SEGUE */
#define E_CODE_RCReverbRARx_C_SEGUE2_Failure 23 // Timeout after RCReverbRARx waiting for C_SEGUE2 */
#define E_CODE_RCCRC4Rx_CMSGS2_DECOD_ERR 24 // Received CRC not equal to computed CRC */
#define E_CODE_RCCRC5Rx_C_BG_DECOD_ERR 25 // Received CRC not equal to computed CRC */
#define E_CODE_RCCRC3Rx_DECOD_ERR 26 // Received CRC not equal to computed CRC */
#define E_CODE_RCPilot3_DEC_PATH_DEL_TIMEOUT 27 // DEC Path Delay timeout */
#define E_CODE_RCPilot3_DEC_TRAINING_TIMEOUT 28 // DEC Training timeout */
#define E_CODE_RCReverb3Rx_C_SEGUE1_Failure 29 // Timeout after RCReverb3Rx waiting for C_SEGUE1 */
#define E_CODE_RCReverb2Rx_SignalEnd_Failure 30 // Timeout waiting for the end of RCReverb2Rx signal */
#define E_CODE_RQuiet2_SignalEnd_Failure 31 // Timeout waiting for the end of RQuiet2 signal */
#define E_CODE_RCReverbFR1Rx_Failure 32 // Timeout waiting for the end of RCReverbFR1Rx signal */
#define E_CODE_RCPilotFR1Rx_SignalEnd_Failure 33 // Timeout waiting for the end of RCPilotFR1Rx signal */
#define E_CODE_RCReverbFR2Rx_C_Segue_Failure 34 // Timeout after RCReverbFR2Rx waiting for C_SEGUE */
#define E_CODE_RCReverbFR5Rx_SignalEnd_TIMEOUT 35 // Timeout waiting for the end of RCReverbFR5Rx signal */
#define E_CODE_RCReverbFR6Rx_C_SEGUE_Failure 36 // Timeout after RCReverbFR6Rx waiting for C_SEGUE */
#define E_CODE_RCReverbFR8Rx_C_SEGUE_FR4_Failure 37 // Timeout after RCReverbFR8Rx waiting for C_SEGUE_FR4 */
#define E_CODE_RCReverbFR8Rx_No_PROFILE 38 // Timeout since no profile was selected */
#define E_CODE_RCReverbFR8Rx_SignalEnd_TIMEOUT 39 // Timeout waiting for the end of RCReverbFR8Rx signal */
#define E_CODE_RCCRCFR1_DECOD_ERR 40 // Received CRC not equal to computed CRC */
#define E_CODE_RCRecovRx_SingnalEnd_TIMEOUT 41 // Timeout waiting for the end of RCRecovRx signal */
#define E_CODE_RSegueFR5Tx_TX_Not_Ready_TIMEOUT 42 // Timeout after RSegueFR5Tx waiting for C_SEGUE2 */
#define E_CODE_RRecovTx_SignalEnd_TIMEOUT 43 // Timeout waiting for the end of RRecovTx signal */
#define E_CODE_RCMedleyFRRx_C_SEGUE2_Failure 44 // Timeout after RCMedleyFRRx waiting for C_SEGUE2 */
#define E_CODE_CONFIGURATION_PARAMETERS_ERROR 45 // one of the configuration parameters do not meet the standard */
#define E_CODE_BAD_MEM_ACCESS 46
#define E_CODE_BAD_INSTRUCTION_ACCESS 47
#define E_CODE_TX_EOC_FIFO_OVERFLOW 48
#define E_CODE_RX_EOC_FIFO_OVERFLOW 49
#define E_CODE_GHS_CD_FLAG_TIME_OUT 50 // Timeout when transmitting Flag in handshake cleardown */
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//STAT_OLRStatus:
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#define STAT_OLRPM_IDLE 0x0000
#define STAT_OLRPM_IN_PROGRESS 0x0001
#define STAT_OLRPM_COMPLETE 0x0002
#define STAT_OLRPM_ABORTED 0x0003
#define STAT_OLRPM_RESPONSE 0x0800
#define STAT_OLR_BITSWAP 0x0010
#define STAT_OLR_DRR 0x0020
#define STAT_OLR_SRA 0x0030
//STAT_PMStatus_US:
#define STAT_PM_CO_REQ 0x0004
#define STAT_PM_SIMPLE_REQ 0x0010
#define STAT_PM_L2_REQ 0x0020
#define STAT_PM_L2_TRIM_REQ 0x0030
// STAT_OLRError_DS, STAT_OLRError_US
//4 bit response reason code:
#define RESP_BUSY 0x01
#define RESP_INVALID_PARAMETERS 0x02
#define RESP_NOT_ENABLED 0x03
#define RESP_NOT_SUPPORTED 0x04
//4 bit internal error code (common for OLR and PM)
#define REQ_INVALID_BiGi 0x10
#define REQ_INVALID_Lp 0x20
#define REQ_INVALID_Bpn 0x30
#define REQ_INVALID_FRAMING_CONSTRAINT 0x40
#define REQ_NOT_IN_L0_STATE 0x50
#define REQ_NOT_IN_L2_STATE 0x60
#define REQ_INVALID_PCB 0x70
#define REQ_VIOLATES_MARGIN 0x80
//STAT_PMError
//4 bit response reason code:
#define RESP_STATE_NOT_DESIRED 0x03
#define RESP_INFEASIBLE_PARAMETERS 0x04
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// OPTN register address and bit field definitions
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#define OPTN_ModeControl 0
#define OPTN_DMTLnkCtl 1
// Reserved 2
#define OPTN_GhsControl 3
// Reserved 4
#define OPTN_PwrManControl 5
#define OPTN_AnnexControl 6
#define OPTN_ModeControl1 7
// Reserved 8
#define OPTN_StateMachineCtrl 9
// Reserved 10
// Reserved 11
#define OPTN_BisLinkControl 12
#define OPTN_ATMAddrConfig 13
#define OPTN_ATMNumCellConfig 14
// Mode control defines the allowable operating modes of an ADSL link. In general, a modem may ///
// use G.Hs or some other mechanism to negotiate the specific mode of operation. ///
// The OPTN_ModeControl CMV is used to select a set of desired modes ///
// The STAT_ModeControl CMV indicates which mode was actually selected ///
// OPTN_ModeControl
#define OPTN_ConfigMode_T1413 0x0001
#define OPTN_ConfigMode_G992_2_AB 0x0002
#define OPTN_ConfigMode_G992_1_A 0x0004
#define OPTN_ConfigMode_G992_1_B 0x0008
#define OPTN_ConfigMode_G992_1_C 0x0010
#define OPTN_ConfigMode_G992_2_C 0x0020
#define OPTN_ConfigMode_G992_3_A 0x0100
#define OPTN_ConfigMode_G992_3_B 0x0200
#define OPTN_ConfigMode_G992_3_I 0x0400
#define OPTN_ConfigMode_G992_3_J 0x0800
#define OPTN_ConfigMode_G992_3_L 0x1000
#define OPTN_ConfigMode_G992_4_A 0x2000
#define OPTN_ConfigMode_G992_4_I 0x4000
#define OPTN_ConfigMode_G992_5 0x8000
// OPTN_PwrManControl
#define OPTN_PwrManWakeUpGhs 0x1
#define OPTN_PwrManWakeUpFR 0x2
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// OPTN_DMT Link Control
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#define OPTN_DMT_DualLatency_Dis 0x200
#define OPTN_DMT_S_Dis 0x100
#define OPTN_DMT_FRAMINGMODE 0x1
#define OPTN_DMT_FRAMINGMODE_MASK 0x7
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// OPTN_BIS Link Control
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#define OPTN_BisLinkContrl_LineProbeDis 0x1
#define OPTN_BisLinkContrl_DSBlackBitsEn 0x2
#define OPTN_BisLinkContrl_DiagnosticModeEn 0x4
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// OPTN_GhsControl
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// for OPTN_GhsControl, we will assign 16bit word as follows
// bit 0~3: set the control over which start(initial) message CPE will send:
//
// BIT: 2 1 0
// 0 0 1 CLR
// 0 1 0 MR
// 0 1 1 MS
// 1 0 0 MP
//
// // bit 4~6: set the control over which message will be sent when we get at lease one CL/CLR exchange
// BIT: 5 4
// 0 1 MS
// 1 0 MR
// 1 1 MP
//
// // bit 15: RT initiated G.hs sample sessions one through eight. Session one is default.
// BIT: 15
// 1 means session one
//
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#define OPTN_GHS_ST_GHS 0x8000
#define OPTN_GHS_INIT_MASK 0x000F
#define OPTN_GHS_RESP_MASK 0x00F0
#define OPTN_RTInitTxMsg_CLR 0x0001
#define OPTN_RTInitTxMsg_MR 0x0002
#define OPTN_RTInitTxMsg_MS 0x0003
#define OPTN_RTInitTxMsg_MP 0x0004
#define OPTN_RTRespTxMsg_MS 0x0010
#define OPTN_RTRespTxMsg_MR 0x0020
#define OPTN_RTRespTxMsg_MP 0x0030
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// OPTN_AnnexControl
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// G.992.3 Annex A/L1/L2 US PSD Mask preferred
#define OPTN_G992_3_AnnexA_PreferredModeMask 0x3000
#define OPTN_G992_3_AnnexA_PreferredModeA 0x0000 // default AnnexA PSD mask ///
#define OPTN_G992_3_AnnexA_PreferredModeL1 0x1000 // AnnexL wide spectrum upstream PSD mask ///
#define OPTN_G992_3_AnnexA_PreferredModeL2 0x2000 // AnnexL narrow spectrum upstream PSD mask ///
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//OPTN_ATMAddrConfig
// Bits 4:0 are Utopia address for BC1
// Bits 9:5 are Utopia address for BC0
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#define OPTN_UTPADDR_BC1 0x001F
#define OPTN_UTPADDR_BC0 0x03E0
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//OPTN_ATMNumCellConfig
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#define OPTN_BC1_NUM_CELL_PAGES 0x000F // Bits 0:3 ///
#define OPTN_BC0_NUM_CELL_PAGES 0x00F0 // Bits 4:7 ///
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// CNFG register address field ///
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////
// these cmvs are used by bis handshake ///
///////////////////////////////////////////
// Each of the CNFG_TPS entries points to a structure of type (TPS_TC_BearerChannel_t)
#define CNFG_TPS_TC_DS0 0
#define CNFG_TPS_TC_DS1 1
#define CNFG_TPS_TC_US0 2
#define CNFG_TPS_TC_US1 3
#define CNFG_HDLC_Overhead_Requirements 4
// Each of the CNFG_PMS entries points to a structure of type (PMS_TC_LatencyPath_t)
#define CNFG_PMS_TC_DS0 5
#define CNFG_PMS_TC_DS1 6
#define CNFG_PMS_TC_US0 7
#define CNFG_PMS_TC_US1 8
// CNFG_PMD_PARAMETERS points to a structure of type (PMD_params_t)
#define CNFG_PMD_PARAMETERS 9
////////////////////////////////////////////////////////////
// these cmvs are used by bis training and showtime code ///
////////////////////////////////////////////////////////////
////////////////
// Tx Config ///
////////////////
#define CNFG_tx_Cnfg_Nbc 10
#define CNFG_tx_Cnfg_Nlp 11
#define CNFG_tx_Cnfg_Rp 12
#define CNFG_tx_Cnfg_Mp 13
#define CNFG_tx_Cnfg_Lp 14
#define CNFG_tx_Cnfg_Tp 15
#define CNFG_tx_Cnfg_Dp 16
#define CNFG_tx_Cnfg_Bpn 17
#define CNFG_tx_Cnfg_FramingMode 18
#define CNFG_tx_Cnfg_MSGLp 19
#define CNFG_tx_Cnfg_MSGc 20
////////////////
// Rx Config ///
////////////////
#define CNFG_rx_Cnfg_Nbc 21
#define CNFG_rx_Cnfg_Nlp 22
#define CNFG_rx_Cnfg_Rp 23
#define CNFG_rx_Cnfg_Mp 24
#define CNFG_rx_Cnfg_Lp 25
#define CNFG_rx_Cnfg_Tp 26
#define CNFG_rx_Cnfg_Dp 27
#define CNFG_rx_Cnfg_Bpn 28
#define CNFG_rx_Cnfg_FramingMode 29
#define CNFG_rx_Cnfg_MSGLp 30
#define CNFG_rx_Cnfg_MSGc 31
#define CNFG_tx_Cnfg_BCnToLPp 32
#define CNFG_rx_Cnfg_BCnToLPp 33
#endif

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#ifndef AMAZON_SW_H
#define AMAZON_SW_H
#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE
#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1
#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2
#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3
#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4
#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5
#define SET_ETH_REG SIOCDEVPRIVATE+6
#define VLAN_TOOLS SIOCDEVPRIVATE+7
#define MAC_TABLE_TOOLS SIOCDEVPRIVATE+8
/*===mac table commands==*/
#define RESET_MAC_TABLE 0
#define READ_MAC_ENTRY 1
#define WRITE_MAC_ENTRY 2
#define ADD_MAC_ENTRY 3
/*====vlan commands===*/
#define CHANGE_VLAN_CTRL 0
#define READ_VLAN_ENTRY 1
#define UPDATE_VLAN_ENTRY 2
#define CLEAR_VLAN_ENTRY 3
#define RESET_VLAN_TABLE 4
#define ADD_VLAN_ENTRY 5
/*
** MDIO constants.
*/
#define MDIO_BASE_STATUS_REG 0x1
#define MDIO_BASE_CONTROL_REG 0x0
#define MDIO_PHY_ID_HIGH_REG 0x2
#define MDIO_PHY_ID_LOW_REG 0x3
#define MDIO_BC_NEGOTIATE 0x0200
#define MDIO_BC_FULL_DUPLEX_MASK 0x0100
#define MDIO_BC_AUTO_NEG_MASK 0x1000
#define MDIO_BC_SPEED_SELECT_MASK 0x2000
#define MDIO_STATUS_100_FD 0x4000
#define MDIO_STATUS_100_HD 0x2000
#define MDIO_STATUS_10_FD 0x1000
#define MDIO_STATUS_10_HD 0x0800
#define MDIO_STATUS_SPEED_DUPLEX_MASK 0x7800
#define MDIO_ADVERTISMENT_REG 0x4
#define MDIO_ADVERT_100_FD 0x100
#define MDIO_ADVERT_100_HD 0x080
#define MDIO_ADVERT_10_FD 0x040
#define MDIO_ADVERT_10_HD 0x020
#define MDIO_LINK_UP_MASK 0x4
#define MDIO_START 0x1
#define MDIO_READ 0x2
#define MDIO_WRITE 0x1
#define MDIO_PREAMBLE 0xfffffffful
#define PHY_RESET 0x8000
#define AUTO_NEGOTIATION_ENABLE 0X1000
#define AUTO_NEGOTIATION_COMPLETE 0x20
#define RESTART_AUTO_NEGOTIATION 0X200
#define PHY0_ADDR 0
#define PHY1_ADDR 1
#define P1M 0
#define AMAZON_SW_REG32(reg_num) *((volatile u32*)(reg_num))
#define OK 0;
#ifdef CONFIG_CPU_LITTLE_ENDIAN
typedef struct mac_table_entry{
u64 mac_address:48;
u64 p0:1;
u64 p1:1;
u64 p2:1;
u64 cr:1;
u64 ma_st:3;
u64 res:9;
}_mac_table_entry;
typedef struct IFX_Switch_VLanTableEntry{
u32 vlan_id:12;
u32 mp0:1;
u32 mp1:1;
u32 mp2:1;
u32 v:1;
u32 res:16;
}_IFX_Switch_VLanTableEntry;
typedef struct mac_table_req{
int cmd;
int index;
u32 data;
u64 entry_value;
}_mac_table_req;
#else //not CONFIG_CPU_LITTLE_ENDIAN
typedef struct mac_table_entry{
u64 mac_address:48;
u64 p0:1;
u64 p1:1;
u64 p2:1;
u64 cr:1;
u64 ma_st:3;
u64 res:9;
}_mac_table_entry;
typedef struct IFX_Switch_VLanTableEntry{
u32 vlan_id:12;
u32 mp0:1;
u32 mp1:1;
u32 mp2:1;
u32 v:1;
u32 res:16;
}_IFX_Switch_VLanTableEntry;
typedef struct mac_table_req{
int cmd;
int index;
u32 data;
u64 entry_value;
}_mac_table_req;
#endif //CONFIG_CPU_LITTLE_ENDIAN
typedef struct vlan_req{
int cmd;
int index;
u32 data;
u32 entry_value;
}_vlan_req;
typedef struct data_req{
int index;
u32 value;
}_data_req;
enum duplex
{
half,
full,
autoneg
};
struct switch_priv {
struct net_device_stats stats;
int rx_packetlen;
u8 *rx_packetdata;
int rx_status;
int tx_packetlen;
#ifdef CONFIG_NET_HW_FLOWCONTROL
int fc_bit;
#endif //CONFIG_NET_HW_FLOWCONTROL
u8 *tx_packetdata;
int tx_status;
struct dma_device_info *dma_device;
struct sk_buff *skb;
spinlock_t lock;
int mdio_phy_addr;
int current_speed;
int current_speed_selection;
int rx_queue_len;
int full_duplex;
enum duplex current_duplex;
};
#endif //AMAZON_SW_H

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#ifndef AMAZON_TPE_H
#define AMAZON_TPE_H
#include <linux/atm.h>
#include <linux/atmdev.h>
#include <linux/netdevice.h>
#include <linux/ioctl.h>
#ifdef CONFIG_IFX_ATM_MIB
/* For ATM-MIB lists */
#include <linux/list.h>
#endif
#include <asm/amazon/atm_mib.h>
/* CBM Queue arranagement
* Q0: free cells pool
* Q1~ Q15: upstream queues
* Q16: QAM downstream
* Q17~Q31: downstream queues
*/
#define AMAZON_ATM_MAX_QUEUE_NUM 32
#define AMAZON_ATM_PORT_NUM 2
#define AMAZON_ATM_FREE_CELLS 4000
#define AMAZON_ATM_MAX_VCC_NUM (AMAZON_ATM_MAX_QUEUE_NUM/2 - 1)
#define AMAZON_AAL0_SDU (ATM_AAL0_SDU+4) //one more word for status
#define CBM_RX_OFFSET 16 //offset from the same q for tx
#define AMAZON_ATM_OAM_Q_ID 16
#define AMAZON_ATM_RM_Q_ID 16
#define AMAZON_ATM_OTHER_Q_ID 16
#define CBM_DEFAULT_Q_OFFSET 1
#define HTUTIMEOUT 0xffff//timeoutofhtutocbm
#define QSB_WFQ_NONUBR_MAX 0x3f00
#define QSB_WFQ_UBR_BYPASS 0x3fff
#define QSB_TP_TS_MAX 65472
#define QSB_TAUS_MAX 64512
#define QSB_GCR_MIN 18
#define HTU_RAM_ACCESS_MAX 1024//maxium time for HTU RAM access
#define SWIE_LOCK 1
#define PROC_ATM 1
#define PROC_MIB 2
#define PROC_VCC 3
#define PROC_AAL5 4
#define PROC_CBM 5
#define PROC_HTU 6
#define PROC_QSB 7
#define PROC_SWIE 8
/***************** internal data structure ********************/
typedef int (*push_back_t)(struct atm_vcc *vcc,struct sk_buff *skb,int err) ;
/* Device private data */
typedef struct{
u8 padding_byte;
u32 tx_max_sdu;
u32 rx_max_sdu;
u32 cnt_cpy; //no. of packets that need a copy due to alignment
}amazon_aal5_dev_t;
typedef struct{
u32 max_q_off; //maxium queues used in real scenario
u32 nrt_thr;
u32 clp0_thr;
u32 clp1_thr;
u32 free_cell_cnt;
#ifdef CONFIG_USE_VENUS
u8 * qd_addr_free; //to work around a bug, bit15 of QDOFF address should be 1
#endif
u8 * qd_addr;
u8 * mem_addr;
u8 allocated;
}amazon_cbm_dev_t;
typedef struct{
}amazon_htu_dev_t;
typedef struct{
u32 tau; //cell delay variation due to concurrency(?)
u32 tstepc; //time step, all legal values are 1,2,4
u32 sbl; //scheduler burse length (for PHY)
}amazon_qsb_dev_t;
typedef struct{
u32 qid; //QID of the current extraction queue
struct semaphore in_sem; // Software-Insertion semaphore
volatile long lock; //lock that avoids race contions between SWIN and SWEX
wait_queue_head_t sleep; //wait queue for SWIE and SWEX
u32 sw; //status word
}amazon_swie_dev_t;
//AAL5 MIB Counter
typedef struct{
u32 tx,rx; //number AAL5 CPCS PDU from/to higher-layer
u32 tx_err,rx_err; //ifInErrors and ifOutErros
u32 tx_drop,rx_drop; //discarded received packets due to mm shortage
u32 htu_unp; //number of unknown received cells
u32 rx_cnt_h; //number of octets received, high 32 bits
u32 rx_cnt_l; //number of octets received, low 32 bits
u32 tx_cnt_h; //number of octets transmitted, high 32 bits
u32 tx_cnt_l; //number of octets transmitted, low 32 bits
u32 tx_ppd; //number of cells for AAL5 upstream PPD discards
u64 rx_cells; //number of cells for downstream
u64 tx_cells; //number of cells for upstream
u32 rx_err_cells; //number of cells dropped due to uncorrectable HEC errors
}amazon_mib_counter_t;
typedef enum {QS_PKT,QS_LEN,QS_ERR,QS_HW_DROP,QS_SW_DROP,QS_MAX} qs_t;
//queue statics no. of packet received / sent
//queue statics no. of bytes received / sent
//queue statics no. of packets with error
//queue statics no. of packets dropped by hw
//queue statics no. of packets dropped by sw
typedef struct{
push_back_t push; //call back function
struct atm_vcc * vcc; //opened vcc
struct timeval access_time; //time when last F4/F5 user cells arrive
int free; //whether this queue is occupied, 0: occupied, 1: free
u32 aal5VccCrcErrors; //MIB counter
u32 aal5VccOverSizedSDUs; //MIB counter
#if defined(AMAZON_ATM_DEBUG) || defined (CONFIG_IFX_ATM_MIB)
u32 qs[QS_MAX];
#endif
}amazon_atm_queue_t;
typedef struct{
int enable; //enable / disable
u32 max_conn; //maximum number of connections per port
u32 tx_max_cr; //Remaining cellrate for this device for tx direction
u32 tx_rem_cr; //Remaining cellrate for this device for tx direction
u32 tx_cur_cr; //Current cellrate for this device for tx direction
}amazon_atm_port_t;
typedef struct{
amazon_aal5_dev_t aal5;
amazon_cbm_dev_t cbm;
amazon_htu_dev_t htu;
amazon_qsb_dev_t qsb;
amazon_swie_dev_t swie;
amazon_mib_counter_t mib_counter;
amazon_atm_queue_t queues[AMAZON_ATM_MAX_QUEUE_NUM];
amazon_atm_port_t ports[AMAZON_ATM_PORT_NUM];
atomic_t dma_tx_free_0;//TX_CH0 has availabe descriptors
} amazon_atm_dev_t;
struct oam_last_activity{
u8 vpi; //vpi for this connection
u16 vci; //vci for t his connection
struct timeval stamp; //time when last F4/F5 user cells arrive
struct oam_last_activity * next;//for link list purpose
};
typedef union{
#ifdef CONFIG_CPU_LITTLE_ENDIAN
struct{
u32 tprs :16;
u32 twfq :14;
u32 vbr :1;
u32 reserved :1;
}bit;
u32 w0;
#else
struct{
u32 reserved :1;
u32 vbr :1;
u32 twfq :14;
u32 tprs :16;
}bit;
u32 w0;
#endif
}qsb_qptl_t;
typedef union{
#ifdef CONFIG_CPU_LITTLE_ENDIAN
struct{
u32 ts :16;
u32 taus :16;
}bit;
u32 w0;
#else
struct{
u32 taus :16;
u32 ts :16;
}bit;
u32 w0;
#endif
}qsb_qvpt_t;
struct amazon_atm_cell_header {
#ifdef CONFIG_CPU_LITTLE_ENDIAN
struct{
u32 clp :1; // Cell Loss Priority
u32 pti :3; // Payload Type Identifier
u32 vci :16; // Virtual Channel Identifier
u32 vpi :8; // Vitual Path Identifier
u32 gfc :4; // Generic Flow Control
}bit;
#else
struct{
u32 gfc :4; // Generic Flow Control
u32 vpi :8; // Vitual Path Identifier
u32 vci :16; // Virtual Channel Identifier
u32 pti :3; // Payload Type Identifier
u32 clp :1; // Cell Loss Priority
}bit;
#endif
};
/************************ Function Declarations **************************/
amazon_atm_dev_t * amazon_atm_create(void);
int amazon_atm_open(struct atm_vcc *vcc,push_back_t);
int amazon_atm_send(struct atm_vcc *vcc,struct sk_buff *skb);
int amazon_atm_send_oam(struct atm_vcc *vcc,void *cell, int flags);
void amazon_atm_close(struct atm_vcc *vcc);
void amazon_atm_cleanup(void);
const struct oam_last_activity* get_oam_time_stamp(void);
//mib-related
int amazon_atm_cell_mib(atm_cell_ifEntry_t * to,u32 itf);
int amazon_atm_aal5_mib(atm_aal5_ifEntry_t * to);
int amazon_atm_vcc_mib(struct atm_vcc *vcc,atm_aal5_vcc_t * to);
int amazon_atm_vcc_mib_x(int vpi, int vci,atm_aal5_vcc_t* to);
#define AMAZON_WRITE_REGISTER_L(data,addr) do{ *((volatile u32*)(addr)) = (u32)(data); wmb();} while (0)
#define AMAZON_READ_REGISTER_L(addr) (*((volatile u32*)(addr)))
/******************************* ioctl stuff****************************************/
#define NUM(dev) (MINOR(dev) & 0xf)
/*
* Ioctl definitions
*/
/* Use 'o' as magic number */
#define AMAZON_ATM_IOC_MAGIC 'o'
/* MIB_CELL: get atm cell level mib counter
* MIB_AAL5: get aal5 mib counter
* MIB_VCC: get vcc mib counter
*/
typedef struct{
int vpi;
int vci;
atm_aal5_vcc_t mib_vcc;
}atm_aal5_vcc_x_t;
#define AMAZON_ATM_MIB_CELL _IOWR(AMAZON_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
#define AMAZON_ATM_MIB_AAL5 _IOWR(AMAZON_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
#define AMAZON_ATM_MIB_VCC _IOWR(AMAZON_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
#define AMAZON_ATM_IOC_MAXNR 3
//sockopt
#define SO_AMAZON_ATM_MIB_VCC __SO_ENCODE(SOL_ATM,5,atm_aal5_vcc_t)
#endif // AMAZON_TPE_H

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#ifndef AMAZON_WDT_H
#define AMAZON_WDT_H
#ifdef __KERNEL__
typedef struct wdt_dev{
char name[16];
int major;
int minor;
int full;
char buff[10];
}wdt_dev;
#define AMAZON_WDT_REG32(addr) (*((volatile u32*)(addr)))
#endif //__KERNEL__
//AMAZON_WDT_IOC_START: start the WDT timer (must provide a initial timeout value)
//AMAZON_WDT_IOC_STOP: stop the WDT
//AMAZON_WDT_IOC_PING: reload the timer to initial value (must happend after a AMAZON_WDT_IOC_START)
#define AMAZON_WDT_IOC_MAGIC 0xc0
#define AMAZON_WDT_IOC_START _IOW( AMAZON_WDT_IOC_MAGIC,0, int)
#define AMAZON_WDT_IOC_STOP _IO( AMAZON_WDT_IOC_MAGIC,1)
#define AMAZON_WDT_IOC_PING _IO( AMAZON_WDT_IOC_MAGIC,2)
#endif //AMAZON_WDT_H

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#ifndef ATM_DEFINES_H
#define ATM_DEFINES_H
//Registers Base Address
#define IO_BASE_ADDR 0xA0000000
#define AAL5_BASE_ADDRESS 0x10104400+IO_BASE_ADDR
#define CBM_BASE_ADDRESS 0x10104000+IO_BASE_ADDR
#define HTU_BASE_ADDRESS 0x10105100+IO_BASE_ADDR
#define QSB_BASE_ADDRESS 0x10105000+IO_BASE_ADDR
#define SWIE_BASE_ADDRESS 0x10105200+IO_BASE_ADDR
//AAL5 Registers
#define AAL5_SISR0_ADDR AAL5_BASE_ADDRESS+0x20
#define AAL5_SIMR0_ADDR AAL5_BASE_ADDRESS+0x24
#define AAL5_SISR1_ADDR AAL5_BASE_ADDRESS+0x28
#define AAL5_SIMR1_ADDR AAL5_BASE_ADDRESS+0x2C
#define AAL5_SMFL_ADDR AAL5_BASE_ADDRESS+0x30
#define AAL5_SATMHD_ADDR AAL5_BASE_ADDRESS+0x34
#define AAL5_SCON_ADDR AAL5_BASE_ADDRESS+0x38
#define AAL5_SCMD_ADDR AAL5_BASE_ADDRESS+0x3C
#define AAL5_RISR0_ADDR AAL5_BASE_ADDRESS+0x40
#define AAL5_RIMR0_ADDR AAL5_BASE_ADDRESS+0x44
#define AAL5_RISR1_ADDR AAL5_BASE_ADDRESS+0x48
#define AAL5_RIMR1_ADDR AAL5_BASE_ADDRESS+0x4C
#define AAL5_RMFL_ADDR AAL5_BASE_ADDRESS+0x50
#define AAL5_RINTINF0_ADDR AAL5_BASE_ADDRESS+0x54
#define AAL5_RINTINF1_ADDR AAL5_BASE_ADDRESS+0x58
#define AAL5_RES5C_ADDR AAL5_BASE_ADDRESS+0x5C
#define AAL5_RIOL_ADDR AAL5_BASE_ADDRESS+0x60
#define AAL5_RIOM_ADDR AAL5_BASE_ADDRESS+0x64
#define AAL5_SOOL_ADDR AAL5_BASE_ADDRESS+0x68
#define AAL5_SOOM_ADDR AAL5_BASE_ADDRESS+0x6C
#define AAL5_RES70_ADDR AAL5_BASE_ADDRESS+0x70
#define AAL5_RES74_ADDR AAL5_BASE_ADDRESS+0x74
#define AAL5_RES78_ADDR AAL5_BASE_ADDRESS+0x78
#define AAL5_RES7C_ADDR AAL5_BASE_ADDRESS+0x7C
#define AAL5_RES80_ADDR AAL5_BASE_ADDRESS+0x80
#define AAL5_RES84_ADDR AAL5_BASE_ADDRESS+0x84
#define AAL5_RES88_ADDR AAL5_BASE_ADDRESS+0x88
#define AAL5_RES8C_ADDR AAL5_BASE_ADDRESS+0x8C
#define AAL5_RES90_ADDR AAL5_BASE_ADDRESS+0x90
#define AAL5_RES94_ADDR AAL5_BASE_ADDRESS+0x94
#define AAL5_RES98_ADDR AAL5_BASE_ADDRESS+0x98
#define AAL5_RES9C_ADDR AAL5_BASE_ADDRESS+0x9C
#define AAL5_RESA0_ADDR AAL5_BASE_ADDRESS+0xA0
#define AAL5_RESA4_ADDR AAL5_BASE_ADDRESS+0xA4
#define AAL5_RESA8_ADDR AAL5_BASE_ADDRESS+0xA8
#define AAL5_RESAC_ADDR AAL5_BASE_ADDRESS+0xAC
#define AAL5_RESB0_ADDR AAL5_BASE_ADDRESS+0xB0
#define AAL5_RESB4_ADDR AAL5_BASE_ADDRESS+0xB4
#define AAL5_RESB8_ADDR AAL5_BASE_ADDRESS+0xB8
#define AAL5_RESBC_ADDR AAL5_BASE_ADDRESS+0xBC
#define AAL5_RESC0_ADDR AAL5_BASE_ADDRESS+0xC0
#define AAL5_RESC4_ADDR AAL5_BASE_ADDRESS+0xC4
#define AAL5_RESC8_ADDR AAL5_BASE_ADDRESS+0xC8
#define AAL5_RESCC_ADDR AAL5_BASE_ADDRESS+0xCC
#define AAL5_RESD0_ADDR AAL5_BASE_ADDRESS+0xD0
#define AAL5_RESD4_ADDR AAL5_BASE_ADDRESS+0xD4
#define AAL5_RESD8_ADDR AAL5_BASE_ADDRESS+0xD8
#define AAL5_RESDC_ADDR AAL5_BASE_ADDRESS+0xDC
#define AAL5_RESE0_ADDR AAL5_BASE_ADDRESS+0xE0
#define AAL5_RESE4_ADDR AAL5_BASE_ADDRESS+0xE4
#define AAL5_RESE8_ADDR AAL5_BASE_ADDRESS+0xE8
#define AAL5_RESEC_ADDR AAL5_BASE_ADDRESS+0xEC
#define AAL5_SSRC0_ADDR AAL5_BASE_ADDRESS+0xF0
#define AAL5_SSRC1_ADDR AAL5_BASE_ADDRESS+0xF4
#define AAL5_RSRC0_ADDR AAL5_BASE_ADDRESS+0xF8
#define AAL5_RSRC1_ADDR AAL5_BASE_ADDRESS+0xFC
#define AAL5S_ISR_QID_MASK 0xFF000000
#define AAL5S_ISR_SAB 0x00000100
#define AAL5S_ISR_SE 0x00000080
#define AAL5S_ISR_MFLE 0x00000040
#define AAL5S_ISR_SBE0 0x00000020
#define AAL5S_ISR_SEG0 0x00000010
#define AAL5S_ISR_TAB 0x00000004
#define AAL5_SIMR_MASK 0x000001c7
#define AAL5_SIMR_SAB 0x00000100
#define AAL5_SIMR_SE 0x00000080
#define AAL5_SIMR_MFLE 0x00000040
#define AAL5_SIMR_TAB 0x00000004
#define AAL5_SIMR_SBE0 0x00000002
#define AAL5_SIMR_SEG0 0x00000001
#define AAL5_SCMD_SEQCOUNT_MASK 0x0000ff00
#define AAL5_SCMD_MODE_POLL 0x00000008
#define AAL5_SCMD_MODE_COUNT 0x00000000
#define AAL5_SCMD_AS 0x00000004
#define AAL5_SCMD_SS 0x00000002
#define AAL5_SCMD_AR 0x00000001
#define AAL5R_ISR_CID_MASK 0xFF000000//ConnectionID
#define AAL5R_ISR_DBC_MASK 0x00FF0000//DiscardedByteCounter
#define AAL5R_ISR_END 0x00002000//End
#define AAL5R_ISR_ICID 0x00001000//InvalidConnectionID
#define AAL5R_ISR_CLP 0x00000800//CellLossPriority
#define AAL5R_ISR_CGST 0x00000400//Congestion
#define AAL5R_ISR_UUE 0x00000200//CPCSUUError
#define AAL5R_ISR_CPIE 0x00000100//CPIError
#define AAL5R_ISR_FE 0x00000080//FrameEnd
#define AAL5R_ISR_MFLE 0x00000040//MaximumFrameLengthExceeded
#define AAL5R_ISR_DBCE 0x00000020//DiscardedByteCounterExceeded
#define AAL5R_ISR_CRC 0x00000010//CRCError
#define AAL5R_ISR_ILEN 0x00000008//InvalidLength
#define AAL5R_ISR_RAB 0x00000004//ReceiveAbort
#define AAL5_RIMR1_MASK 0x00003ffc
#define AAL5_RIMR1_END 0x00002000//End
#define AAL5_RIMR1_ICID 0x00001000//InvalidConnectionID
#define AAL5_RIMR1_CLP 0x00000800//CellLossPriority
#define AAL5_RIMR1_CGST 0x00000400//Congestion
#define AAL5_RIMR1_UUE 0x00000200//CPCSUUError
#define AAL5_RIMR1_CPIE 0x00000100//CPIError
#define AAL5_RIMR1_FE 0x00000080//FrameEnd
#define AAL5_RIMR1_MFLE 0x00000040//MaximumFrameLengthExceeded
#define AAL5_RIMR1_DBCE 0x00000020//DiscardedByteCounterExceeded
#define AAL5_RIMR1_CRC 0x00000010//CRCError
#define AAL5_RIMR1_ILEN 0x00000008//InvalidLength
#define AAL5_RIMR1_RAB 0x00000004//ReceiveAbort
//AAL5 Reassambly Errors
#define AAL5_STW1_MASK 0x33//Error mask
#define AAL5_STW0_MASK 0x5c//Error mask
#define AAL5_STW0_BE 0x3//padding bytes mask
#define AAL5_STW1_CBM 0x20//Transfer from CBM to A5R abnormally ended
#define AAL5_STW1_CH 0x10//Invalid Channel number error
#define AAL5_STW1_CLP 0x8//CLP value of cells in packet is 1
#define AAL5_STW1_CG 0x4//Cell in packet expired congestion
#define AAL5_STW1_UU 0x2//CPCS-UU value error
#define AAL5_STW1_CPI 0x1//CPI value error
#define AAL5_STW0_FE 0x80//Frame end
#define AAL5_STW0_MFL 0x40//Maximum frame length error
#define AAL5_STW0_CRC 0x10//CRC error
#define AAL5_STW0_IL 0x8//Invalid length
#define AAL5_STW0_RA 0x4//Received abort
//CBM Registers
#define CBM_NRTTHR_ADDR CBM_BASE_ADDRESS+0x10//NonRealTimeThreshold
#define CBM_CLP0THR_ADDR CBM_BASE_ADDRESS+0x14//CLP0Threshold
#define CBM_CLP1THR_ADDR CBM_BASE_ADDRESS+0x18//CLP1Threshold
#define CBM_QDOFF_ADDR CBM_BASE_ADDRESS+0x1C//QueueDescriptorOffset
#define CBM_CFG_ADDR CBM_BASE_ADDRESS+0x20//Configuration
#define CBM_HWEXPAR0_ADDR CBM_BASE_ADDRESS+0x24//HWExtractParameter0
#define CBM_RES28_ADDR CBM_BASE_ADDRESS+0x28
#define CBM_WMSTAT0_ADDR CBM_BASE_ADDRESS+0x2C
#define CBM_HWEXCMD_ADDR CBM_BASE_ADDRESS+0x30//HWExtractCommand0
#define CBM_RES34_ADDR CBM_BASE_ADDRESS+0x34
#define CBM_HWEXSTAT0_ADDR CBM_BASE_ADDRESS+0x38//HWExtractStatus0
#define CBM_RES3C_ADDR CBM_BASE_ADDRESS+0x3C
#define CBM_RES40_ADDR CBM_BASE_ADDRESS+0x40
#define CBM_CNT_ADDR CBM_BASE_ADDRESS+0x44//CellCount
#define CBM_RES48_ADDR CBM_BASE_ADDRESS+0x48
#define CBM_LFR_ADDR CBM_BASE_ADDRESS+0x4C//PointertolastCellinfreeCellQueue
#define CBM_FFR_ADDR CBM_BASE_ADDRESS+0x50//PointertofirstCellinfreeCellQueue
#define CBM_RES54_ADDR CBM_BASE_ADDRESS+0x54
#define CBM_RES58_ADDR CBM_BASE_ADDRESS+0x58
#define CBM_RES5C_ADDR CBM_BASE_ADDRESS+0x5C
#define CBM_RES60_ADDR CBM_BASE_ADDRESS+0x60
#define CBM_RES64_ADDR CBM_BASE_ADDRESS+0x64
#define CBM_RES68_ADDR CBM_BASE_ADDRESS+0x68
#define CBM_RES6C_ADDR CBM_BASE_ADDRESS+0x6C
#define CBM_RES70_ADDR CBM_BASE_ADDRESS+0x70
#define CBM_RES74_ADDR CBM_BASE_ADDRESS+0x74
#define CBM_RES78_ADDR CBM_BASE_ADDRESS+0x78
#define CBM_RES7C_ADDR CBM_BASE_ADDRESS+0x7C
#define CBM_RES80_ADDR CBM_BASE_ADDRESS+0x80
#define CBM_RES84_ADDR CBM_BASE_ADDRESS+0x84
#define CBM_RES88_ADDR CBM_BASE_ADDRESS+0x88
#define CBM_RES8C_ADDR CBM_BASE_ADDRESS+0x8C
#define CBM_RES90_ADDR CBM_BASE_ADDRESS+0x90
#define CBM_RES94_ADDR CBM_BASE_ADDRESS+0x94
#define CBM_RES98_ADDR CBM_BASE_ADDRESS+0x98
#define CBM_RES9C_ADDR CBM_BASE_ADDRESS+0x9C
#define CBM_RESA0_ADDR CBM_BASE_ADDRESS+0xA0
#define CBM_RESA4_ADDR CBM_BASE_ADDRESS+0xA4
#define CBM_RESA8_ADDR CBM_BASE_ADDRESS+0xA8
#define CBM_RESAC_ADDR CBM_BASE_ADDRESS+0xAC
#define CBM_RESB0_ADDR CBM_BASE_ADDRESS+0xB0
#define CBM_RESB4_ADDR CBM_BASE_ADDRESS+0xB4
#define CBM_RESB8_ADDR CBM_BASE_ADDRESS+0xB8
#define CBM_RESBC_ADDR CBM_BASE_ADDRESS+0xBC
#define CBM_INTINF0_ADDR CBM_BASE_ADDRESS+0xC0//InterruptInfo0
#define CBM_INTCMD_ADDR CBM_BASE_ADDRESS+0xC4//InterruptCommand0
#define CBM_IMR0_ADDR CBM_BASE_ADDRESS+0xC8//InterruptMask
#define CBM_SRC0_ADDR CBM_BASE_ADDRESS+0xCC//ServiceRequestControl
#define CBM_RESD0_ADDR CBM_BASE_ADDRESS+0xD0
#define CBM_RESD4_ADDR CBM_BASE_ADDRESS+0xD4
#define CBM_RESD8_ADDR CBM_BASE_ADDRESS+0xD8
#define CBM_RESDC_ADDR CBM_BASE_ADDRESS+0xDC
#define CBM_RESE0_ADDR CBM_BASE_ADDRESS+0xE0
#define CBM_AAL5IDIS_ADDR CBM_BASE_ADDRESS+0xE4//MIB-No.EPDdiscardedpacketsupstream
#define CBM_AAL5ODIS_ADDR CBM_BASE_ADDRESS+0xE8//MIB-No.PPDdiscardedpacketsupstream
#define CBM_RESEC_ADDR CBM_BASE_ADDRESS+0xEC
#define CBM_RESF0_ADDR CBM_BASE_ADDRESS+0xF0
#define CBM_RESF4_ADDR CBM_BASE_ADDRESS+0xF4
#define CBM_RESF8_ADDR CBM_BASE_ADDRESS+0xF8
#define CBM_RESFC_ADDR CBM_BASE_ADDRESS+0xFC
//CBMCFG
#define CBM_CFG_INTLCK0EN 0x00000008
#define CBM_CFG_INT0HLT 0x00000004
#define CBM_CFG_START 0x00000001
#define CBM_HWEXPAR_PN_A5 0x00002000
#define CBM_HWEXPAR_PN_CM 0x00000000
#define CBM_HWEXPAR_SUBADD_PORTMASK 0x00000070
#define CBM_HWEXPAR_SUBADD_ADU 0x00000000
#define CBM_HWEXPAR_SUBADD_AAL2 0x00000080
#define CBM_HWEXPAR_SUBADD_SWIE 0x00000100
#define CBM_HWEXCMD_SFE2 0x00000100
#define CBM_HWEXCMD_FE2 0x00000080
#define CBM_HWEXCMD_SCE2 0x00000040
#define CBM_HWEXCMD_SFE1 0x00000020
#define CBM_HWEXCMD_FE1 0x00000010
#define CBM_HWEXCMD_SCE1 0x00000008
#define CBM_HWEXCMD_SFE0 0x00000004
#define CBM_HWEXCMD_FE0 0x00000002
#define CBM_HWEXCMD_SCE0 0x00000001
#define CBM_INTINF0_QID_MASK 0xFF000000
#define CBM_INTINF0_ORIGIN_MASK 0x00F00000
#define CBM_INTINF0_EF 0x00004000
#define CBM_INTINF0_ACA 0x00002000
#define CBM_INTINF0_ERR 0x00001000
#define CBM_INTINF0_DISC 0x00000800
#define CBM_INTINF0_QSBV 0x00000400
#define CBM_INTINF0_Q0E 0x00000200
#define CBM_INTINF0_Q0I 0x00000100
#define CBM_INTINF0_RDE 0x00000080
#define CBM_INTINF0_OPF 0x00000040
#define CBM_INTINF0_NFCA 0x00000020
#define CBM_INTINF0_CLP1TR 0x00000010
#define CBM_INTINF0_CLP0TR 0x00000008
#define CBM_INTINF0_NRTTR 0x00000004
#define CBM_INTINF0_QFD 0x00000002
#define CBM_INTINF0_QTR 0x00000001
#define CBM_INTINF0_QID_SHIFT 24
//CBM QD Word 3
#define CBM_QD_W3_QOS_0 0x00000000
#define CBM_QD_W3_QOS_1 0x40000000
#define CBM_QD_W3_QOS_2 0x80000000
#define CBM_QD_W3_QOS_3 0xc0000000
#define CBM_QD_W3_DIR_UP 0x20000000
#define CBM_QD_W3_DIR_DOWN 0x00000000
#define CBM_QD_W3_CLPt 0x10000000
#define CBM_QD_W3_RT 0x08000000
#define CBM_QD_W3_AAL5 0x04000000
#define CBM_QD_W3_INT_NOINT 0x00000000
#define CBM_QD_W3_INT_ACA 0x01000000
#define CBM_QD_W3_INT_EOF 0x02000000
#define CBM_QD_W3_INT_BOTH 0x03000000
#define CBM_QD_W3_THRESHOLD_MASK 0x00ff0000
#define CBM_QD_W3_WM_EN 0x00000010
#define CBM_QD_W3_HCR 0x00000008
#define CBM_QD_W3_SBID_MASK 0x00000001
#define CBM_QD_W3_THRESHOLD_SHIFT 16
//WATER MARK STATUS
#define CBM_WM_NRT_MASK 0x00040000
#define CBM_WM_CLP0_MASK 0x00020000
#define CBM_WM_CLP1_MASK 0x00010000
//CBMNRTTHR, CBMCLP0THR, CBMCLP0THR
#define CBM_NRT_WM_NONE 0x00000000//no water mark
#define CBM_WM_3_1 0x00010000//3/4 to set, 1/4 to release
#define CBM_WM_3_2 0x00020000//3/4 to set, 2/4 to release
#define CBM_WM_2_1 0x00030000//2/4 to set, 1/4 to release
#define CBM_THR_MASK 0x0000FFFF
#define CBM_IMR_MASK 0x0000fbff
#define CBM_IMR_reserved 0xFFFF0400
#define CBM_IMR_RFULL 0x00008000//EndofFrame
#define CBM_IMR_EF 0x00004000//EndofFrame
#define CBM_IMR_ACA 0x00002000//AnyCellArrived
#define CBM_IMR_ERR 0x00001000//FPI Error
#define CBM_IMR_DISC 0x00000800//Discard
#define CBM_IMR_reserved1 0x00000400//reserved
#define CBM_IMR_Q0E 0x00000200//Queue0Extract
#define CBM_IMR_Q0I 0x00000100//Queue0Insert
#define CBM_IMR_RDE 0x00000080//ReadEmptyQueue
#define CBM_IMR_OPF 0x00000040//OncePerFrame
#define CBM_IMR_NFCA 0x00000020//NoFreeCellAvailable
#define CBM_IMR_CLP1TR 0x00000010//CLP1ThresholdReached
#define CBM_IMR_CLP0TR 0x00000008//CLP0ThresholdReached
#define CBM_IMR_NRTTR 0x00000004//NonRealTimeThresholdReached
#define CBM_IMR_QFD 0x00000002//QueueFrameDiscard
#define CBM_IMR_QTR 0x00000001//QueueThresholdReached
#define CBM_EXSTAT_FB 0x00000010
#define CBM_EXSTAT_SCB 0x00000008
#define CBM_EXSTAT_Q0 0x00000004
#define CBM_EXSTAT_RDE 0x00000002
#define CBM_EXSTAT_QV 0x00000001
//HTU Registers
#define HTU_RX0_ADDR HTU_BASE_ADDRESS+0x10
#define HTU_RX1_ADDR HTU_BASE_ADDRESS+0x14
#define HTU_RES18_ADDR HTU_BASE_ADDRESS+0x18
#define HTU_RES1C_ADDR HTU_BASE_ADDRESS+0x1C
#define HTU_RES20_ADDR HTU_BASE_ADDRESS+0x20
#define HTU_RES24_ADDR HTU_BASE_ADDRESS+0x24
#define HTU_RES28_ADDR HTU_BASE_ADDRESS+0x28
#define HTU_RES2C_ADDR HTU_BASE_ADDRESS+0x2C
#define HTU_PCF0PAT_ADDR HTU_BASE_ADDRESS+0x30
#define HTU_PCF1PAT_ADDR HTU_BASE_ADDRESS+0x34
#define HTU_RES38_ADDR HTU_BASE_ADDRESS+0x38
#define HTU_RES3C_ADDR HTU_BASE_ADDRESS+0x3C
#define HTU_RES40_ADDR HTU_BASE_ADDRESS+0x40
#define HTU_RES44_ADDR HTU_BASE_ADDRESS+0x44
#define HTU_RES48_ADDR HTU_BASE_ADDRESS+0x48
#define HTU_RES4C_ADDR HTU_BASE_ADDRESS+0x4C
#define HTU_PCF0MASK_ADDR HTU_BASE_ADDRESS+0x50
#define HTU_PCF1MASK_ADDR HTU_BASE_ADDRESS+0x54
#define HTU_RES58_ADDR HTU_BASE_ADDRESS+0x58
#define HTU_RES5C_ADDR HTU_BASE_ADDRESS+0x5C
#define HTU_RES60_ADDR HTU_BASE_ADDRESS+0x60
#define HTU_RES64_ADDR HTU_BASE_ADDRESS+0x64
#define HTU_RES68_ADDR HTU_BASE_ADDRESS+0x68
#define HTU_RES6C_ADDR HTU_BASE_ADDRESS+0x6C
#define HTU_TIMEOUT_ADDR HTU_BASE_ADDRESS+0x70
#define HTU_DESTOAM_ADDR HTU_BASE_ADDRESS+0x74
#define HTU_DESTRM_ADDR HTU_BASE_ADDRESS+0x78
#define HTU_DESTOTHER_ADDR HTU_BASE_ADDRESS+0x7C
#define HTU_CFG_ADDR HTU_BASE_ADDRESS+0x80
#define HTU_RES84_ADDR HTU_BASE_ADDRESS+0x84
#define HTU_RES88_ADDR HTU_BASE_ADDRESS+0x88
#define HTU_RES8C_ADDR HTU_BASE_ADDRESS+0x8C
#define HTU_INFNOENTRY_ADDR HTU_BASE_ADDRESS+0x90
#define HTU_INFTIMEOUT_ADDR HTU_BASE_ADDRESS+0x94
#define HTU_RES98_STAT HTU_BASE_ADDRESS+0x98
#define HTU_RES9C_ADDR HTU_BASE_ADDRESS+0x9C
#define HTU_MIBCIUP HTU_BASE_ADDRESS+0xA0//MIB Counter In Unknown Protoc Register
#define HTU_CNTTIMEOUT_ADDR HTU_BASE_ADDRESS+0xA4
#define HTU_RESA8_ADDR HTU_BASE_ADDRESS+0xA8
#define HTU_RESAC_ADDR HTU_BASE_ADDRESS+0xAC
#define HTU_RAMADDR_ADDR HTU_BASE_ADDRESS+0xB0
#define HTU_RAMCMD_ADDR HTU_BASE_ADDRESS+0xB4
#define HTU_RAMSTAT_ADDR HTU_BASE_ADDRESS+0xB8
#define HTU_RESBC_ADDR HTU_BASE_ADDRESS+0xBC
#define HTU_RAMDAT1_ADDR HTU_BASE_ADDRESS+0xC0
#define HTU_RAMDAT2_ADDR HTU_BASE_ADDRESS+0xC4
#define HTU_RESCC_ADDR HTU_BASE_ADDRESS+0xCC
#define HTU_RESD0_ADDR HTU_BASE_ADDRESS+0xD0
#define HTU_RESD4_ADDR HTU_BASE_ADDRESS+0xD4
#define HTU_RESD8_ADDR HTU_BASE_ADDRESS+0xD8
#define HTU_RESDC_ADDR HTU_BASE_ADDRESS+0xDC
#define HTU_RESE0_ADDR HTU_BASE_ADDRESS+0xE0
#define HTU_RESE4_ADDR HTU_BASE_ADDRESS+0xE4
#define HTU_IMR0_ADDR HTU_BASE_ADDRESS+0xE8
#define HTU_RESEC_ADDR HTU_BASE_ADDRESS+0xEC
#define HTU_ISR0_ADDR HTU_BASE_ADDRESS+0xF0
#define HTU_RESF4_ADDR HTU_BASE_ADDRESS+0xF4
#define HTU_SRC0_ADDR HTU_BASE_ADDRESS+0xF8
#define HTU_RESFC_ADDR HTU_BASE_ADDRESS+0xFC
//HTU_CFG
#define HTU_CFG_START 0x00000001
#define HTU_RAMCMD_RMW 0x00000004
#define HTU_RAMCMD_RD 0x00000002
#define HTU_RAMCMD_WR 0x00000001
#define HTU_RAMDAT1_VCON 0x00000080//validconnection
#define HTU_RAMDAT1_VCT 0x00000040//vcivalueistransparent
#define HTU_RAMDAT1_QIDS 0x00000020//qid selects a cell in cbm
#define HTU_RAMDAT1_VCI3 0x00000010//vci3->oamqueue
#define HTU_RAMDAT1_VCI4 0x00000008//vci4->oamqueue
#define HTU_RAMDAT1_VCI6 0x00000004//vci6->rmqueue
#define HTU_RAMDAT1_PTI4 0x00000002//pti4->oamqueue
#define HTU_RAMDAT1_PTI5 0x00000001//pti5->oamqueue
#define HTU_RAMDAT2_PTI6 0x00000800
#define HTU_RAMDAT2_PTI7 0x00000400
#define HTU_RAMDAT2_F4U 0x00000200
#define HTU_RAMDAT2_F5U 0x00000100
#define HTU_RAMDAT2_QID_MASK 0x000000ff
#define HTU_ISR_NE 0x00000001
#define HTU_ISR_TORD 0x00000002
#define HTU_ISR_IT 0x00000008
#define HTU_ISR_OTOC 0x00000010
#define HTU_ISR_ONEC 0x00000020
#define HTU_ISR_PNE 0x00000040
#define HTU_ISR_PT 0x00000080
#define HTU_ISR_MASK 0x000000ff
//QSB Registers
#define QSB_BIP0_ADDR QSB_BASE_ADDRESS+0x00
#define QSB_BIP1_ADDR QSB_BASE_ADDRESS+0x04
#define QSB_BIP2_ADDR QSB_BASE_ADDRESS+0x08
#define QSB_BIP3_ADDR QSB_BASE_ADDRESS+0x0C
#define QSB_RSVP_ADDR QSB_BASE_ADDRESS+0x10
#define QSB_TNOW_ADDR QSB_BASE_ADDRESS+0x14
#define QSB_TNOWCYC_ADDR QSB_BASE_ADDRESS+0x18
#define QSB_TAU_ADDR QSB_BASE_ADDRESS+0x1C
#define QSB_L1BRS_ADDR QSB_BASE_ADDRESS+0x20
#define QSB_SBL_ADDR QSB_BASE_ADDRESS+0x24
#define QSB_CONFIG_ADDR QSB_BASE_ADDRESS+0x28
#define QSB_RTM_ADDR QSB_BASE_ADDRESS+0x2C
#define QSB_RTD_ADDR QSB_BASE_ADDRESS+0x30
#define QSB_RAMAC_ADDR QSB_BASE_ADDRESS+0x34
#define QSB_ISR_ADDR QSB_BASE_ADDRESS+0x38
#define QSB_IMR_ADDR QSB_BASE_ADDRESS+0x3C
#define QSB_SRC_ADDR QSB_BASE_ADDRESS+0x40
#define QSB_TABLESEL_QVPT 8
#define QSB_TABLESEL_QPT 1
#define QSB_TABLESEL_SCT 2
#define QSB_TABLESEL_SPT 3
#define QSB_TABLESEL_CALENDARWFQ 4/*notusedbyFW*/
#define QSB_TABLESEL_L2WFQ 5/*notusedbyFW*/
#define QSB_TABLESEL_CALENDARRS 6/*notusedbyFW*/
#define QSB_TABLESEL_L2BITMAPRS 7/*notusedbyFW*/
#define QSB_TABLESEL_SHIFT 24
#define QSB_TWFQ_MASK 0x3FFF0000
#define QSB_TPRS_MASK 0x0000FFFF
#define QSB_SBID_MASK 0xF
#define QSB_TWFQ_SHIFT 16
#define QSB_SCDRATE_MASK 0x00007FFF
#define QSB_SBVALID_MASK 0x80000000
#define QSB_ISR_WFQLE 0x00000001
#define QSB_ISR_WFQBE 0x00000002
#define QSB_ISR_RSLE 0x00000004
#define QSB_ISR_RSBE 0x00000008
#define QSB_ISR_MUXOV 0x00000010
#define QSB_ISR_CDVOV 0x00000020
#define QSB_ISR_PARAMI 0x00000040
#define QSB_ISR_SLOSS 0x00000080
#define QSB_ISR_IIPS 0x00000100
#define QSB_IMR_WFQLE 0x00000001
#define QSB_IMR_WFQBE 0x00000002
#define QSB_IMR_RSLE 0x00000004
#define QSB_IMR_RSBE 0x00000008
#define QSB_IMR_MUXOV 0x00000010
#define QSB_IMR_CDVOV 0x00000020
#define QSB_IMR_PARAMI 0x00000040
#define QSB_IMR_SLOSS 0x00000080
#define QSB_IMR_IIPS 0x00000100
#define QSB_READ 0x0
#define QSB_WRITE 0x80000000
#define QSB_READ_ALL 0xFFFFFFFF
#if 1 //some bug with QSB access mask
#define QSB_QPT_SET_MASK 0x0
#define QSB_QVPT_SET_MASK 0x0
#define QSB_SET_SCT_MASK 0x0
#define QSB_SET_SPT_MASK 0x0
#define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF
#else //some bug with QSB access mask
#define QSB_QPT_SET_MASK 0x80000000
#define QSB_QVPT_SET_MASK 0x0
#define QSB_SET_SCT_MASK 0xFFFFFFE0
#define QSB_SET_SPT_MASK 0x7FF8C000
#define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF
#endif //some bug with QSB access mask
#define QSB_SPT_SBVALID 0x80000000
#define QSB_RAMAC_REG_LOW 0x0
#define QSB_RAMAC_REG_HIGH 0x00010000
#define SRC_SRE_ENABLE 0x1000
#define SRC_CLRR 0x4000 //request clear bit
//SWIE Registers
#define SWIE_IQID_ADDR SWIE_BASE_ADDRESS+0x0c//SWIEInsertQueueDescriptor
#define SWIE_ICMD_ADDR SWIE_BASE_ADDRESS+0x10//SWIEInsertCommand
#define SWIE_ISTAT_ADDR SWIE_BASE_ADDRESS+0x14//SWIEInsertStatus
#define SWIE_ESTAT_ADDR SWIE_BASE_ADDRESS+0x18//SWIEExtractStatus
#define SWIE_ISRC_ADDR SWIE_BASE_ADDRESS+0x74//SWIEInsertServiceRequestControl
#define SWIE_ESRC_ADDR SWIE_BASE_ADDRESS+0x78//SWIEExtractServiceRequestControl
#define SWIE_ICELL_ADDR SWIE_BASE_ADDRESS+0x80//SWIEInsertCell(0x80-0xb4)
#define SWIE_ECELL_ADDR SWIE_BASE_ADDRESS+0xc0//SWIEExtractCell(0xc0-0xf4)
#define SWIE_ISTAT_DONE 0x1
#define SWIE_ESTAT_DONE 0x1
#define SWIE_ICMD_START 0x00000001//Startcommandforinsertion
#define SWIE_CBM_SCE0 CBM_HWEXCMD_SCE0//CBMcommandforSingle-Cell-Extract
#define SWIE_CBM_PID_SUBADDR 0x00001000//CBMPortIDandSubAddressforUTOPIA
//Extracted cell format
//52bytes AAL0 PDU + "Input cell additional data"(14bits)
#define SWIE_ADDITION_DATA_MASK 0x7fff
#define SWIE_EPORT_MASK 0x7000//Source ID (000 AUB0, 001 AUB1)
#define SWIE_EF4USER_MASK 0x800
#define SWIE_EF5USER_MASK 0x400
#define SWIE_EOAM_MASK 0x200
#define SWIE_EAUU_MASK 0x100
#define SWIE_EVCI3_MASK 0x80
#define SWIE_EVCI4_MASK 0x40
#define SWIE_EVCI6_MASK 0x20
#define SWIE_EPTI4_MASK 0x10
#define SWIE_EPTI5_MASK 0x8
#define SWIE_EPTI6_MASK 0x4
#define SWIE_EPTI7_MASK 0x2
#define SWIE_ECRC10ERROR_MASK 0x1
#define CBM_CELL_SIZE 0x40
#define CBM_QD_SIZE 0x10
#define AAL5R_TRAILER_LEN 12
#define AAL5S_INBOUND_HEADER 8
//constants
//TODO: to be finalized by system guys
//DMA QOS defined by ATM QoS Service type
#define DMA_RX_CH0 0
#define DMA_RX_CH1 1
#define DMA_TX_CH0 0
#define DMA_TX_CH1 1
#define CBR_DMA_QOS CBM_QD_W3_QOS_0
#define VBR_RT_DMA_QOS CBM_QD_W3_QOS_0
#define VBR_NRT_DMA_QOS CBM_QD_W3_QOS_0
#define UBR_PLUS_DMA_QOS CBM_QD_W3_QOS_0
#define UBR_DMA_QOS CBM_QD_W3_QOS_0
#define SRC_TOS_MIPS 0
#define AAL5R_SRPN 0x00000006//a5rneedshigherprioritythanDR
#define AAL5S_SRPN 0x00000005
#define CBM_MIPS_SRPN 0x00000004
#define QSB_SRPN 0x00000023
#define HTU_SRPN1 0x00000022
#define HTU_SRPN0 0x00000021
#endif //ATM_DEFINES_H

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#ifndef AMAZON_ATM_MIB_H
#define AMAZON_ATM_MIB_H
#ifdef CONFIG_IFX_ATM_MIB
#include <asm/types.h>
#ifdef __KERNEL__
#include <linux/list.h>
#endif
#endif /* CONFIG_IFX_ATM_MIB */
#ifndef __KERNEL__
#include <atmMIB/local_list.h>
typedef unsigned int __u32;
#endif
typedef struct{
__u32 ifHCInOctets_h;
__u32 ifHCInOctets_l;
__u32 ifHCOutOctets_h;
__u32 ifHCOutOctets_l;
__u32 ifInErrors;
__u32 ifInUnknownProtos;
__u32 ifOutErrors;
}atm_cell_ifEntry_t;
typedef struct{
__u32 ifHCInOctets_h;
__u32 ifHCInOctets_l;
__u32 ifHCOutOctets_h;
__u32 ifHCOutOctets_l;
__u32 ifInUcastPkts;
__u32 ifOutUcastPkts;
__u32 ifInErrors;
__u32 ifInDiscards;
__u32 ifOutErros;
__u32 ifOutDiscards;
}atm_aal5_ifEntry_t;
typedef struct{
__u32 aal5VccCrcErrors;
__u32 aal5VccSarTimeOuts;//no timer support yet
__u32 aal5VccOverSizedSDUs;
}atm_aal5_vcc_t;
#if defined(CONFIG_IFX_ATM_MIB) || defined(IFX_CONFIG_SNMP_ATM_MIB)
/* ATM-MIB data structures */
typedef struct atmIfConfEntry {
int ifIndex;
int atmInterfaceMaxVpcs;
int atmInterfaceMaxVccs;
int atmInterfaceConfVpcs;
int atmInterfaceConfVccs;
int atmInterfaceMaxActiveVpiBits;
int atmInterfaceMaxActiveVciBits;
int atmInterfaceIlmiVpi;
int atmInterfaceIlmiVci;
int atmInterfaceAddressType;
char atmInterfaceAdminAddress[40];
unsigned long atmInterfaceMyNeighborIpAddress;
char atmInterfaceMyNeighborIfName[20];
int atmInterfaceCurrentMaxVpiBits;
int atmInterfaceCurrentMaxVciBits;
char atmInterfaceSubscrAddress[40];
int flags;
}atmIfConfEntry;
typedef struct atmTrafficDescParamEntry {
/* Following three parameters are used to update VCC QoS values */
int ifIndex;
short atmVclvpi;
int atmVclvci;
unsigned int atmTrafficParamIndex;
unsigned char traffic_class;
int max_pcr;
/* Subramani: Added min_pcr */
int min_pcr;
int cdv;
int scr;
int mbs;
int atmTrafficRowStatus;
int atmTrafficFrameDiscard;
struct list_head vpivci_head;
struct list_head list;
}atmTrafficDescParamEntry;
typedef struct atmVclEntry {
int ifIndex;
short atmVclvpi;
int atmVclvci;
char vpivci[20];
int atmVclAdminStatus;
int atmVclOperStatus;
unsigned long atmVclLastChange;
struct atmTrafficDescParamEntry *atmVclRxTrafficPtr;
struct atmTrafficDescParamEntry *atmVclTxTrafficPtr;
unsigned char atmVccAalType;
unsigned int atmVccAal5TxSduSize;
unsigned int atmVccAal5RxSduSize;
int atmVccAal5Encap;
int atmVclRowStatus;
int atmVclCastType;
int atmVclConnKind;
struct list_head list;
int flags;
}atmVclEntry;
typedef union union_atmptrs {
struct atmIfConfEntry *atmIfConfEntry_ptr;
struct atmTrafficDescParamEntry *atmTrafficDescParamEntry_ptr;
struct atmVclEntry *atmVclEntry_ptr;
}union_atmptrs;
/* ATM Character device major number */
#define ATM_MEI_MAJOR 107
/* Protocol Constants */
#define IFX_PROTO_RAW 0
#define IFX_PROTO_BR2684 1
#define IFX_PROTO_PPPOATM 2
#define IFX_PROTO_CLIP 3
/* IOCTL Command Set for ATM-MIB */
#define GET_ATM_IF_CONF_DATA 0x0AB0
#define SET_ATM_IF_CONF_DATA 0x0AB1
#define SET_ATM_QOS_DATA 0x0BC0
#define GET_ATM_VCL_DATA 0x0CD0
#define SET_ATM_VCL_DATA 0x0CD1
#define FIND_VCC_IN_KERNEL 0x0DE0
/* User defined flags for VCL Table */
#define ATMVCCAAL5CPCSTRANSMITSDUSIZE 9
#define ATMVCCAAL5CPCSRECEIVESDUSIZE 10
#endif /* CONFIG_IFX_ATM_MIB || IFX_CONFIG_SNMP_ATM_MIB */
#endif //AMAZON_ATM_MIB_H

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//*************************************************************************
//* Summary of definitions which are used in each peripheral *
//*************************************************************************
#ifndef peripheral_definitions_h
#define peripheral_definitions_h
typedef unsigned char UINT8;
typedef signed char INT8;
typedef unsigned short UINT16;
typedef signed short INT16;
typedef unsigned int UINT32;
typedef signed int INT32;
typedef unsigned long long UINT64;
typedef signed long long INT64;
#define REG8( addr ) (*(volatile UINT8 *) (addr))
#define REG16( addr ) (*(volatile UINT16 *)(addr))
#define REG32( addr ) (*(volatile UINT32 *)(addr))
#define REG64( addr ) (*(volatile UINT64 *)(addr))
/* define routine to set FPI access in Supervisor Mode */
#define IFX_SUPERVISOR_ON() REG32(FB0_CFG) = 0x01
/* Supervisor mode ends, following functions will be done in User mode */
#define IFX_SUPERVISOR_OFF() REG32(FB0_CFG) = 0x00
/* Supervisor mode ends, following functions will be done in User mode */
#define IFX_SUPERVISOR_MODE() REG32(FB0_CFG)
/* Supervisor mode ends, following functions will be done in User mode */
#define IFX_SUPERVISOR_SET(svm) REG32(FB0_CFG) = svm
/* enable all Interrupts in IIU */
//#define IFX_ENABLE_IRQ(irq_mask, im_base) REG32(im_base | IIU_MASK) = irq_mask
///* get all high priority interrupt bits in IIU */
//#define IFX_GET_IRQ_MASKED(im_base) REG32(im_base | IIU_IRMASKED)
///* signal ends of interrupt to IIU */
//#define IFX_CLEAR_DIRECT_IRQ(irq_bit, im_base) REG32(im_base | IIU_IR) = irq_bit
///* force IIU interrupt register */
//#define IFX_FORCE_IIU_REGISTER(data, im_base) REG32(im_base | IIU_IRDEBUG) = data
///* get all bits of interrupt register */
//#define IFX_GET_IRQ_UNMASKED(im_base) REG32(im_base | IIU_IR)
/* insert a NOP instruction */
#define NOP _nop()
/* CPU goes to power down mode until interrupt occurs */
#define IFX_CPU_SLEEP _sleep()
/* enable all interrupts to CPU */
#define IFX_CPU_ENABLE_ALL_INTERRUPT sys_enable_int()
/* get all low priority interrupt bits in peripheral */
#define IFX_GET_LOW_PRIO_IRQ(int_reg) REG32(int_reg)
/* clear low priority interrupt bit in peripheral */
#define IFX_CLEAR_LOW_PRIO_IRQ(irq_bit, int_reg) REG32(int_reg) = irq_bit
/* write FPI bus */
#define WRITE_FPI_BYTE(data, addr) REG8(addr) = data
#define WRITE_FPI_16BIT(data, addr) REG16(addr) = data
#define WRITE_FPI_32BIT(data, addr) REG32(addr) = data
/* read FPI bus */
#define READ_FPI_BYTE(addr) REG8(addr)
#define READ_FPI_16BIT(addr) REG16(addr)
#define READ_FPI_32BIT(addr) REG32(addr)
/* write peripheral register */
#define WRITE_PERIPHERAL_REGISTER(data, addr) REG32(addr) = data
#ifdef CONFIG_CPU_LITTLE_ENDIAN
#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr) = data
#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr) = data
#else //not CONFIG_CPU_LITTLE_ENDIAN
#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr+2) = data
#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr+3) = data
#endif //CONFIG_CPU_LITTLE_ENDIAN
/* read peripheral register */
#define READ_PERIPHERAL_REGISTER(addr) REG32(addr)
/* read/modify(or)/write peripheral register */
#define RMW_OR_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) | data
/* read/modify(and)/write peripheral register */
#define RMW_AND_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) & (UINT32)data
/* CPU-independent mnemonic constants */
/* CLC register bits */
#define IFX_CLC_ENABLE 0x00000000
#define IFX_CLC_DISABLE 0x00000001
#define IFX_CLC_DISABLE_STATUS 0x00000002
#define IFX_CLC_SUSPEND_ENABLE 0x00000004
#define IFX_CLC_CLOCK_OFF_DISABLE 0x00000008
#define IFX_CLC_OVERWRITE_SPEN_FSOE 0x00000010
#define IFX_CLC_FAST_CLOCK_SWITCH_OFF 0x00000020
#define IFX_CLC_RUN_DIVIDER_MASK 0x0000FF00
#define IFX_CLC_RUN_DIVIDER_OFFSET 8
#define IFX_CLC_SLEEP_DIVIDER_MASK 0x00FF0000
#define IFX_CLC_SLEEP_DIVIDER_OFFSET 16
#define IFX_CLC_SPECIFIC_DIVIDER_MASK 0x00FF0000
#define IFX_CLC_SPECIFIC_DIVIDER_OFFSET 24
/* number of cycles to wait for interrupt service routine to be called */
#define WAIT_CYCLES 50
#endif /* PERIPHERAL_DEFINITIONS_H not yet defined */

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/*
* ifx_ssc.h defines some data sructures used in ifx_ssc.c
*
* Copyright (C) 2004 Michael Schoenenborn (IFX COM TI BT)
*
*
*/
#ifndef __IFX_SSC_H
#define __IFX_SSC_H
#ifdef __KERNEL__
#include <asm/amazon/ifx_ssc_defines.h>
#endif //__KERNEL__
#define PORT_CNT 1 // assume default value
/* symbolic constants to be used in SSC routines */
// ### TO DO: bad performance
#define IFX_SSC_TXFIFO_ITL 1
#define IFX_SSC_RXFIFO_ITL 1
struct ifx_ssc_statistics{
unsigned int abortErr; /* abort error */
unsigned int modeErr; /* master/slave mode error */
unsigned int txOvErr; /* TX Overflow error */
unsigned int txUnErr; /* TX Underrun error */
unsigned int rxOvErr; /* RX Overflow error */
unsigned int rxUnErr; /* RX Underrun error */
unsigned int rxBytes;
unsigned int txBytes;
};
struct ifx_ssc_hwopts {
unsigned int AbortErrDetect :1; /* Abort Error detection (in slave mode) */
unsigned int rxOvErrDetect :1; /* Receive Overflow Error detection */
unsigned int rxUndErrDetect :1; /* Receive Underflow Error detection */
unsigned int txOvErrDetect :1; /* Transmit Overflow Error detection */
unsigned int txUndErrDetect :1; /* Transmit Underflow Error detection */
unsigned int echoMode :1; /* Echo mode */
unsigned int loopBack :1; /* Loopback mode */
unsigned int idleValue :1; /* Idle value */
unsigned int clockPolarity :1; /* Idle clock is high or low */
unsigned int clockPhase :1; /* Tx on trailing or leading edge*/
unsigned int headingControl :1; /* LSB first or MSB first */
unsigned int dataWidth :6; /* from 2 up to 32 bits */
unsigned int masterSelect :1; /* Master or Slave mode */
unsigned int modeRxTx :2; /* rx/tx mode */
unsigned int gpoCs :8; /* choose outputs to use for chip select */
unsigned int gpoInv :8; /* invert GPO outputs */
};
struct ifx_ssc_frm_opts {
bool FrameEnable; // SFCON.SFEN
unsigned int DataLength; // SFCON.DLEN
unsigned int PauseLength; // SFCON.PLEN
unsigned int IdleData; // SFCON.IDAT
unsigned int IdleClock; // SFCON.ICLK
bool StopAfterPause; // SFCON.STOP
};
struct ifx_ssc_frm_status {
bool DataBusy; // SFSTAT.DBSY
bool PauseBusy; // SFSTAT.PBSY
unsigned int DataCount; // SFSTAT.DCNT
unsigned int PauseCount; // SFSTAT.PCNT
bool EnIntAfterData; // SFCON.IBEN
bool EnIntAfterPause;// SFCON.IAEN
};
typedef struct {
char *buf;
size_t len;
} ifx_ssc_buf_item_t;
// data structures for batch execution
typedef union {
struct {
bool save_options;
} init;
ifx_ssc_buf_item_t read;
ifx_ssc_buf_item_t write;
ifx_ssc_buf_item_t rd_wr;
unsigned int set_baudrate;
struct ifx_ssc_frm_opts set_frm;
unsigned int set_gpo;
struct ifx_ssc_hwopts set_hwopts;
}ifx_ssc_batch_cmd_param;
struct ifx_ssc_batch_list {
unsigned int cmd;
ifx_ssc_batch_cmd_param cmd_param;
struct ifx_ssc_batch_list *next;
};
#ifdef __KERNEL__
#define IFX_SSC_IS_MASTER(p) ((p)->opts.masterSelect == SSC_MASTER_MODE)
struct ifx_ssc_port{
unsigned long mapbase;
struct ifx_ssc_hwopts opts;
struct ifx_ssc_statistics stats;
struct ifx_ssc_frm_status frm_status;
struct ifx_ssc_frm_opts frm_opts;
/* wait queue for ifx_ssc_read() */
wait_queue_head_t rwait, pwait;
int port_nr;
char port_is_open; /* exclusive open - boolean */
// int no_of_bits; /* number of _valid_ bits */
// int elem_size; /* shift for element (no of bytes)*/
/* buffer and pointers to the read/write position */
char *rxbuf; /* buffer for RX */
char *rxbuf_end; /* buffer end pointer for RX */
volatile char *rxbuf_ptr; /* buffer write pointer for RX */
char *txbuf; /* buffer for TX */
char *txbuf_end; /* buffer end pointer for TX */
volatile char *txbuf_ptr; /* buffer read pointer for TX */
unsigned int baud;
/* each channel has its own interrupts */
/* (transmit/receive/error/frame) */
unsigned int txirq, rxirq, errirq, frmirq;
};
/* default values for SSC configuration */
// values of CON
#define IFX_SSC_DEF_IDLE_DATA 1 /* enable */
#define IFX_SSC_DEF_BYTE_VALID_CTL 1 /* enable */
#define IFX_SSC_DEF_DATA_WIDTH 32 /* bits */
#define IFX_SSC_DEF_ABRT_ERR_DETECT 0 /* disable */
#define IFX_SSC_DEF_RO_ERR_DETECT 1 /* enable */
#define IFX_SSC_DEF_RU_ERR_DETECT 0 /* disable */
#define IFX_SSC_DEF_TO_ERR_DETECT 0 /* disable */
#define IFX_SSC_DEF_TU_ERR_DETECT 0 /* disable */
#define IFX_SSC_DEF_LOOP_BACK 0 /* disable */
#define IFX_SSC_DEF_ECHO_MODE 0 /* disable */
#define IFX_SSC_DEF_CLOCK_POLARITY 0 /* low */
#define IFX_SSC_DEF_CLOCK_PHASE 1 /* 0: shift on leading edge, latch on trailling edge, 1, otherwise */
#define IFX_SSC_DEF_HEADING_CONTROL IFX_SSC_MSB_FIRST
#define IFX_SSC_DEF_MODE_RXTX IFX_SSC_MODE_RXTX
// other values
#define IFX_SSC_DEF_MASTERSLAVE IFX_SSC_MASTER_MODE /* master */
#define IFX_SSC_DEF_BAUDRATE 1000000
#define IFX_SSC_DEF_RMC 0x10
#define IFX_SSC_DEF_TXFIFO_FL 8
#define IFX_SSC_DEF_RXFIFO_FL 1
#if 1 //TODO
#define IFX_SSC_DEF_GPO_CS 2 /* no chip select */
#define IFX_SSC_DEF_GPO_INV 0 /* no chip select */
#else
#error "what is ur Chip Select???"
#endif
#define IFX_SSC_DEF_SFCON 0 /* no serial framing */
#if 0
#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\
IFX_SSC_R_BIT | IFX_SSC_E_BIT | IFX_SSC_F_BIT
#endif
#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\
IFX_SSC_R_BIT | IFX_SSC_E_BIT
#endif /* __KERNEL__ */
// batch execution commands
#define IFX_SSC_BATCH_CMD_INIT 1
#define IFX_SSC_BATCH_CMD_READ 2
#define IFX_SSC_BATCH_CMD_WRITE 3
#define IFX_SSC_BATCH_CMD_RD_WR 4
#define IFX_SSC_BATCH_CMD_SET_BAUDRATE 5
#define IFX_SSC_BATCH_CMD_SET_HWOPTS 6
#define IFX_SSC_BATCH_CMD_SET_FRM 7
#define IFX_SSC_BATCH_CMD_SET_GPO 8
#define IFX_SSC_BATCH_CMD_FIFO_FLUSH 9
//#define IFX_SSC_BATCH_CMD_
//#define IFX_SSC_BATCH_CMD_
#define IFX_SSC_BATCH_CMD_END_EXEC 0
/* Macros to configure SSC hardware */
/* headingControl: */
#define IFX_SSC_LSB_FIRST 0
#define IFX_SSC_MSB_FIRST 1
/* dataWidth: */
#define IFX_SSC_MIN_DATA_WIDTH 2
#define IFX_SSC_MAX_DATA_WIDTH 32
/* master/slave mode select */
#define IFX_SSC_MASTER_MODE 1
#define IFX_SSC_SLAVE_MODE 0
/* rx/tx mode */
// ### TO DO: !!! ATTENTION! Hardware dependency => move to ifx_ssc_defines.h
#define IFX_SSC_MODE_RXTX 0
#define IFX_SSC_MODE_RX 1
#define IFX_SSC_MODE_TX 2
#define IFX_SSC_MODE_OFF 3
#define IFX_SSC_MODE_MASK IFX_SSC_MODE_RX | IFX_SSC_MODE_TX
/* GPO values */
#define IFX_SSC_MAX_GPO_OUT 7
#define IFX_SSC_RXREQ_BLOCK_SIZE 32768
/***********************/
/* defines for ioctl's */
/***********************/
#define IFX_SSC_IOCTL_MAGIC 'S'
/* read out the statistics */
#define IFX_SSC_STATS_READ _IOR(IFX_SSC_IOCTL_MAGIC, 1, struct ifx_ssc_statistics)
/* clear the statistics */
#define IFX_SSC_STATS_RESET _IO(IFX_SSC_IOCTL_MAGIC, 2)
/* set the baudrate */
#define IFX_SSC_BAUD_SET _IOW(IFX_SSC_IOCTL_MAGIC, 3, unsigned int)
/* get the current baudrate */
#define IFX_SSC_BAUD_GET _IOR(IFX_SSC_IOCTL_MAGIC, 4, unsigned int)
/* set hardware options */
#define IFX_SSC_HWOPTS_SET _IOW(IFX_SSC_IOCTL_MAGIC, 5, struct ifx_ssc_hwopts)
/* get the current hardware options */
#define IFX_SSC_HWOPTS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 6, struct ifx_ssc_hwopts)
/* set transmission mode */
#define IFX_SSC_RXTX_MODE_SET _IOW(IFX_SSC_IOCTL_MAGIC, 7, unsigned int)
/* get the current transmission mode */
#define IFX_SSC_RXTX_MODE_GET _IOR(IFX_SSC_IOCTL_MAGIC, 8, unsigned int)
/* abort transmission */
#define IFX_SSC_ABORT _IO(IFX_SSC_IOCTL_MAGIC, 9)
#define IFX_SSC_FIFO_FLUSH _IO(IFX_SSC_IOCTL_MAGIC, 9)
/* set general purpose outputs */
#define IFX_SSC_GPO_OUT_SET _IOW(IFX_SSC_IOCTL_MAGIC, 32, unsigned int)
/* clear general purpose outputs */
#define IFX_SSC_GPO_OUT_CLR _IOW(IFX_SSC_IOCTL_MAGIC, 33, unsigned int)
/* get general purpose outputs */
#define IFX_SSC_GPO_OUT_GET _IOR(IFX_SSC_IOCTL_MAGIC, 34, unsigned int)
/*** serial framing ***/
/* get status of serial framing */
#define IFX_SSC_FRM_STATUS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 48, struct ifx_ssc_frm_status)
/* get counter reload values and control bits */
#define IFX_SSC_FRM_CONTROL_GET _IOR(IFX_SSC_IOCTL_MAGIC, 49, struct ifx_ssc_frm_opts)
/* set counter reload values and control bits */
#define IFX_SSC_FRM_CONTROL_SET _IOW(IFX_SSC_IOCTL_MAGIC, 50, struct ifx_ssc_frm_opts)
/*** batch execution ***/
/* do batch execution */
#define IFX_SSC_BATCH_EXEC _IOW(IFX_SSC_IOCTL_MAGIC, 64, struct ifx_ssc_batch_list)
#ifdef __KERNEL__
// routines from ifx_ssc.c
// ### TO DO
/* kernel interface for read and write */
ssize_t ifx_ssc_kread(int, char *, size_t);
ssize_t ifx_ssc_kwrite(int, const char *, size_t);
#ifdef CONFIG_IFX_VP_KERNEL_TEST
void ifx_ssc_tc(void);
#endif // CONFIG_IFX_VP_KERNEL_TEST
#endif //__KERNEL__
#endif // __IFX_SSC_H

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#ifndef IFX_SSC_DEFINES_H
#define IFX_SSC_DEFINES_H
#include "ifx_peripheral_definitions.h"
/* maximum SSC FIFO size */
#define IFX_SSC_MAX_FIFO_SIZE 32
/* register map of SSC */
/* address of the Clock Control Register of the SSC */
#define IFX_SSC_CLC 0x00000000
/* IFX_SSC_CLC register is significant in bits 23 downto 8 and in bits 5, 3, 2, 0
bit 1 is hardware modified*/
#define IFX_SSC_CLC_readmask 0x00FFFFEF
#define IFX_SSC_CLC_writemask 0x00FFFF3D
#define IFX_SSC_CLC_hwmask 0x00000002
#define IFX_SSC_CLC_dontcare (IFX_SSC_CLC_readmask & IFX_SSC_CLC_writemask & ~IFX_SSC_CLC_hwmask)
/* address of Port Input Select Register of the SSC */
#define IFX_SSC_PISEL 0x00000004
/* IFX_SSC_PISEL register is significant in lowest three bits only */
#define IFX_SSC_PISEL_readmask 0x00000007
#define IFX_SSC_PISEL_writemask 0x00000007
#define IFX_SSC_PISEL_hwmask 0x00000000
#define IFX_SSC_PISEL_dontcare (IFX_SSC_PISEL_readmask & IFX_SSC_PISEL_writemask & ~IFX_SSC_PISEL_hwmask)
/* address of Identification Register of the SSC */
#define IFX_SSC_ID 0x00000008
/* IFX_SSC_ID register is significant in no bit */
#define IFX_SSC_ID_readmask 0x0000FF3F
#define IFX_SSC_ID_writemask 0x00000000
#define IFX_SSC_ID_hwmask 0x00000000
#define IFX_SSC_ID_dontcare (IFX_SSC_ID_readmask & IFX_SSC_ID_writemask & ~IFX_SSC_ID_hwmask)
/* address of the Control Register of the SSC */
#define IFX_SSC_CON 0x00000010
/* IFX_SSC_CON register is significant in bits 23:22, 20:16 and 12:0 */
#define IFX_SSC_CON_readmask 0x01DF1FFF
#define IFX_SSC_CON_writemask 0x01DF1FFF
#define IFX_SSC_CON_hwmask 0x00000000
#define IFX_SSC_CON_dontcare (IFX_SSC_CON_readmask & IFX_SSC_CON_writemask & ~IFX_SSC_CON_hwmask)
/* address of the Status Register of the SSC */
#define IFX_SSC_STATE 0x00000014
/* IFX_SSC_STATE register is readable in bits 30:28, 26:24, 20:16, 12:7 and 2:0
all bits except 1:0 are hardware modified */
#define IFX_SSC_STATE_readmask 0x771F3F87
#define IFX_SSC_STATE_writemask 0x00000000
#define IFX_SSC_STATE_hwmask 0x771F3F84
#define IFX_SSC_STATE_dontcare (IFX_SSC_STATE_readmask & IFX_SSC_STATE_writemask & ~IFX_SSC_STATE_hwmask)
/* address of the Write Hardware Modified Control Register Bits of the SSC */
#define IFX_SSC_WHBSTATE 0x00000018
/* IFX_SSC_WHBSTATE register is write only */
#define IFX_SSC_WHBSTATE_readmask 0x00000000
#define IFX_SSC_WHBSTATE_writemask 0x0000FFFF
#define IFX_SSC_WHBSTATE_hwmask 0x00000000
#define IFX_SSC_WHBSTATE_dontcare (IFX_SSC_WHBSTATE_readmask & IFX_SSC_WHBSTATE_writemask & ~IFX_SSC_WHBSTATE_hwmask)
/* address of the Baudrate Timer Reload Register of the SSC */
#define IFX_SSC_BR 0x00000040
/* IFX_SSC_BR register is significant in bit 15 downto 0*/
#define IFX_SSC_BR_readmask 0x0000FFFF
#define IFX_SSC_BR_writemask 0x0000FFFF
#define IFX_SSC_BR_hwmask 0x00000000
#define IFX_SSC_BR_dontcare (IFX_SSC_BR_readmask & IFX_SSC_BR_writemask & ~IFX_SSC_BR_hwmask)
/* address of the Baudrate Timer Status Register of the SSC */
#define IFX_SSC_BRSTAT 0x00000044
/* IFX_SSC_BRSTAT register is significant in bit 15 downto 0*/
#define IFX_SSC_BRSTAT_readmask 0x0000FFFF
#define IFX_SSC_BRSTAT_writemask 0x00000000
#define IFX_SSC_BRSTAT_hwmask 0x0000FFFF
#define IFX_SSC_BRSTAT_dontcare (IFX_SSC_BRSTAT_readmask & IFX_SSC_BRSTAT_writemask & ~IFX_SSC_BRSTAT_hwmask)
/* address of the Transmitter Buffer Register of the SSC */
#define IFX_SSC_TB 0x00000020
/* IFX_SSC_TB register is significant in bit 31 downto 0*/
#define IFX_SSC_TB_readmask 0xFFFFFFFF
#define IFX_SSC_TB_writemask 0xFFFFFFFF
#define IFX_SSC_TB_hwmask 0x00000000
#define IFX_SSC_TB_dontcare (IFX_SSC_TB_readmask & IFX_SSC_TB_writemask & ~IFX_SSC_TB_hwmask)
/* address of the Reciver Buffer Register of the SSC */
#define IFX_SSC_RB 0x00000024
/* IFX_SSC_RB register is significant in no bits*/
#define IFX_SSC_RB_readmask 0xFFFFFFFF
#define IFX_SSC_RB_writemask 0x00000000
#define IFX_SSC_RB_hwmask 0xFFFFFFFF
#define IFX_SSC_RB_dontcare (IFX_SSC_RB_readmask & IFX_SSC_RB_writemask & ~IFX_SSC_RB_hwmask)
/* address of the Receive FIFO Control Register of the SSC */
#define IFX_SSC_RXFCON 0x00000030
/* IFX_SSC_RXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */
#define IFX_SSC_RXFCON_readmask 0x00003F03
#define IFX_SSC_RXFCON_writemask 0x00003F03
#define IFX_SSC_RXFCON_hwmask 0x00000000
#define IFX_SSC_RXFCON_dontcare (IFX_SSC_RXFCON_readmask & IFX_SSC_RXFCON_writemask & ~IFX_SSC_RXFCON_hwmask)
/* address of the Transmit FIFO Control Register of the SSC */
#define IFX_SSC_TXFCON 0x00000034
/* IFX_SSC_TXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */
#define IFX_SSC_TXFCON_readmask 0x00003F03
#define IFX_SSC_TXFCON_writemask 0x00003F03
#define IFX_SSC_TXFCON_hwmask 0x00000000
#define IFX_SSC_TXFCON_dontcare (IFX_SSC_TXFCON_readmask & IFX_SSC_TXFCON_writemask & ~IFX_SSC_TXFCON_hwmask)
/* address of the FIFO Status Register of the SSC */
#define IFX_SSC_FSTAT 0x00000038
/* IFX_SSC_FSTAT register is significant in no bit*/
#define IFX_SSC_FSTAT_readmask 0x00003F3F
#define IFX_SSC_FSTAT_writemask 0x00000000
#define IFX_SSC_FSTAT_hwmask 0x00003F3F
#define IFX_SSC_FSTAT_dontcare (IFX_SSC_FSTAT_readmask & IFX_SSC_FSTAT_writemask & ~IFX_SSC_FSTAT_hwmask)
/* address of the Data Frame Control register of the SSC */
#define IFX_SSC_SFCON 0x00000060
#define IFX_SSC_SFCON_readmask 0xFFDFFFFD
#define IFX_SSC_SFCON_writemask 0xFFDFFFFD
#define IFX_SSC_SFCON_hwmask 0x00000000
#define IFX_SSC_SFCON_dontcare (IFX_SSC_SFCON_readmask & IFX_SSC_SFCON_writemask & ~IFX_SSC_SFCON_hwmask)
/* address of the Data Frame Status register of the SSC */
#define IFX_SSC_SFSTAT 0x00000064
#define IFX_SSC_SFSTAT_readmask 0xFFC0FFF3
#define IFX_SSC_SFSTAT_writemask 0x00000000
#define IFX_SSC_SFSTAT_hwmask 0xFFC0FFF3
#define IFX_SSC_SFSTAT_dontcare (IFX_SSC_SFSTAT_readmask & IFX_SSC_SFSTAT_writemask & ~IFX_SSC_SFSTAT_hwmask)
/* address of the General Purpose Output Control register of the SSC */
#define IFX_SSC_GPOCON 0x00000070
#define IFX_SSC_GPOCON_readmask 0x0000FFFF
#define IFX_SSC_GPOCON_writemask 0x0000FFFF
#define IFX_SSC_GPOCON_hwmask 0x00000000
#define IFX_SSC_GPOCON_dontcare (IFX_SSC_GPOCON_readmask & IFX_SSC_GPOCON_writemask & ~IFX_SSC_GPOCON_hwmask)
/* address of the General Purpose Output Status register of the SSC */
#define IFX_SSC_GPOSTAT 0x00000074
#define IFX_SSC_GPOSTAT_readmask 0x000000FF
#define IFX_SSC_GPOSTAT_writemask 0x00000000
#define IFX_SSC_GPOSTAT_hwmask 0x00000000
#define IFX_SSC_GPOSTAT_dontcare (IFX_SSC_GPOSTAT_readmask & IFX_SSC_GPOSTAT_writemask & ~IFX_SSC_GPOSTAT_hwmask)
/* address of the Force GPO Status register of the SSC */
#define IFX_SSC_WHBGPOSTAT 0x00000078
#define IFX_SSC_WHBGPOSTAT_readmask 0x00000000
#define IFX_SSC_WHBGPOSTAT_writemask 0x0000FFFF
#define IFX_SSC_WHBGPOSTAT_hwmask 0x00000000
#define IFX_SSC_WHBGPOSTAT_dontcare (IFX_SSC_WHBGPOSTAT_readmask & IFX_SSC_WHBGPOSTAT_writemask & ~IFX_SSC_WHBGPOSTAT_hwmask)
/* address of the Receive Request Register of the SSC */
#define IFX_SSC_RXREQ 0x00000080
#define IFX_SSC_RXREQ_readmask 0x0000FFFF
#define IFX_SSC_RXREQ_writemask 0x0000FFFF
#define IFX_SSC_RXREQ_hwmask 0x00000000
#define IFX_SSC_RXREQ_dontcare (IFX_SSC_RXREQ_readmask & IFX_SSC_RXREQ_writemask & ~IFX_SSC_RXREQ_hwmask)
/* address of the Receive Count Register of the SSC */
#define IFX_SSC_RXCNT 0x00000084
#define IFX_SSC_RXCNT_readmask 0x0000FFFF
#define IFX_SSC_RXCNT_writemask 0x00000000
#define IFX_SSC_RXCNT_hwmask 0x0000FFFF
#define IFX_SSC_RXCNT_dontcare (IFX_SSC_RXCNT_readmask & IFX_SSC_RXCNT_writemask & ~IFX_SSC_RXCNT_hwmask)
/* address of the DMA Configuration Register of the SSC */
#define IFX_SSC_DMACON 0x000000EC
#define IFX_SSC_DMACON_readmask 0x0000FFFF
#define IFX_SSC_DMACON_writemask 0x00000000
#define IFX_SSC_DMACON_hwmask 0x0000FFFF
#define IFX_SSC_DMACON_dontcare (IFX_SSC_DMACON_readmask & IFX_SSC_DMACON_writemask & ~IFX_SSC_DMACON_hwmask)
//------------------------------------------------------
// interrupt register for enabling interrupts, mask register of irq_reg
#define IFX_SSC_IRN_EN 0xF4
// read/write
#define IFX_SSC_IRN_EN_readmask 0x0000000F
#define IFX_SSC_IRN_EN_writemask 0x0000000F
#define IFX_SSC_IRN_EN_hwmask 0x00000000
#define IFX_SSC_IRN_EN_dontcare (IFX_SSC_IRN_EN_readmask & IFX_SSC_IRN_EN_writemask & ~IFX_SSC_IRN_EN_hwmask)
// interrupt register for accessing interrupts
#define IFX_SSC_IRN_CR 0xF8
// read/write
#define IFX_SSC_IRN_CR_readmask 0x0000000F
#define IFX_SSC_IRN_CR_writemask 0x0000000F
#define IFX_SSC_IRN_CR_hwmask 0x0000000F
#define IFX_SSC_IRN_CR_dontcare (IFX_SSC_IRN_CR_readmask & IFX_SSC_IRN_CR_writemask & ~IFX_SSC_IRN_CR_hwmask)
// interrupt register for stimulating interrupts
#define IFX_SSC_IRN_ICR 0xFC
// read/write
#define IFX_SSC_IRN_ICR_readmask 0x0000000F
#define IFX_SSC_IRN_ICR_writemask 0x0000000F
#define IFX_SSC_IRN_ICR_hwmask 0x00000000
#define IFX_SSC_IRN_ICR_dontcare (IFX_SSC_IRN_ICR_readmask & IFX_SSC_IRN_ICR_writemask & ~IFX_SSC_IRN_ICR_hwmask)
//---------------------------------------------------------------------
// Number of IRQs and bitposition of IRQ
#define IFX_SSC_NUM_IRQ 4
#define IFX_SSC_T_BIT 0x00000001
#define IFX_SSC_R_BIT 0x00000002
#define IFX_SSC_E_BIT 0x00000004
#define IFX_SSC_F_BIT 0x00000008
/* bit masks for SSC registers */
/* ID register */
#define IFX_SSC_PERID_REV_MASK 0x0000001F
#define IFX_SSC_PERID_CFG_MASK 0x00000020
#define IFX_SSC_PERID_ID_MASK 0x0000FF00
#define IFX_SSC_PERID_REV_OFFSET 0
#define IFX_SSC_PERID_CFG_OFFSET 5
#define IFX_SSC_PERID_ID_OFFSET 8
#define IFX_SSC_PERID_ID 0x45
#define IFX_SSC_PERID_DMA_ON 0x00000020
#define IFX_SSC_PERID_RXFS_MASK 0x003F0000
#define IFX_SSC_PERID_RXFS_OFFSET 16
#define IFX_SSC_PERID_TXFS_MASK 0x3F000000
#define IFX_SSC_PERID_TXFS_OFFSET 24
/* PISEL register */
#define IFX_SSC_PISEL_MASTER_IN_A 0x0000
#define IFX_SSC_PISEL_MASTER_IN_B 0x0001
#define IFX_SSC_PISEL_SLAVE_IN_A 0x0000
#define IFX_SSC_PISEL_SLAVE_IN_B 0x0002
#define IFX_SSC_PISEL_CLOCK_IN_A 0x0000
#define IFX_SSC_PISEL_CLOCK_IN_B 0x0004
/* IFX_SSC_CON register */
#define IFX_SSC_CON_ECHO_MODE_ON 0x01000000
#define IFX_SSC_CON_ECHO_MODE_OFF 0x00000000
#define IFX_SSC_CON_IDLE_HIGH 0x00800000
#define IFX_SSC_CON_IDLE_LOW 0x00000000
#define IFX_SSC_CON_ENABLE_BYTE_VALID 0x00400000
#define IFX_SSC_CON_DISABLE_BYTE_VALID 0x00000000
#define IFX_SSC_CON_DATA_WIDTH_OFFSET 16
#define IFX_SSC_CON_DATA_WIDTH_MASK 0x001F0000
#define IFX_SSC_ENCODE_DATA_WIDTH(width) (((width - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET) & IFX_SSC_CON_DATA_WIDTH_MASK)
#define IFX_SSC_CON_RESET_ON_BAUDERR 0x00002000
#define IFX_SSC_CON_GO_ON_ON_BAUDERR 0x00000000
#define IFX_SSC_CON_RX_UFL_CHECK 0x00001000
#define IFX_SSC_CON_RX_UFL_IGNORE 0x00000000
#define IFX_SSC_CON_TX_UFL_CHECK 0x00000800
#define IFX_SSC_CON_TX_UFL_IGNORE 0x00000000
#define IFX_SSC_CON_ABORT_ERR_CHECK 0x00000400
#define IFX_SSC_CON_ABORT_ERR_IGNORE 0x00000000
#define IFX_SSC_CON_RX_OFL_CHECK 0x00000200
#define IFX_SSC_CON_RX_OFL_IGNORE 0x00000000
#define IFX_SSC_CON_TX_OFL_CHECK 0x00000100
#define IFX_SSC_CON_TX_OFL_IGNORE 0x00000000
#define IFX_SSC_CON_ALL_ERR_CHECK 0x00001F00
#define IFX_SSC_CON_ALL_ERR_IGNORE 0x00000000
#define IFX_SSC_CON_LOOPBACK_MODE 0x00000080
#define IFX_SSC_CON_NO_LOOPBACK 0x00000000
#define IFX_SSC_CON_HALF_DUPLEX 0x00000080
#define IFX_SSC_CON_FULL_DUPLEX 0x00000000
#define IFX_SSC_CON_CLOCK_FALL 0x00000040
#define IFX_SSC_CON_CLOCK_RISE 0x00000000
#define IFX_SSC_CON_SHIFT_THEN_LATCH 0x00000000
#define IFX_SSC_CON_LATCH_THEN_SHIFT 0x00000020
#define IFX_SSC_CON_MSB_FIRST 0x00000010
#define IFX_SSC_CON_LSB_FIRST 0x00000000
#define IFX_SSC_CON_ENABLE_CSB 0x00000008
#define IFX_SSC_CON_DISABLE_CSB 0x00000000
#define IFX_SSC_CON_INVERT_CSB 0x00000004
#define IFX_SSC_CON_TRUE_CSB 0x00000000
#define IFX_SSC_CON_RX_OFF 0x00000002
#define IFX_SSC_CON_RX_ON 0x00000000
#define IFX_SSC_CON_TX_OFF 0x00000001
#define IFX_SSC_CON_TX_ON 0x00000000
/* IFX_SSC_STATE register */
#define IFX_SSC_STATE_RX_BYTE_VALID_OFFSET 28
#define IFX_SSC_STATE_RX_BYTE_VALID_MASK 0x70000000
#define IFX_SSC_DECODE_RX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET)
#define IFX_SSC_STATE_TX_BYTE_VALID_OFFSET 24
#define IFX_SSC_STATE_TX_BYTE_VALID_MASK 0x07000000
#define IFX_SSC_DECODE_TX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_TX_BYTE_VALID_MASK) >> IFX_SSC_STATE_TX_BYTE_VALID_OFFSET)
#define IFX_SSC_STATE_BIT_COUNT_OFFSET 16
#define IFX_SSC_STATE_BIT_COUNT_MASK 0x001F0000
#define IFX_SSC_DECODE_DATA_WIDTH(con_state) (((con_state & IFX_SSC_STATE_BIT_COUNT_MASK) >> IFX_SSC_STATE_BIT_COUNT_OFFSET) + 1)
#define IFX_SSC_STATE_BUSY 0x00002000
#define IFX_SSC_STATE_RX_UFL 0x00001000
#define IFX_SSC_STATE_TX_UFL 0x00000800
#define IFX_SSC_STATE_ABORT_ERR 0x00000400
#define IFX_SSC_STATE_RX_OFL 0x00000200
#define IFX_SSC_STATE_TX_OFL 0x00000100
#define IFX_SSC_STATE_MODE_ERR 0x00000080
#define IFX_SSC_STATE_SLAVE_IS_SELECTED 0x00000004
#define IFX_SSC_STATE_IS_MASTER 0x00000002
#define IFX_SSC_STATE_IS_ENABLED 0x00000001
/* WHBSTATE register */
#define IFX_SSC_WHBSTATE_DISABLE_SSC 0x0001
#define IFX_SSC_WHBSTATE_CONFIGURATION_MODE 0x0001
#define IFX_SSC_WHBSTATE_CLR_ENABLE 0x0001
#define IFX_SSC_WHBSTATE_ENABLE_SSC 0x0002
#define IFX_SSC_WHBSTATE_RUN_MODE 0x0002
#define IFX_SSC_WHBSTATE_SET_ENABLE 0x0002
#define IFX_SSC_WHBSTATE_SLAVE_MODE 0x0004
#define IFX_SSC_WHBSTATE_CLR_MASTER_SELECT 0x0004
#define IFX_SSC_WHBSTATE_MASTER_MODE 0x0008
#define IFX_SSC_WHBSTATE_SET_MASTER_SELECT 0x0008
#define IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR 0x0010
#define IFX_SSC_WHBSTATE_SET_RX_UFL_ERROR 0x0020
#define IFX_SSC_WHBSTATE_CLR_MODE_ERROR 0x0040
#define IFX_SSC_WHBSTATE_SET_MODE_ERROR 0x0080
#define IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR 0x0100
#define IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR 0x0200
#define IFX_SSC_WHBSTATE_CLR_ABORT_ERROR 0x0400
#define IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR 0x0800
#define IFX_SSC_WHBSTATE_SET_TX_OFL_ERROR 0x1000
#define IFX_SSC_WHBSTATE_SET_RX_OFL_ERROR 0x2000
#define IFX_SSC_WHBSTATE_SET_ABORT_ERROR 0x4000
#define IFX_SSC_WHBSTATE_SET_TX_UFL_ERROR 0x8000
#define IFX_SSC_WHBSTATE_CLR_ALL_ERROR 0x0F50
#define IFX_SSC_WHBSTATE_SET_ALL_ERROR 0xF0A0
/* BR register */
#define IFX_SSC_BR_BAUDRATE_OFFSET 0
#define IFX_SSC_BR_BAUDRATE_MASK 0xFFFF
/* BR_STAT register */
#define IFX_SSC_BRSTAT_BAUDTIMER_OFFSET 0
#define IFX_SSC_BRSTAT_BAUDTIMER_MASK 0xFFFF
/* TB register */
#define IFX_SSC_TB_DATA_OFFSET 0
#define IFX_SSC_TB_DATA_MASK 0xFFFFFFFF
/* RB register */
#define IFX_SSC_RB_DATA_OFFSET 0
#define IFX_SSC_RB_DATA_MASK 0xFFFFFFFF
/* RXFCON and TXFCON registers */
#define IFX_SSC_XFCON_FIFO_DISABLE 0x0000
#define IFX_SSC_XFCON_FIFO_ENABLE 0x0001
#define IFX_SSC_XFCON_FIFO_FLUSH 0x0002
#define IFX_SSC_XFCON_ITL_MASK 0x00003F00
#define IFX_SSC_XFCON_ITL_OFFSET 8
/* FSTAT register */
#define IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET 0
#define IFX_SSC_FSTAT_RECEIVED_WORDS_MASK 0x003F
#define IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET 8
#define IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK 0x3F00
/* GPOCON register */
#define IFX_SSC_GPOCON_INVOUT0_POS 0
#define IFX_SSC_GPOCON_INV_OUT0 0x00000001
#define IFX_SSC_GPOCON_TRUE_OUT0 0x00000000
#define IFX_SSC_GPOCON_INVOUT1_POS 1
#define IFX_SSC_GPOCON_INV_OUT1 0x00000002
#define IFX_SSC_GPOCON_TRUE_OUT1 0x00000000
#define IFX_SSC_GPOCON_INVOUT2_POS 2
#define IFX_SSC_GPOCON_INV_OUT2 0x00000003
#define IFX_SSC_GPOCON_TRUE_OUT2 0x00000000
#define IFX_SSC_GPOCON_INVOUT3_POS 3
#define IFX_SSC_GPOCON_INV_OUT3 0x00000008
#define IFX_SSC_GPOCON_TRUE_OUT3 0x00000000
#define IFX_SSC_GPOCON_INVOUT4_POS 4
#define IFX_SSC_GPOCON_INV_OUT4 0x00000010
#define IFX_SSC_GPOCON_TRUE_OUT4 0x00000000
#define IFX_SSC_GPOCON_INVOUT5_POS 5
#define IFX_SSC_GPOCON_INV_OUT5 0x00000020
#define IFX_SSC_GPOCON_TRUE_OUT5 0x00000000
#define IFX_SSC_GPOCON_INVOUT6_POS 6
#define IFX_SSC_GPOCON_INV_OUT6 0x00000040
#define IFX_SSC_GPOCON_TRUE_OUT6 0x00000000
#define IFX_SSC_GPOCON_INVOUT7_POS 7
#define IFX_SSC_GPOCON_INV_OUT7 0x00000080
#define IFX_SSC_GPOCON_TRUE_OUT7 0x00000000
#define IFX_SSC_GPOCON_INV_OUT_ALL 0x000000FF
#define IFX_SSC_GPOCON_TRUE_OUT_ALL 0x00000000
#define IFX_SSC_GPOCON_ISCSB0_POS 8
#define IFX_SSC_GPOCON_IS_CSB0 0x00000100
#define IFX_SSC_GPOCON_IS_GPO0 0x00000000
#define IFX_SSC_GPOCON_ISCSB1_POS 9
#define IFX_SSC_GPOCON_IS_CSB1 0x00000200
#define IFX_SSC_GPOCON_IS_GPO1 0x00000000
#define IFX_SSC_GPOCON_ISCSB2_POS 10
#define IFX_SSC_GPOCON_IS_CSB2 0x00000400
#define IFX_SSC_GPOCON_IS_GPO2 0x00000000
#define IFX_SSC_GPOCON_ISCSB3_POS 11
#define IFX_SSC_GPOCON_IS_CSB3 0x00000800
#define IFX_SSC_GPOCON_IS_GPO3 0x00000000
#define IFX_SSC_GPOCON_ISCSB4_POS 12
#define IFX_SSC_GPOCON_IS_CSB4 0x00001000
#define IFX_SSC_GPOCON_IS_GPO4 0x00000000
#define IFX_SSC_GPOCON_ISCSB5_POS 13
#define IFX_SSC_GPOCON_IS_CSB5 0x00002000
#define IFX_SSC_GPOCON_IS_GPO5 0x00000000
#define IFX_SSC_GPOCON_ISCSB6_POS 14
#define IFX_SSC_GPOCON_IS_CSB6 0x00004000
#define IFX_SSC_GPOCON_IS_GPO6 0x00000000
#define IFX_SSC_GPOCON_ISCSB7_POS 15
#define IFX_SSC_GPOCON_IS_CSB7 0x00008000
#define IFX_SSC_GPOCON_IS_GPO7 0x00000000
#define IFX_SSC_GPOCON_IS_CSB_ALL 0x0000FF00
#define IFX_SSC_GPOCON_IS_GPO_ALL 0x00000000
/* GPOSTAT register */
#define IFX_SSC_GPOSTAT_OUT0 0x00000001
#define IFX_SSC_GPOSTAT_OUT1 0x00000002
#define IFX_SSC_GPOSTAT_OUT2 0x00000004
#define IFX_SSC_GPOSTAT_OUT3 0x00000008
#define IFX_SSC_GPOSTAT_OUT4 0x00000010
#define IFX_SSC_GPOSTAT_OUT5 0x00000020
#define IFX_SSC_GPOSTAT_OUT6 0x00000040
#define IFX_SSC_GPOSTAT_OUT7 0x00000080
#define IFX_SSC_GPOSTAT_OUT_ALL 0x000000FF
/* WHBGPOSTAT register */
#define IFX_SSC_WHBGPOSTAT_CLROUT0_POS 0
#define IFX_SSC_WHBGPOSTAT_CLR_OUT0 0x00000001
#define IFX_SSC_WHBGPOSTAT_CLROUT1_POS 1
#define IFX_SSC_WHBGPOSTAT_CLR_OUT1 0x00000002
#define IFX_SSC_WHBGPOSTAT_CLROUT2_POS 2
#define IFX_SSC_WHBGPOSTAT_CLR_OUT2 0x00000004
#define IFX_SSC_WHBGPOSTAT_CLROUT3_POS 3
#define IFX_SSC_WHBGPOSTAT_CLR_OUT3 0x00000008
#define IFX_SSC_WHBGPOSTAT_CLROUT4_POS 4
#define IFX_SSC_WHBGPOSTAT_CLR_OUT4 0x00000010
#define IFX_SSC_WHBGPOSTAT_CLROUT5_POS 5
#define IFX_SSC_WHBGPOSTAT_CLR_OUT5 0x00000020
#define IFX_SSC_WHBGPOSTAT_CLROUT6_POS 6
#define IFX_SSC_WHBGPOSTAT_CLR_OUT6 0x00000040
#define IFX_SSC_WHBGPOSTAT_CLROUT7_POS 7
#define IFX_SSC_WHBGPOSTAT_CLR_OUT7 0x00000080
#define IFX_SSC_WHBGPOSTAT_CLR_OUT_ALL 0x000000FF
#define IFX_SSC_WHBGPOSTAT_OUT0_POS 0
#define IFX_SSC_WHBGPOSTAT_OUT1_POS 1
#define IFX_SSC_WHBGPOSTAT_OUT2_POS 2
#define IFX_SSC_WHBGPOSTAT_OUT3_POS 3
#define IFX_SSC_WHBGPOSTAT_OUT4_POS 4
#define IFX_SSC_WHBGPOSTAT_OUT5_POS 5
#define IFX_SSC_WHBGPOSTAT_OUT6_POS 6
#define IFX_SSC_WHBGPOSTAT_OUT7_POS 7
#define IFX_SSC_WHBGPOSTAT_SETOUT0_POS 8
#define IFX_SSC_WHBGPOSTAT_SET_OUT0 0x00000100
#define IFX_SSC_WHBGPOSTAT_SETOUT1_POS 9
#define IFX_SSC_WHBGPOSTAT_SET_OUT1 0x00000200
#define IFX_SSC_WHBGPOSTAT_SETOUT2_POS 10
#define IFX_SSC_WHBGPOSTAT_SET_OUT2 0x00000400
#define IFX_SSC_WHBGPOSTAT_SETOUT3_POS 11
#define IFX_SSC_WHBGPOSTAT_SET_OUT3 0x00000800
#define IFX_SSC_WHBGPOSTAT_SETOUT4_POS 12
#define IFX_SSC_WHBGPOSTAT_SET_OUT4 0x00001000
#define IFX_SSC_WHBGPOSTAT_SETOUT5_POS 13
#define IFX_SSC_WHBGPOSTAT_SET_OUT5 0x00002000
#define IFX_SSC_WHBGPOSTAT_SETOUT6_POS 14
#define IFX_SSC_WHBGPOSTAT_SET_OUT6 0x00004000
#define IFX_SSC_WHBGPOSTAT_SETOUT7_POS 15
#define IFX_SSC_WHBGPOSTAT_SET_OUT7 0x00008000
#define IFX_SSC_WHBGPOSTAT_SET_OUT_ALL 0x0000FF00
/* SFCON register */
#define IFX_SSC_SFCON_SF_ENABLE 0x00000001
#define IFX_SSC_SFCON_SF_DISABLE 0x00000000
#define IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE 0x00000004
#define IFX_SSC_SFCON_FIR_DISABLE_BEFORE_PAUSE 0x00000000
#define IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE 0x00000008
#define IFX_SSC_SFCON_FIR_DISABLE_AFTER_PAUSE 0x00000000
#define IFX_SSC_SFCON_DATA_LENGTH_MASK 0x0000FFF0
#define IFX_SSC_SFCON_DATA_LENGTH_OFFSET 4
#define IFX_SSC_SFCON_PAUSE_DATA_MASK 0x00030000
#define IFX_SSC_SFCON_PAUSE_DATA_OFFSET 16
#define IFX_SSC_SFCON_PAUSE_DATA_0 0x00000000
#define IFX_SSC_SFCON_PAUSE_DATA_1 0x00010000
#define IFX_SSC_SFCON_PAUSE_DATA_IDLE 0x00020000
#define IFX_SSC_SFCON_PAUSE_CLOCK_MASK 0x000C0000
#define IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET 18
#define IFX_SSC_SFCON_PAUSE_CLOCK_0 0x00000000
#define IFX_SSC_SFCON_PAUSE_CLOCK_1 0x00040000
#define IFX_SSC_SFCON_PAUSE_CLOCK_IDLE 0x00080000
#define IFX_SSC_SFCON_PAUSE_CLOCK_RUN 0x000C0000
#define IFX_SSC_SFCON_STOP_AFTER_PAUSE 0x00100000
#define IFX_SSC_SFCON_CONTINUE_AFTER_PAUSE 0x00000000
#define IFX_SSC_SFCON_PAUSE_LENGTH_MASK 0xFFC00000
#define IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET 22
#define IFX_SSC_SFCON_DATA_LENGTH_MAX 4096
#define IFX_SSC_SFCON_PAUSE_LENGTH_MAX 1024
#define IFX_SSC_SFCON_EXTRACT_DATA_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET)
#define IFX_SSC_SFCON_EXTRACT_PAUSE_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET)
#define IFX_SSC_SFCON_SET_DATA_LENGTH(value) ((value << IFX_SSC_SFCON_DATA_LENGTH_OFFSET) & IFX_SSC_SFCON_DATA_LENGTH_MASK)
#define IFX_SSC_SFCON_SET_PAUSE_LENGTH(value) ((value << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) & IFX_SSC_SFCON_PAUSE_LENGTH_MASK)
/* SFSTAT register */
#define IFX_SSC_SFSTAT_IN_DATA 0x00000001
#define IFX_SSC_SFSTAT_IN_PAUSE 0x00000002
#define IFX_SSC_SFSTAT_DATA_COUNT_MASK 0x0000FFF0
#define IFX_SSC_SFSTAT_DATA_COUNT_OFFSET 4
#define IFX_SSC_SFSTAT_PAUSE_COUNT_MASK 0xFFF00000
#define IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET 20
#define IFX_SSC_SFSTAT_EXTRACT_DATA_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET)
#define IFX_SSC_SFSTAT_EXTRACT_PAUSE_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET)
/* RXREQ register */
#define IFX_SSC_RXREQ_RXCOUNT_MASK 0x0000FFFF
#define IFX_SSC_RXREQ_RXCOUNT_OFFSET 0
/* RXCNT register */
#define IFX_SSC_RXCNT_TODO_MASK 0x0000FFFF
#define IFX_SSC_RXCNT_TODO_OFFSET 0
/* DMACON register */
#define IFX_SSC_DMACON_RXON 0x00000001
#define IFX_SSC_DMACON_RXOFF 0x00000000
#define IFX_SSC_DMACON_TXON 0x00000002
#define IFX_SSC_DMACON_TXOFF 0x00000000
#define IFX_SSC_DMACON_DMAON 0x00000003
#define IFX_SSC_DMACON_DMAOFF 0x00000000
#define IFX_SSC_DMACON_CLASS_MASK 0x0000000C
#define IFX_SSC_DMACON_CLASS_OFFSET 2
/* register access macros */
#define ifx_ssc_fstat_received_words(status) (status & 0x003F)
#define ifx_ssc_fstat_words_to_transmit(status) ((status & 0x3F00) >> 8)
#define ifx_ssc_change_status(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_WHBSTATE))
#define ifx_ssc_set_config(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_CON))
#define ifx_ssc_get_config(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_CON))
#define ifx_ssc_get_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_STATE))
#define ifx_ssc_receive(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_RB))
#define ifx_ssc_transmit(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_TB))
#define ifx_ssc_fifo_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_FSTAT))
#define ifx_ssc_set_baudrate(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_BR))
#define ifx_ssc_extract_rx_fifo_size(id) ((id & IFX_SSC_PERID_RXFS_MASK) >> IFX_SSC_PERID_RXFS_OFFSET)
#define ifx_ssc_extract_tx_fifo_size(id) ((id & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
#endif

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/* irq.h - AMAZON interrupts */
#ifndef __AMAZON_IRQ
#define __AMAZON_IRQ
/************************************************************************
* Interrupt information
*************************************************************************/
/* these vectors are to handle the interrupts from the internal AMAZON
interrupt controller. THe INT_NUM values are really just indices into
an array and are set up so that we can use the INT_NUM as a shift
to calculate a mask value. */
#define INT_NUM_IRQ0 8
#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
#define INT_NUM_IM0_IRL1 (INT_NUM_IRQ0 + 1)
#define INT_NUM_IM0_IRL2 (INT_NUM_IRQ0 + 2)
#define INT_NUM_IM0_IRL3 (INT_NUM_IRQ0 + 3)
#define INT_NUM_IM0_IRL4 (INT_NUM_IRQ0 + 4)
#define INT_NUM_IM0_IRL5 (INT_NUM_IRQ0 + 5)
#define INT_NUM_IM0_IRL6 (INT_NUM_IRQ0 + 6)
#define INT_NUM_IM0_IRL7 (INT_NUM_IRQ0 + 7)
#define INT_NUM_IM0_IRL8 (INT_NUM_IRQ0 + 8)
#define INT_NUM_IM0_IRL9 (INT_NUM_IRQ0 + 9)
#define INT_NUM_IM0_IRL10 (INT_NUM_IRQ0 + 10)
#define INT_NUM_IM0_IRL11 (INT_NUM_IRQ0 + 11)
#define INT_NUM_IM0_IRL12 (INT_NUM_IRQ0 + 12)
#define INT_NUM_IM0_IRL13 (INT_NUM_IRQ0 + 13)
#define INT_NUM_IM0_IRL14 (INT_NUM_IRQ0 + 14)
#define INT_NUM_IM0_IRL15 (INT_NUM_IRQ0 + 15)
#define INT_NUM_IM0_IRL16 (INT_NUM_IRQ0 + 16)
#define INT_NUM_IM0_IRL17 (INT_NUM_IRQ0 + 17)
#define INT_NUM_IM0_IRL18 (INT_NUM_IRQ0 + 18)
#define INT_NUM_IM0_IRL19 (INT_NUM_IRQ0 + 19)
#define INT_NUM_IM0_IRL20 (INT_NUM_IRQ0 + 20)
#define INT_NUM_IM0_IRL21 (INT_NUM_IRQ0 + 21)
#define INT_NUM_IM0_IRL22 (INT_NUM_IRQ0 + 22)
#define INT_NUM_IM0_IRL23 (INT_NUM_IRQ0 + 23)
#define INT_NUM_IM0_IRL24 (INT_NUM_IRQ0 + 24)
#define INT_NUM_IM0_IRL25 (INT_NUM_IRQ0 + 25)
#define INT_NUM_IM0_IRL26 (INT_NUM_IRQ0 + 26)
#define INT_NUM_IM0_IRL27 (INT_NUM_IRQ0 + 27)
#define INT_NUM_IM0_IRL28 (INT_NUM_IRQ0 + 28)
#define INT_NUM_IM0_IRL29 (INT_NUM_IRQ0 + 29)
#define INT_NUM_IM0_IRL30 (INT_NUM_IRQ0 + 30)
#define INT_NUM_IM0_IRL31 (INT_NUM_IRQ0 + 31)
#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32)
#define INT_NUM_IM1_IRL1 (INT_NUM_IM1_IRL0 + 1)
#define INT_NUM_IM1_IRL2 (INT_NUM_IM1_IRL0 + 2)
#define INT_NUM_IM1_IRL3 (INT_NUM_IM1_IRL0 + 3)
#define INT_NUM_IM1_IRL4 (INT_NUM_IM1_IRL0 + 4)
#define INT_NUM_IM1_IRL5 (INT_NUM_IM1_IRL0 + 5)
#define INT_NUM_IM1_IRL6 (INT_NUM_IM1_IRL0 + 6)
#define INT_NUM_IM1_IRL7 (INT_NUM_IM1_IRL0 + 7)
#define INT_NUM_IM1_IRL8 (INT_NUM_IM1_IRL0 + 8)
#define INT_NUM_IM1_IRL9 (INT_NUM_IM1_IRL0 + 9)
#define INT_NUM_IM1_IRL10 (INT_NUM_IM1_IRL0 + 10)
#define INT_NUM_IM1_IRL11 (INT_NUM_IM1_IRL0 + 11)
#define INT_NUM_IM1_IRL12 (INT_NUM_IM1_IRL0 + 12)
#define INT_NUM_IM1_IRL13 (INT_NUM_IM1_IRL0 + 13)
#define INT_NUM_IM1_IRL14 (INT_NUM_IM1_IRL0 + 14)
#define INT_NUM_IM1_IRL15 (INT_NUM_IM1_IRL0 + 15)
#define INT_NUM_IM1_IRL16 (INT_NUM_IM1_IRL0 + 16)
#define INT_NUM_IM1_IRL17 (INT_NUM_IM1_IRL0 + 17)
#define INT_NUM_IM1_IRL18 (INT_NUM_IM1_IRL0 + 18)
#define INT_NUM_IM1_IRL19 (INT_NUM_IM1_IRL0 + 19)
#define INT_NUM_IM1_IRL20 (INT_NUM_IM1_IRL0 + 20)
#define INT_NUM_IM1_IRL21 (INT_NUM_IM1_IRL0 + 21)
#define INT_NUM_IM1_IRL22 (INT_NUM_IM1_IRL0 + 22)
#define INT_NUM_IM1_IRL23 (INT_NUM_IM1_IRL0 + 23)
#define INT_NUM_IM1_IRL24 (INT_NUM_IM1_IRL0 + 24)
#define INT_NUM_IM1_IRL25 (INT_NUM_IM1_IRL0 + 25)
#define INT_NUM_IM1_IRL26 (INT_NUM_IM1_IRL0 + 26)
#define INT_NUM_IM1_IRL27 (INT_NUM_IM1_IRL0 + 27)
#define INT_NUM_IM1_IRL28 (INT_NUM_IM1_IRL0 + 28)
#define INT_NUM_IM1_IRL29 (INT_NUM_IM1_IRL0 + 29)
#define INT_NUM_IM1_IRL30 (INT_NUM_IM1_IRL0 + 30)
#define INT_NUM_IM1_IRL31 (INT_NUM_IM1_IRL0 + 31)
#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64)
#define INT_NUM_IM2_IRL1 (INT_NUM_IM2_IRL0 + 1)
#define INT_NUM_IM2_IRL2 (INT_NUM_IM2_IRL0 + 2)
#define INT_NUM_IM2_IRL3 (INT_NUM_IM2_IRL0 + 3)
#define INT_NUM_IM2_IRL4 (INT_NUM_IM2_IRL0 + 4)
#define INT_NUM_IM2_IRL5 (INT_NUM_IM2_IRL0 + 5)
#define INT_NUM_IM2_IRL6 (INT_NUM_IM2_IRL0 + 6)
#define INT_NUM_IM2_IRL7 (INT_NUM_IM2_IRL0 + 7)
#define INT_NUM_IM2_IRL8 (INT_NUM_IM2_IRL0 + 8)
#define INT_NUM_IM2_IRL9 (INT_NUM_IM2_IRL0 + 9)
#define INT_NUM_IM2_IRL10 (INT_NUM_IM2_IRL0 + 10)
#define INT_NUM_IM2_IRL11 (INT_NUM_IM2_IRL0 + 11)
#define INT_NUM_IM2_IRL12 (INT_NUM_IM2_IRL0 + 12)
#define INT_NUM_IM2_IRL13 (INT_NUM_IM2_IRL0 + 13)
#define INT_NUM_IM2_IRL14 (INT_NUM_IM2_IRL0 + 14)
#define INT_NUM_IM2_IRL15 (INT_NUM_IM2_IRL0 + 15)
#define INT_NUM_IM2_IRL16 (INT_NUM_IM2_IRL0 + 16)
#define INT_NUM_IM2_IRL17 (INT_NUM_IM2_IRL0 + 17)
#define INT_NUM_IM2_IRL18 (INT_NUM_IM2_IRL0 + 18)
#define INT_NUM_IM2_IRL19 (INT_NUM_IM2_IRL0 + 19)
#define INT_NUM_IM2_IRL20 (INT_NUM_IM2_IRL0 + 20)
#define INT_NUM_IM2_IRL21 (INT_NUM_IM2_IRL0 + 21)
#define INT_NUM_IM2_IRL22 (INT_NUM_IM2_IRL0 + 22)
#define INT_NUM_IM2_IRL23 (INT_NUM_IM2_IRL0 + 23)
#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24)
#define INT_NUM_IM2_IRL25 (INT_NUM_IM2_IRL0 + 25)
#define INT_NUM_IM2_IRL26 (INT_NUM_IM2_IRL0 + 26)
#define INT_NUM_IM2_IRL27 (INT_NUM_IM2_IRL0 + 27)
#define INT_NUM_IM2_IRL28 (INT_NUM_IM2_IRL0 + 28)
#define INT_NUM_IM2_IRL29 (INT_NUM_IM2_IRL0 + 29)
#define INT_NUM_IM2_IRL30 (INT_NUM_IM2_IRL0 + 30)
#define INT_NUM_IM2_IRL31 (INT_NUM_IM2_IRL0 + 31)
#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96)
#define INT_NUM_IM3_IRL1 (INT_NUM_IM3_IRL0 + 1)
#define INT_NUM_IM3_IRL2 (INT_NUM_IM3_IRL0 + 2)
#define INT_NUM_IM3_IRL3 (INT_NUM_IM3_IRL0 + 3)
#define INT_NUM_IM3_IRL4 (INT_NUM_IM3_IRL0 + 4)
#define INT_NUM_IM3_IRL5 (INT_NUM_IM3_IRL0 + 5)
#define INT_NUM_IM3_IRL6 (INT_NUM_IM3_IRL0 + 6)
#define INT_NUM_IM3_IRL7 (INT_NUM_IM3_IRL0 + 7)
#define INT_NUM_IM3_IRL8 (INT_NUM_IM3_IRL0 + 8)
#define INT_NUM_IM3_IRL9 (INT_NUM_IM3_IRL0 + 9)
#define INT_NUM_IM3_IRL10 (INT_NUM_IM3_IRL0 + 10)
#define INT_NUM_IM3_IRL11 (INT_NUM_IM3_IRL0 + 11)
#define INT_NUM_IM3_IRL12 (INT_NUM_IM3_IRL0 + 12)
#define INT_NUM_IM3_IRL13 (INT_NUM_IM3_IRL0 + 13)
#define INT_NUM_IM3_IRL14 (INT_NUM_IM3_IRL0 + 14)
#define INT_NUM_IM3_IRL15 (INT_NUM_IM3_IRL0 + 15)
#define INT_NUM_IM3_IRL16 (INT_NUM_IM3_IRL0 + 16)
#define INT_NUM_IM3_IRL17 (INT_NUM_IM3_IRL0 + 17)
#define INT_NUM_IM3_IRL18 (INT_NUM_IM3_IRL0 + 18)
#define INT_NUM_IM3_IRL19 (INT_NUM_IM3_IRL0 + 19)
#define INT_NUM_IM3_IRL20 (INT_NUM_IM3_IRL0 + 20)
#define INT_NUM_IM3_IRL21 (INT_NUM_IM3_IRL0 + 21)
#define INT_NUM_IM3_IRL22 (INT_NUM_IM3_IRL0 + 22)
#define INT_NUM_IM3_IRL23 (INT_NUM_IM3_IRL0 + 23)
#define INT_NUM_IM3_IRL24 (INT_NUM_IM3_IRL0 + 24)
#define INT_NUM_IM3_IRL25 (INT_NUM_IM3_IRL0 + 25)
#define INT_NUM_IM3_IRL26 (INT_NUM_IM3_IRL0 + 26)
#define INT_NUM_IM3_IRL27 (INT_NUM_IM3_IRL0 + 27)
#define INT_NUM_IM3_IRL28 (INT_NUM_IM3_IRL0 + 28)
#define INT_NUM_IM3_IRL29 (INT_NUM_IM3_IRL0 + 29)
#define INT_NUM_IM3_IRL30 (INT_NUM_IM3_IRL0 + 30)
#define INT_NUM_IM3_IRL31 (INT_NUM_IM3_IRL0 + 31)
#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
#define INT_NUM_IM4_IRL1 (INT_NUM_IM4_IRL0 + 1)
#define INT_NUM_IM4_IRL2 (INT_NUM_IM4_IRL0 + 2)
#define INT_NUM_IM4_IRL3 (INT_NUM_IM4_IRL0 + 3)
#define INT_NUM_IM4_IRL4 (INT_NUM_IM4_IRL0 + 4)
#define INT_NUM_IM4_IRL5 (INT_NUM_IM4_IRL0 + 5)
#define INT_NUM_IM4_IRL6 (INT_NUM_IM4_IRL0 + 6)
#define INT_NUM_IM4_IRL7 (INT_NUM_IM4_IRL0 + 7)
#define INT_NUM_IM4_IRL8 (INT_NUM_IM4_IRL0 + 8)
#define INT_NUM_IM4_IRL9 (INT_NUM_IM4_IRL0 + 9)
#define INT_NUM_IM4_IRL10 (INT_NUM_IM4_IRL0 + 10)
#define INT_NUM_IM4_IRL11 (INT_NUM_IM4_IRL0 + 11)
#define INT_NUM_IM4_IRL12 (INT_NUM_IM4_IRL0 + 12)
#define INT_NUM_IM4_IRL13 (INT_NUM_IM4_IRL0 + 13)
#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
#define INT_NUM_IM4_IRL15 (INT_NUM_IM4_IRL0 + 15)
#define INT_NUM_IM4_IRL16 (INT_NUM_IM4_IRL0 + 16)
#define INT_NUM_IM4_IRL17 (INT_NUM_IM4_IRL0 + 17)
#define INT_NUM_IM4_IRL18 (INT_NUM_IM4_IRL0 + 18)
#define INT_NUM_IM4_IRL19 (INT_NUM_IM4_IRL0 + 19)
#define INT_NUM_IM4_IRL20 (INT_NUM_IM4_IRL0 + 20)
#define INT_NUM_IM4_IRL21 (INT_NUM_IM4_IRL0 + 21)
#define INT_NUM_IM4_IRL22 (INT_NUM_IM4_IRL0 + 22)
#define INT_NUM_IM4_IRL23 (INT_NUM_IM4_IRL0 + 23)
#define INT_NUM_IM4_IRL24 (INT_NUM_IM4_IRL0 + 24)
#define INT_NUM_IM4_IRL25 (INT_NUM_IM4_IRL0 + 25)
#define INT_NUM_IM4_IRL26 (INT_NUM_IM4_IRL0 + 26)
#define INT_NUM_IM4_IRL27 (INT_NUM_IM4_IRL0 + 27)
#define INT_NUM_IM4_IRL28 (INT_NUM_IM4_IRL0 + 28)
#define INT_NUM_IM4_IRL29 (INT_NUM_IM4_IRL0 + 29)
#define INT_NUM_IM4_IRL30 (INT_NUM_IM4_IRL0 + 30)
#define INT_NUM_IM4_IRL31 (INT_NUM_IM4_IRL0 + 31)
/****** Interrupt Assigments ***********/
#define AMAZON_DMA_INT INT_NUM_IM0_IRL0
#define IFX_SSC_TIR INT_NUM_IM0_IRL29
#define IFX_SSC_RIR INT_NUM_IM0_IRL30
#define IFX_SSC_EIR INT_NUM_IM0_IRL31
#define AMAZON_MEI_INT INT_NUM_IM2_IRL8
#define AMAZONASC_TIR INT_NUM_IM4_IRL15/* TX interrupt */
#define AMAZONASC_RIR INT_NUM_IM4_IRL16/* RX interrupt */
#define AMAZONASC_EIR INT_NUM_IM4_IRL17/* ERROR interrupt */
#define AMAZON_TIMER6_INT INT_NUM_IM1_IRL23
#define AMAZON_SWIE_INT INT_NUM_IM3_IRL8
#define AMAZON_CBM_INT INT_NUM_IM3_IRL9
#define AMAZON_AAL5_INT INT_NUM_IM3_IRL10
#define AMAZON_HTU_INT INT_NUM_IM3_IRL11
#define AMAZON_QSB_INT INT_NUM_IM3_IRL12
#define MIPS_CPU_TIMER_IRQ 7
#endif /* __AMAZON_IRQ */

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#ifndef AMAZON_MODEL_H
#define AMAZON_MODEL_H
/******************************************************************************
Copyright (c) 2002, Infineon Technologies. All rights reserved.
No Warranty
Because the program is licensed free of charge, there is no warranty for
the program, to the extent permitted by applicable law. Except when
otherwise stated in writing the copyright holders and/or other parties
provide the program "as is" without warranty of any kind, either
expressed or implied, including, but not limited to, the implied
warranties of merchantability and fitness for a particular purpose. The
entire risk as to the quality and performance of the program is with
you. should the program prove defective, you assume the cost of all
necessary servicing, repair or correction.
In no event unless required by applicable law or agreed to in writing
will any copyright holder, or any other party who may modify and/or
redistribute the program as permitted above, be liable to you for
damages, including any general, special, incidental or consequential
damages arising out of the use or inability to use the program
(including but not limited to loss of data or data being rendered
inaccurate or losses sustained by you or third parties or a failure of
the program to operate with any other programs), even if such holder or
other party has been advised of the possibility of such damages.
******************************************************************************/
#define BOARD_SYSTEM_TYPE "AMAZON"
#define SYSTEM_MODEL_NAME "Amazon Gateway Package 3.2 Version"
#endif

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/*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* port.h
*
* Global Amazon port driver header file
*
*/
/* Modification history */
/* 21Jun2004 btxu Generate from Inca_IP project */
#ifndef PORT_H
#define PORT_H
struct amazon_port_ioctl_parm {
int port;
int pin;
int value;
};
#define AMAZON_PORT_IOC_MAGIC 0xbf
#define AMAZON_PORT_IOCOD _IOW( AMAZON_PORT_IOC_MAGIC,0,struct amazon_port_ioctl_parm)
#define AMAZON_PORT_IOCPUDSEL _IOW( AMAZON_PORT_IOC_MAGIC,1,struct amazon_port_ioctl_parm)
#define AMAZON_PORT_IOCPUDEN _IOW( AMAZON_PORT_IOC_MAGIC,2,struct amazon_port_ioctl_parm)
#define AMAZON_PORT_IOCSTOFF _IOW( AMAZON_PORT_IOC_MAGIC,3,struct amazon_port_ioctl_parm)
#define AMAZON_PORT_IOCDIR _IOW( AMAZON_PORT_IOC_MAGIC,4,struct amazon_port_ioctl_parm)
#define AMAZON_PORT_IOCOUTPUT _IOW( AMAZON_PORT_IOC_MAGIC,5,struct amazon_port_ioctl_parm)
#define AMAZON_PORT_IOCINPUT _IOWR(AMAZON_PORT_IOC_MAGIC,6,struct amazon_port_ioctl_parm)
#define AMAZON_PORT_IOCALTSEL0 _IOW( AMAZON_PORT_IOC_MAGIC,7,struct amazon_port_ioctl_parm)
#define AMAZON_PORT_IOCALTSEL1 _IOW( AMAZON_PORT_IOC_MAGIC,8,struct amazon_port_ioctl_parm)
int amazon_port_reserve_pin(int port, int pin, int module_id);
int amazon_port_free_pin(int port, int pin, int module_id);
int amazon_port_set_open_drain(int port, int pin, int module_id);
int amazon_port_clear_open_drain(int port, int pin, int module_id);
int amazon_port_set_pudsel(int port, int pin, int module_id);
int amazon_port_clear_pudsel(int port, int pin, int module_id);
int amazon_port_set_puden(int port, int pin, int module_id);
int amazon_port_clear_puden(int port, int pin, int module_id);
int amazon_port_set_stoff(int port, int pin, int module_id);
int amazon_port_clear_stoff(int port, int pin, int module_id);
int amazon_port_set_dir_out(int port, int pin, int module_id);
int amazon_port_set_dir_in(int port, int pin, int module_id);
int amazon_port_set_output(int port, int pin, int module_id);
int amazon_port_clear_output(int port, int pin, int module_id);
int amazon_port_get_input(int port, int pin, int module_id);
int amazon_port_set_altsel0(int port, int pin, int module_id);
int amazon_port_clear_altsel0(int port, int pin, int module_id);
int amazon_port_set_altsel1(int port, int pin, int module_id);
int amazon_port_clear_altsel1(int port, int pin, int module_id);
#endif /* PORT_H */

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/* incaAscSio.h - (AMAZON) ASC UART tty driver header */
#ifndef __AMAZON_ASC_H
#define __AMAZON_ASC_H
/* channel operating modes */
#define ASCOPT_CSIZE 0x00000003
#define ASCOPT_CS7 0x00000001
#define ASCOPT_CS8 0x00000002
#define ASCOPT_PARENB 0x00000004
#define ASCOPT_STOPB 0x00000008
#define ASCOPT_PARODD 0x00000010
#define ASCOPT_CREAD 0x00000020
#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
/* ASC input select (0 or 1) */
#define CONSOLE_TTY 0
/* use fractional divider for baudrate settings */
#define AMAZONASC_USE_FDV
#ifdef AMAZONASC_USE_FDV
#define AMAZONASC_FDV_LOW_BAUDRATE 71
#ifdef CONFIG_USE_IKOS
#define AMAZONASC_FDV_HIGH_BAUDRATE 443
#else
#define AMAZONASC_FDV_HIGH_BAUDRATE 498
#endif //CONFIG_USE_IKOS
#endif /*AMAZONASC_USE_FDV*/
#define AMAZONASC_TXFIFO_FL 1
#define AMAZONASC_RXFIFO_FL 1
#define AMAZONASC_TXFIFO_FULL 16
/* interrupt lines masks for the ASC device interrupts*/
/* change these macroses if it's necessary */
#define AMAZONASC_IRQ_LINE_ALL 0x000F0000 /* all IRQs */
#define AMAZONASC_IRQ_LINE_TIR 0x00010000 /* TIR - Tx */
#define AMAZONASC_IRQ_LINE_RIR 0x00020000 /* RIR - Rx */
#define AMAZONASC_IRQ_LINE_EIR 0x00040000 /* EIR - Err */
#define AMAZONASC_IRQ_LINE_TBIR 0x00080000 /* TBIR - Tx Buf*/
/* CLC register's bits and bitfields */
#define ASCCLC_DISR 0x00000001
#define ASCCLC_DISS 0x00000002
#define ASCCLC_RMCMASK 0x0000FF00
#define ASCCLC_RMCOFFSET 8
/* CON register's bits and bitfields */
#define ASCCON_MODEMASK 0x0007
#define ASCCON_M_8SYNC 0x0
#define ASCCON_M_8ASYNC 0x1
#define ASCCON_M_8IRDAASYNC 0x2
#define ASCCON_M_7ASYNCPAR 0x3
#define ASCCON_M_9ASYNC 0x4
#define ASCCON_M_8WAKEUPASYNC 0x5
#define ASCCON_M_8ASYNCPAR 0x7
#define ASCCON_STP 0x0008
#define ASCCON_REN 0x0010
#define ASCCON_PEN 0x0020
#define ASCCON_FEN 0x0040
#define ASCCON_OEN 0x0080
#define ASCCON_PE 0x0100
#define ASCCON_FE 0x0200
#define ASCCON_OE 0x0400
#define ASCCON_FDE 0x0800
#define ASCCON_ODD 0x1000
#define ASCCON_BRS 0x2000
#define ASCCON_LB 0x4000
#define ASCCON_R 0x8000
#define ASCCON_ANY (ASCCON_PE|ASCCON_FE|ASCCON_OE)
/* WHBCON register's bits and bitfields */
#define ASCWHBCON_CLRREN 0x0010
#define ASCWHBCON_SETREN 0x0020
#define ASCWHBCON_CLRPE 0x0100
#define ASCWHBCON_CLRFE 0x0200
#define ASCWHBCON_CLROE 0x0400
#define ASCWHBCON_SETPE 0x0800
#define ASCWHBCON_SETFE 0x1000
#define ASCWHBCON_SETOE 0x2000
/* ABCON register's bits and bitfields */
#define ASCABCON_ABEN 0x0001
#define ASCABCON_AUREN 0x0002
#define ASCABCON_ABSTEN 0x0004
#define ASCABCON_ABDETEN 0x0008
#define ASCABCON_FCDETEN 0x0010
#define ASCABCON_EMMASK 0x0300
#define ASCABCON_EMOFF 8
#define ASCABCON_EM_DISAB 0x0
#define ASCABCON_EM_DURAB 0x1
#define ASCABCON_EM_ALWAYS 0x2
#define ASCABCON_TXINV 0x0400
#define ASCABCON_RXINV 0x0800
/* FDV register mask, offset and bitfields*/
#define ASCFDV_VALUE_MASK 0x000001FF
/* WHBABCON register's bits and bitfields */
#define ASCWHBABCON_SETABEN 0x0001
#define ASCWHBABCON_CLRABEN 0x0002
/* ABSTAT register's bits and bitfields */
#define ASCABSTAT_FCSDET 0x0001
#define ASCABSTAT_FCCDET 0x0002
#define ASCABSTAT_SCSDET 0x0004
#define ASCABSTAT_SCCDET 0x0008
#define ASCABSTAT_DETWAIT 0x0010
/* WHBABSTAT register's bits and bitfields */
#define ASCWHBABSTAT_CLRFCSDET 0x0001
#define ASCWHBABSTAT_SETFCSDET 0x0002
#define ASCWHBABSTAT_CLRFCCDET 0x0004
#define ASCWHBABSTAT_SETFCCDET 0x0008
#define ASCWHBABSTAT_CLRSCSDET 0x0010
#define ASCWHBABSTAT_SETSCSDET 0x0020
#define ASCWHBABSTAT_SETSCCDET 0x0040
#define ASCWHBABSTAT_CLRSCCDET 0x0080
#define ASCWHBABSTAT_CLRDETWAIT 0x0100
#define ASCWHBABSTAT_SETDETWAIT 0x0200
/* TXFCON register's bits and bitfields */
#define ASCTXFCON_TXFEN 0x0001
#define ASCTXFCON_TXFFLU 0x0002
#define ASCTXFCON_TXTMEN 0x0004
#define ASCTXFCON_TXFITLMASK 0x3F00
#define ASCTXFCON_TXFITLOFF 8
/* RXFCON register's bits and bitfields */
#define ASCRXFCON_RXFEN 0x0001
#define ASCRXFCON_RXFFLU 0x0002
#define ASCRXFCON_RXTMEN 0x0004
#define ASCRXFCON_RXFITLMASK 0x3F00
#define ASCRXFCON_RXFITLOFF 8
/* FSTAT register's bits and bitfields */
#define ASCFSTAT_RXFFLMASK 0x003F
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8
#endif /* __AMAZON_ASC_H */

7
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#ifndef __AMAZON_IRQ_H
#define __AMAZON_IRQ_H
#define NR_IRQS 256
#include_next <irq.h>
#endif

52
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003, 2004 Ralf Baechle
*/
#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
#define __ASM_MACH_GENERIC_MANGLE_PORT_H
#define __swizzle_addr_b(port) (port)
#define __swizzle_addr_w(port) ((port) ^ 2)
#define __swizzle_addr_l(port) (port)
#define __swizzle_addr_q(port) (port)
/*
* Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
* less sane hardware forces software to fiddle with this...
*
* Regardless, if the host bus endianness mismatches that of PCI/ISA, then
* you can't have the numerical value of data and byte addresses within
* multibyte quantities both preserved at the same time. Hence two
* variations of functions: non-prefixed ones that preserve the value
* and prefixed ones that preserve byte addresses. The latters are
* typically used for moving raw data between a peripheral and memory (cf.
* string I/O functions), hence the "__mem_" prefix.
*/
#if defined(CONFIG_SWAP_IO_SPACE)
# define ioswabb(a,x) (x)
# define __mem_ioswabb(a,x) (x)
# define ioswabw(a,x) le16_to_cpu(x)
# define __mem_ioswabw(a,x) (x)
# define ioswabl(a,x) le32_to_cpu(x)
# define __mem_ioswabl(a,x) (x)
# define ioswabq(a,x) le64_to_cpu(x)
# define __mem_ioswabq(a,x) (x)
#else
# define ioswabb(a,x) (x)
# define __mem_ioswabb(a,x) (x)
# define ioswabw(a,x) (x)
# define __mem_ioswabw(a,x) cpu_to_le16(x)
# define ioswabl(a,x) (x)
# define __mem_ioswabl(a,x) cpu_to_le32(x)
# define ioswabq(a,x) (x)
# define __mem_ioswabq(a,x) cpu_to_le32(x)
#endif
#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */

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#
# Copyright (C) 2006 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/image.mk
define Image/BuildKernel
$(STAGING_DIR)/bin/lzma e $(KDIR)/vmlinux $(KDIR)/vmlinux.lzma
mkimage -A mips -O linux -T kernel -C lzma -a 0x80002000 -e \
0x80002000 \
-n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \
-d $(KDIR)/vmlinux.lzma $(KDIR)/uImage
cp $(KDIR)/uImage $(BIN_DIR)/openwrt-$(BOARD)-$(KERNEL)-uImage
endef
define Image/Build/squashfs
$(call prepare_generic_squashfs,$(BIN_DIR)/openwrt-$(BOARD)-$(KERNEL)-$(1).image)
endef
define Image/Build
cat $(KDIR)/uImage $(KDIR)/root.$(1) > $(BIN_DIR)/openwrt-$(BOARD)-$(KERNEL)-$(1).image
$(call Image/Build/$(1),$(1))
endef
$(eval $(call BuildImage))

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diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
--- linux.old/arch/mips/Kconfig 2007-02-02 23:55:52.912446784 +0100
+++ linux.dev/arch/mips/Kconfig 2007-02-03 21:50:25.262027104 +0100
@@ -145,6 +145,17 @@
note that a kernel built with this option selected will not be
able to run on normal units.
+config AMAZON
+ bool "Amazon support (EXPERIMENTAL)"
+ depends on EXPERIMENTAL
+ select DMA_NONCOHERENT
+ select IRQ_CPU
+ select SYS_HAS_CPU_MIPS32_R1
+ select HAVE_STD_PC_SERIAL_PORT
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_HAS_EARLY_PRINTK
+
config MIPS_COBALT
bool "Cobalt Server"
select DMA_NONCOHERENT
@@ -766,6 +776,7 @@
endchoice
+source "arch/mips/amazon/Kconfig"
source "arch/mips/ddb5xxx/Kconfig"
source "arch/mips/gt64120/ev64120/Kconfig"
source "arch/mips/jazz/Kconfig"
diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
--- linux.old/arch/mips/Makefile 2007-02-02 23:55:52.913446632 +0100
+++ linux.dev/arch/mips/Makefile 2007-02-03 17:40:29.193776000 +0100
@@ -267,6 +267,13 @@
load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
#
+# Infineon AMAZON
+#
+core-$(CONFIG_AMAZON) += arch/mips/amazon/
+cflags-$(CONFIG_AMAZON) += -Iinclude/asm-mips/mach-amazon
+load-$(CONFIG_AMAZON) += 0xffffffff80002000
+
+#
# Cobalt Server
#
core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
--- linux.old/include/asm-mips/bootinfo.h 2007-02-02 23:55:52.913446632 +0100
+++ linux.dev/include/asm-mips/bootinfo.h 2007-02-03 17:51:02.531494032 +0100
@@ -212,6 +212,12 @@
#define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */
#define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
+/*
+ * Valid machtype for group ATHEROS
+ */
+#define MACH_GROUP_INFINEON 27
+#define MACH_INFINEON_AMAZON 0
+
#define CL_SIZE COMMAND_LINE_SIZE
const char *get_system_type(void);

12
target/linux/amazon-2.6/patches/110-char_drivers.patch Normal file
View File

@ -0,0 +1,12 @@
Index: linux-2.6.21.5/drivers/char/Makefile
===================================================================
--- linux-2.6.21.5.orig/drivers/char/Makefile 2007-06-24 07:44:10.606341712 +0200
+++ linux-2.6.21.5/drivers/char/Makefile 2007-06-24 07:44:46.633864696 +0200
@@ -103,6 +103,7 @@
obj-$(CONFIG_HANGCHECK_TIMER) += hangcheck-timer.o
obj-$(CONFIG_TCG_TPM) += tpm/
+obj-$(CONFIG_AMAZONE_WDT) += amazone_wdt.o
# Files generated that shall be removed upon make clean
clean-files := consolemap_deftbl.c defkeymap.c

9
target/linux/amazon-2.6/patches/130-mtd_drivers.patch Normal file
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@ -0,0 +1,9 @@
Index: linux-2.6.21.5/drivers/mtd/maps/Makefile
===================================================================
--- linux-2.6.21.5.orig/drivers/mtd/maps/Makefile 2007-06-24 07:55:22.138253344 +0200
+++ linux-2.6.21.5/drivers/mtd/maps/Makefile 2007-06-24 07:56:58.207648576 +0200
@@ -72,3 +72,4 @@
obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o
obj-$(CONFIG_MTD_MTX1) += mtx-1_flash.o
obj-$(CONFIG_MTD_TQM834x) += tqm834x.o
+obj-$(CONFIG_AMAZON_MTD) += amazon.o

10
target/linux/amazon-2.6/patches/140-net_drivers.patch Normal file
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@ -0,0 +1,10 @@
Index: linux-2.6.21.5/drivers/net/Makefile
===================================================================
--- linux-2.6.21.5.orig/drivers/net/Makefile 2007-06-24 09:03:20.308277264 +0200
+++ linux-2.6.21.5/drivers/net/Makefile 2007-06-24 09:05:13.560060376 +0200
@@ -219,3 +219,5 @@
obj-$(CONFIG_FS_ENET) += fs_enet/
obj-$(CONFIG_NETXEN_NIC) += netxen/
+
+obj-$(CONFIG_AMAZON_NET_SW) += amazon_sw.o

12
target/linux/amazon-2.6/patches/150-serial_driver.patch Normal file
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@ -0,0 +1,12 @@
Index: linux-2.6.21.5/drivers/serial/Makefile
===================================================================
--- linux-2.6.21.5.orig/drivers/serial/Makefile 2007-06-24 10:51:45.005412992 +0200
+++ linux-2.6.21.5/drivers/serial/Makefile 2007-06-24 10:51:54.885910928 +0200
@@ -5,6 +5,7 @@
#
obj-$(CONFIG_SERIAL_CORE) += serial_core.o
+obj-$(CONFIG_AMAZON_ASC_UART) += amazon_asc.o
obj-$(CONFIG_SERIAL_21285) += 21285.o
obj-$(CONFIG_SERIAL_8250) += 8250.o
obj-$(CONFIG_SERIAL_8250_PNP) += 8250_pnp.o

14
target/linux/amazon-2.6/patches/160-cfi-swap.patch Normal file
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@ -0,0 +1,14 @@
--- linux-2.6.21.5/drivers/mtd/chips/cfi_cmdset_0002.c 2007-07-23 23:15:50.403369508 +0200
+++ linux-2.6.21.5.orig/drivers/mtd/chips/cfi_cmdset_0002.c 2007-07-23 23:26:43.028560499 +0200
@@ -1007,7 +1007,9 @@
int ret = 0;
map_word oldd;
int retry_cnt = 0;
-
+#ifdef CONFIG_AMAZON
+ adr ^= 2;
+#endif
adr += chip->start;
spin_lock(chip->mutex);