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lots of code cleanup for ifxmips 

SVN-Revision: 11570
owl
John Crispin 2008-06-23 20:31:34 +00:00
parent 81af6da037
commit 6e266198e9
17 changed files with 375 additions and 468 deletions
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50
target/linux/ifxmips/files/arch/mips/ifxmips/board.c
View File

@ -1,6 +1,4 @@
/*
* arch/mips/ifxmips/board.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@ -16,7 +14,6 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/autoconf.h>
@ -43,13 +40,11 @@
#define BOARD_TWINPASS "Twinpass"
#define BOARD_TWINPASS_CHIPID 0x3012D083
#define BOARD_DANUBE "Danube"
static unsigned int chiprev;
static struct platform_device *ifxmips_devs[MAX_IFXMIPS_DEVS];
static struct platform_device ifxmips_led[] =
static struct platform_device
ifxmips_led[] =
{
{
.id = 0,
@ -57,7 +52,8 @@ static struct platform_device ifxmips_led[] =
},
};
static struct platform_device ifxmips_gpio[] =
static struct platform_device
ifxmips_gpio[] =
{
{
.id = 0,
@ -65,7 +61,8 @@ static struct platform_device ifxmips_gpio[] =
},
};
static struct platform_device ifxmips_mii[] =
static struct platform_device
ifxmips_mii[] =
{
{
.id = 0,
@ -73,7 +70,8 @@ static struct platform_device ifxmips_mii[] =
},
};
static struct platform_device ifxmips_wdt[] =
static struct platform_device
ifxmips_wdt[] =
{
{
.id = 0,
@ -81,17 +79,20 @@ static struct platform_device ifxmips_wdt[] =
},
};
static struct physmap_flash_data ifxmips_mtd_data = {
static struct physmap_flash_data
ifxmips_mtd_data = {
.width = 2,
};
static struct resource ifxmips_mtd_resource = {
static struct resource
ifxmips_mtd_resource = {
.start = IFXMIPS_FLASH_START,
.end = IFXMIPS_FLASH_START + IFXMIPS_FLASH_MAX - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device ifxmips_mtd[] =
static struct platform_device
ifxmips_mtd[] =
{
{
.id = 0,
@ -105,16 +106,20 @@ static struct platform_device ifxmips_mtd[] =
};
#ifdef CONFIG_GPIO_DEVICE
static struct resource ifxmips_gpio_dev_resources[] = {
static struct resource
ifxmips_gpio_dev_resources[] = {
{
.name = "gpio",
.flags = 0,
.start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12),
.end = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12),
.start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) |
(1 << 4) | (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12),
.end = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) |
(1 << 4) | (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12),
},
};
static struct platform_device ifxmips_gpio_dev[] = {
static struct platform_device
ifxmips_gpio_dev[] = {
{
.name = "GPIODEV",
.id = -1,
@ -140,18 +145,11 @@ get_system_type (void)
return BOARD_SYSTEM_TYPE;
}
int __init ifxmips_init_devices(void)
int __init
ifxmips_init_devices(void)
{
/*
* This is where we detect what chip we are running on
* Currently we support 3 chips
* 1.) Danube
* 2.) Twinpass (Danube without dsl phy)
*/
int dev = 0;
/* the following devices are generic for all targets */
ifxmips_devs[dev++] = ifxmips_led;
ifxmips_devs[dev++] = ifxmips_gpio;
ifxmips_devs[dev++] = ifxmips_mii;

123
target/linux/ifxmips/files/arch/mips/ifxmips/cgu.c
View File

@ -1,6 +1,4 @@
/*
* arch/mips/ifxmips/cgu.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@ -16,10 +14,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2007 Xu Liang, infineon
*
* Rewrite of Infineon IFXMips code
* Copyright (C) 2008 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/kernel.h>
@ -75,9 +70,10 @@
#define CGU_IF_CLK_USBSEL GET_BITS(*IFXMIPS_CGU_IF_CLK, 5, 4)
#define CGU_IF_CLK_MIISEL GET_BITS(*IFXMIPS_CGU_IF_CLK, 1, 0)
static u32 cgu_get_pll0_fdiv(void);
static unsigned int cgu_get_pll0_fdiv(void);
static inline u32 get_input_clock(int pll)
static inline unsigned int
get_input_clock(int pll)
{
switch(pll)
{
@ -110,8 +106,8 @@ static inline u32 get_input_clock(int pll)
}
}
static inline u32
cal_dsm(int pll, u32 num, u32 den)
static inline unsigned int
cal_dsm(int pll, unsigned int num, unsigned int den)
{
u64 res, clock = get_input_clock(pll);
@ -120,32 +116,37 @@ cal_dsm(int pll, u32 num, u32 den)
return res;
}
static inline u32
mash_dsm(int pll, u32 M, u32 N, u32 K)
static inline unsigned int
mash_dsm(int pll, unsigned int M, unsigned int N, unsigned int K)
{
u32 num = ((N + 1) << 10) + K;
u32 den = (M + 1) << 10;
unsigned int num = ((N + 1) << 10) + K;
unsigned int den = (M + 1) << 10;
return cal_dsm(pll, num, den);
}
static inline u32 ssff_dsm_1(int pll, u32 M, u32 N, u32 K)
static inline unsigned int
ssff_dsm_1(int pll, unsigned int M, unsigned int N, unsigned int K)
{
u32 num = ((N + 1) << 11) + K + 512;
u32 den = (M + 1) << 11;
unsigned int num = ((N + 1) << 11) + K + 512;
unsigned int den = (M + 1) << 11;
return cal_dsm(pll, num, den);
}
static inline u32 ssff_dsm_2(int pll, u32 M, u32 N, u32 K)
static inline unsigned int
ssff_dsm_2(int pll, unsigned int M, unsigned int N, unsigned int K)
{
u32 num = K >= 512 ? ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
u32 den = (M + 1) << 12;
unsigned int num = K >= 512 ?
((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
unsigned int den = (M + 1) << 12;
return cal_dsm(pll, num, den);
}
static inline u32 dsm(int pll, u32 M, u32 N, u32 K, u32 dsmsel, u32 phase_div_en)
static inline unsigned int
dsm(int pll, unsigned int M, unsigned int N, unsigned int K,
unsigned int dsmsel, unsigned int phase_div_en)
{
if(!dsmsel)
return mash_dsm(pll, M, N, K);
@ -155,19 +156,23 @@ static inline u32 dsm(int pll, u32 M, u32 N, u32 K, u32 dsmsel, u32 phase_div_en
return ssff_dsm_2(pll, M, N, K);
}
static inline u32 cgu_get_pll0_fosc(void)
static inline unsigned int
cgu_get_pll0_fosc(void)
{
if(CGU_PLL0_BYPASS)
return get_input_clock(0);
else
return !CGU_PLL0_CFG_FRAC_EN
? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE)
: dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL,
CGU_PLL0_PHASE_DIVIDER_ENABLE)
: dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK,
CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
}
static inline u32 cgu_get_pll0_fps(int phase)
static inline unsigned int
cgu_get_pll0_fps(int phase)
{
register u32 fps = cgu_get_pll0_fosc();
register unsigned int fps = cgu_get_pll0_fosc();
switch(phase)
{
@ -183,14 +188,16 @@ static inline u32 cgu_get_pll0_fps(int phase)
return fps;
}
static u32 cgu_get_pll0_fdiv(void)
static unsigned int
cgu_get_pll0_fdiv(void)
{
register u32 div = CGU_PLL2_CFG_INPUT_DIV + 1;
register unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
return (cgu_get_pll0_fosc() + (div >> 1)) / div;
}
static inline u32 cgu_get_pll1_fosc(void)
static inline unsigned int
cgu_get_pll1_fosc(void)
{
if(CGU_PLL1_BYPASS)
return get_input_clock(1);
@ -200,19 +207,22 @@ static inline u32 cgu_get_pll1_fosc(void)
: dsm(1, CGU_PLL1_CFG_PLLM, CGU_PLL1_CFG_PLLN, CGU_PLL1_CFG_PLLK, CGU_PLL1_CFG_DSMSEL, 0);
}
static inline u32 cgu_get_pll1_fps(void)
static inline unsigned int
cgu_get_pll1_fps(void)
{
register u32 fps = cgu_get_pll1_fosc();
register unsigned int fps = cgu_get_pll1_fosc();
return ((fps << 1) + 1) / 3;
}
static inline u32 cgu_get_pll1_fdiv(void)
static inline unsigned int
cgu_get_pll1_fdiv(void)
{
return cgu_get_pll1_fosc();
}
static inline u32 cgu_get_pll2_fosc(void)
static inline unsigned int
cgu_get_pll2_fosc(void)
{
u64 res, clock = get_input_clock(2);
@ -225,9 +235,10 @@ static inline u32 cgu_get_pll2_fosc(void)
return res;
}
static inline u32 cgu_get_pll2_fps(int phase)
static inline unsigned int
cgu_get_pll2_fps(int phase)
{
register u32 fps = cgu_get_pll2_fosc();
register unsigned int fps = cgu_get_pll2_fosc();
switch ( phase )
{
@ -242,16 +253,18 @@ static inline u32 cgu_get_pll2_fps(int phase)
return fps;
}
static inline u32 cgu_get_pll2_fdiv(void)
static inline unsigned int
cgu_get_pll2_fdiv(void)
{
register u32 div = CGU_IF_CLK_PCI_CLK + 1;
register unsigned int div = CGU_IF_CLK_PCI_CLK + 1;
return (cgu_get_pll2_fosc() + (div >> 1)) / div;
}
u32 cgu_get_mips_clock(int cpu)
unsigned int
cgu_get_mips_clock(int cpu)
{
register u32 ret = cgu_get_pll0_fosc();
register u32 cpusel = cpu == 0 ? CGU_SYS_CPU0SEL : CGU_SYS_CPU1SEL;
register unsigned int ret = cgu_get_pll0_fosc();
register unsigned int cpusel = cpu == 0 ? CGU_SYS_CPU0SEL : CGU_SYS_CPU1SEL;
if(cpusel == 0)
return ret;
@ -272,14 +285,16 @@ u32 cgu_get_mips_clock(int cpu)
}
}
u32 cgu_get_cpu_clock(void)
unsigned int
cgu_get_cpu_clock(void)
{
return cgu_get_mips_clock(0);
}
u32 cgu_get_io_region_clock(void)
unsigned int
cgu_get_io_region_clock(void)
{
register u32 ret = cgu_get_pll0_fosc();
register unsigned int ret = cgu_get_pll0_fosc();
switch(CGU_SYS_DDR_SEL)
{
@ -295,9 +310,10 @@ u32 cgu_get_io_region_clock(void)
}
}
u32 cgu_get_fpi_bus_clock(int fpi)
unsigned int
cgu_get_fpi_bus_clock(int fpi)
{
register u32 ret = cgu_get_io_region_clock();
register unsigned int ret = cgu_get_io_region_clock();
if((fpi == 2) && (CGU_SYS_FPI_SEL))
ret >>= 1;
@ -305,7 +321,8 @@ u32 cgu_get_fpi_bus_clock(int fpi)
return ret;
}
u32 cgu_get_pp32_clock(void)
unsigned int
cgu_get_pp32_clock(void)
{
switch(CGU_SYS_PPESEL)
{
@ -321,7 +338,8 @@ u32 cgu_get_pp32_clock(void)
}
}
u32 cgu_get_ethernet_clock(int mii)
unsigned int
cgu_get_ethernet_clock(int mii)
{
switch(CGU_IF_CLK_MIISEL)
{
@ -337,7 +355,8 @@ u32 cgu_get_ethernet_clock(int mii)
return 0;
}
u32 cgu_get_usb_clock(void)
unsigned int
cgu_get_usb_clock(void)
{
switch(CGU_IF_CLK_USBSEL)
{
@ -353,15 +372,16 @@ u32 cgu_get_usb_clock(void)
return 0;
}
u32 cgu_get_clockout(int clkout)
unsigned int
cgu_get_clockout(int clkout)
{
u32 fosc1 = cgu_get_pll1_fosc();
u32 fosc2 = cgu_get_pll2_fosc();
unsigned int fosc1 = cgu_get_pll1_fosc();
unsigned int fosc2 = cgu_get_pll2_fosc();
if(clkout > 3 || clkout < 0)
return 0;
switch ( ((u32)clkout << 2) | GET_BITS(*IFXMIPS_CGU_IF_CLK, 15 - clkout * 2, 14 - clkout * 2) )
switch(((unsigned int)clkout << 2) | GET_BITS(*IFXMIPS_CGU_IF_CLK, 15 - clkout * 2, 14 - clkout * 2))
{
case 0: /* 32.768KHz */
case 15:
@ -391,6 +411,5 @@ u32 cgu_get_clockout(int clkout)
case 11:/* 60MHz */
return (fosc2 + 2) / 5;
}
return 0;
}

18
target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c
View File

@ -32,9 +32,9 @@
#define DMA_INT_BUDGET 100 /*budget for interrupt handling */
#define DMA_POLL_COUNTER 4 /*fix me, set the correct counter value here! */
extern void mask_and_ack_ifxmips_irq (unsigned int irq_nr);
extern void enable_ifxmips_irq (unsigned int irq_nr);
extern void disable_ifxmips_irq (unsigned int irq_nr);
extern void ifxmips_mask_and_ack_irq (unsigned int irq_nr);
extern void ifxmips_enable_irq (unsigned int irq_nr);
extern void ifxmips_disable_irq (unsigned int irq_nr);
u64 *g_desc_list;
_dma_device_info dma_devs[MAX_DMA_DEVICE_NUM];
@ -101,7 +101,7 @@ enable_ch_irq (_dma_channel_info *pCh)
ifxmips_w32(0x4a, IFXMIPS_DMA_CIE);
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
local_irq_restore(flag);
enable_ifxmips_irq(pCh->irq);
ifxmips_enable_irq(pCh->irq);
}
void
@ -116,7 +116,7 @@ disable_ch_irq (_dma_channel_info *pCh)
ifxmips_w32(0, IFXMIPS_DMA_CIE);
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);
local_irq_restore(flag);
mask_and_ack_ifxmips_irq(pCh->irq);
ifxmips_mask_and_ack_irq(pCh->irq);
}
void
@ -182,7 +182,7 @@ rx_chan_intr_handler (int chan_no)
ifxmips_w32(tmp, IFXMIPS_DMA_CS);
g_ifxmips_dma_int_status &= ~(1 << chan_no);
local_irq_restore(flag);
enable_ifxmips_irq(dma_chan[chan_no].irq);
ifxmips_enable_irq(dma_chan[chan_no].irq);
}
}
@ -276,7 +276,7 @@ dma_interrupt (int irq, void *dev_id)
ifxmips_w32(0, IFXMIPS_DMA_IRNEN);
g_ifxmips_dma_int_status |= 1 << chan_no;
ifxmips_w32(tmp, IFXMIPS_DMA_IRNEN);
mask_and_ack_ifxmips_irq(irq);
ifxmips_mask_and_ack_irq(irq);
if (!g_ifxmips_dma_in_process)
{
@ -387,7 +387,7 @@ dma_device_register(_dma_device_info *dev)
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
ifxmips_w32(0x30000, IFXMIPS_DMA_CCTRL);
local_irq_restore(flag);
enable_ifxmips_irq(dma_chan[chan_no].irq);
ifxmips_enable_irq(dma_chan[chan_no].irq);
}
}
}
@ -438,7 +438,7 @@ dma_device_unregister (_dma_device_info *dev)
{
pCh = dev->rx_chan[i];
chan_no = (int)(dev->rx_chan[i] - dma_chan);
disable_ifxmips_irq(pCh->irq);
ifxmips_disable_irq(pCh->irq);
local_irq_save(flag);
g_ifxmips_dma_int_status &= ~(1 << chan_no);

110
target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c
View File

@ -13,9 +13,10 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 infineon
* Copyright (C) 2004 btxu Generate from INCA-IP project
* Copyright (C) 2005 Jin-Sze.Sow Comments edited
* Copyright (C) 2006 Huang Xiaogang Modification & verification on Danube chip
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/module.h>
@ -43,10 +44,6 @@
#define MAX_PORTS 2
#define PINS_PER_PORT 16
#define DRVNAME "ifxmips_gpio"
static unsigned int ifxmips_gpio_major = 0;
#ifdef CONFIG_IFXMIPS_GPIO_RST_BTN
#define IFXMIPS_RST_PIN 15
#define IFXMIPS_RST_PORT 1
@ -65,18 +62,12 @@ struct event_t {
};
#endif
/* TODO do we need this ? */
static struct semaphore port_sem;
/* TODO do we really need this ? return in a define is forbidden by coding style */
#define IFXMIPS_GPIO_SANITY {if (port > MAX_PORTS || pin > PINS_PER_PORT) return -EINVAL; }
int
ifxmips_port_reserve_pin(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
printk("%s : call to obseleted function\n", __func__);
return 0;
}
EXPORT_SYMBOL(ifxmips_port_reserve_pin);
@ -86,7 +77,6 @@ ifxmips_port_free_pin (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
printk("%s : call to obseleted function\n", __func__);
return 0;
}
EXPORT_SYMBOL(ifxmips_port_free_pin);
@ -95,8 +85,8 @@ int
ifxmips_port_set_open_drain(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_OD + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_OD + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_open_drain);
@ -105,8 +95,8 @@ int
ifxmips_port_clear_open_drain(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_OD + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_OD + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_clear_open_drain);
@ -115,8 +105,8 @@ int
ifxmips_port_set_pudsel(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_pudsel);
@ -125,8 +115,8 @@ int
ifxmips_port_clear_pudsel (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_clear_pudsel);
@ -135,8 +125,8 @@ int
ifxmips_port_set_puden(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_puden);
@ -145,8 +135,8 @@ int
ifxmips_port_clear_puden(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_clear_puden);
@ -155,8 +145,8 @@ int
ifxmips_port_set_stoff(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_stoff);
@ -165,8 +155,8 @@ int
ifxmips_port_clear_stoff(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_clear_stoff);
@ -175,8 +165,8 @@ int
ifxmips_port_set_dir_out(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_DIR + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_DIR + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_dir_out);
@ -185,8 +175,8 @@ int
ifxmips_port_set_dir_in(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_DIR + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_DIR + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_dir_in);
@ -195,8 +185,8 @@ int
ifxmips_port_set_output(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_OUT + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_OUT + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_output);
@ -205,8 +195,8 @@ int
ifxmips_port_clear_output(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_OUT + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_OUT + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_clear_output);
@ -215,7 +205,6 @@ int
ifxmips_port_get_input(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
if (ifxmips_r32(IFXMIPS_GPIO_P0_IN + (port * 0xC)) & (1 << pin))
return 0;
else
@ -227,8 +216,8 @@ int
ifxmips_port_set_altsel0(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_altsel0);
@ -237,8 +226,8 @@ int
ifxmips_port_clear_altsel0(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_clear_altsel0);
@ -247,8 +236,8 @@ int
ifxmips_port_set_altsel1(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_set_altsel1);
@ -257,21 +246,23 @@ int
ifxmips_port_clear_altsel1(unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
return 0;
}
EXPORT_SYMBOL(ifxmips_port_clear_altsel1);
#ifdef CONFIG_IFXMIPS_GPIO_RST_BTN
static inline void add_msg(struct sk_buff *skb, char *msg)
static inline void
add_msg(struct sk_buff *skb, char *msg)
{
char *scratch;
scratch = skb_put(skb, strlen(msg) + 1);
sprintf(scratch, msg);
}
static void hotplug_button(struct work_struct *wq)
static void
hotplug_button(struct work_struct *wq)
{
struct sk_buff *skb;
struct event_t *event;
@ -283,18 +274,14 @@ static void hotplug_button(struct work_struct *wq)
if(!uevent_sock)
goto done;
/* allocate message with the maximum possible size */
s = event->set ? "pressed" : "released";
len = strlen(s) + 2;
skb = alloc_skb(len + 2048, GFP_KERNEL);
if(!skb)
goto done;
/* add header */
scratch = skb_put(skb, len);
sprintf(scratch, "%s@",s);
/* copy keys to our continuous event payload buffer */
add_msg(skb, "HOME=/");
add_msg(skb, "PATH=/sbin:/bin:/usr/sbin:/usr/bin");
add_msg(skb, "SUBSYSTEM=button");
@ -307,12 +294,12 @@ static void hotplug_button(struct work_struct *wq)
NETLINK_CB(skb).dst_group = 1;
netlink_broadcast(uevent_sock, skb, 0, 1, GFP_KERNEL);
done:
kfree(event);
}
static void reset_button_poll(unsigned long unused)
static void
reset_button_poll(unsigned long unused)
{
struct event_t *event;
@ -325,7 +312,7 @@ static void reset_button_poll(unsigned long unused)
pressed = 0;
else
pressed = 1;
printk("button was %s\n", (pressed ? "pressed" : "released"));
printk("reset button was %s\n", (pressed ? "pressed" : "released"));
event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC);
if (!event)
{
@ -346,24 +333,17 @@ ifxmips_gpio_probe (struct platform_device *dev)
{
int retval = 0;
sema_init (&port_sem, 1);
#ifdef CONFIG_IFXMIPS_GPIO_RST_BTN
ifxmips_port_set_open_drain(IFXMIPS_RST_PORT, IFXMIPS_RST_PIN);
ifxmips_port_clear_altsel0(IFXMIPS_RST_PORT, IFXMIPS_RST_PIN);
ifxmips_port_clear_altsel1(IFXMIPS_RST_PORT, IFXMIPS_RST_PIN);
ifxmips_port_set_dir_in(IFXMIPS_RST_PORT, IFXMIPS_RST_PIN);
seen = jiffies;
init_timer(&rst_button_timer);
rst_button_timer.function = reset_button_poll;
rst_button_timer.expires = jiffies + HZ;
add_timer(&rst_button_timer);
#endif
printk(KERN_INFO DRVNAME ": device successfully initialized #%d.\n", ifxmips_gpio_major);
return retval;
}
@ -373,8 +353,6 @@ ifxmips_gpio_remove (struct platform_device *pdev)
#ifdef CONFIG_IFXMIPS_GPIO_RST_BTN
del_timer_sync(&rst_button_timer);
#endif
unregister_chrdev(ifxmips_gpio_major, DRVNAME);
return 0;
}
@ -383,7 +361,7 @@ platform_driver ifxmips_gpio_driver = {
.probe = ifxmips_gpio_probe,
.remove = ifxmips_gpio_remove,
.driver = {
.name = DRVNAME,
.name = "ifxmips_gpio",
.owner = THIS_MODULE,
},
};
@ -393,7 +371,7 @@ ifxmips_gpio_init (void)
{
int ret = platform_driver_register(&ifxmips_gpio_driver);
if (ret)
printk(KERN_INFO DRVNAME ": Error registering platfom driver!");
printk(KERN_INFO "ifxmips_gpio : Error registering platfom driver!");
return ret;
}

2
target/linux/ifxmips/files/arch/mips/ifxmips/gptu.c
View File

@ -827,9 +827,7 @@ ifxmips_gptu_exit (void)
disable_irq (timer_dev.timer[i].irq);
free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
}
ifxmips_disable_gptu();
misc_deregister(&gptu_miscdev);
}

65
target/linux/ifxmips/files/arch/mips/ifxmips/interrupt.c
View File

@ -1,6 +1,4 @@
/*
* arch/mips/ifxmips/interrupt.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@ -16,12 +14,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 Wu Qi Ming infineon
*
* Rewrite of Infineon IFXMips code, thanks to infineon for the support,
* software and hardware
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/init.h>
@ -37,9 +30,8 @@
#include <asm/ifxmips/ifxmips_irq.h>
#include <asm/irq_cpu.h>
void
disable_ifxmips_irq (unsigned int irq_nr)
ifxmips_disable_irq(unsigned int irq_nr)
{
int i;
u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
@ -55,10 +47,10 @@ disable_ifxmips_irq (unsigned int irq_nr)
irq_nr -= INT_NUM_IM_OFFSET;
}
}
EXPORT_SYMBOL (disable_ifxmips_irq);
EXPORT_SYMBOL(ifxmips_disable_irq);
void
mask_and_ack_ifxmips_irq (unsigned int irq_nr)
ifxmips_mask_and_ack_irq(unsigned int irq_nr)
{
int i;
u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
@ -78,10 +70,10 @@ mask_and_ack_ifxmips_irq (unsigned int irq_nr)
irq_nr -= INT_NUM_IM_OFFSET;
}
}
EXPORT_SYMBOL (mask_and_ack_ifxmips_irq);
EXPORT_SYMBOL(ifxmips_mask_and_ack_irq);
void
enable_ifxmips_irq (unsigned int irq_nr)
ifxmips_enable_irq(unsigned int irq_nr)
{
int i;
u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
@ -98,32 +90,33 @@ enable_ifxmips_irq (unsigned int irq_nr)
irq_nr -= INT_NUM_IM_OFFSET;
}
}
EXPORT_SYMBOL (enable_ifxmips_irq);
EXPORT_SYMBOL(ifxmips_enable_irq);
static unsigned int
startup_ifxmips_irq (unsigned int irq)
ifxmips_startup_irq(unsigned int irq)
{
enable_ifxmips_irq (irq);
ifxmips_enable_irq(irq);
return 0;
}
static void
end_ifxmips_irq (unsigned int irq)
ifxmips_end_irq(unsigned int irq)
{
if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
enable_ifxmips_irq (irq);
ifxmips_enable_irq (irq);
}
static struct hw_interrupt_type ifxmips_irq_type = {
static struct hw_interrupt_type
ifxmips_irq_type = {
"IFXMIPS",
.startup = startup_ifxmips_irq,
.enable = enable_ifxmips_irq,
.disable = disable_ifxmips_irq,
.unmask = enable_ifxmips_irq,
.ack = end_ifxmips_irq,
.mask = disable_ifxmips_irq,
.mask_ack = mask_and_ack_ifxmips_irq,
.end = end_ifxmips_irq,
.startup = ifxmips_startup_irq,
.enable = ifxmips_enable_irq,
.disable = ifxmips_disable_irq,
.unmask = ifxmips_enable_irq,
.ack = ifxmips_end_irq,
.mask = ifxmips_disable_irq,
.mask_ack = ifxmips_mask_and_ack_irq,
.end = ifxmips_end_irq,
};
static inline int
@ -136,7 +129,6 @@ ls1bit32(unsigned long x)
".set pop \n"
: "=r" (x)
: "r" (x));
return 31 - x;
}
@ -163,7 +155,8 @@ plat_irq_dispatch (void)
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
unsigned int i;
if (pending & CAUSEF_IP7){
if(pending & CAUSEF_IP7)
{
do_IRQ(MIPS_CPU_TIMER_IRQ);
goto out;
} else {
@ -182,7 +175,8 @@ out:
return;
}
static struct irqaction cascade = {
static struct irqaction
cascade = {
.handler = no_action,
.flags = IRQF_DISABLED,
.name = "cascade",
@ -194,26 +188,15 @@ arch_init_irq(void)
int i;
for(i = 0; i < 5; i++)
{
ifxmips_w32(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
}
mips_cpu_irq_init();
for(i = 2; i <= 6; i++)
{
setup_irq(i, &cascade);
}
for(i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
{
#if 0
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
#endif
set_irq_chip_and_handler(i, &ifxmips_irq_type, handle_level_irq);
}
set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
}

3
target/linux/ifxmips/files/arch/mips/ifxmips/pmu.c
View File

@ -1,6 +1,4 @@
/*
* arch/mips/ifxmips/pmu.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@ -16,7 +14,6 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/kernel.h>

26
target/linux/ifxmips/files/arch/mips/ifxmips/prom.c
View File

@ -1,6 +1,4 @@
/*
* arch/mips/ifxmips/prom.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@ -16,12 +14,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 Wu Qi Ming infineon
*
* Rewrite of Infineon IFXMips code, thanks to infineon for the support,
* software and hardware
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/init.h>
@ -29,10 +22,9 @@
#include <asm/bootinfo.h>
#include <asm/ifxmips/ifxmips.h>
static char buf[1024];
u32 *prom_cp1_base = NULL;
u32 prom_cp1_size = 0;
unsigned int *prom_cp1_base = NULL;
unsigned int prom_cp1_size = 0;
void
prom_free_prom_memory(void)
@ -62,17 +54,15 @@ prom_printf(const char * fmt, ...)
buf_end = buf + l;
for(p = buf; p < buf_end; p++)
{
prom_putchar(*p);
}
}
u32 *prom_get_cp1_base(void)
unsigned int *prom_get_cp1_base(void)
{
return prom_cp1_base;
}
u32 prom_get_cp1_size(void)
unsigned int prom_get_cp1_size(void)
{
return prom_cp1_size;
}
@ -117,13 +107,15 @@ prom_init(void)
prom_cp1_size = 2;
memsize -= prom_cp1_size;
prom_cp1_base = (u32*)(0xA0000000 + (memsize * 1024 * 1024));
prom_cp1_base = (unsigned int*)(0xA0000000 + (memsize * 1024 * 1024));
prom_printf(KERN_INFO "Using %dMB Ram and reserving %dMB for cp1\n", memsize, prom_cp1_size);
prom_printf(KERN_INFO "Using %dMB Ram and reserving %dMB for cp1\n",
memsize, prom_cp1_size);
memsize *= 1024 * 1024;
if(!*arcs_cmdline)
strcpy(&(arcs_cmdline[0]), "console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit");
strcpy(&(arcs_cmdline[0]),
"console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit");
add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
}

8
target/linux/ifxmips/files/arch/mips/ifxmips/reset.c
View File

@ -1,6 +1,4 @@
/*
* arch/mips/ifxmips/prom.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@ -15,13 +13,7 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 infineon
*
* Rewrite of Infineon IFXMips code, thanks to infineon for the support,
* software and hardware
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/kernel.h>

33
target/linux/ifxmips/files/arch/mips/ifxmips/setup.c
View File

@ -1,6 +1,4 @@
/*
* arch/mips/ifxmips/setup.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@ -16,12 +14,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2004 peng.liu@infineon.com
*
* Rewrite of Infineon IFXMips code, thanks to infineon for the support,
* software and hardware
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#include <linux/init.h>
@ -30,21 +23,16 @@
#include <asm/traps.h>
#include <asm/cpu.h>
#include <asm/irq.h>
#include <asm/bootinfo.h>
#include <asm/ifxmips/ifxmips.h>
#include <asm/ifxmips/ifxmips_irq.h>
#include <asm/ifxmips/ifxmips_pmu.h>
#include <asm/ifxmips/ifxmips_prom.h>
static unsigned int r4k_offset; /* Amount to increment compare reg each time */
static unsigned int r4k_cur; /* What counter should be at next timer irq */
static unsigned int r4k_offset;
static unsigned int r4k_cur;
extern void ifxmips_reboot_setup(void);
void prom_printf (const char * fmt, ...);
void
__init bus_error_init (void)
{
/* nothing yet */
}
unsigned int
ifxmips_get_ddr_hz(void)
@ -82,9 +70,7 @@ ifxmips_get_fpi_hz (void)
{
unsigned int ddr_clock = ifxmips_get_ddr_hz();
if(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
{
return ddr_clock >> 1;
}
return ddr_clock;
}
EXPORT_SYMBOL(ifxmips_get_fpi_hz);
@ -96,7 +82,8 @@ ifxmips_get_cpu_ver (void)
}
EXPORT_SYMBOL(ifxmips_get_cpu_ver);
static __inline__ u32 get_counter_resolution(void)
static __inline__ u32
ifxmips_get_counter_resolution(void)
{
u32 res;
__asm__ __volatile__(
@ -125,7 +112,7 @@ ifxmips_be_handler(struct pt_regs *regs, int is_fixup)
void __init
plat_time_init(void)
{
mips_hpt_frequency = ifxmips_get_cpu_hz()/get_counter_resolution();
mips_hpt_frequency = ifxmips_get_cpu_hz() / ifxmips_get_counter_resolution();
r4k_cur = (read_c0_count() + r4k_offset);
write_c0_compare(r4k_cur);
ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT | IFXMIPS_PMU_PWDCR_FPI);
@ -136,23 +123,17 @@ plat_time_init (void)
ifxmips_w32(0x80C0, IFXMIPS_GPTU_GPT_T6CON);
}
extern const char* get_system_type (void);
//void (*board_time_init)(void);
void __init
plat_mem_setup(void)
{
u32 status;
prom_printf("This %s has a cpu rev of 0x%X\n", get_system_type(), ifxmips_get_cpu_ver());
//TODO WHY ???
/* clear RE bit*/
status = read_c0_status();
status &= (~(1<<25));
write_c0_status(status);
ifxmips_reboot_setup();
// board_time_init = ifxmips_time_init;
board_be_handler = &ifxmips_be_handler;
ioport_resource.start = IOPORT_RESOURCE_START;

14
target/linux/ifxmips/files/drivers/char/ifxmips_ssc.c
View File

@ -73,7 +73,7 @@ static unsigned int ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info);
static void tx_int (struct ifx_ssc_port *);
extern unsigned int ifxmips_get_fpi_hz (void);
extern void mask_and_ack_ifxmips_irq (unsigned int irq_nr);
extern void ifxmips_mask_and_ack_irq (unsigned int irq_nr);
static inline unsigned int
ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info)
@ -297,9 +297,9 @@ ifx_ssc_abort (struct ifx_ssc_port *info)
wake_up_interruptible (&info->rwait);
// clear pending int's
mask_and_ack_ifxmips_irq(IFXMIPS_SSC_RIR);
mask_and_ack_ifxmips_irq(IFXMIPS_SSC_TIR);
mask_and_ack_ifxmips_irq(IFXMIPS_SSC_EIR);
ifxmips_mask_and_ack_irq(IFXMIPS_SSC_RIR);
ifxmips_mask_and_ack_irq(IFXMIPS_SSC_TIR);
ifxmips_mask_and_ack_irq(IFXMIPS_SSC_EIR);
// clear error flags
ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
@ -354,9 +354,9 @@ ifx_ssc_open (struct inode *inode, struct file *filp)
ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
// clear pending interrupts
mask_and_ack_ifxmips_irq(IFXMIPS_SSC_RIR);
mask_and_ack_ifxmips_irq(IFXMIPS_SSC_TIR);
mask_and_ack_ifxmips_irq(IFXMIPS_SSC_EIR);
ifxmips_mask_and_ack_irq(IFXMIPS_SSC_RIR);
ifxmips_mask_and_ack_irq(IFXMIPS_SSC_TIR);
ifxmips_mask_and_ack_irq(IFXMIPS_SSC_EIR);
ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);

48
target/linux/ifxmips/files/drivers/mtd/maps/ifxmips.c
View File

@ -1,6 +1,4 @@
/*
* Driver for IFXMIPS flashmap
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@ -16,7 +14,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Copyright (C) 2004 Liu Peng Infineon IFAP DC COM CPE
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
* Copyright (C) 2008 John Crispin <blogic@openwrt.org>
*/
#include <linux/module.h>
@ -32,11 +30,10 @@
#include <linux/magic.h>
#include <linux/platform_device.h>
#define DRVNAME "ifxmips_mtd"
static struct map_info
ifxmips_map = {
.name = DRVNAME,
.name = "ifxmips_mtd",
.bankwidth = 2,
.size = 0x400000,
};
@ -62,25 +59,24 @@ ifxmips_write16 (struct map_info *map, map_word d, unsigned long adr)
void
ifxmips_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
{
u8 *p;
u8 *to_8;
unsigned char *p;
unsigned char *to_8;
from = (unsigned long)(from + map->virt);
p = (u8 *) from;
to_8 = (u8 *) to;
while(len--){
p = (unsigned char*) from;
to_8 = (unsigned char*) to;
while(len--)
*to_8++ = *p++;
}
}
void
ifxmips_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
{
u8 *p = (u8*) from;
u8 *to_8;
unsigned char *p = (unsigned char*)from;
unsigned char *to_8;
to += (unsigned long) map->virt;
to_8 = (u8*)to;
to_8 = (unsigned char*)to;
while(len--){
*p++ = *to_8++;
}
@ -115,7 +111,7 @@ find_uImage_size (unsigned long start_offset){
unsigned long temp;
ifxmips_copy_from(&ifxmips_map, &temp, start_offset + 12, 4);
printk(KERN_INFO DRVNAME ": kernel size is %ld \n", temp + 0x40);
printk(KERN_INFO "ifxmips_mtd: kernel size is %ld \n", temp + 0x40);
return temp + 0x40;
}
@ -145,15 +141,17 @@ ifxmips_mtd_probe (struct platform_device *dev)
ifxmips_map.phys = IFXMIPS_FLASH_START;
ifxmips_map.virt = ioremap_nocache(IFXMIPS_FLASH_START, IFXMIPS_FLASH_MAX);
ifxmips_map.size = IFXMIPS_FLASH_MAX;
if (!ifxmips_map.virt) {
printk(KERN_WARNING DRVNAME ": failed to ioremap!\n");
if(!ifxmips_map.virt)
{
printk(KERN_WARNING "ifxmips_mtd: failed to ioremap!\n");
return -EIO;
}
ifxmips_mtd = (struct mtd_info *) do_map_probe("cfi_probe", &ifxmips_map);
if (!ifxmips_mtd) {
if(!ifxmips_mtd)
{
iounmap(ifxmips_map.virt);
printk(KERN_WARNING DRVNAME ": probing failed\n");
printk(KERN_WARNING "ifxmips_mtd: probing failed\n");
return -ENXIO;
}
@ -161,8 +159,9 @@ ifxmips_mtd_probe (struct platform_device *dev)
uimage_size = find_uImage_size(ifxmips_partitions[2].offset);
if(detect_squashfs_partition(ifxmips_partitions[2].offset + uimage_size)){
printk(KERN_INFO DRVNAME ": found a squashfs following the uImage\n");
if(detect_squashfs_partition(ifxmips_partitions[2].offset + uimage_size))
{
printk(KERN_INFO "ifxmips_mtd: found a squashfs following the uImage\n");
} else {
uimage_size &= ~0xffff;
uimage_size += 0x10000;
@ -175,7 +174,7 @@ ifxmips_mtd_probe (struct platform_device *dev)
parts = &ifxmips_partitions[0];
add_mtd_partitions(ifxmips_mtd, parts, 4);
printk(KERN_INFO DRVNAME ": added ifxmips flash with %dMB\n", ifxmips_mtd->size >> 20);
printk(KERN_INFO "ifxmips_mtd: added ifxmips flash with %dMB\n", ifxmips_mtd->size >> 20);
return 0;
}
@ -183,7 +182,7 @@ static struct
platform_driver ifxmips_mtd_driver = {
.probe = ifxmips_mtd_probe,
.driver = {
.name = DRVNAME,
.name = "ifxmips_mtd",
.owner = THIS_MODULE,
},
};
@ -193,8 +192,7 @@ init_ifxmips_mtd (void)
{
int ret = platform_driver_register(&ifxmips_mtd_driver);
if(ret)
printk(KERN_INFO DRVNAME ": error registering platfom driver!");
printk(KERN_INFO "ifxmips_mtd: error registering platfom driver!");
return ret;
}

106
target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c
View File

@ -1,6 +1,4 @@
/*
* drivers/net/ifxmips_mii0.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@ -15,13 +13,8 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 Infineon
*
* Rewrite of Infineon IFXMips code, thanks to infineon for the support,
* software and hardware
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
* Copyright (C) 2005 Wu Qi Ming <Qi-Ming.Wu@infineon.com>
* Copyright (C) 2008 John Crispin <blogic@openwrt.org>
*/
#include <linux/kernel.h>
@ -74,14 +67,13 @@ ifxmips_read_mdio (u32 phy_addr, u32 phy_reg)
ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC);
while(ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
val = ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
return val;
}
int
ifxmips_switch_open (struct net_device *dev)
ifxmips_ifxmips_mii_open(struct net_device *dev)
{
struct switch_priv* priv = (struct switch_priv*)dev->priv;
struct ifxmips_mii_priv* priv = (struct ifxmips_mii_priv*)dev->priv;
struct dma_device_info* dma_dev = priv->dma_device;
int i;
@ -90,30 +82,26 @@ ifxmips_switch_open (struct net_device *dev)
if((dma_dev->rx_chan[i])->control == IFXMIPS_DMA_CH_ON)
(dma_dev->rx_chan[i])->open(dma_dev->rx_chan[i]);
}
netif_start_queue(dev);
return 0;
}
int
switch_release (struct net_device *dev){
struct switch_priv* priv = (struct switch_priv*)dev->priv;
ifxmips_mii_release(struct net_device *dev){
struct ifxmips_mii_priv* priv = (struct ifxmips_mii_priv*)dev->priv;
struct dma_device_info* dma_dev = priv->dma_device;
int i;
for(i = 0; i < dma_dev->max_rx_chan_num; i++)
dma_dev->rx_chan[i]->close(dma_dev->rx_chan[i]);
netif_stop_queue(dev);
return 0;
}
int
switch_hw_receive (struct net_device* dev,struct dma_device_info* dma_dev)
ifxmips_mii_hw_receive(struct net_device* dev,struct dma_device_info* dma_dev)
{
struct switch_priv *priv = (struct switch_priv*)dev->priv;
struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv*)dev->priv;
unsigned char* buf = NULL;
struct sk_buff *skb = NULL;
int len = 0;
@ -123,7 +111,7 @@ switch_hw_receive (struct net_device* dev,struct dma_device_info* dma_dev)
if(len >= ETHERNET_PACKET_DMA_BUFFER_SIZE)
{
printk(KERN_INFO DRVNAME ": packet too large %d\n",len);
goto switch_hw_receive_err_exit;
goto ifxmips_mii_hw_receive_err_exit;
}
/* remove CRC */
@ -131,13 +119,14 @@ switch_hw_receive (struct net_device* dev,struct dma_device_info* dma_dev)
if(skb == NULL)
{
printk(KERN_INFO DRVNAME ": cannot restore pointer\n");
goto switch_hw_receive_err_exit;
goto ifxmips_mii_hw_receive_err_exit;
}
if(len > (skb->end - skb->tail))
{
printk(KERN_INFO DRVNAME ": BUG, len:%d end:%p tail:%p\n", (len+4), skb->end, skb->tail);
goto switch_hw_receive_err_exit;
printk(KERN_INFO DRVNAME ": BUG, len:%d end:%p tail:%p\n",
(len+4), skb->end, skb->tail);
goto ifxmips_mii_hw_receive_err_exit;
}
skb_put(skb, len);
@ -147,17 +136,15 @@ switch_hw_receive (struct net_device* dev,struct dma_device_info* dma_dev)
priv->stats.rx_packets++;
priv->stats.rx_bytes += len;
return 0;
switch_hw_receive_err_exit:
ifxmips_mii_hw_receive_err_exit:
if(len == 0)
{
if(skb)
dev_kfree_skb_any(skb);
priv->stats.rx_errors++;
priv->stats.rx_dropped++;
return -EIO;
} else {
return len;
@ -165,10 +152,10 @@ switch_hw_receive_err_exit:
}
int
switch_hw_tx (char *buf, int len, struct net_device *dev)
ifxmips_mii_hw_tx(char *buf, int len, struct net_device *dev)
{
int ret = 0;
struct switch_priv *priv = dev->priv;
struct ifxmips_mii_priv *priv = dev->priv;
struct dma_device_info* dma_dev = priv->dma_device;
ret = dma_device_write(dma_dev, buf, len, priv->skb);
@ -177,11 +164,11 @@ switch_hw_tx (char *buf, int len, struct net_device *dev)
}
int
switch_tx (struct sk_buff *skb, struct net_device *dev)
ifxmips_mii_tx(struct sk_buff *skb, struct net_device *dev)
{
int len;
char *data;
struct switch_priv *priv = dev->priv;
struct ifxmips_mii_priv *priv = dev->priv;
struct dma_device_info* dma_dev = priv->dma_device;
len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
@ -194,7 +181,7 @@ switch_tx (struct sk_buff *skb, struct net_device *dev)
wmb();
if (switch_hw_tx(data, len, dev) != len)
if(ifxmips_mii_hw_tx(data, len, dev) != len)
{
dev_kfree_skb_any(skb);
priv->stats.tx_errors++;
@ -208,20 +195,15 @@ switch_tx (struct sk_buff *skb, struct net_device *dev)
}
void
switch_tx_timeout (struct net_device *dev)
ifxmips_mii_tx_timeout(struct net_device *dev)
{
int i;
struct switch_priv* priv = (struct switch_priv*)dev->priv;
struct ifxmips_mii_priv* priv = (struct ifxmips_mii_priv*)dev->priv;
priv->stats.tx_errors++;
for(i = 0; i < priv->dma_device->max_tx_chan_num; i++)
{
priv->dma_device->tx_chan[i]->disable_irq(priv->dma_device->tx_chan[i]);
}
netif_wake_queue(dev);
return;
}
@ -233,7 +215,7 @@ dma_intr_handler (struct dma_device_info* dma_dev, int status)
switch(status)
{
case RCV_INT:
switch_hw_receive(ifxmips_mii0_dev, dma_dev);
ifxmips_mii_hw_receive(ifxmips_mii0_dev, dma_dev);
break;
case TX_BUF_FULL_INT:
@ -296,33 +278,27 @@ ifxmips_get_stats (struct net_device *dev)
}
static int
switch_init (struct net_device *dev)
ifxmips_mii_dev_init(struct net_device *dev)
{
u64 retval = 0;
int i;
struct switch_priv *priv;
struct ifxmips_mii_priv *priv;
ether_setup(dev);
printk(KERN_INFO DRVNAME ": %s is up\n", dev->name);
dev->open = ifxmips_switch_open;
dev->stop = switch_release;
dev->hard_start_xmit = switch_tx;
dev->open = ifxmips_ifxmips_mii_open;
dev->stop = ifxmips_mii_release;
dev->hard_start_xmit = ifxmips_mii_tx;
dev->get_stats = ifxmips_get_stats;
dev->tx_timeout = switch_tx_timeout;
dev->tx_timeout = ifxmips_mii_tx_timeout;
dev->watchdog_timeo = 10 * HZ;
memset(dev->priv, 0, sizeof(struct switch_priv));
memset(dev->priv, 0, sizeof(struct ifxmips_mii_priv));
priv = dev->priv;
priv->dma_device = dma_device_reserve("PPE");
if(!priv->dma_device){
BUG();
return -ENODEV;
}
priv->dma_device->buffer_alloc = &ifxmips_etop_dma_buffer_alloc;
priv->dma_device->buffer_free = &ifxmips_etop_dma_buffer_free;
priv->dma_device->intr_handler = &dma_intr_handler;
@ -335,12 +311,10 @@ switch_init (struct net_device *dev)
}
for(i = 0; i < priv->dma_device->max_tx_chan_num; i++)
{
if(i == 0)
priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_ON;
else
priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_OFF;
}
dma_device_register(priv->dma_device);
@ -368,7 +342,7 @@ switch_init (struct net_device *dev)
}
static void
ifxmips_sw_chip_init (int mode)
ifxmips_mii_chip_init(int mode)
{
ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_PPE);
@ -377,11 +351,8 @@ ifxmips_sw_chip_init (int mode)
ifxmips_w32((ifxmips_r32(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG);
else if(mode == MII_MODE)
ifxmips_w32((ifxmips_r32(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG);
ifxmips_w32(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL);
ifxmips_w32(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG);
wmb();
}
@ -390,12 +361,9 @@ ifxmips_mii_probe(struct platform_device *dev)
{
int result = 0;
ifxmips_mii0_dev = alloc_etherdev(sizeof(struct switch_priv));
ifxmips_mii0_dev->init = switch_init;
ifxmips_mii0_dev = alloc_etherdev(sizeof(struct ifxmips_mii_priv));
ifxmips_mii0_dev->init = ifxmips_mii_dev_init;
strcpy(ifxmips_mii0_dev->name, "eth%d");
result = register_netdev(ifxmips_mii0_dev);
if (result)
{
@ -404,7 +372,7 @@ ifxmips_mii_probe(struct platform_device *dev)
}
/* ifxmips eval kit connects the phy/switch in REV mode */
ifxmips_sw_chip_init(REV_MII_MODE);
ifxmips_mii_chip_init(REV_MII_MODE);
printk(KERN_INFO DRVNAME ": driver loaded!\n");
out:
@ -414,7 +382,7 @@ out:
static int
ifxmips_mii_remove(struct platform_device *dev)
{
struct switch_priv *priv = (struct switch_priv*)ifxmips_mii0_dev->priv;
struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv*)ifxmips_mii0_dev->priv;
printk(KERN_INFO DRVNAME ": ifxmips_mii0 cleanup\n");
@ -423,7 +391,6 @@ ifxmips_mii_remove(struct platform_device *dev)
kfree(priv->dma_device);
kfree(ifxmips_mii0_dev->priv);
unregister_netdev(ifxmips_mii0_dev);
return 0;
}
@ -443,7 +410,6 @@ ifxmips_mii_init(void)
int ret = platform_driver_register(&ifxmips_mii_driver);
if (ret)
printk(KERN_INFO DRVNAME ": Error registering platfom driver!");
return ret;
}
@ -455,3 +421,7 @@ ifxmips_mii_cleanup(void)
module_init(ifxmips_mii_init);
module_exit(ifxmips_mii_cleanup);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
MODULE_DESCRIPTION("ethernet map driver for IFXMIPS boards");

4
target/linux/ifxmips/files/drivers/serial/ifxmips_asc.c
View File

@ -193,7 +193,7 @@ ifxmipsasc_tx_int (int irq, void *port)
{
ifxmips_w32(ASC_IRNCR_TIR, IFXMIPS_ASC1_IRNCR);
ifxmipsasc_start_tx(port);
mask_and_ack_ifxmips_irq(irq);
ifxmips_mask_and_ack_irq(irq);
return IRQ_HANDLED;
}
@ -213,7 +213,7 @@ ifxmipsasc_rx_int (int irq, void *port)
{
ifxmips_w32(ASC_IRNCR_RIR, IFXMIPS_ASC1_IRNCR);
ifxmipsasc_rx_chars((struct uart_port *) port);
mask_and_ack_ifxmips_irq(irq);
ifxmips_mask_and_ack_irq(irq);
return IRQ_HANDLED;
}

2
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_irq.h
View File

@ -64,6 +64,6 @@
#define IFXMIPS_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
#define IFXMIPS_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
extern void mask_and_ack_ifxmips_irq (unsigned int irq_nr);
extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr);
#endif

3
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mei_linux.h
View File

@ -60,6 +60,7 @@
#include <asm/ifxmips/ifxmips_mei_app_ioctl.h>
#include <asm/ifxmips/ifxmips_gpio.h>
#include <asm/ifxmips/ifxmips_led.h>
#include <asm/ifxmips/ifxmips_irq.h>
#ifdef CONFIG_DEVFS_FS
#define IFXMIPS_DEVNAME "ifxmips"
@ -79,7 +80,7 @@
up(&id)
#define MEI_MASK_AND_ACK_IRQ \
mask_and_ack_ifxmips_irq
ifxmips_mask_and_ack_irq
#define MEI_DISABLE_IRQ \
disable_irq

2
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mii0.h
View File

@ -229,7 +229,7 @@ enum duplex
autoneg
};
struct switch_priv {
struct ifxmips_mii_priv {
struct net_device_stats stats;
int rx_packetlen;
u8 *rx_packetdata;