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lantiq: Use the BAR0 base address in the ath PCI fixup code 

Fixes support for AR9287 on TP-Link TD-W8980 and possibly other devices
which have an ath wifi chip at a PCI address other than 0xb8000000
(TD-W8980 for example has it's wifi chip at 0xbc000000).

Signed-off-by: Geoffrey McRae <geoff@spacevs.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 46869
owl
Felix Fietkau 2015-09-11 16:35:46 +00:00
parent 9da3a62839
commit 6c1adb3eec
2 changed files with 8 additions and 8 deletions
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8
target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch
View File

@ -431,8 +431,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+#include <linux/delay.h> +#include <linux/delay.h>
+#include <lantiq_soc.h> +#include <lantiq_soc.h>
+ +
+#define LTQ_PCI_MEM_BASE 0x18000000
+
+struct ath_fixup { +struct ath_fixup {
+ u16 *cal_data; + u16 *cal_data;
+ unsigned slot; + unsigned slot;
@ -448,6 +446,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ u16 cmd; + u16 cmd;
+ u32 bar0; + u32 bar0;
+ u32 val; + u32 val;
+ u32 base;
+ unsigned i; + unsigned i;
+ +
+ for (i = 0; i < ath_num_fixups; i++) { + for (i = 0; i < ath_num_fixups; i++) {
@ -471,14 +470,15 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ +
+ pr_info("pci %s: fixup device configuration\n", pci_name(dev)); + pr_info("pci %s: fixup device configuration\n", pci_name(dev));
+ +
+ mem = ioremap(LTQ_PCI_MEM_BASE, 0x10000); + base = dev->resource[0].start;
+ mem = ioremap(base, 0x10000);
+ if (!mem) { + if (!mem) {
+ pr_err("pci %s: ioremap error\n", pci_name(dev)); + pr_err("pci %s: ioremap error\n", pci_name(dev));
+ return; + return;
+ } + }
+ +
+ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, LTQ_PCI_MEM_BASE); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, base);
+ pci_read_config_word(dev, PCI_COMMAND, &cmd); + pci_read_config_word(dev, PCI_COMMAND, &cmd);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config_word(dev, PCI_COMMAND, cmd); + pci_write_config_word(dev, PCI_COMMAND, cmd);

8
target/linux/lantiq/patches-4.1/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch
View File

@ -431,8 +431,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+#include <linux/delay.h> +#include <linux/delay.h>
+#include <lantiq_soc.h> +#include <lantiq_soc.h>
+ +
+#define LTQ_PCI_MEM_BASE 0x18000000
+
+struct ath_fixup { +struct ath_fixup {
+ u16 *cal_data; + u16 *cal_data;
+ unsigned slot; + unsigned slot;
@ -448,6 +446,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ u16 cmd; + u16 cmd;
+ u32 bar0; + u32 bar0;
+ u32 val; + u32 val;
+ u32 base;
+ unsigned i; + unsigned i;
+ +
+ for (i = 0; i < ath_num_fixups; i++) { + for (i = 0; i < ath_num_fixups; i++) {
@ -471,14 +470,15 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ +
+ pr_info("pci %s: fixup device configuration\n", pci_name(dev)); + pr_info("pci %s: fixup device configuration\n", pci_name(dev));
+ +
+ mem = ioremap(LTQ_PCI_MEM_BASE, 0x10000); + base = dev->resource[0].start;
+ mem = ioremap(base, 0x10000);
+ if (!mem) { + if (!mem) {
+ pr_err("pci %s: ioremap error\n", pci_name(dev)); + pr_err("pci %s: ioremap error\n", pci_name(dev));
+ return; + return;
+ } + }
+ +
+ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, LTQ_PCI_MEM_BASE); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, base);
+ pci_read_config_word(dev, PCI_COMMAND, &cmd); + pci_read_config_word(dev, PCI_COMMAND, &cmd);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config_word(dev, PCI_COMMAND, cmd); + pci_write_config_word(dev, PCI_COMMAND, cmd);