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share common INTC code 

SVN-Revision: 17440
owl
Gabor Juhos 2009-08-30 19:15:58 +00:00
parent 051c44e0c5
commit 6b482c872b
14 changed files with 139 additions and 145 deletions
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16
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/common.h Normal file
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@ -0,0 +1,16 @@
/*
* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __ASM_MACH_RALINK_COMMON_H
#define __ASM_MACH_RALINK_COMMON_H
void __init ramips_intc_irq_init(unsigned intc_base, unsigned irq,
unsigned irq_base);
u32 ramips_intc_get_status(void);
#endif /* __ASM_MACH_RALINK_COMMON_H */

11
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h
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@ -53,7 +53,6 @@ extern unsigned long rt288x_mach_type;
#define RT288X_GPIO_COUNT 32
extern void __iomem *rt288x_sysc_base;
extern void __iomem *rt288x_intc_base;
extern void __iomem *rt288x_memc_base;
static inline void rt288x_sysc_wr(u32 val, unsigned reg)
@ -66,16 +65,6 @@ static inline u32 rt288x_sysc_rr(unsigned reg)
return __raw_readl(rt288x_sysc_base + reg);
}
static inline void rt288x_intc_wr(u32 val, unsigned reg)
{
__raw_writel(val, rt288x_intc_base + reg);
}
static inline u32 rt288x_intc_rr(unsigned reg)
{
return __raw_readl(rt288x_intc_base + reg);
}
static inline void rt288x_memc_wr(u32 val, unsigned reg)
{
__raw_writel(val, rt288x_memc_base + reg);

10
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
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@ -75,16 +75,6 @@
#define RT2880_RESET_FE BIT(18)
#define RT2880_RESET_PCM BIT(19)
/* TIMER registers */
/* INTC register */
#define INTC_REG_STATUS0 0x00
#define INTC_REG_STATUS1 0x04
#define INTC_REG_TYPE 0x20
#define INTC_REG_RAW_STATUS 0x30
#define INTC_REG_ENABLE 0x34
#define INTC_REG_DISABLE 0x38
#define RT2880_INTC_INT_TIMER0 BIT(0)
#define RT2880_INTC_INT_TIMER1 BIT(1)
#define RT2880_INTC_INT_UART0 BIT(2)

11
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h
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@ -55,7 +55,6 @@ extern unsigned long rt305x_sys_freq;
#define RT305X_INTC_IRQ_OTG (RT305X_INTC_IRQ_BASE + 18)
extern void __iomem *rt305x_sysc_base;
extern void __iomem *rt305x_intc_base;
extern void __iomem *rt305x_memc_base;
static inline void rt305x_sysc_wr(u32 val, unsigned reg)
@ -68,16 +67,6 @@ static inline u32 rt305x_sysc_rr(unsigned reg)
return __raw_readl(rt305x_sysc_base + reg);
}
static inline void rt305x_intc_wr(u32 val, unsigned reg)
{
__raw_writel(val, rt305x_intc_base + reg);
}
static inline u32 rt305x_intc_rr(unsigned reg)
{
return __raw_readl(rt305x_intc_base + reg);
}
static inline void rt305x_memc_wr(u32 val, unsigned reg)
{
__raw_writel(val, rt305x_memc_base + reg);

10
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
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@ -79,16 +79,6 @@
#define RT305X_RESET_OTG BIT(22)
#define RT305X_RESET_ESW BIT(23)
/* TIMER registers */
/* INTC register */
#define INTC_REG_STATUS0 0x00
#define INTC_REG_STATUS1 0x04
#define INTC_REG_TYPE 0x20
#define INTC_REG_RAW_STATUS 0x30
#define INTC_REG_ENABLE 0x34
#define INTC_REG_DISABLE 0x38
#define RT305X_INTC_INT_SYSCTL BIT(0)
#define RT305X_INTC_INT_TIMER0 BIT(1)
#define RT305X_INTC_INT_TIMER1 BIT(2)

10
target/linux/ramips/files/arch/mips/ralink/common/Makefile Normal file
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@ -0,0 +1,10 @@
#
# Makefile for the Ralink common stuff
#
# Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License version 2 as published
# by the Free Software Foundation.
obj-y := intc.o

98
target/linux/ramips/files/arch/mips/ralink/common/intc.c Normal file
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@ -0,0 +1,98 @@
/*
* Ralink SoC Interrupt controller routines
*
* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/bitops.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/mach-ralink/common.h>
/* INTC register offsets */
#define INTC_REG_STATUS0 0x00
#define INTC_REG_STATUS1 0x04
#define INTC_REG_TYPE 0x20
#define INTC_REG_RAW_STATUS 0x30
#define INTC_REG_ENABLE 0x34
#define INTC_REG_DISABLE 0x38
#define INTC_INT_GLOBAL BIT(31)
#define INTC_IRQ_COUNT 32
static unsigned int ramips_intc_irq_base;
static void __iomem *ramips_intc_base;
static inline void ramips_intc_wr(u32 val, unsigned reg)
{
__raw_writel(val, ramips_intc_base + reg);
}
static inline u32 ramips_intc_rr(unsigned reg)
{
return __raw_readl(ramips_intc_base + reg);
}
static void ramips_intc_irq_unmask(unsigned int irq)
{
irq -= ramips_intc_irq_base;
ramips_intc_wr((1 << irq), INTC_REG_ENABLE);
}
static void ramips_intc_irq_mask(unsigned int irq)
{
irq -= ramips_intc_irq_base;
ramips_intc_wr((1 << irq), INTC_REG_DISABLE);
}
static struct irq_chip ramips_intc_irq_chip = {
.name = "INTC",
.unmask = ramips_intc_irq_unmask,
.mask = ramips_intc_irq_mask,
.mask_ack = ramips_intc_irq_mask,
};
static struct irqaction ramips_intc_irqaction = {
.handler = no_action,
.name = "cascade [INTC]",
};
void __init ramips_intc_irq_init(unsigned intc_base, unsigned irq,
unsigned irq_base)
{
int i;
ramips_intc_base = ioremap_nocache(intc_base, PAGE_SIZE);
ramips_intc_irq_base = irq_base;
/* disable all interrupts */
ramips_intc_wr(~0, INTC_REG_DISABLE);
/* route all INTC interrupts to MIPS HW0 interrupt */
ramips_intc_wr(0, INTC_REG_TYPE);
for (i = ramips_intc_irq_base;
i < ramips_intc_irq_base + INTC_IRQ_COUNT; i++) {
set_irq_chip_and_handler(i, &ramips_intc_irq_chip,
handle_level_irq);
}
setup_irq(irq, &ramips_intc_irqaction);
ramips_intc_wr(INTC_INT_GLOBAL, INTC_REG_ENABLE);
}
u32 ramips_intc_get_status(void)
{
return ramips_intc_rr(INTC_REG_STATUS0);
}

52
target/linux/ramips/files/arch/mips/ralink/rt288x/irq.c
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@ -17,6 +17,7 @@
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/mach-ralink/common.h>
#include <asm/mach-ralink/rt288x.h>
#include <asm/mach-ralink/rt288x_regs.h>
@ -24,7 +25,7 @@ static void rt288x_intc_irq_dispatch(void)
{
u32 pending;
pending = rt288x_intc_rr(INTC_REG_STATUS0);
pending = ramips_intc_get_status();
if (pending & RT2880_INTC_INT_TIMER0)
do_IRQ(RT2880_INTC_IRQ_TIMER0);
@ -47,52 +48,6 @@ static void rt288x_intc_irq_dispatch(void)
spurious_interrupt();
}
static void rt288x_intc_irq_unmask(unsigned int irq)
{
irq -= RT288X_INTC_IRQ_BASE;
rt288x_intc_wr((1 << irq), INTC_REG_ENABLE);
}
static void rt288x_intc_irq_mask(unsigned int irq)
{
irq -= RT288X_INTC_IRQ_BASE;
rt288x_intc_wr((1 << irq), INTC_REG_DISABLE);
}
struct irq_chip rt288x_intc_irq_chip = {
.name = "RT288X INTC",
.unmask = rt288x_intc_irq_unmask,
.mask = rt288x_intc_irq_mask,
.mask_ack = rt288x_intc_irq_mask,
};
static struct irqaction rt288x_intc_irqaction = {
.handler = no_action,
.name = "cascade [RT288X INTC]",
};
static void __init rt288x_intc_irq_init(void)
{
int i;
/* disable all interrupts */
rt288x_intc_wr(~0, INTC_REG_DISABLE);
/* route all INTC interrupts to MIPS HW0 interrupt */
rt288x_intc_wr(0, INTC_REG_TYPE);
for (i = RT288X_INTC_IRQ_BASE;
i < RT288X_INTC_IRQ_BASE + RT288X_INTC_IRQ_COUNT; i++) {
irq_desc[i].status = IRQ_DISABLED;
set_irq_chip_and_handler(i, &rt288x_intc_irq_chip,
handle_level_irq);
}
setup_irq(RT288X_CPU_IRQ_INTC, &rt288x_intc_irqaction);
rt288x_intc_wr(RT2880_INTC_INT_GLOBAL, INTC_REG_ENABLE);
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned long pending;
@ -121,5 +76,6 @@ asmlinkage void plat_irq_dispatch(void)
void __init arch_init_irq(void)
{
mips_cpu_irq_init();
rt288x_intc_irq_init();
ramips_intc_irq_init(RT2880_INTC_BASE, RT288X_CPU_IRQ_INTC,
RT288X_INTC_IRQ_BASE);
}

1
target/linux/ramips/files/arch/mips/ralink/rt288x/rt288x.c
View File

@ -26,7 +26,6 @@ EXPORT_SYMBOL_GPL(rt288x_cpu_freq);
unsigned long rt288x_sys_freq;
EXPORT_SYMBOL_GPL(rt288x_sys_freq);
void __iomem * rt288x_intc_base;
void __iomem * rt288x_sysc_base;
void __iomem * rt288x_memc_base;

1
target/linux/ramips/files/arch/mips/ralink/rt288x/setup.c
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@ -108,7 +108,6 @@ void __init plat_mem_setup(void)
{
set_io_port_base(KSEG1);
rt288x_intc_base = ioremap_nocache(RT2880_INTC_BASE, RT2880_INTC_SIZE);
rt288x_sysc_base = ioremap_nocache(RT2880_SYSC_BASE, RT2880_SYSC_SIZE);
rt288x_memc_base = ioremap_nocache(RT2880_MEMC_BASE, RT2880_MEMC_SIZE);

52
target/linux/ramips/files/arch/mips/ralink/rt305x/irq.c
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@ -16,6 +16,7 @@
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/mach-ralink/common.h>
#include <asm/mach-ralink/rt305x.h>
#include <asm/mach-ralink/rt305x_regs.h>
@ -23,7 +24,7 @@ static void rt305x_intc_irq_dispatch(void)
{
u32 pending;
pending = rt305x_intc_rr(INTC_REG_STATUS0);
pending = ramips_intc_get_status();
if (pending & RT305X_INTC_INT_TIMER0)
do_IRQ(RT305X_INTC_IRQ_TIMER0);
@ -43,52 +44,6 @@ static void rt305x_intc_irq_dispatch(void)
spurious_interrupt();
}
static void rt305x_intc_irq_unmask(unsigned int irq)
{
irq -= RT305X_INTC_IRQ_BASE;
rt305x_intc_wr((1 << irq), INTC_REG_ENABLE);
}
static void rt305x_intc_irq_mask(unsigned int irq)
{
irq -= RT305X_INTC_IRQ_BASE;
rt305x_intc_wr((1 << irq), INTC_REG_DISABLE);
}
struct irq_chip rt305x_intc_irq_chip = {
.name = "RT305X INTC",
.unmask = rt305x_intc_irq_unmask,
.mask = rt305x_intc_irq_mask,
.mask_ack = rt305x_intc_irq_mask,
};
static struct irqaction rt305x_intc_irqaction = {
.handler = no_action,
.name = "cascade [RT305X INTC]",
};
static void __init rt305x_intc_irq_init(void)
{
int i;
/* disable all interrupts */
rt305x_intc_wr(~0, INTC_REG_DISABLE);
/* route all INTC interrupts to MIPS HW0 interrupt */
rt305x_intc_wr(0, INTC_REG_TYPE);
for (i = RT305X_INTC_IRQ_BASE;
i < RT305X_INTC_IRQ_BASE + RT305X_INTC_IRQ_COUNT; i++) {
set_irq_chip_and_handler(i, &rt305x_intc_irq_chip,
handle_level_irq);
}
setup_irq(RT305X_CPU_IRQ_INTC, &rt305x_intc_irqaction);
/* enable interrupt masking */
rt305x_intc_wr(RT305X_INTC_INT_GLOBAL, INTC_REG_ENABLE);
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned long pending;
@ -114,5 +69,6 @@ asmlinkage void plat_irq_dispatch(void)
void __init arch_init_irq(void)
{
mips_cpu_irq_init();
rt305x_intc_irq_init();
ramips_intc_irq_init(RT305X_INTC_BASE, RT305X_CPU_IRQ_INTC,
RT305X_INTC_IRQ_BASE);
}

1
target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c
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@ -26,7 +26,6 @@ EXPORT_SYMBOL_GPL(rt305x_cpu_freq);
unsigned long rt305x_sys_freq;
EXPORT_SYMBOL_GPL(rt305x_sys_freq);
void __iomem * rt305x_intc_base;
void __iomem * rt305x_sysc_base;
void __iomem * rt305x_memc_base;

1
target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c
View File

@ -103,7 +103,6 @@ void __init plat_mem_setup(void)
{
set_io_port_base(KSEG1);
rt305x_intc_base = ioremap_nocache(RT305X_INTC_BASE, PAGE_SIZE);
rt305x_sysc_base = ioremap_nocache(RT305X_SYSC_BASE, PAGE_SIZE);
rt305x_memc_base = ioremap_nocache(RT305X_MEMC_BASE, PAGE_SIZE);

10
target/linux/ramips/patches-2.6.30/100-mips-ralink-core.patch
View File

@ -1,21 +1,25 @@
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -603,6 +603,20 @@ else
@@ -603,6 +603,24 @@ else
load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff81100000
endif
+#
+# Ralink SoC common stuff
+#
+core-$(CONFIG_MIPS_RALINK) += arch/mips/ralink/common/
+cflags-$(CONFIG_MIPS_RALINK) += -I$(srctree)/arch/mips/include/asm/mach-ralink
+
+#
+# Ralink RT288x
+#
+core-$(CONFIG_RALINK_RT288X) += arch/mips/ralink/rt288x/
+cflags-$(CONFIG_RALINK_RT288X) += -I$(srctree)/arch/mips/include/asm/mach-ralink
+load-$(CONFIG_RALINK_RT288X) += 0xffffffff88000000
+
+#
+# Ralink RT305x
+#
+core-$(CONFIG_RALINK_RT305X) += arch/mips/ralink/rt305x/
+cflags-$(CONFIG_RALINK_RT305X) += -I$(srctree)/arch/mips/include/asm/mach-ralink
+load-$(CONFIG_RALINK_RT305X) += 0xffffffff80000000
+
# temporary until string.h is fixed