mirror of https://github.com/hak5/openwrt-owl.git
brcm63xx: add USB support for BCM63268
Add and enable USB support for the BCM63268 family of SoCs. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 39323owl
Jonas Gorski
parent
33f426c795
commit
6b3e1c8de6
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@ -0,0 +1,71 @@
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -585,6 +585,9 @@
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#define TIMER_CTL_MONOTONIC_MASK (1 << 30)
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#define TIMER_CTL_ENABLE_MASK (1 << 31)
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+/* Clock reset control (63268 only) */
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+#define TIMER_CLK_RST_CTL_REG 0x2c
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+#define CLK_RST_CTL_USB_REF_CLK_EN (1 << 18)
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/*************************************************************************
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* _REG relative to RSET_WDT
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@@ -1666,6 +1669,11 @@
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#define STRAPBUS_63268_FCVO_SHIFT 21
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#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
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+#define MISC_IDDQ_CTRL_6328_REG 0x48
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+#define MISC_IDDQ_CTRL_63268_REG 0x4c
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+
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+#define IDDQ_CTRL_63268_USBH (1 << 4)
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+
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#define MISC_STRAPBUS_6328_REG 0x240
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#define STRAPBUS_6328_FCVO_SHIFT 7
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#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
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--- a/arch/mips/bcm63xx/clk.c
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+++ b/arch/mips/bcm63xx/clk.c
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@@ -62,6 +62,26 @@ static void bcm_ub_hwclock_set(u32 mask,
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bcm_perf_writel(reg, PERF_UB_CKCTL_REG);
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}
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+static void bcm_misc_iddq_set(u32 mask, int enable)
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+{
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+ u32 offset;
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+ u32 reg;
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+
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+ if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
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+ offset = MISC_IDDQ_CTRL_6328_REG;
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+ else if (BCMCPU_IS_63268())
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+ offset = MISC_IDDQ_CTRL_63268_REG;
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+ else
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+ return;
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+
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+ reg = bcm_misc_readl(offset);
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+ if (enable)
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+ reg &= ~mask;
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+ else
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+ reg |= mask;
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+ bcm_misc_writel(reg, offset);
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+}
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+
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/*
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* Ethernet MAC "misc" clock: dma clocks and main clock on 6348
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*/
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@@ -199,7 +219,17 @@ static void usbh_set(struct clk *clk, in
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} else if (BCMCPU_IS_6368()) {
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bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
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} else if (BCMCPU_IS_63268()) {
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+ u32 reg;
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+
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bcm_hwclock_set(CKCTL_63268_USBH_EN, enable);
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+ bcm_misc_iddq_set(IDDQ_CTRL_63268_USBH, enable);
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+ bcm63xx_core_set_reset(BCM63XX_RESET_USBH, !enable);
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+ reg = bcm_timer_readl(TIMER_CLK_RST_CTL_REG);
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+ if (enable)
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+ reg |= CLK_RST_CTL_USB_REF_CLK_EN;
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+ else
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+ reg &= ~CLK_RST_CTL_USB_REF_CLK_EN;
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+ bcm_timer_writel(reg, TIMER_CLK_RST_CTL_REG);
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} else {
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return;
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}
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@ -0,0 +1,117 @@
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -1152,11 +1152,18 @@
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#define USBH_PRIV_SETUP_6368_REG 0x28
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#define USBH_PRIV_SETUP_IOC_SHIFT 4
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#define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT)
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+#define USBH_PRIV_SETUP_IPP_SHIFT 5
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+#define USBH_PRIV_SETUP_IPP_MASK (1 << USBH_PRIV_SETUP_IPP_SHIFT)
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#define USBH_PRIV_SETUP_6318_REG 0x00
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+#define USBH_PRIV_PLL_CTRL1_6368_REG 0x18
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#define USBH_PRIV_PLL_CTRL1_6318_REG 0x04
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-#define USBH_PRIV_PLL_CTRL1_SUSP_EN (1 << 27)
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-#define USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN (1 << 31)
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+
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+#define USBH_PRIV_PLL_CTRL1_6318_SUSP_EN (1 << 27)
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+#define USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN (1 << 31)
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+#define USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN (1 << 9)
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+#define USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY (1 << 10)
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+
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#define USBH_PRIV_SIM_CTRL_6318_REG 0x20
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#define USBH_PRIV_SIM_CTRL_LADDR_SEL (1 << 5)
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--- a/arch/mips/bcm63xx/Kconfig
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+++ b/arch/mips/bcm63xx/Kconfig
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@@ -72,6 +72,8 @@ config BCM63XX_CPU_63268
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bool "support 63268 CPU"
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select SYS_HAS_CPU_BMIPS4350
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select HW_HAS_PCI
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+ select BCM63XX_OHCI
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+ select BCM63XX_EHCI
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endmenu
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source "arch/mips/bcm63xx/boards/Kconfig"
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--- a/arch/mips/bcm63xx/dev-usb-ehci.c
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+++ b/arch/mips/bcm63xx/dev-usb-ehci.c
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@@ -82,7 +82,7 @@ static struct platform_device bcm63xx_eh
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int __init bcm63xx_ehci_register(void)
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{
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if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() &&
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- !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
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+ !BCMCPU_IS_6362() && !BCMCPU_IS_6368() && !BCMCPU_IS_63268())
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return 0;
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ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0);
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--- a/arch/mips/bcm63xx/usb-common.c
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+++ b/arch/mips/bcm63xx/usb-common.c
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@@ -109,9 +109,24 @@ void bcm63xx_usb_priv_ohci_cfg_set(void)
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reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
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reg |= USBH_PRIV_SETUP_IOC_MASK;
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bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
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+ } else if (BCMCPU_IS_63268()) {
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);
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+ reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK;
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+ reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG);
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+
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
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+ reg |= USBH_PRIV_SETUP_IOC_MASK;
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+ reg &= ~USBH_PRIV_SETUP_IPP_MASK;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
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+
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6368_REG);
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+ reg &= ~(USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN |
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+ USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY);
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6368_REG);
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} else if (BCMCPU_IS_6318()) {
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reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
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- reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN;
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+ reg |= USBH_PRIV_PLL_CTRL1_6318_SUSP_EN;
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bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
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reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG);
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@@ -124,7 +139,7 @@ void bcm63xx_usb_priv_ohci_cfg_set(void)
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bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG);
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reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
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- reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN;
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+ reg &= ~USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN;
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bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
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reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG);
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@@ -165,9 +180,24 @@ void bcm63xx_usb_priv_ehci_cfg_set(void)
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reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
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reg |= USBH_PRIV_SETUP_IOC_MASK;
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bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
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+ } else if (BCMCPU_IS_63268()) {
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);
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+ reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK;
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+ reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG);
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+
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
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+ reg |= USBH_PRIV_SETUP_IOC_MASK;
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+ reg &= ~USBH_PRIV_SETUP_IPP_MASK;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
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+
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6368_REG);
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+ reg &= ~(USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN |
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+ USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY);
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6368_REG);
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} else if (BCMCPU_IS_6318()) {
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reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
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- reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN;
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+ reg |= USBH_PRIV_PLL_CTRL1_6318_SUSP_EN;
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bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
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reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG);
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@@ -180,7 +210,7 @@ void bcm63xx_usb_priv_ehci_cfg_set(void)
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bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG);
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reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
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- reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN;
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+ reg &= ~USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN;
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bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
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reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG);
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@ -11,7 +11,7 @@
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bcm_gpio_writel(val, GPIO_MODE_REG);
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -767,6 +767,8 @@
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@@ -770,6 +770,8 @@
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#define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
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#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
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#define GPIO_MODE_6358_UTOPIA (1 << 12)
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@ -10,7 +10,7 @@ Subject: [PATCH 54/81] bcm63xx_enet: enable rgmii clock on external ports
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -1083,6 +1083,19 @@
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@@ -1086,6 +1086,19 @@
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#define ENETSW_PORTOV_FDX_MASK (1 << 1)
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#define ENETSW_PORTOV_LINKUP_MASK (1 << 0)
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@ -115,7 +115,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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return -ENODEV;
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -824,6 +824,7 @@
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@@ -827,6 +827,7 @@
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#define GPIO_STRAPBUS_REG 0x40
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#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
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#define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
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@ -123,8 +123,8 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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#define STRAPBUS_6368_BOOT_SEL_MASK 0x3
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#define STRAPBUS_6368_BOOT_SEL_NAND 0
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#define STRAPBUS_6368_BOOT_SEL_SERIAL 1
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@@ -1682,6 +1683,7 @@
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#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
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@@ -1697,6 +1698,7 @@
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#define IDDQ_CTRL_63268_USBH (1 << 4)
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#define MISC_STRAPBUS_6328_REG 0x240
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+#define STRAPBUS_6328_HSSPI_CLK_FAST (1 << 4)
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