mirror of https://github.com/hak5/openwrt-owl.git
ipq806x: dwc3: Fix power_on and power_off sequence
Picking commit from QSDK https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/commit/drivers/phy/phy-qcom-dwc3.c?h=eggplant&id=d316437c9cdb70023a760342678f32e27241725a The commit fixes: - dwc3 phy module unloading - possibly fixes FS#177 when some devices were improperly enumerated as HS while being SS thus stucking the driver during boot. Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>owl
Pavel Kubelun
Felix Fietkau
parent
c263e18a53
commit
6617f3c6ab
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@ -7,8 +7,8 @@ Signed-off-by: Andy Gross <agross@codeaurora.org>
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---
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drivers/phy/Kconfig | 12 +
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drivers/phy/Makefile | 1 +
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drivers/phy/phy-qcom-dwc3.c | 546 ++++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 559 insertions(+)
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drivers/phy/phy-qcom-dwc3.c | 575 ++++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 588 insertions(+)
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create mode 100644 drivers/phy/phy-qcom-dwc3.c
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--- a/drivers/phy/Kconfig
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@ -39,7 +39,7 @@ Signed-off-by: Andy Gross <agross@codeaurora.org>
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+obj-$(CONFIG_PHY_QCOM_DWC3) += phy-qcom-dwc3.o
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--- /dev/null
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+++ b/drivers/phy/phy-qcom-dwc3.c
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@@ -0,0 +1,546 @@
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@@ -0,0 +1,575 @@
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+/* Copyright (c) 2014-2015, Code Aurora Forum. All rights reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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@ -299,36 +299,21 @@ Signed-off-by: Andy Gross <agross@codeaurora.org>
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+ return ret;
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+}
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+
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+static int qcom_dwc3_phy_power_on(struct phy *phy)
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+static int qcom_dwc3_hs_phy_init(struct phy *phy)
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+{
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+ int ret;
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+ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
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+ int ret;
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+ u32 val;
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+
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+ ret = clk_prepare_enable(phy_dwc3->xo_clk);
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+ if (ret)
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+ return ret;
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+
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+ ret = clk_prepare_enable(phy_dwc3->ref_clk);
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+ if (ret)
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+ if (ret) {
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+ clk_disable_unprepare(phy_dwc3->xo_clk);
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+
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+ return ret;
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+}
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+
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+static int qcom_dwc3_phy_power_off(struct phy *phy)
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+{
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+ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
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+
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+ clk_disable_unprepare(phy_dwc3->ref_clk);
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+ clk_disable_unprepare(phy_dwc3->xo_clk);
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+
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+ return 0;
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+}
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+
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+static int qcom_dwc3_hs_phy_init(struct phy *phy)
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+{
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+ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
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+ u32 val;
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+ return ret;
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+ }
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+
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+ /*
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+ * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel
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@ -353,12 +338,32 @@ Signed-off-by: Andy Gross <agross@codeaurora.org>
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+ return 0;
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+}
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+
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+static int qcom_dwc3_hs_phy_exit(struct phy *phy)
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+{
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+ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
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+
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+ clk_disable_unprepare(phy_dwc3->ref_clk);
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+ clk_disable_unprepare(phy_dwc3->xo_clk);
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+
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+ return 0;
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+}
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+
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+static int qcom_dwc3_ss_phy_init(struct phy *phy)
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+{
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+ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
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+ int ret;
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+ u32 data = 0;
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+
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+ ret = clk_prepare_enable(phy_dwc3->xo_clk);
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+ if (ret)
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+ return ret;
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+
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+ ret = clk_prepare_enable(phy_dwc3->ref_clk);
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+ if (ret) {
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+ clk_disable_unprepare(phy_dwc3->xo_clk);
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+ return ret;
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+ }
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+
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+ /* reset phy */
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+ data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG);
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+ writel(data | SSUSB_CTRL_SS_PHY_RESET,
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@ -381,6 +386,30 @@ Signed-off-by: Andy Gross <agross@codeaurora.org>
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+ writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
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+
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+ /*
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+ * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates
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+ * in HS mode instead of SS mode. Workaround it by asserting
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+ * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode
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+ */
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+ ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, 0x102D, &data);
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+ if (ret)
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+ goto err_phy_trans;
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+
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+ data |= (1 << 7);
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+ ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x102D, data);
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+ if (ret)
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+ goto err_phy_trans;
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+
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+ ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, 0x1010, &data);
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+ if (ret)
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+ goto err_phy_trans;
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+
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+ data &= ~0xff0;
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+ data |= 0x20;
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+ ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x1010, data);
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+ if (ret)
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+ goto err_phy_trans;
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+
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+ /*
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+ * Fix RX Equalization setting as follows
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+ * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
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+ * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
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@ -462,7 +491,10 @@ Signed-off-by: Andy Gross <agross@codeaurora.org>
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+ qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
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+ SSUSB_CTRL_REF_USE_PAD, 0x0);
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+ qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
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+ 0x0, SSUSB_CTRL_TEST_POWERDOWN);
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+ SSUSB_CTRL_TEST_POWERDOWN, 0x0);
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+
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+ clk_disable_unprepare(phy_dwc3->ref_clk);
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+ clk_disable_unprepare(phy_dwc3->xo_clk);
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+
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+ return 0;
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+}
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@ -470,8 +502,7 @@ Signed-off-by: Andy Gross <agross@codeaurora.org>
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+static const struct qcom_dwc3_phy_drvdata qcom_dwc3_hs_drvdata = {
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+ .ops = {
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+ .init = qcom_dwc3_hs_phy_init,
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+ .power_on = qcom_dwc3_phy_power_on,
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+ .power_off = qcom_dwc3_phy_power_off,
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+ .exit = qcom_dwc3_hs_phy_exit,
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+ .owner = THIS_MODULE,
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+ },
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+ .clk_rate = 60000000,
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@ -481,8 +512,6 @@ Signed-off-by: Andy Gross <agross@codeaurora.org>
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+ .ops = {
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+ .init = qcom_dwc3_ss_phy_init,
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+ .exit = qcom_dwc3_ss_phy_exit,
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+ .power_on = qcom_dwc3_phy_power_on,
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+ .power_off = qcom_dwc3_phy_power_off,
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+ .owner = THIS_MODULE,
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+ },
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+ .clk_rate = 125000000,
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