mirror of https://github.com/hak5/openwrt-owl.git
octeon: add patches which are not upstreamed yet
Signed-off-by: Roman Yeryomin <roman@advem.lv> SVN-Revision: 42811owl
John Crispin
parent
7350373657
commit
619de2faf2
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@ -0,0 +1,202 @@
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From d8ce75934b888df0bd73dfd9c030a2b034a04977 Mon Sep 17 00:00:00 2001
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From: Alex Smith <alex.smith@imgtec.com>
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Date: Thu, 29 May 2014 11:10:01 +0100
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Subject: [PATCH] MIPS: octeon: Add interface mode detection for Octeon II
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Add interface mode detection for Octeon II. This is necessary to detect
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the interface modes correctly on the UBNT E200 board. Code is taken
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from the UBNT GPL source release, with some alterations: SRIO, ILK and
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RXAUI interface modes are removed and instead return disabled as these
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modes are not currently supported.
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Signed-off-by: Alex Smith <alex.smith@imgtec.com>
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Tested-by: David Daney <david.daney@cavium.com>
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Cc: linux-mips@linux-mips.org
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Patchwork: https://patchwork.linux-mips.org/patch/7039/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/cavium-octeon/executive/cvmx-helper.c | 166 ++++++++++++++++++++++++
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1 file changed, 166 insertions(+)
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--- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
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+++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
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@@ -104,6 +104,158 @@ int cvmx_helper_ports_on_interface(int i
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}
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/**
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+ * @INTERNAL
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+ * Return interface mode for CN68xx.
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+ */
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+static cvmx_helper_interface_mode_t __cvmx_get_mode_cn68xx(int interface)
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+{
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+ union cvmx_mio_qlmx_cfg qlm_cfg;
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+ switch (interface) {
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+ case 0:
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+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0));
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+ /* QLM is disabled when QLM SPD is 15. */
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+ if (qlm_cfg.s.qlm_spd == 15)
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+
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+ if (qlm_cfg.s.qlm_cfg == 2)
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+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
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+ else if (qlm_cfg.s.qlm_cfg == 3)
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+ return CVMX_HELPER_INTERFACE_MODE_XAUI;
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+ else
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ case 2:
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+ case 3:
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+ case 4:
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+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(interface));
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+ /* QLM is disabled when QLM SPD is 15. */
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+ if (qlm_cfg.s.qlm_spd == 15)
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+
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+ if (qlm_cfg.s.qlm_cfg == 2)
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+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
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+ else if (qlm_cfg.s.qlm_cfg == 3)
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+ return CVMX_HELPER_INTERFACE_MODE_XAUI;
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+ else
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ case 7:
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+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(3));
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+ /* QLM is disabled when QLM SPD is 15. */
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+ if (qlm_cfg.s.qlm_spd == 15) {
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ } else if (qlm_cfg.s.qlm_cfg != 0) {
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+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1));
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+ if (qlm_cfg.s.qlm_cfg != 0)
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ }
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+ return CVMX_HELPER_INTERFACE_MODE_NPI;
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+ case 8:
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+ return CVMX_HELPER_INTERFACE_MODE_LOOP;
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+ default:
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ }
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+}
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+
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+/**
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+ * @INTERNAL
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+ * Return interface mode for an Octeon II
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+ */
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+static cvmx_helper_interface_mode_t __cvmx_get_mode_octeon2(int interface)
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+{
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+ union cvmx_gmxx_inf_mode mode;
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+
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+ if (OCTEON_IS_MODEL(OCTEON_CN68XX))
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+ return __cvmx_get_mode_cn68xx(interface);
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+
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+ if (interface == 2)
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+ return CVMX_HELPER_INTERFACE_MODE_NPI;
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+
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+ if (interface == 3)
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+ return CVMX_HELPER_INTERFACE_MODE_LOOP;
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+
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+ /* Only present in CN63XX & CN66XX Octeon model */
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+ if ((OCTEON_IS_MODEL(OCTEON_CN63XX) &&
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+ (interface == 4 || interface == 5)) ||
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+ (OCTEON_IS_MODEL(OCTEON_CN66XX) &&
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+ interface >= 4 && interface <= 7)) {
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ }
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+
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+ if (OCTEON_IS_MODEL(OCTEON_CN66XX)) {
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+ union cvmx_mio_qlmx_cfg mio_qlm_cfg;
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+
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+ /* QLM2 is SGMII0 and QLM1 is SGMII1 */
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+ if (interface == 0)
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+ mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2));
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+ else if (interface == 1)
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+ mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1));
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+ else
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+
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+ if (mio_qlm_cfg.s.qlm_spd == 15)
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+
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+ if (mio_qlm_cfg.s.qlm_cfg == 9)
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+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
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+ else if (mio_qlm_cfg.s.qlm_cfg == 11)
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+ return CVMX_HELPER_INTERFACE_MODE_XAUI;
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+ else
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ } else if (OCTEON_IS_MODEL(OCTEON_CN61XX)) {
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+ union cvmx_mio_qlmx_cfg qlm_cfg;
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+
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+ if (interface == 0) {
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+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2));
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+ if (qlm_cfg.s.qlm_cfg == 2)
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+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
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+ else if (qlm_cfg.s.qlm_cfg == 3)
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+ return CVMX_HELPER_INTERFACE_MODE_XAUI;
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+ else
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ } else if (interface == 1) {
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+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0));
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+ if (qlm_cfg.s.qlm_cfg == 2)
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+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
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+ else if (qlm_cfg.s.qlm_cfg == 3)
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+ return CVMX_HELPER_INTERFACE_MODE_XAUI;
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+ else
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ }
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+ } else if (OCTEON_IS_MODEL(OCTEON_CNF71XX)) {
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+ if (interface == 0) {
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+ union cvmx_mio_qlmx_cfg qlm_cfg;
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+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0));
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+ if (qlm_cfg.s.qlm_cfg == 2)
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+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
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+ }
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ }
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+
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+ if (interface == 1 && OCTEON_IS_MODEL(OCTEON_CN63XX))
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+
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+ mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
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+
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+ if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
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+ switch (mode.cn63xx.mode) {
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+ case 0:
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+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
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+ case 1:
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+ return CVMX_HELPER_INTERFACE_MODE_XAUI;
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+ default:
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ }
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+ } else {
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+ if (!mode.s.en)
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+
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+ if (mode.s.type)
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+ return CVMX_HELPER_INTERFACE_MODE_GMII;
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+ else
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+ return CVMX_HELPER_INTERFACE_MODE_RGMII;
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+ }
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+}
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+
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+/**
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* Get the operating mode of an interface. Depending on the Octeon
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* chip and configuration, this function returns an enumeration
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* of the type of packet I/O supported by an interface.
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@@ -116,6 +268,20 @@ int cvmx_helper_ports_on_interface(int i
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cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
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{
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union cvmx_gmxx_inf_mode mode;
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+
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+ if (interface < 0 ||
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+ interface >= cvmx_helper_get_number_of_interfaces())
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+
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+ /*
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+ * Octeon II models
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+ */
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+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))
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+ return __cvmx_get_mode_octeon2(interface);
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+
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+ /*
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+ * Octeon and Octeon Plus models
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+ */
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if (interface == 2)
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return CVMX_HELPER_INTERFACE_MODE_NPI;
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@ -0,0 +1,47 @@
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From a53825ef4e9b2f42a21ad2b903f4d0ce691a5d63 Mon Sep 17 00:00:00 2001
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From: Eunbong Song <eunb.song@samsung.com>
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Date: Tue, 22 Apr 2014 06:16:15 +0000
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Subject: [PATCH] MIPS: Octeon: Add twsi interrupt initialization for OCTEON
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3XXX, 5XXX, 63XX
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In octeon_3xxx.dts file, there is a definiton for twsi/twsi2 interrupts.
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But there is no code for initialization of this interrupts. This patch adds
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code for initialization of twsi interrupts.
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Signed-off-by: Eunbong Song <eunb.song@samsung.com>
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Cc: linux-kernel@vger.kernel.org
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Cc: linux-mips@linux-mips.org
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Patchwork: https://patchwork.linux-mips.org/patch/6816/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/cavium-octeon/octeon-irq.c | 2 ++
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arch/mips/include/asm/mach-cavium-octeon/irq.h | 2 ++
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2 files changed, 4 insertions(+)
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--- a/arch/mips/cavium-octeon/octeon-irq.c
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+++ b/arch/mips/cavium-octeon/octeon-irq.c
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@@ -1260,11 +1260,13 @@ static void __init octeon_irq_init_ciu(v
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for (i = 0; i < 4; i++)
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octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 0, i + 40);
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+ octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_TWSI, 0, 45);
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octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_RML, 0, 46);
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for (i = 0; i < 4; i++)
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octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_TIMER0, 0, i + 52);
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octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 0, 56);
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+ octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_TWSI2, 0, 59);
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/* CIU_1 */
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for (i = 0; i < 16; i++)
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--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
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+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
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@@ -35,6 +35,8 @@ enum octeon_irq {
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OCTEON_IRQ_PCI_MSI2,
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OCTEON_IRQ_PCI_MSI3,
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+ OCTEON_IRQ_TWSI,
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+ OCTEON_IRQ_TWSI2,
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OCTEON_IRQ_RML,
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OCTEON_IRQ_TIMER0,
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OCTEON_IRQ_TIMER1,
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