mirror of https://github.com/hak5/openwrt-owl.git
ar8216: add swconfig attribute to display ARL table on AR8327/AR8337
Add global read-only swconfig attribute "arl_table" to display the address resolution table. So far the chip-specific part is implemented for AR8327/AR8337 only as I don't have the datasheets for the other AR8XXX chips. Successfully tested on TL-WDR4300 (AR8327rev2) and TL-WDR4900 (AR8327rev4). Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> SVN-Revision: 44104owl
Felix Fietkau
parent
6ce848f622
commit
3a313a3e11
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@ -134,19 +134,6 @@ const struct ar8xxx_mib_desc ar8236_mibs[39] = {
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static DEFINE_MUTEX(ar8xxx_dev_list_lock);
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static LIST_HEAD(ar8xxx_dev_list);
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static inline void
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split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
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{
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regaddr >>= 1;
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*r1 = regaddr & 0x1e;
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regaddr >>= 5;
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*r2 = regaddr & 0x7;
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regaddr >>= 3;
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*page = regaddr & 0x1ff;
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}
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/* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
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static int
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ar8xxx_phy_poll_reset(struct mii_bus *bus)
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@ -217,7 +204,7 @@ ar8xxx_phy_init(struct ar8xxx_priv *priv)
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ar8xxx_phy_poll_reset(bus);
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}
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static u32
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u32
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mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
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{
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struct mii_bus *bus = priv->mii_bus;
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@ -229,7 +216,7 @@ mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
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return (hi << 16) | lo;
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}
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static void
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void
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mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
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{
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struct mii_bus *bus = priv->mii_bus;
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@ -1291,6 +1278,78 @@ unlock:
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return ret;
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}
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int
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ar8xxx_sw_get_arl_table(struct switch_dev *dev,
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const struct switch_attr *attr,
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struct switch_val *val)
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{
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struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
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struct mii_bus *bus = priv->mii_bus;
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const struct ar8xxx_chip *chip = priv->chip;
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char *buf = priv->arl_buf;
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int i, j, k, len = 0;
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struct arl_entry *a, *a1;
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u32 status;
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if (!chip->get_arl_entry)
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return -EOPNOTSUPP;
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mutex_lock(&priv->reg_mutex);
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mutex_lock(&bus->mdio_lock);
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chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
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for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
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a = &priv->arl_table[i];
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duplicate:
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chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
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if (!status)
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break;
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/* avoid duplicates
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* ARL table can include multiple valid entries
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* per MAC, just with differing status codes
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*/
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for (j = 0; j < i; ++j) {
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a1 = &priv->arl_table[j];
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if (a->port == a1->port && !memcmp(a->mac, a1->mac, sizeof(a->mac)))
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goto duplicate;
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}
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}
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mutex_unlock(&bus->mdio_lock);
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len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
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"address resolution table\n");
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if (i == AR8XXX_NUM_ARL_RECORDS)
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len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
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"Too many entries found, displaying the first %d only!\n",
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AR8XXX_NUM_ARL_RECORDS);
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for (j = 0; j < priv->dev.ports; ++j) {
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for (k = 0; k < i; ++k) {
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a = &priv->arl_table[k];
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if (a->port != j)
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continue;
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len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
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"Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
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j,
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a->mac[5], a->mac[4], a->mac[3],
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a->mac[2], a->mac[1], a->mac[0]);
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}
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}
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val->value.s = buf;
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val->len = len;
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mutex_unlock(&priv->reg_mutex);
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return 0;
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}
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static const struct switch_attr ar8xxx_sw_attr_globals[] = {
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{
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.type = SWITCH_TYPE_INT,
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@ -1338,6 +1397,13 @@ static const struct switch_attr ar8xxx_sw_attr_globals[] = {
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.get = ar8xxx_sw_get_mirror_source_port,
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.max = AR8216_NUM_PORTS - 1
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},
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{
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.type = SWITCH_TYPE_STRING,
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.name = "arl_table",
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.description = "Get ARL table",
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.set = NULL,
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.get = ar8xxx_sw_get_arl_table,
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},
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};
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const struct switch_attr ar8xxx_sw_attr_port[2] = {
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@ -337,6 +337,18 @@ enum {
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AR8XXX_VER_AR8337 = 0x13,
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};
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#define AR8XXX_NUM_ARL_RECORDS 100
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enum arl_op {
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AR8XXX_ARL_INITIALIZE,
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AR8XXX_ARL_GET_NEXT
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};
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struct arl_entry {
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u8 port;
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u8 mac[6];
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};
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struct ar8xxx_priv;
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struct ar8xxx_mib_desc {
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@ -372,6 +384,8 @@ struct ar8xxx_chip {
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void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
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void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
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void (*set_mirror_regs)(struct ar8xxx_priv *priv);
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void (*get_arl_entry)(struct ar8xxx_priv *priv, struct arl_entry *a,
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u32 *status, enum arl_op op);
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int (*sw_hw_apply)(struct switch_dev *dev);
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const struct ar8xxx_mib_desc *mib_decs;
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@ -396,6 +410,8 @@ struct ar8xxx_priv {
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bool initialized;
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bool port4_phy;
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char buf[2048];
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struct arl_entry arl_table[AR8XXX_NUM_ARL_RECORDS];
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char arl_buf[AR8XXX_NUM_ARL_RECORDS * 32 + 256];
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bool link_up[AR8X16_MAX_PORTS];
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bool init;
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@ -422,6 +438,10 @@ struct ar8xxx_priv {
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int monitor_port;
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};
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u32
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mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum);
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void
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mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val);
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u32
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ar8xxx_read(struct ar8xxx_priv *priv, int reg);
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void
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@ -500,6 +520,10 @@ ar8xxx_sw_get_port_mib(struct switch_dev *dev,
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const struct switch_attr *attr,
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struct switch_val *val);
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int
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ar8xxx_sw_get_arl_table(struct switch_dev *dev,
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const struct switch_attr *attr,
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struct switch_val *val);
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int
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ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
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static inline struct ar8xxx_priv *
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@ -555,6 +579,19 @@ ar8xxx_reg_clear(struct ar8xxx_priv *priv, int reg, u32 val)
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ar8xxx_rmw(priv, reg, val, 0);
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}
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static inline void
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split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
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{
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regaddr >>= 1;
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*r1 = regaddr & 0x1e;
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regaddr >>= 5;
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*r2 = regaddr & 0x7;
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regaddr >>= 3;
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*page = regaddr & 0x1ff;
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}
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static inline void
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wait_for_page_switch(void)
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{
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@ -971,6 +971,78 @@ ar8327_sw_get_eee(struct switch_dev *dev,
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return 0;
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}
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static void
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ar8327_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
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{
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int timeout = 20;
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while (mii_read32(priv, r2, r1) & AR8327_ATU_FUNC_BUSY && --timeout)
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udelay(10);
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if (!timeout)
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pr_err("ar8327: timeout waiting for atu to become ready\n");
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}
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static void ar8327_get_arl_entry(struct ar8xxx_priv *priv,
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struct arl_entry *a, u32 *status, enum arl_op op)
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{
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struct mii_bus *bus = priv->mii_bus;
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u16 r2, page;
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u16 r1_data0, r1_data1, r1_data2, r1_func;
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u32 t, val0, val1, val2;
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int i;
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split_addr(AR8327_REG_ATU_DATA0, &r1_data0, &r2, &page);
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r2 |= 0x10;
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r1_data1 = (AR8327_REG_ATU_DATA1 >> 1) & 0x1e;
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r1_data2 = (AR8327_REG_ATU_DATA2 >> 1) & 0x1e;
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r1_func = (AR8327_REG_ATU_FUNC >> 1) & 0x1e;
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switch (op) {
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case AR8XXX_ARL_INITIALIZE:
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/* all ATU registers are on the same page
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* therefore set page only once
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*/
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bus->write(bus, 0x18, 0, page);
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wait_for_page_switch();
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ar8327_wait_atu_ready(priv, r2, r1_func);
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mii_write32(priv, r2, r1_data0, 0);
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mii_write32(priv, r2, r1_data1, 0);
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mii_write32(priv, r2, r1_data2, 0);
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break;
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case AR8XXX_ARL_GET_NEXT:
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mii_write32(priv, r2, r1_func,
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AR8327_ATU_FUNC_OP_GET_NEXT |
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AR8327_ATU_FUNC_BUSY);
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ar8327_wait_atu_ready(priv, r2, r1_func);
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val0 = mii_read32(priv, r2, r1_data0);
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val1 = mii_read32(priv, r2, r1_data1);
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val2 = mii_read32(priv, r2, r1_data2);
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*status = val2 & AR8327_ATU_STATUS;
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if (!*status)
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break;
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i = 0;
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t = AR8327_ATU_PORT0;
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while (!(val1 & t) && ++i < AR8327_NUM_PORTS)
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t <<= 1;
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a->port = i;
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a->mac[0] = (val0 & AR8327_ATU_ADDR0) >> AR8327_ATU_ADDR0_S;
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a->mac[1] = (val0 & AR8327_ATU_ADDR1) >> AR8327_ATU_ADDR1_S;
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a->mac[2] = (val0 & AR8327_ATU_ADDR2) >> AR8327_ATU_ADDR2_S;
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a->mac[3] = (val0 & AR8327_ATU_ADDR3) >> AR8327_ATU_ADDR3_S;
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a->mac[4] = (val1 & AR8327_ATU_ADDR4) >> AR8327_ATU_ADDR4_S;
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a->mac[5] = (val1 & AR8327_ATU_ADDR5) >> AR8327_ATU_ADDR5_S;
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break;
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}
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}
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static int
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ar8327_sw_hw_apply(struct switch_dev *dev)
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{
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@ -1041,6 +1113,13 @@ static const struct switch_attr ar8327_sw_attr_globals[] = {
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.get = ar8xxx_sw_get_mirror_source_port,
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.max = AR8327_NUM_PORTS - 1
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},
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{
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.type = SWITCH_TYPE_STRING,
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.name = "arl_table",
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.description = "Get ARL table",
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.set = NULL,
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.get = ar8xxx_sw_get_arl_table,
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},
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};
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static const struct switch_attr ar8327_sw_attr_port[] = {
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@ -1114,6 +1193,7 @@ const struct ar8xxx_chip ar8327_chip = {
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.vtu_load_vlan = ar8327_vtu_load_vlan,
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.phy_fixup = ar8327_phy_fixup,
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.set_mirror_regs = ar8327_set_mirror_regs,
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.get_arl_entry = ar8327_get_arl_entry,
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.sw_hw_apply = ar8327_sw_hw_apply,
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.num_mibs = ARRAY_SIZE(ar8236_mibs),
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@ -1146,6 +1226,7 @@ const struct ar8xxx_chip ar8337_chip = {
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.vtu_load_vlan = ar8327_vtu_load_vlan,
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.phy_fixup = ar8327_phy_fixup,
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.set_mirror_regs = ar8327_set_mirror_regs,
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.get_arl_entry = ar8327_get_arl_entry,
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.sw_hw_apply = ar8327_sw_hw_apply,
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.num_mibs = ARRAY_SIZE(ar8236_mibs),
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@ -114,8 +114,29 @@
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#define AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH 3
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#define AR8327_REG_ATU_DATA0 0x600
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#define AR8327_ATU_ADDR0 BITS(0, 8)
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#define AR8327_ATU_ADDR0_S 0
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#define AR8327_ATU_ADDR1 BITS(8, 8)
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#define AR8327_ATU_ADDR1_S 8
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#define AR8327_ATU_ADDR2 BITS(16, 8)
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#define AR8327_ATU_ADDR2_S 16
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#define AR8327_ATU_ADDR3 BITS(24, 8)
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#define AR8327_ATU_ADDR3_S 24
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#define AR8327_REG_ATU_DATA1 0x604
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#define AR8327_ATU_ADDR4 BITS(0, 8)
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#define AR8327_ATU_ADDR4_S 0
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#define AR8327_ATU_ADDR5 BITS(8, 8)
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#define AR8327_ATU_ADDR5_S 8
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#define AR8327_ATU_PORTS BITS(16, 7)
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#define AR8327_ATU_PORT0 BIT(16)
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#define AR8327_ATU_PORT1 BIT(17)
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#define AR8327_ATU_PORT2 BIT(18)
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#define AR8327_ATU_PORT3 BIT(19)
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#define AR8327_ATU_PORT4 BIT(20)
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#define AR8327_ATU_PORT5 BIT(21)
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#define AR8327_ATU_PORT6 BIT(22)
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#define AR8327_REG_ATU_DATA2 0x608
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#define AR8327_ATU_STATUS BITS(0, 4)
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#define AR8327_REG_ATU_FUNC 0x60c
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#define AR8327_ATU_FUNC_OP BITS(0, 4)
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