mirror of https://github.com/hak5/openwrt-owl.git
fix SPI register switch and prepare for UDC, thanks to Henk Vergonet (#4783)
SVN-Revision: 14914owl
Florian Fainelli
parent
fb5b85c7c8
commit
32c29f1aaf
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@ -4,6 +4,7 @@ menu "CPU support"
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config BCM63XX_CPU_6338
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bool "support 6338 CPU"
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select USB_ARCH_HAS_OHCI
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select USB_ARCH_HAS_UDC
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select USB_OHCI_BIG_ENDIAN_DESC
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select USB_OHCI_BIG_ENDIAN_MMIO
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@ -11,6 +12,7 @@ config BCM63XX_CPU_6348
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bool "support 6348 CPU"
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select HW_HAS_PCI
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select USB_ARCH_HAS_OHCI
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select USB_ARCH_HAS_UDC
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select USB_OHCI_BIG_ENDIAN_DESC
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select USB_OHCI_BIG_ENDIAN_MMIO
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@ -3,6 +3,7 @@ obj-y += dev-uart.o
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obj-y += dev-pcmcia.o
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obj-y += dev-usb-ohci.o
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obj-y += dev-usb-ehci.o
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obj-y += dev-usb-udc.o
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obj-y += dev-enet.o
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obj-y += dev-wdt.o
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obj-y += dev-spi.o
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@ -27,6 +27,7 @@
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#include <bcm63xx_dev_pcmcia.h>
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#include <bcm63xx_dev_usb_ohci.h>
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#include <bcm63xx_dev_usb_ehci.h>
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#include <bcm63xx_dev_usb_udc.h>
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#include <bcm63xx_dev_spi.h>
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#include <board_bcm963xx.h>
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@ -163,27 +164,23 @@ static struct board_info __initdata board_FAST2404 = {
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};
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static struct board_info __initdata board_DV201AMR = {
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.name = "DV201AMR",
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.expected_cpu_id = 0x6348,
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.name = "DV201AMR",
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.expected_cpu_id = 0x6348,
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.has_enet0 = 1,
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.has_enet1 = 1,
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.has_pci = 1,
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.has_pci = 1,
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.has_ohci0 = 1,
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.has_udc0 = 1,
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.has_enet0 = 1,
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.has_enet1 = 1,
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.enet0 = {
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.has_phy = 1,
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.use_internal_phy = 1,
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},
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.enet1 = {
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.force_speed_100 = 1,
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.force_duplex_full = 1,
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},
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.has_ohci0 = 1,
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.has_pccard = 1,
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.has_ehci0 = 1,
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.enet1 = {
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.force_speed_100 = 1,
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.force_duplex_full = 1,
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},
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};
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static struct board_info __initdata board_96348gw_a = {
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@ -525,6 +522,8 @@ int __init board_register_devices(void)
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if (board.has_ehci0)
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bcm63xx_ehci_register();
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if (board.has_udc0)
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bcm63xx_udc_register();
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/* Generate MAC address for WLAN and
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* register our SPROM */
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if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
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@ -136,6 +136,26 @@ static struct clk clk_usbh = {
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.set = usbh_set,
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};
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/*
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* USB slave clock
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*/
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static void usbs_set(struct clk *clk, int enable)
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{
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u32 mask;
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switch(bcm63xx_get_cpu_id()) {
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case BCM6338_CPU_ID: mask = CKCTL_6338_USBS_EN; break;
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case BCM6348_CPU_ID: mask = CKCTL_6348_USBS_EN; break;
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default:
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return;
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}
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bcm_hwclock_set(mask, enable);
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}
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static struct clk clk_usbs = {
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.set = usbs_set,
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};
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/*
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* SPI clock
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*/
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@ -202,6 +222,8 @@ struct clk *clk_get(struct device *dev, const char *id)
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return &clk_ephy;
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if (!strcmp(id, "usbh"))
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return &clk_usbh;
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if (!strcmp(id, "usbs"))
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return &clk_usbs;
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if (!strcmp(id, "spi"))
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return &clk_spi;
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if (!strcmp(id, "periph"))
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@ -37,6 +37,7 @@ static const unsigned long bcm96338_regs_base[] = {
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[RSET_PERF] = BCM_6338_PERF_BASE,
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[RSET_TIMER] = BCM_6338_TIMER_BASE,
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[RSET_WDT] = BCM_6338_WDT_BASE,
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[RSET_UDC0] = BCM_6338_UDC0_BASE,
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[RSET_UART0] = BCM_6338_UART0_BASE,
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[RSET_GPIO] = BCM_6338_GPIO_BASE,
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[RSET_SPI] = BCM_6338_SPI_BASE,
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@ -48,6 +49,7 @@ static const int bcm96338_irqs[] = {
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[IRQ_SPI] = BCM_6338_SPI_IRQ,
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[IRQ_UART0] = BCM_6338_UART0_IRQ,
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[IRQ_DSL] = BCM_6338_DSL_IRQ,
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[IRQ_UDC0] = BCM_6338_UDC0_IRQ,
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[IRQ_ENET0] = BCM_6338_ENET0_IRQ,
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[IRQ_ENET_PHY] = BCM_6338_ENET_PHY_IRQ,
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[IRQ_ENET0_RXDMA] = BCM_6338_ENET0_RXDMA_IRQ,
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@ -83,6 +85,7 @@ static const unsigned long bcm96348_regs_base[] = {
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[RSET_OHCI0] = BCM_6348_OHCI0_BASE,
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[RSET_OHCI_PRIV] = BCM_6348_OHCI_PRIV_BASE,
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[RSET_USBH_PRIV] = BCM_6348_USBH_PRIV_BASE,
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[RSET_UDC0] = BCM_6348_UDC0_BASE,
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[RSET_MPI] = BCM_6348_MPI_BASE,
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[RSET_PCMCIA] = BCM_6348_PCMCIA_BASE,
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[RSET_SDRAM] = BCM_6348_SDRAM_BASE,
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@ -99,6 +102,7 @@ static const int bcm96348_irqs[] = {
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[IRQ_SPI] = BCM_6348_SPI_IRQ,
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[IRQ_UART0] = BCM_6348_UART0_IRQ,
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[IRQ_DSL] = BCM_6348_DSL_IRQ,
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[IRQ_UDC0] = BCM_6348_UDC0_IRQ,
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[IRQ_ENET0] = BCM_6348_ENET0_IRQ,
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[IRQ_ENET1] = BCM_6348_ENET1_IRQ,
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[IRQ_ENET_PHY] = BCM_6348_ENET_PHY_IRQ,
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@ -0,0 +1,58 @@
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/*
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* Copyright (C) 2009 Henk Vergonet <Henk.Vergonet@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <bcm63xx_cpu.h>
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static struct resource udc_resources[] = {
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{
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.start = -1, /* filled at runtime */
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.end = -1, /* filled at runtime */
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.flags = IORESOURCE_MEM,
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},
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{
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.start = -1, /* filled at runtime */
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 udc_dmamask = ~(u32)0;
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static struct platform_device bcm63xx_udc_device = {
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.name = "bcm63xx-udc",
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.id = 0,
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.num_resources = ARRAY_SIZE(udc_resources),
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.resource = udc_resources,
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.dev = {
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.dma_mask = &udc_dmamask,
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.coherent_dma_mask = 0xffffffff,
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},
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};
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int __init bcm63xx_udc_register(void)
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{
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if (!BCMCPU_IS_6338() && !BCMCPU_IS_6348())
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return 0;
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udc_resources[0].start = bcm63xx_regset_address(RSET_UDC0);
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udc_resources[0].end = udc_resources[0].start;
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udc_resources[0].end += RSET_UDC_SIZE - 1;
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udc_resources[1].start = bcm63xx_get_irq_number(IRQ_UDC0);
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return platform_device_register(&bcm63xx_udc_device);
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}
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@ -4,6 +4,8 @@
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#include <linux/types.h>
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#include <linux/init.h>
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#include <bcm63xx_regs.h>
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/*
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* Macro to fetch bcm63xx cpu id and revision, should be optimized at
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* compile time if only one CPU support is enabled (idea stolen from
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@ -106,12 +108,18 @@ enum bcm63xx_regs_set {
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*/
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#define BCM_6338_PERF_BASE (0xfffe0000)
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#define BCM_6338_TIMER_BASE (0xfffe0000)
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#define BCM_6338_WDT_BASE (0xfffe001c)
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#define BCM_6338_BB_BASE (0xfffe0100) /* bus bridge registers */
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#define BCM_6338_TIMER_BASE (0xfffe0200)
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#define BCM_6338_WDT_BASE (0xfffe021c)
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#define BCM_6338_UART0_BASE (0xfffe0300)
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#define BCM_6338_GPIO_BASE (0xfffe0400)
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#define BCM_6338_SPI_BASE (0xfffe0c00)
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#define BCM_6338_DSL_BASE (0xfffe1000)
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#define BCM_6338_SAR_BASE (0xfffe2000)
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#define BCM_6338_ENETDMA_BASE (0xfffe2400)
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#define BCM_6338_USBDMA_BASE (0xfffe2400)
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#define BCM_6338_ENET0_BASE (0xfffe2800)
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#define BCM_6338_UDC0_BASE (0xfffe3000) /* USB_CTL_BASE */
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#define BCM_6338_MEMC_BASE (0xfffe3100)
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/*
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@ -119,12 +127,14 @@ enum bcm63xx_regs_set {
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*/
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#define BCM_6348_DSL_LMEM_BASE (0xfff00000)
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#define BCM_6348_PERF_BASE (0xfffe0000)
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#define BCM_6348_BB_BASE (0xfffe0100) /* bus bridge registers */
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#define BCM_6348_TIMER_BASE (0xfffe0200)
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#define BCM_6348_WDT_BASE (0xfffe021c)
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#define BCM_6348_UART0_BASE (0xfffe0300)
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#define BCM_6348_GPIO_BASE (0xfffe0400)
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#define BCM_6348_SPI_BASE (0xfffe0c00)
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#define BCM_6348_UDC0_BASE (0xfffe1000)
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#define BCM_6348_USBDMA_BASE (0xfffe1400)
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#define BCM_6348_OHCI0_BASE (0xfffe1b00)
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#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
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#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
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@ -132,6 +142,8 @@ enum bcm63xx_regs_set {
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#define BCM_6348_PCMCIA_BASE (0xfffe2054)
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#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
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#define BCM_6348_DSL_BASE (0xfffe3000)
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#define BCM_6348_SAR_BASE (0xfffe4000)
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#define BCM_6348_UBUS_BASE (0xfffe5000)
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#define BCM_6348_ENET0_BASE (0xfffe6000)
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#define BCM_6348_ENET1_BASE (0xfffe6800)
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#define BCM_6348_ENETDMA_BASE (0xfffe7000)
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@ -351,6 +363,8 @@ switch (reg) {
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return SPI_BCM_6348_SPI_CMD;
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case SPI_INT_MASK_ST:
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return SPI_BCM_6348_SPI_MASK_INT_ST;
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case SPI_INT_MASK:
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return SPI_BCM_6348_SPI_INT_MASK;
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case SPI_INT_STATUS:
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return SPI_BCM_6348_SPI_INT_STATUS;
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case SPI_ST:
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@ -367,7 +381,7 @@ switch (reg) {
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return SPI_BCM_6348_SPI_MSG_CTL;
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case SPI_MSG_DATA:
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return SPI_BCM_6348_SPI_MSG_DATA;
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case SPI_BCM_6348_SPI_RX_DATA:
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case SPI_RX_DATA:
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return SPI_BCM_6348_SPI_RX_DATA;
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}
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#endif
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@ -411,6 +425,7 @@ enum bcm63xx_irq {
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IRQ_UART0,
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IRQ_SPI,
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IRQ_DSL,
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IRQ_UDC0,
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IRQ_ENET0,
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IRQ_ENET1,
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IRQ_ENET_PHY,
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@ -434,7 +449,7 @@ enum bcm63xx_irq {
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#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4)
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#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
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#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
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#define BCM_6338_USBS_IRQ (IRQ_INTERNAL_BASE + 7)
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#define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7)
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#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
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#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
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#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10)
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@ -453,10 +468,17 @@ enum bcm63xx_irq {
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#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
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#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
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#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
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#define BCM_6348_UDC0_IRQ (IRQ_INTERNAL_BASE + 6)
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#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
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#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
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#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
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#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
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#define BCM_6348_USB_CNTL_RX_DMA (IRQ_INTERNAL_BASE + 14)
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#define BCM_6348_USB_CNTL_TX_DMA (IRQ_INTERNAL_BASE + 15)
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#define BCM_6348_USB_BULK_RX_DMA (IRQ_INTERNAL_BASE + 16)
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#define BCM_6348_USB_BULK_TX_DMA (IRQ_INTERNAL_BASE + 17)
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#define BCM_6348_USB_ISO_RX_DMA (IRQ_INTERNAL_BASE + 18)
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#define BCM_6348_USB_ISO_TX_DMA (IRQ_INTERNAL_BASE + 19)
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#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
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#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
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#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
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@ -0,0 +1,6 @@
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#ifndef BCM63XX_DEV_USB_UDC_H_
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#define BCM63XX_DEV_USB_UDC_H_
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int bcm63xx_udc_register(void);
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#endif /* BCM63XX_DEV_USB_UDC_H_ */
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@ -41,6 +41,7 @@ struct board_info {
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unsigned int has_pccard:1;
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unsigned int has_ohci0:1;
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unsigned int has_ehci0:1;
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unsigned int has_udc0:1;
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/* ethernet config */
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struct bcm63xx_enet_platform_data enet0;
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