mirror of https://github.com/hak5/openwrt-owl.git
Gabor Juhos
parent
512df38f5c
commit
32a18a05f8
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@ -0,0 +1,228 @@
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CONFIG_AG71XX=y
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CONFIG_AG71XX_AR8216_SUPPORT=y
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# CONFIG_AG71XX_DEBUG is not set
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# CONFIG_AG71XX_DEBUG_FS is not set
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CONFIG_AR8216_PHY=y
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CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
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CONFIG_ARCH_DISCARD_MEMBLOCK=y
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# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
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# CONFIG_ARCH_HAS_ILOG2_U32 is not set
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# CONFIG_ARCH_HAS_ILOG2_U64 is not set
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
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CONFIG_ARCH_REQUIRE_GPIOLIB=y
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# CONFIG_ARCH_SUPPORTS_MSI is not set
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ATH79=y
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CONFIG_ATH79_DEV_AP9X_PCI=y
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CONFIG_ATH79_DEV_DSA=y
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CONFIG_ATH79_DEV_ETH=y
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CONFIG_ATH79_DEV_GPIO_BUTTONS=y
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CONFIG_ATH79_DEV_LEDS_GPIO=y
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CONFIG_ATH79_DEV_M25P80=y
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CONFIG_ATH79_DEV_SPI=y
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CONFIG_ATH79_DEV_USB=y
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CONFIG_ATH79_DEV_WMAC=y
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CONFIG_ATH79_MACH_ALFA_AP96=y
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CONFIG_ATH79_MACH_ALFA_NX=y
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CONFIG_ATH79_MACH_ALL0258N=y
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CONFIG_ATH79_MACH_AP113=y
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CONFIG_ATH79_MACH_AP121=y
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CONFIG_ATH79_MACH_AP81=y
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CONFIG_ATH79_MACH_AP83=y
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CONFIG_ATH79_MACH_AP96=y
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CONFIG_ATH79_MACH_AW_NR580=y
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CONFIG_ATH79_MACH_DB120=y
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CONFIG_ATH79_MACH_DIR_600_A1=y
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CONFIG_ATH79_MACH_DIR_615_C1=y
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CONFIG_ATH79_MACH_DIR_825_B1=y
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CONFIG_ATH79_MACH_EAP7660D=y
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CONFIG_ATH79_MACH_HORNET_UB=y
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CONFIG_ATH79_MACH_JA76PF=y
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CONFIG_ATH79_MACH_JWAP003=y
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CONFIG_ATH79_MACH_MZK_W04NU=y
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CONFIG_ATH79_MACH_MZK_W300NH=y
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CONFIG_ATH79_MACH_NBG460N=y
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CONFIG_ATH79_MACH_OM2P=y
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CONFIG_ATH79_MACH_PB42=y
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CONFIG_ATH79_MACH_PB44=y
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CONFIG_ATH79_MACH_PB92=y
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CONFIG_ATH79_MACH_RB4XX=y
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CONFIG_ATH79_MACH_RB750=y
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CONFIG_ATH79_MACH_RW2458N=y
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CONFIG_ATH79_MACH_TEW_632BRP=y
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CONFIG_ATH79_MACH_TEW_673GRU=y
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CONFIG_ATH79_MACH_TL_MR11U=y
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CONFIG_ATH79_MACH_TL_MR3020=y
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CONFIG_ATH79_MACH_TL_MR3X20=y
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CONFIG_ATH79_MACH_TL_WA901ND=y
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CONFIG_ATH79_MACH_TL_WA901ND_V2=y
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CONFIG_ATH79_MACH_TL_WR1043ND=y
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CONFIG_ATH79_MACH_TL_WR2543N=y
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CONFIG_ATH79_MACH_TL_WR703N=y
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CONFIG_ATH79_MACH_TL_WR741ND=y
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CONFIG_ATH79_MACH_TL_WR741ND_V4=y
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CONFIG_ATH79_MACH_TL_WR841N_V1=y
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CONFIG_ATH79_MACH_TL_WR941ND=y
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CONFIG_ATH79_MACH_UBNT=y
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CONFIG_ATH79_MACH_UBNT_XM=y
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CONFIG_ATH79_MACH_WHR_HP_G300N=y
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CONFIG_ATH79_MACH_WNDR3700=y
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CONFIG_ATH79_MACH_WNR2000=y
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CONFIG_ATH79_MACH_WP543=y
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CONFIG_ATH79_MACH_WPE72=y
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CONFIG_ATH79_MACH_WRT160NL=y
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CONFIG_ATH79_MACH_WRT400N=y
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CONFIG_ATH79_MACH_WZR_HP_AG300H=y
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CONFIG_ATH79_MACH_WZR_HP_G300NH=y
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CONFIG_ATH79_MACH_WZR_HP_G300NH2=y
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CONFIG_ATH79_MACH_WZR_HP_G450H=y
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CONFIG_ATH79_MACH_ZCN_1523H=y
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CONFIG_ATH79_NVRAM=y
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CONFIG_ATH79_PCI_ATH9K_FIXUP=y
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# CONFIG_ATH79_WDT is not set
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CONFIG_BCMA_POSSIBLE=y
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CONFIG_CC_OPTIMIZE_FOR_SIZE=y
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CONFIG_CEVT_R4K=y
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CONFIG_CEVT_R4K_LIB=y
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CONFIG_CMDLINE="rootfstype=squashfs,yaffs,jffs2 noinitrd"
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CONFIG_CMDLINE_BOOL=y
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# CONFIG_CMDLINE_OVERRIDE is not set
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CONFIG_CPU_BIG_ENDIAN=y
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CONFIG_CPU_HAS_PREFETCH=y
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CONFIG_CPU_HAS_SYNC=y
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CONFIG_CPU_MIPS32=y
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CONFIG_CPU_MIPS32_R2=y
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CONFIG_CPU_MIPSR2=y
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CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
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CONFIG_CPU_SUPPORTS_HIGHMEM=y
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CONFIG_CSRC_R4K=y
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CONFIG_CSRC_R4K_LIB=y
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CONFIG_DECOMPRESS_LZMA=y
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CONFIG_DMA_NONCOHERENT=y
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CONFIG_EARLY_PRINTK=y
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CONFIG_GENERIC_ATOMIC64=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
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CONFIG_GENERIC_CMOS_UPDATE=y
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# CONFIG_GENERIC_CPU_DEVICES is not set
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CONFIG_GENERIC_GPIO=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIO_NXP_74HC153=y
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CONFIG_GPIO_PCF857X=y
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CONFIG_GPIO_SYSFS=y
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CONFIG_HARDWARE_WATCHPOINTS=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT=y
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CONFIG_HAVE_ARCH_JUMP_LABEL=y
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CONFIG_HAVE_ARCH_KGDB=y
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CONFIG_HAVE_C_RECORDMCOUNT=y
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CONFIG_HAVE_DMA_API_DEBUG=y
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CONFIG_HAVE_DMA_ATTRS=y
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CONFIG_HAVE_DYNAMIC_FTRACE=y
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CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
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CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
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CONFIG_HAVE_GENERIC_DMA_COHERENT=y
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CONFIG_HAVE_GENERIC_HARDIRQS=y
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CONFIG_HAVE_IDE=y
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CONFIG_HAVE_IRQ_WORK=y
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CONFIG_HAVE_MEMBLOCK=y
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CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
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CONFIG_HAVE_OPROFILE=y
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CONFIG_HAVE_PERF_EVENTS=y
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CONFIG_HW_HAS_PCI=y
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CONFIG_I2C=y
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CONFIG_I2C_ALGOBIT=y
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CONFIG_I2C_BOARDINFO=y
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CONFIG_I2C_GPIO=y
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# CONFIG_I2C_PXA_PCI is not set
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CONFIG_IMAGE_CMDLINE_HACK=y
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CONFIG_INITRAMFS_ROOT_GID=0
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CONFIG_INITRAMFS_ROOT_UID=0
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CONFIG_INITRAMFS_SOURCE="../../root"
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CONFIG_IP17XX_PHY=y
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CONFIG_IRQ_CPU=y
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CONFIG_IRQ_FORCED_THREADING=y
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# CONFIG_LANTIQ is not set
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# CONFIG_LEDS_GPIO is not set
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# CONFIG_LEDS_RB750 is not set
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# CONFIG_LEDS_WNDR3700_USB is not set
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# CONFIG_M25PXX_USE_FAST_READ is not set
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CONFIG_MARVELL_PHY=y
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CONFIG_MICREL_PHY=y
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# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
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CONFIG_MIPS=y
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CONFIG_MIPS_L1_CACHE_SHIFT=5
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CONFIG_MIPS_MACHINE=y
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CONFIG_MIPS_MT_DISABLED=y
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# CONFIG_MLX4_CORE is not set
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# CONFIG_MTD_CFI_INTELEXT is not set
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CONFIG_MTD_CMDLINE_PARTS=y
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CONFIG_MTD_JEDECPROBE=y
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CONFIG_MTD_M25P80=y
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CONFIG_MTD_MYLOADER_PARTS=y
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2
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CONFIG_MTD_REDBOOT_PARTS=y
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CONFIG_MTD_TPLINK_PARTS=y
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CONFIG_MTD_WRT160NL_PARTS=y
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CONFIG_MYLOADER=y
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CONFIG_NEED_DMA_MAP_STATE=y
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CONFIG_NEED_PER_CPU_KM=y
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CONFIG_NET_DSA=y
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CONFIG_NET_DSA_MV88E6060=y
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CONFIG_NET_DSA_MV88E6063=y
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CONFIG_NET_DSA_TAG_TRAILER=y
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CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
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CONFIG_PAGEFLAGS_EXTENDED=y
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CONFIG_PCI=y
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CONFIG_PCI_AR724X=y
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CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PERF_USE_VMALLOC=y
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CONFIG_PHYLIB=y
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# CONFIG_PREEMPT_RCU is not set
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# CONFIG_QUOTACTL is not set
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CONFIG_RTL8306_PHY=y
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CONFIG_RTL8366RB_PHY=y
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CONFIG_RTL8366S_PHY=y
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CONFIG_RTL8366_SMI=y
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CONFIG_RTL8367_PHY=y
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# CONFIG_SCSI_DMA is not set
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CONFIG_SERIAL_8250_NR_UARTS=1
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CONFIG_SERIAL_8250_RUNTIME_UARTS=1
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CONFIG_SERIAL_AR933X=y
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CONFIG_SERIAL_AR933X_CONSOLE=y
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CONFIG_SERIAL_AR933X_NR_UARTS=2
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# CONFIG_SLAB is not set
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CONFIG_SLUB=y
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CONFIG_SOC_AR71XX=y
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CONFIG_SOC_AR724X=y
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CONFIG_SOC_AR913X=y
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CONFIG_SOC_AR933X=y
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CONFIG_SOC_AR934X=y
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CONFIG_SPI=y
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CONFIG_SPI_AP83=y
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CONFIG_SPI_ATH79=y
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CONFIG_SPI_BITBANG=y
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CONFIG_SPI_GPIO=y
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CONFIG_SPI_MASTER=y
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# CONFIG_SPI_RB4XX is not set
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# CONFIG_SPI_RB4XX_CPLD is not set
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# CONFIG_SPI_VSC7385 is not set
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CONFIG_SWCONFIG=y
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CONFIG_SWCONFIG_LEDS=y
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CONFIG_SYS_HAS_CPU_MIPS32_R2=y
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CONFIG_SYS_HAS_EARLY_PRINTK=y
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CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
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CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
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CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
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CONFIG_USB_ARCH_HAS_XHCI=y
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CONFIG_USB_SUPPORT=y
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CONFIG_XZ_DEC=y
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CONFIG_ZONE_DMA_FLAG=0
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@ -0,0 +1,294 @@
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/*
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* net/dsa/mv88e6063.c - Driver for Marvell 88e6063 switch chips
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* Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org>
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*
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* This driver was base on: net/dsa/mv88e6060.c
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* net/dsa/mv88e6063.c - Driver for Marvell 88e6060 switch chips
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* Copyright (c) 2008-2009 Marvell Semiconductor
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/list.h>
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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#include <net/dsa.h>
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#define REG_BASE 0x10
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#define REG_PHY(p) (REG_BASE + (p))
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#define REG_PORT(p) (REG_BASE + 8 + (p))
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#define REG_GLOBAL (REG_BASE + 0x0f)
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#define NUM_PORTS 7
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static int reg_read(struct dsa_switch *ds, int addr, int reg)
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{
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return mdiobus_read(ds->master_mii_bus, addr, reg);
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}
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#define REG_READ(addr, reg) \
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({ \
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int __ret; \
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\
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__ret = reg_read(ds, addr, reg); \
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if (__ret < 0) \
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return __ret; \
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__ret; \
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})
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static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
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{
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return mdiobus_write(ds->master_mii_bus, addr, reg, val);
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}
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||||||
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#define REG_WRITE(addr, reg, val) \
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({ \
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int __ret; \
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\
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__ret = reg_write(ds, addr, reg, val); \
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if (__ret < 0) \
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return __ret; \
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})
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static char *mv88e6063_probe(struct mii_bus *bus, int sw_addr)
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{
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int ret;
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ret = mdiobus_read(bus, REG_PORT(0), 0x03);
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if (ret >= 0) {
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ret &= 0xfff0;
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if (ret == 0x1530)
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return "Marvell 88E6063";
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}
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|
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return NULL;
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}
|
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|
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static int mv88e6063_switch_reset(struct dsa_switch *ds)
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|
{
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int i;
|
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int ret;
|
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|
||||||
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/*
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* Set all ports to the disabled state.
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*/
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for (i = 0; i < NUM_PORTS; i++) {
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ret = REG_READ(REG_PORT(i), 0x04);
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REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
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||||||
|
}
|
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|
||||||
|
/*
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||||||
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* Wait for transmit queues to drain.
|
||||||
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*/
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msleep(2);
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|
||||||
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/*
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* Reset the switch.
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*/
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REG_WRITE(REG_GLOBAL, 0x0a, 0xa130);
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|
||||||
|
/*
|
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* Wait up to one second for reset to complete.
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||||||
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*/
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for (i = 0; i < 1000; i++) {
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ret = REG_READ(REG_GLOBAL, 0x00);
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||||||
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if ((ret & 0x8000) == 0x0000)
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break;
|
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|
||||||
|
msleep(1);
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||||||
|
}
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|
if (i == 1000)
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return -ETIMEDOUT;
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|
||||||
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return 0;
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}
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|
||||||
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static int mv88e6063_setup_global(struct dsa_switch *ds)
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{
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/*
|
||||||
|
* Disable discarding of frames with excessive collisions,
|
||||||
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* set the maximum frame size to 1536 bytes, and mask all
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||||||
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* interrupt sources.
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||||||
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*/
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REG_WRITE(REG_GLOBAL, 0x04, 0x0800);
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|
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/*
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|
* Enable automatic address learning, set the address
|
||||||
|
* database size to 1024 entries, and set the default aging
|
||||||
|
* time to 5 minutes.
|
||||||
|
*/
|
||||||
|
REG_WRITE(REG_GLOBAL, 0x0a, 0x2130);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mv88e6063_setup_port(struct dsa_switch *ds, int p)
|
||||||
|
{
|
||||||
|
int addr = REG_PORT(p);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Do not force flow control, disable Ingress and Egress
|
||||||
|
* Header tagging, disable VLAN tunneling, and set the port
|
||||||
|
* state to Forwarding. Additionally, if this is the CPU
|
||||||
|
* port, enable Ingress and Egress Trailer tagging mode.
|
||||||
|
*/
|
||||||
|
REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Port based VLAN map: give each port its own address
|
||||||
|
* database, allow the CPU port to talk to each of the 'real'
|
||||||
|
* ports, and allow each of the 'real' ports to only talk to
|
||||||
|
* the CPU port.
|
||||||
|
*/
|
||||||
|
REG_WRITE(addr, 0x06,
|
||||||
|
((p & 0xf) << 12) |
|
||||||
|
(dsa_is_cpu_port(ds, p) ?
|
||||||
|
ds->phys_port_mask :
|
||||||
|
(1 << ds->dst->cpu_port)));
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Port Association Vector: when learning source addresses
|
||||||
|
* of packets, add the address to the address database using
|
||||||
|
* a port bitmap that has only the bit for this port set and
|
||||||
|
* the other bits clear.
|
||||||
|
*/
|
||||||
|
REG_WRITE(addr, 0x0b, 1 << p);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mv88e6063_setup(struct dsa_switch *ds)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = mv88e6063_switch_reset(ds);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
/* @@@ initialise atu */
|
||||||
|
|
||||||
|
ret = mv88e6063_setup_global(ds);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
for (i = 0; i < NUM_PORTS; i++) {
|
||||||
|
ret = mv88e6063_setup_port(ds, i);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mv88e6063_set_addr(struct dsa_switch *ds, u8 *addr)
|
||||||
|
{
|
||||||
|
REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
|
||||||
|
REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
|
||||||
|
REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mv88e6063_port_to_phy_addr(int port)
|
||||||
|
{
|
||||||
|
if (port >= 0 && port <= NUM_PORTS)
|
||||||
|
return REG_PHY(port);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mv88e6063_phy_read(struct dsa_switch *ds, int port, int regnum)
|
||||||
|
{
|
||||||
|
int addr;
|
||||||
|
|
||||||
|
addr = mv88e6063_port_to_phy_addr(port);
|
||||||
|
if (addr == -1)
|
||||||
|
return 0xffff;
|
||||||
|
|
||||||
|
return reg_read(ds, addr, regnum);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int
|
||||||
|
mv88e6063_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
|
||||||
|
{
|
||||||
|
int addr;
|
||||||
|
|
||||||
|
addr = mv88e6063_port_to_phy_addr(port);
|
||||||
|
if (addr == -1)
|
||||||
|
return 0xffff;
|
||||||
|
|
||||||
|
return reg_write(ds, addr, regnum, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mv88e6063_poll_link(struct dsa_switch *ds)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < DSA_MAX_PORTS; i++) {
|
||||||
|
struct net_device *dev;
|
||||||
|
int uninitialized_var(port_status);
|
||||||
|
int link;
|
||||||
|
int speed;
|
||||||
|
int duplex;
|
||||||
|
int fc;
|
||||||
|
|
||||||
|
dev = ds->ports[i];
|
||||||
|
if (dev == NULL)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
link = 0;
|
||||||
|
if (dev->flags & IFF_UP) {
|
||||||
|
port_status = reg_read(ds, REG_PORT(i), 0x00);
|
||||||
|
if (port_status < 0)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
link = !!(port_status & 0x1000);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!link) {
|
||||||
|
if (netif_carrier_ok(dev)) {
|
||||||
|
printk(KERN_INFO "%s: link down\n", dev->name);
|
||||||
|
netif_carrier_off(dev);
|
||||||
|
}
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
speed = (port_status & 0x0100) ? 100 : 10;
|
||||||
|
duplex = (port_status & 0x0200) ? 1 : 0;
|
||||||
|
fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;
|
||||||
|
|
||||||
|
if (!netif_carrier_ok(dev)) {
|
||||||
|
printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
|
||||||
|
"flow control %sabled\n", dev->name,
|
||||||
|
speed, duplex ? "full" : "half",
|
||||||
|
fc ? "en" : "dis");
|
||||||
|
netif_carrier_on(dev);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct dsa_switch_driver mv88e6063_switch_driver = {
|
||||||
|
.tag_protocol = htons(ETH_P_TRAILER),
|
||||||
|
.probe = mv88e6063_probe,
|
||||||
|
.setup = mv88e6063_setup,
|
||||||
|
.set_addr = mv88e6063_set_addr,
|
||||||
|
.phy_read = mv88e6063_phy_read,
|
||||||
|
.phy_write = mv88e6063_phy_write,
|
||||||
|
.poll_link = mv88e6063_poll_link,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int __init mv88e6063_init(void)
|
||||||
|
{
|
||||||
|
register_switch_driver(&mv88e6063_switch_driver);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
module_init(mv88e6063_init);
|
||||||
|
|
||||||
|
static void __exit mv88e6063_cleanup(void)
|
||||||
|
{
|
||||||
|
unregister_switch_driver(&mv88e6063_switch_driver);
|
||||||
|
}
|
||||||
|
module_exit(mv88e6063_cleanup);
|
||||||
|
|
@ -0,0 +1,24 @@
|
||||||
|
From cf6855546330c3d349d41496975f32255bb6fd07 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Fri, 9 Dec 2011 22:02:57 +0100
|
||||||
|
Subject: [PATCH 01/35] MIPS: ath79: avoid a kernel bug on AR913X
|
||||||
|
|
||||||
|
Wireless mac registration causes a BUG on AR913X SoCs due to
|
||||||
|
a missing 'else'.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
---
|
||||||
|
arch/mips/ath79/dev-wmac.c | 2 +-
|
||||||
|
1 files changed, 1 insertions(+), 1 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/dev-wmac.c
|
||||||
|
+++ b/arch/mips/ath79/dev-wmac.c
|
||||||
|
@@ -96,7 +96,7 @@ void __init ath79_register_wmac(u8 *cal_
|
||||||
|
{
|
||||||
|
if (soc_is_ar913x())
|
||||||
|
ar913x_wmac_setup();
|
||||||
|
- if (soc_is_ar933x())
|
||||||
|
+ else if (soc_is_ar933x())
|
||||||
|
ar933x_wmac_setup();
|
||||||
|
else
|
||||||
|
BUG();
|
||||||
|
|
@ -0,0 +1,151 @@
|
||||||
|
From c98b48027516a2e71688a5957e4e0120f4aa8c61 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Fri, 18 Nov 2011 09:47:44 +0100
|
||||||
|
Subject: [PATCH 02/35] MIPS: ath79: separate common PCI code
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
The 'pcibios_map_irq' and 'pcibios_plat_dev_init'
|
||||||
|
are common functions and only instance one of them
|
||||||
|
can be present in a single kernel.
|
||||||
|
|
||||||
|
Currently these functions can be built only if the
|
||||||
|
CONFIG_SOC_AR724X option is selected. However the
|
||||||
|
ath79 platform contain support for the AR71XX SoCs,.
|
||||||
|
The AR71XX SoCs have a differnet PCI controller,
|
||||||
|
and those will require a different code.
|
||||||
|
|
||||||
|
Move the common PCI code into a separeate file in
|
||||||
|
order to be able to use that with other SoCs as
|
||||||
|
well.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: René Bolldorf <xsecute@googlemail.com>
|
||||||
|
|
||||||
|
v4: - add an Acked-by tag from René
|
||||||
|
v3: - no changes
|
||||||
|
v2: - no changes
|
||||||
|
---
|
||||||
|
arch/mips/ath79/Makefile | 1 +
|
||||||
|
arch/mips/ath79/pci.c | 46 +++++++++++++++++++++++++++++++++++++++++++
|
||||||
|
arch/mips/pci/pci-ath724x.c | 34 -------------------------------
|
||||||
|
3 files changed, 47 insertions(+), 34 deletions(-)
|
||||||
|
create mode 100644 arch/mips/ath79/pci.c
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/Makefile
|
||||||
|
+++ b/arch/mips/ath79/Makefile
|
||||||
|
@@ -11,6 +11,7 @@
|
||||||
|
obj-y := prom.o setup.o irq.o common.o clock.o gpio.o
|
||||||
|
|
||||||
|
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
|
||||||
|
+obj-$(CONFIG_PCI) += pci.o
|
||||||
|
|
||||||
|
#
|
||||||
|
# Devices
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/arch/mips/ath79/pci.c
|
||||||
|
@@ -0,0 +1,46 @@
|
||||||
|
+/*
|
||||||
|
+ * Atheros AR71XX/AR724X specific PCI setup code
|
||||||
|
+ *
|
||||||
|
+ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
|
||||||
|
+ *
|
||||||
|
+ * This program is free software; you can redistribute it and/or modify it
|
||||||
|
+ * under the terms of the GNU General Public License version 2 as published
|
||||||
|
+ * by the Free Software Foundation.
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+#include <linux/pci.h>
|
||||||
|
+#include <asm/mach-ath79/pci-ath724x.h>
|
||||||
|
+
|
||||||
|
+static struct ath724x_pci_data *pci_data;
|
||||||
|
+static int pci_data_size;
|
||||||
|
+
|
||||||
|
+void ath724x_pci_add_data(struct ath724x_pci_data *data, int size)
|
||||||
|
+{
|
||||||
|
+ pci_data = data;
|
||||||
|
+ pci_data_size = size;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
|
||||||
|
+{
|
||||||
|
+ unsigned int devfn = dev->devfn;
|
||||||
|
+ int irq = -1;
|
||||||
|
+
|
||||||
|
+ if (devfn > pci_data_size - 1)
|
||||||
|
+ return irq;
|
||||||
|
+
|
||||||
|
+ irq = pci_data[devfn].irq;
|
||||||
|
+
|
||||||
|
+ return irq;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||||
|
+{
|
||||||
|
+ unsigned int devfn = dev->devfn;
|
||||||
|
+
|
||||||
|
+ if (devfn > pci_data_size - 1)
|
||||||
|
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||||
|
+
|
||||||
|
+ dev->dev.platform_data = pci_data[devfn].pdata;
|
||||||
|
+
|
||||||
|
+ return PCIBIOS_SUCCESSFUL;
|
||||||
|
+}
|
||||||
|
--- a/arch/mips/pci/pci-ath724x.c
|
||||||
|
+++ b/arch/mips/pci/pci-ath724x.c
|
||||||
|
@@ -9,7 +9,6 @@
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/pci.h>
|
||||||
|
-#include <asm/mach-ath79/pci-ath724x.h>
|
||||||
|
|
||||||
|
#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
|
||||||
|
#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
|
||||||
|
@@ -19,8 +18,6 @@
|
||||||
|
#define ATH724X_PCI_MEM_SIZE 0x08000000
|
||||||
|
|
||||||
|
static DEFINE_SPINLOCK(ath724x_pci_lock);
|
||||||
|
-static struct ath724x_pci_data *pci_data;
|
||||||
|
-static int pci_data_size;
|
||||||
|
|
||||||
|
static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
|
||||||
|
int size, uint32_t *value)
|
||||||
|
@@ -133,37 +130,6 @@ static struct pci_controller ath724x_pci
|
||||||
|
.mem_resource = &ath724x_mem_resource,
|
||||||
|
};
|
||||||
|
|
||||||
|
-void ath724x_pci_add_data(struct ath724x_pci_data *data, int size)
|
||||||
|
-{
|
||||||
|
- pci_data = data;
|
||||||
|
- pci_data_size = size;
|
||||||
|
-}
|
||||||
|
-
|
||||||
|
-int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
|
||||||
|
-{
|
||||||
|
- unsigned int devfn = dev->devfn;
|
||||||
|
- int irq = -1;
|
||||||
|
-
|
||||||
|
- if (devfn > pci_data_size - 1)
|
||||||
|
- return irq;
|
||||||
|
-
|
||||||
|
- irq = pci_data[devfn].irq;
|
||||||
|
-
|
||||||
|
- return irq;
|
||||||
|
-}
|
||||||
|
-
|
||||||
|
-int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||||
|
-{
|
||||||
|
- unsigned int devfn = dev->devfn;
|
||||||
|
-
|
||||||
|
- if (devfn > pci_data_size - 1)
|
||||||
|
- return PCIBIOS_DEVICE_NOT_FOUND;
|
||||||
|
-
|
||||||
|
- dev->dev.platform_data = pci_data[devfn].pdata;
|
||||||
|
-
|
||||||
|
- return PCIBIOS_SUCCESSFUL;
|
||||||
|
-}
|
||||||
|
-
|
||||||
|
static int __init ath724x_pcibios_init(void)
|
||||||
|
{
|
||||||
|
register_pci_controller(&ath724x_pci_controller);
|
||||||
|
|
@ -0,0 +1,103 @@
|
||||||
|
From 204fd70abd99099f6c2e2213a2baa1d51c03a039 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Fri, 18 Nov 2011 09:50:50 +0100
|
||||||
|
Subject: [PATCH 03/35] MIPS: ath79: rename pci-ath724x.h
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
The declared function in this header file is used by the
|
||||||
|
ath79 platform code only. Move the header to the platform
|
||||||
|
directory.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: René Bolldorf <xsecute@googlemail.com>
|
||||||
|
|
||||||
|
v4: - add an Acked-by tag from René
|
||||||
|
v3: - move include "pci.h" out of the #ifdef CONFIG_PCI section
|
||||||
|
v2: - no changes
|
||||||
|
---
|
||||||
|
arch/mips/ath79/mach-ubnt-xm.c | 2 +-
|
||||||
|
arch/mips/ath79/pci.c | 2 +-
|
||||||
|
arch/mips/ath79/pci.h | 21 +++++++++++++++++++++
|
||||||
|
arch/mips/include/asm/mach-ath79/pci-ath724x.h | 21 ---------------------
|
||||||
|
4 files changed, 23 insertions(+), 23 deletions(-)
|
||||||
|
create mode 100644 arch/mips/ath79/pci.h
|
||||||
|
delete mode 100644 arch/mips/include/asm/mach-ath79/pci-ath724x.h
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
+++ b/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
@@ -15,13 +15,13 @@
|
||||||
|
|
||||||
|
#ifdef CONFIG_PCI
|
||||||
|
#include <linux/ath9k_platform.h>
|
||||||
|
-#include <asm/mach-ath79/pci-ath724x.h>
|
||||||
|
#endif /* CONFIG_PCI */
|
||||||
|
|
||||||
|
#include "machtypes.h"
|
||||||
|
#include "dev-gpio-buttons.h"
|
||||||
|
#include "dev-leds-gpio.h"
|
||||||
|
#include "dev-spi.h"
|
||||||
|
+#include "pci.h"
|
||||||
|
|
||||||
|
#define UBNT_XM_GPIO_LED_L1 0
|
||||||
|
#define UBNT_XM_GPIO_LED_L2 1
|
||||||
|
--- a/arch/mips/ath79/pci.c
|
||||||
|
+++ b/arch/mips/ath79/pci.c
|
||||||
|
@@ -9,7 +9,7 @@
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/pci.h>
|
||||||
|
-#include <asm/mach-ath79/pci-ath724x.h>
|
||||||
|
+#include "pci.h"
|
||||||
|
|
||||||
|
static struct ath724x_pci_data *pci_data;
|
||||||
|
static int pci_data_size;
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/arch/mips/ath79/pci.h
|
||||||
|
@@ -0,0 +1,21 @@
|
||||||
|
+/*
|
||||||
|
+ * Atheros 724x PCI support
|
||||||
|
+ *
|
||||||
|
+ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
|
||||||
|
+ *
|
||||||
|
+ * This program is free software; you can redistribute it and/or modify it
|
||||||
|
+ * under the terms of the GNU General Public License version 2 as published
|
||||||
|
+ * by the Free Software Foundation.
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
|
||||||
|
+#define __ASM_MACH_ATH79_PCI_ATH724X_H
|
||||||
|
+
|
||||||
|
+struct ath724x_pci_data {
|
||||||
|
+ int irq;
|
||||||
|
+ void *pdata;
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
|
||||||
|
+
|
||||||
|
+#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/pci-ath724x.h
|
||||||
|
+++ /dev/null
|
||||||
|
@@ -1,21 +0,0 @@
|
||||||
|
-/*
|
||||||
|
- * Atheros 724x PCI support
|
||||||
|
- *
|
||||||
|
- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
|
||||||
|
- *
|
||||||
|
- * This program is free software; you can redistribute it and/or modify it
|
||||||
|
- * under the terms of the GNU General Public License version 2 as published
|
||||||
|
- * by the Free Software Foundation.
|
||||||
|
- */
|
||||||
|
-
|
||||||
|
-#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
|
||||||
|
-#define __ASM_MACH_ATH79_PCI_ATH724X_H
|
||||||
|
-
|
||||||
|
-struct ath724x_pci_data {
|
||||||
|
- int irq;
|
||||||
|
- void *pdata;
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
|
||||||
|
-
|
||||||
|
-#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
|
||||||
|
|
@ -0,0 +1,62 @@
|
||||||
|
From 7e59b95e3424c078de0d75d699433da0dd289fc1 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Fri, 18 Nov 2011 10:13:37 +0100
|
||||||
|
Subject: [PATCH 04/35] MIPS: ath79: make ath724x_pcibios_init visible for external code
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
Signed-off-by: René Bolldorf <xsecute@googlemail.com>
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
|
||||||
|
v4: - add a sob tag
|
||||||
|
v3: - no changes
|
||||||
|
v2: - fix a typo in my e-mail address
|
||||||
|
---
|
||||||
|
arch/mips/include/asm/mach-ath79/pci.h | 20 ++++++++++++++++++++
|
||||||
|
arch/mips/pci/pci-ath724x.c | 3 ++-
|
||||||
|
2 files changed, 22 insertions(+), 1 deletions(-)
|
||||||
|
create mode 100644 arch/mips/include/asm/mach-ath79/pci.h
|
||||||
|
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/pci.h
|
||||||
|
@@ -0,0 +1,20 @@
|
||||||
|
+/*
|
||||||
|
+ * Atheros 724x PCI support
|
||||||
|
+ *
|
||||||
|
+ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
|
||||||
|
+ *
|
||||||
|
+ * This program is free software; you can redistribute it and/or modify it
|
||||||
|
+ * under the terms of the GNU General Public License version 2 as published
|
||||||
|
+ * by the Free Software Foundation.
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+#ifndef __ASM_MACH_ATH79_PCI_H
|
||||||
|
+#define __ASM_MACH_ATH79_PCI_H
|
||||||
|
+
|
||||||
|
+#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X)
|
||||||
|
+int ath724x_pcibios_init(void);
|
||||||
|
+#else
|
||||||
|
+static inline int ath724x_pcibios_init(void) { return 0 };
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
+#endif /* __ASM_MACH_ATH79_PCI_H */
|
||||||
|
--- a/arch/mips/pci/pci-ath724x.c
|
||||||
|
+++ b/arch/mips/pci/pci-ath724x.c
|
||||||
|
@@ -9,6 +9,7 @@
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/pci.h>
|
||||||
|
+#include <asm/mach-ath79/pci.h>
|
||||||
|
|
||||||
|
#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
|
||||||
|
#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
|
||||||
|
@@ -130,7 +131,7 @@ static struct pci_controller ath724x_pci
|
||||||
|
.mem_resource = &ath724x_mem_resource,
|
||||||
|
};
|
||||||
|
|
||||||
|
-static int __init ath724x_pcibios_init(void)
|
||||||
|
+int __init ath724x_pcibios_init(void)
|
||||||
|
{
|
||||||
|
register_pci_controller(&ath724x_pci_controller);
|
||||||
|
|
||||||
|
|
@ -0,0 +1,80 @@
|
||||||
|
From fbf38a9b03d0c47ed602f090ebb2d8ecc0d51d04 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Fri, 18 Nov 2011 10:25:26 +0100
|
||||||
|
Subject: [PATCH 05/35] MIPS: ath79: add a common PCI registration function
|
||||||
|
|
||||||
|
The current code unconditionally registers the AR724X
|
||||||
|
specific PCI controller, even if the kernel is running
|
||||||
|
on a different SoC.
|
||||||
|
|
||||||
|
Add a common function for PCI controller registration,
|
||||||
|
and only register the AR724X PCI controller if the kernel
|
||||||
|
is running on an AR724X SoC.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
|
||||||
|
v4: - simplify ath79_register_pci function
|
||||||
|
v3: - fix compile error if CONFIG_PCI is not defined
|
||||||
|
- add __init annotation to ath79_register_pci
|
||||||
|
v2: - no changes
|
||||||
|
---
|
||||||
|
arch/mips/ath79/mach-ubnt-xm.c | 1 +
|
||||||
|
arch/mips/ath79/pci.c | 10 ++++++++++
|
||||||
|
arch/mips/ath79/pci.h | 6 ++++++
|
||||||
|
arch/mips/pci/pci-ath724x.c | 2 --
|
||||||
|
4 files changed, 17 insertions(+), 2 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
+++ b/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
@@ -111,6 +111,7 @@ static void __init ubnt_xm_init(void)
|
||||||
|
ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
|
||||||
|
#endif /* CONFIG_PCI */
|
||||||
|
|
||||||
|
+ ath79_register_pci();
|
||||||
|
}
|
||||||
|
|
||||||
|
MIPS_MACHINE(ATH79_MACH_UBNT_XM,
|
||||||
|
--- a/arch/mips/ath79/pci.c
|
||||||
|
+++ b/arch/mips/ath79/pci.c
|
||||||
|
@@ -9,6 +9,8 @@
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/pci.h>
|
||||||
|
+#include <asm/mach-ath79/ath79.h>
|
||||||
|
+#include <asm/mach-ath79/pci.h>
|
||||||
|
#include "pci.h"
|
||||||
|
|
||||||
|
static struct ath724x_pci_data *pci_data;
|
||||||
|
@@ -44,3 +46,11 @@ int pcibios_plat_dev_init(struct pci_dev
|
||||||
|
|
||||||
|
return PCIBIOS_SUCCESSFUL;
|
||||||
|
}
|
||||||
|
+
|
||||||
|
+int __init ath79_register_pci(void)
|
||||||
|
+{
|
||||||
|
+ if (soc_is_ar724x())
|
||||||
|
+ return ath724x_pcibios_init();
|
||||||
|
+
|
||||||
|
+ return -ENODEV;
|
||||||
|
+}
|
||||||
|
--- a/arch/mips/ath79/pci.h
|
||||||
|
+++ b/arch/mips/ath79/pci.h
|
||||||
|
@@ -18,4 +18,10 @@ struct ath724x_pci_data {
|
||||||
|
|
||||||
|
void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
|
||||||
|
|
||||||
|
+#ifdef CONFIG_PCI
|
||||||
|
+int ath79_register_pci(void);
|
||||||
|
+#else
|
||||||
|
+static inline int ath79_register_pci(void) { return 0; }
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
|
||||||
|
--- a/arch/mips/pci/pci-ath724x.c
|
||||||
|
+++ b/arch/mips/pci/pci-ath724x.c
|
||||||
|
@@ -137,5 +137,3 @@ int __init ath724x_pcibios_init(void)
|
||||||
|
|
||||||
|
return PCIBIOS_SUCCESSFUL;
|
||||||
|
}
|
||||||
|
-
|
||||||
|
-arch_initcall(ath724x_pcibios_init);
|
||||||
|
|
@ -0,0 +1,318 @@
|
||||||
|
From 9510a9988638ae2386277a832fab2df8ca37d75a Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Fri, 18 Nov 2011 11:07:26 +0100
|
||||||
|
Subject: [PATCH 06/35] MIPS: ath79: rename pci-ath724x.c to make it reflect the real SoC name
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: René Bolldorf <xsecute@googlemail.com>
|
||||||
|
|
||||||
|
v4: - add an Acked-by tag from René
|
||||||
|
v4: - no changes
|
||||||
|
v3: - no changes
|
||||||
|
v2: - no changes
|
||||||
|
---
|
||||||
|
arch/mips/pci/Makefile | 2 +-
|
||||||
|
arch/mips/pci/pci-ar724x.c | 139 +++++++++++++++++++++++++++++++++++++++++++
|
||||||
|
arch/mips/pci/pci-ath724x.c | 139 -------------------------------------------
|
||||||
|
3 files changed, 140 insertions(+), 140 deletions(-)
|
||||||
|
create mode 100644 arch/mips/pci/pci-ar724x.c
|
||||||
|
delete mode 100644 arch/mips/pci/pci-ath724x.c
|
||||||
|
|
||||||
|
--- a/arch/mips/pci/Makefile
|
||||||
|
+++ b/arch/mips/pci/Makefile
|
||||||
|
@@ -19,7 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
|
||||||
|
obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
|
||||||
|
ops-bcm63xx.o
|
||||||
|
obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
|
||||||
|
-obj-$(CONFIG_SOC_AR724X) += pci-ath724x.o
|
||||||
|
+obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o
|
||||||
|
|
||||||
|
#
|
||||||
|
# These are still pretty much in the old state, watch, go blind.
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/arch/mips/pci/pci-ar724x.c
|
||||||
|
@@ -0,0 +1,139 @@
|
||||||
|
+/*
|
||||||
|
+ * Atheros 724x PCI support
|
||||||
|
+ *
|
||||||
|
+ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
|
||||||
|
+ *
|
||||||
|
+ * This program is free software; you can redistribute it and/or modify it
|
||||||
|
+ * under the terms of the GNU General Public License version 2 as published
|
||||||
|
+ * by the Free Software Foundation.
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+#include <linux/pci.h>
|
||||||
|
+#include <asm/mach-ath79/pci.h>
|
||||||
|
+
|
||||||
|
+#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
|
||||||
|
+#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
|
||||||
|
+
|
||||||
|
+#define ATH724X_PCI_DEV_BASE 0x14000000
|
||||||
|
+#define ATH724X_PCI_MEM_BASE 0x10000000
|
||||||
|
+#define ATH724X_PCI_MEM_SIZE 0x08000000
|
||||||
|
+
|
||||||
|
+static DEFINE_SPINLOCK(ath724x_pci_lock);
|
||||||
|
+
|
||||||
|
+static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
|
||||||
|
+ int size, uint32_t *value)
|
||||||
|
+{
|
||||||
|
+ unsigned long flags, addr, tval, mask;
|
||||||
|
+
|
||||||
|
+ if (devfn)
|
||||||
|
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||||
|
+
|
||||||
|
+ if (where & (size - 1))
|
||||||
|
+ return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||||
|
+
|
||||||
|
+ spin_lock_irqsave(&ath724x_pci_lock, flags);
|
||||||
|
+
|
||||||
|
+ switch (size) {
|
||||||
|
+ case 1:
|
||||||
|
+ addr = where & ~3;
|
||||||
|
+ mask = 0xff000000 >> ((where % 4) * 8);
|
||||||
|
+ tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
|
||||||
|
+ tval = tval & ~mask;
|
||||||
|
+ *value = (tval >> ((4 - (where % 4))*8));
|
||||||
|
+ break;
|
||||||
|
+ case 2:
|
||||||
|
+ addr = where & ~3;
|
||||||
|
+ mask = 0xffff0000 >> ((where % 4)*8);
|
||||||
|
+ tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
|
||||||
|
+ tval = tval & ~mask;
|
||||||
|
+ *value = (tval >> ((4 - (where % 4))*8));
|
||||||
|
+ break;
|
||||||
|
+ case 4:
|
||||||
|
+ *value = reg_read(ATH724X_PCI_DEV_BASE + where);
|
||||||
|
+ break;
|
||||||
|
+ default:
|
||||||
|
+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
||||||
|
+
|
||||||
|
+ return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
||||||
|
+
|
||||||
|
+ return PCIBIOS_SUCCESSFUL;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
|
||||||
|
+ int size, uint32_t value)
|
||||||
|
+{
|
||||||
|
+ unsigned long flags, tval, addr, mask;
|
||||||
|
+
|
||||||
|
+ if (devfn)
|
||||||
|
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||||
|
+
|
||||||
|
+ if (where & (size - 1))
|
||||||
|
+ return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||||
|
+
|
||||||
|
+ spin_lock_irqsave(&ath724x_pci_lock, flags);
|
||||||
|
+
|
||||||
|
+ switch (size) {
|
||||||
|
+ case 1:
|
||||||
|
+ addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
|
||||||
|
+ mask = 0xff000000 >> ((where % 4)*8);
|
||||||
|
+ tval = reg_read(addr);
|
||||||
|
+ tval = tval & ~mask;
|
||||||
|
+ tval |= (value << ((4 - (where % 4))*8)) & mask;
|
||||||
|
+ reg_write(addr, tval);
|
||||||
|
+ break;
|
||||||
|
+ case 2:
|
||||||
|
+ addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
|
||||||
|
+ mask = 0xffff0000 >> ((where % 4)*8);
|
||||||
|
+ tval = reg_read(addr);
|
||||||
|
+ tval = tval & ~mask;
|
||||||
|
+ tval |= (value << ((4 - (where % 4))*8)) & mask;
|
||||||
|
+ reg_write(addr, tval);
|
||||||
|
+ break;
|
||||||
|
+ case 4:
|
||||||
|
+ reg_write((ATH724X_PCI_DEV_BASE + where), value);
|
||||||
|
+ break;
|
||||||
|
+ default:
|
||||||
|
+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
||||||
|
+
|
||||||
|
+ return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
||||||
|
+
|
||||||
|
+ return PCIBIOS_SUCCESSFUL;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static struct pci_ops ath724x_pci_ops = {
|
||||||
|
+ .read = ath724x_pci_read,
|
||||||
|
+ .write = ath724x_pci_write,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct resource ath724x_io_resource = {
|
||||||
|
+ .name = "PCI IO space",
|
||||||
|
+ .start = 0,
|
||||||
|
+ .end = 0,
|
||||||
|
+ .flags = IORESOURCE_IO,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct resource ath724x_mem_resource = {
|
||||||
|
+ .name = "PCI memory space",
|
||||||
|
+ .start = ATH724X_PCI_MEM_BASE,
|
||||||
|
+ .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
|
||||||
|
+ .flags = IORESOURCE_MEM,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct pci_controller ath724x_pci_controller = {
|
||||||
|
+ .pci_ops = &ath724x_pci_ops,
|
||||||
|
+ .io_resource = &ath724x_io_resource,
|
||||||
|
+ .mem_resource = &ath724x_mem_resource,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+int __init ath724x_pcibios_init(void)
|
||||||
|
+{
|
||||||
|
+ register_pci_controller(&ath724x_pci_controller);
|
||||||
|
+
|
||||||
|
+ return PCIBIOS_SUCCESSFUL;
|
||||||
|
+}
|
||||||
|
--- a/arch/mips/pci/pci-ath724x.c
|
||||||
|
+++ /dev/null
|
||||||
|
@@ -1,139 +0,0 @@
|
||||||
|
-/*
|
||||||
|
- * Atheros 724x PCI support
|
||||||
|
- *
|
||||||
|
- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
|
||||||
|
- *
|
||||||
|
- * This program is free software; you can redistribute it and/or modify it
|
||||||
|
- * under the terms of the GNU General Public License version 2 as published
|
||||||
|
- * by the Free Software Foundation.
|
||||||
|
- */
|
||||||
|
-
|
||||||
|
-#include <linux/pci.h>
|
||||||
|
-#include <asm/mach-ath79/pci.h>
|
||||||
|
-
|
||||||
|
-#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
|
||||||
|
-#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
|
||||||
|
-
|
||||||
|
-#define ATH724X_PCI_DEV_BASE 0x14000000
|
||||||
|
-#define ATH724X_PCI_MEM_BASE 0x10000000
|
||||||
|
-#define ATH724X_PCI_MEM_SIZE 0x08000000
|
||||||
|
-
|
||||||
|
-static DEFINE_SPINLOCK(ath724x_pci_lock);
|
||||||
|
-
|
||||||
|
-static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
|
||||||
|
- int size, uint32_t *value)
|
||||||
|
-{
|
||||||
|
- unsigned long flags, addr, tval, mask;
|
||||||
|
-
|
||||||
|
- if (devfn)
|
||||||
|
- return PCIBIOS_DEVICE_NOT_FOUND;
|
||||||
|
-
|
||||||
|
- if (where & (size - 1))
|
||||||
|
- return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||||
|
-
|
||||||
|
- spin_lock_irqsave(&ath724x_pci_lock, flags);
|
||||||
|
-
|
||||||
|
- switch (size) {
|
||||||
|
- case 1:
|
||||||
|
- addr = where & ~3;
|
||||||
|
- mask = 0xff000000 >> ((where % 4) * 8);
|
||||||
|
- tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
|
||||||
|
- tval = tval & ~mask;
|
||||||
|
- *value = (tval >> ((4 - (where % 4))*8));
|
||||||
|
- break;
|
||||||
|
- case 2:
|
||||||
|
- addr = where & ~3;
|
||||||
|
- mask = 0xffff0000 >> ((where % 4)*8);
|
||||||
|
- tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
|
||||||
|
- tval = tval & ~mask;
|
||||||
|
- *value = (tval >> ((4 - (where % 4))*8));
|
||||||
|
- break;
|
||||||
|
- case 4:
|
||||||
|
- *value = reg_read(ATH724X_PCI_DEV_BASE + where);
|
||||||
|
- break;
|
||||||
|
- default:
|
||||||
|
- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
||||||
|
-
|
||||||
|
- return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||||
|
- }
|
||||||
|
-
|
||||||
|
- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
||||||
|
-
|
||||||
|
- return PCIBIOS_SUCCESSFUL;
|
||||||
|
-}
|
||||||
|
-
|
||||||
|
-static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
|
||||||
|
- int size, uint32_t value)
|
||||||
|
-{
|
||||||
|
- unsigned long flags, tval, addr, mask;
|
||||||
|
-
|
||||||
|
- if (devfn)
|
||||||
|
- return PCIBIOS_DEVICE_NOT_FOUND;
|
||||||
|
-
|
||||||
|
- if (where & (size - 1))
|
||||||
|
- return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||||
|
-
|
||||||
|
- spin_lock_irqsave(&ath724x_pci_lock, flags);
|
||||||
|
-
|
||||||
|
- switch (size) {
|
||||||
|
- case 1:
|
||||||
|
- addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
|
||||||
|
- mask = 0xff000000 >> ((where % 4)*8);
|
||||||
|
- tval = reg_read(addr);
|
||||||
|
- tval = tval & ~mask;
|
||||||
|
- tval |= (value << ((4 - (where % 4))*8)) & mask;
|
||||||
|
- reg_write(addr, tval);
|
||||||
|
- break;
|
||||||
|
- case 2:
|
||||||
|
- addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
|
||||||
|
- mask = 0xffff0000 >> ((where % 4)*8);
|
||||||
|
- tval = reg_read(addr);
|
||||||
|
- tval = tval & ~mask;
|
||||||
|
- tval |= (value << ((4 - (where % 4))*8)) & mask;
|
||||||
|
- reg_write(addr, tval);
|
||||||
|
- break;
|
||||||
|
- case 4:
|
||||||
|
- reg_write((ATH724X_PCI_DEV_BASE + where), value);
|
||||||
|
- break;
|
||||||
|
- default:
|
||||||
|
- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
||||||
|
-
|
||||||
|
- return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||||
|
- }
|
||||||
|
-
|
||||||
|
- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
||||||
|
-
|
||||||
|
- return PCIBIOS_SUCCESSFUL;
|
||||||
|
-}
|
||||||
|
-
|
||||||
|
-static struct pci_ops ath724x_pci_ops = {
|
||||||
|
- .read = ath724x_pci_read,
|
||||||
|
- .write = ath724x_pci_write,
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static struct resource ath724x_io_resource = {
|
||||||
|
- .name = "PCI IO space",
|
||||||
|
- .start = 0,
|
||||||
|
- .end = 0,
|
||||||
|
- .flags = IORESOURCE_IO,
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static struct resource ath724x_mem_resource = {
|
||||||
|
- .name = "PCI memory space",
|
||||||
|
- .start = ATH724X_PCI_MEM_BASE,
|
||||||
|
- .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
|
||||||
|
- .flags = IORESOURCE_MEM,
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static struct pci_controller ath724x_pci_controller = {
|
||||||
|
- .pci_ops = &ath724x_pci_ops,
|
||||||
|
- .io_resource = &ath724x_io_resource,
|
||||||
|
- .mem_resource = &ath724x_mem_resource,
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-int __init ath724x_pcibios_init(void)
|
||||||
|
-{
|
||||||
|
- register_pci_controller(&ath724x_pci_controller);
|
||||||
|
-
|
||||||
|
- return PCIBIOS_SUCCESSFUL;
|
||||||
|
-}
|
||||||
|
|
@ -0,0 +1,266 @@
|
||||||
|
From 0cbee5634678ffbd10bee9e302d013392dd8289e Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Fri, 18 Nov 2011 11:16:33 +0100
|
||||||
|
Subject: [PATCH 07/35] MIPS: ath79: replace ath724x to ar724x
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
Replace the 'ath724x' to 'ar724x' in function, variable and
|
||||||
|
structure names to reflect the name of the real SoC.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: René Bolldorf <xsecute@googlemail.com>
|
||||||
|
|
||||||
|
v4: - add an Acked-by tag from René
|
||||||
|
- refreshed due to the changes in a previous patch
|
||||||
|
v3: - no changes
|
||||||
|
v2: - no changes
|
||||||
|
---
|
||||||
|
arch/mips/ath79/mach-ubnt-xm.c | 4 +-
|
||||||
|
arch/mips/ath79/pci.c | 6 ++--
|
||||||
|
arch/mips/ath79/pci.h | 10 +++---
|
||||||
|
arch/mips/include/asm/mach-ath79/pci.h | 4 +-
|
||||||
|
arch/mips/pci/pci-ar724x.c | 62 ++++++++++++++++----------------
|
||||||
|
5 files changed, 43 insertions(+), 43 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
+++ b/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
@@ -84,7 +84,7 @@ static struct ath79_spi_platform_data ub
|
||||||
|
#ifdef CONFIG_PCI
|
||||||
|
static struct ath9k_platform_data ubnt_xm_eeprom_data;
|
||||||
|
|
||||||
|
-static struct ath724x_pci_data ubnt_xm_pci_data[] = {
|
||||||
|
+static struct ar724x_pci_data ubnt_xm_pci_data[] = {
|
||||||
|
{
|
||||||
|
.irq = UBNT_XM_PCI_IRQ,
|
||||||
|
.pdata = &ubnt_xm_eeprom_data,
|
||||||
|
@@ -108,7 +108,7 @@ static void __init ubnt_xm_init(void)
|
||||||
|
memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
|
||||||
|
sizeof(ubnt_xm_eeprom_data.eeprom_data));
|
||||||
|
|
||||||
|
- ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
|
||||||
|
+ ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
|
||||||
|
#endif /* CONFIG_PCI */
|
||||||
|
|
||||||
|
ath79_register_pci();
|
||||||
|
--- a/arch/mips/ath79/pci.c
|
||||||
|
+++ b/arch/mips/ath79/pci.c
|
||||||
|
@@ -13,10 +13,10 @@
|
||||||
|
#include <asm/mach-ath79/pci.h>
|
||||||
|
#include "pci.h"
|
||||||
|
|
||||||
|
-static struct ath724x_pci_data *pci_data;
|
||||||
|
+static struct ar724x_pci_data *pci_data;
|
||||||
|
static int pci_data_size;
|
||||||
|
|
||||||
|
-void ath724x_pci_add_data(struct ath724x_pci_data *data, int size)
|
||||||
|
+void ar724x_pci_add_data(struct ar724x_pci_data *data, int size)
|
||||||
|
{
|
||||||
|
pci_data = data;
|
||||||
|
pci_data_size = size;
|
||||||
|
@@ -50,7 +50,7 @@ int pcibios_plat_dev_init(struct pci_dev
|
||||||
|
int __init ath79_register_pci(void)
|
||||||
|
{
|
||||||
|
if (soc_is_ar724x())
|
||||||
|
- return ath724x_pcibios_init();
|
||||||
|
+ return ar724x_pcibios_init();
|
||||||
|
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
--- a/arch/mips/ath79/pci.h
|
||||||
|
+++ b/arch/mips/ath79/pci.h
|
||||||
|
@@ -8,15 +8,15 @@
|
||||||
|
* by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
|
||||||
|
-#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
|
||||||
|
-#define __ASM_MACH_ATH79_PCI_ATH724X_H
|
||||||
|
+#ifndef _ATH79_PCI_H
|
||||||
|
+#define _ATH79_PCI_H
|
||||||
|
|
||||||
|
-struct ath724x_pci_data {
|
||||||
|
+struct ar724x_pci_data {
|
||||||
|
int irq;
|
||||||
|
void *pdata;
|
||||||
|
};
|
||||||
|
|
||||||
|
-void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
|
||||||
|
+void ar724x_pci_add_data(struct ar724x_pci_data *data, int size);
|
||||||
|
|
||||||
|
#ifdef CONFIG_PCI
|
||||||
|
int ath79_register_pci(void);
|
||||||
|
@@ -24,4 +24,4 @@ int ath79_register_pci(void);
|
||||||
|
static inline int ath79_register_pci(void) { return 0; }
|
||||||
|
#endif
|
||||||
|
|
||||||
|
-#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
|
||||||
|
+#endif /* _ATH79_PCI_H */
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/pci.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/pci.h
|
||||||
|
@@ -12,9 +12,9 @@
|
||||||
|
#define __ASM_MACH_ATH79_PCI_H
|
||||||
|
|
||||||
|
#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X)
|
||||||
|
-int ath724x_pcibios_init(void);
|
||||||
|
+int ar724x_pcibios_init(void);
|
||||||
|
#else
|
||||||
|
-static inline int ath724x_pcibios_init(void) { return 0 };
|
||||||
|
+static inline int ar724x_pcibios_init(void) { return 0 };
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __ASM_MACH_ATH79_PCI_H */
|
||||||
|
--- a/arch/mips/pci/pci-ar724x.c
|
||||||
|
+++ b/arch/mips/pci/pci-ar724x.c
|
||||||
|
@@ -14,13 +14,13 @@
|
||||||
|
#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
|
||||||
|
#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
|
||||||
|
|
||||||
|
-#define ATH724X_PCI_DEV_BASE 0x14000000
|
||||||
|
-#define ATH724X_PCI_MEM_BASE 0x10000000
|
||||||
|
-#define ATH724X_PCI_MEM_SIZE 0x08000000
|
||||||
|
+#define AR724X_PCI_DEV_BASE 0x14000000
|
||||||
|
+#define AR724X_PCI_MEM_BASE 0x10000000
|
||||||
|
+#define AR724X_PCI_MEM_SIZE 0x08000000
|
||||||
|
|
||||||
|
-static DEFINE_SPINLOCK(ath724x_pci_lock);
|
||||||
|
+static DEFINE_SPINLOCK(ar724x_pci_lock);
|
||||||
|
|
||||||
|
-static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
|
||||||
|
+static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
|
||||||
|
int size, uint32_t *value)
|
||||||
|
{
|
||||||
|
unsigned long flags, addr, tval, mask;
|
||||||
|
@@ -31,38 +31,38 @@ static int ath724x_pci_read(struct pci_b
|
||||||
|
if (where & (size - 1))
|
||||||
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||||
|
|
||||||
|
- spin_lock_irqsave(&ath724x_pci_lock, flags);
|
||||||
|
+ spin_lock_irqsave(&ar724x_pci_lock, flags);
|
||||||
|
|
||||||
|
switch (size) {
|
||||||
|
case 1:
|
||||||
|
addr = where & ~3;
|
||||||
|
mask = 0xff000000 >> ((where % 4) * 8);
|
||||||
|
- tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
|
||||||
|
+ tval = reg_read(AR724X_PCI_DEV_BASE + addr);
|
||||||
|
tval = tval & ~mask;
|
||||||
|
*value = (tval >> ((4 - (where % 4))*8));
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
addr = where & ~3;
|
||||||
|
mask = 0xffff0000 >> ((where % 4)*8);
|
||||||
|
- tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
|
||||||
|
+ tval = reg_read(AR724X_PCI_DEV_BASE + addr);
|
||||||
|
tval = tval & ~mask;
|
||||||
|
*value = (tval >> ((4 - (where % 4))*8));
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
- *value = reg_read(ATH724X_PCI_DEV_BASE + where);
|
||||||
|
+ *value = reg_read(AR724X_PCI_DEV_BASE + where);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
||||||
|
+ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
|
||||||
|
|
||||||
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||||
|
}
|
||||||
|
|
||||||
|
- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
||||||
|
+ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
|
||||||
|
|
||||||
|
return PCIBIOS_SUCCESSFUL;
|
||||||
|
}
|
||||||
|
|
||||||
|
-static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
|
||||||
|
+static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
|
||||||
|
int size, uint32_t value)
|
||||||
|
{
|
||||||
|
unsigned long flags, tval, addr, mask;
|
||||||
|
@@ -73,11 +73,11 @@ static int ath724x_pci_write(struct pci_
|
||||||
|
if (where & (size - 1))
|
||||||
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||||
|
|
||||||
|
- spin_lock_irqsave(&ath724x_pci_lock, flags);
|
||||||
|
+ spin_lock_irqsave(&ar724x_pci_lock, flags);
|
||||||
|
|
||||||
|
switch (size) {
|
||||||
|
case 1:
|
||||||
|
- addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
|
||||||
|
+ addr = (AR724X_PCI_DEV_BASE + where) & ~3;
|
||||||
|
mask = 0xff000000 >> ((where % 4)*8);
|
||||||
|
tval = reg_read(addr);
|
||||||
|
tval = tval & ~mask;
|
||||||
|
@@ -85,7 +85,7 @@ static int ath724x_pci_write(struct pci_
|
||||||
|
reg_write(addr, tval);
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
- addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
|
||||||
|
+ addr = (AR724X_PCI_DEV_BASE + where) & ~3;
|
||||||
|
mask = 0xffff0000 >> ((where % 4)*8);
|
||||||
|
tval = reg_read(addr);
|
||||||
|
tval = tval & ~mask;
|
||||||
|
@@ -93,47 +93,47 @@ static int ath724x_pci_write(struct pci_
|
||||||
|
reg_write(addr, tval);
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
- reg_write((ATH724X_PCI_DEV_BASE + where), value);
|
||||||
|
+ reg_write((AR724X_PCI_DEV_BASE + where), value);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
||||||
|
+ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
|
||||||
|
|
||||||
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||||
|
}
|
||||||
|
|
||||||
|
- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
||||||
|
+ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
|
||||||
|
|
||||||
|
return PCIBIOS_SUCCESSFUL;
|
||||||
|
}
|
||||||
|
|
||||||
|
-static struct pci_ops ath724x_pci_ops = {
|
||||||
|
- .read = ath724x_pci_read,
|
||||||
|
- .write = ath724x_pci_write,
|
||||||
|
+static struct pci_ops ar724x_pci_ops = {
|
||||||
|
+ .read = ar724x_pci_read,
|
||||||
|
+ .write = ar724x_pci_write,
|
||||||
|
};
|
||||||
|
|
||||||
|
-static struct resource ath724x_io_resource = {
|
||||||
|
+static struct resource ar724x_io_resource = {
|
||||||
|
.name = "PCI IO space",
|
||||||
|
.start = 0,
|
||||||
|
.end = 0,
|
||||||
|
.flags = IORESOURCE_IO,
|
||||||
|
};
|
||||||
|
|
||||||
|
-static struct resource ath724x_mem_resource = {
|
||||||
|
+static struct resource ar724x_mem_resource = {
|
||||||
|
.name = "PCI memory space",
|
||||||
|
- .start = ATH724X_PCI_MEM_BASE,
|
||||||
|
- .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
|
||||||
|
+ .start = AR724X_PCI_MEM_BASE,
|
||||||
|
+ .end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
};
|
||||||
|
|
||||||
|
-static struct pci_controller ath724x_pci_controller = {
|
||||||
|
- .pci_ops = &ath724x_pci_ops,
|
||||||
|
- .io_resource = &ath724x_io_resource,
|
||||||
|
- .mem_resource = &ath724x_mem_resource,
|
||||||
|
+static struct pci_controller ar724x_pci_controller = {
|
||||||
|
+ .pci_ops = &ar724x_pci_ops,
|
||||||
|
+ .io_resource = &ar724x_io_resource,
|
||||||
|
+ .mem_resource = &ar724x_mem_resource,
|
||||||
|
};
|
||||||
|
|
||||||
|
-int __init ath724x_pcibios_init(void)
|
||||||
|
+int __init ar724x_pcibios_init(void)
|
||||||
|
{
|
||||||
|
- register_pci_controller(&ath724x_pci_controller);
|
||||||
|
+ register_pci_controller(&ar724x_pci_controller);
|
||||||
|
|
||||||
|
return PCIBIOS_SUCCESSFUL;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,132 @@
|
||||||
|
From db464f2ad82c03f847d8eabbb8251b5c567e6720 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Fri, 18 Nov 2011 11:52:41 +0100
|
||||||
|
Subject: [PATCH 08/35] MIPS: ath79: use io-accessor macros in pci-ar724x.c
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: René Bolldorf <xsecute@googlemail.com>
|
||||||
|
|
||||||
|
v4: - add an Acked-by tag from René
|
||||||
|
v3: - no changes
|
||||||
|
v2: - no changes
|
||||||
|
---
|
||||||
|
arch/mips/pci/pci-ar724x.c | 38 ++++++++++++++++++++++++--------------
|
||||||
|
1 files changed, 24 insertions(+), 14 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/pci/pci-ar724x.c
|
||||||
|
+++ b/arch/mips/pci/pci-ar724x.c
|
||||||
|
@@ -11,19 +11,19 @@
|
||||||
|
#include <linux/pci.h>
|
||||||
|
#include <asm/mach-ath79/pci.h>
|
||||||
|
|
||||||
|
-#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
|
||||||
|
-#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
|
||||||
|
-
|
||||||
|
-#define AR724X_PCI_DEV_BASE 0x14000000
|
||||||
|
+#define AR724X_PCI_CFG_BASE 0x14000000
|
||||||
|
+#define AR724X_PCI_CFG_SIZE 0x1000
|
||||||
|
#define AR724X_PCI_MEM_BASE 0x10000000
|
||||||
|
#define AR724X_PCI_MEM_SIZE 0x08000000
|
||||||
|
|
||||||
|
static DEFINE_SPINLOCK(ar724x_pci_lock);
|
||||||
|
+static void __iomem *ar724x_pci_devcfg_base;
|
||||||
|
|
||||||
|
static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
|
||||||
|
int size, uint32_t *value)
|
||||||
|
{
|
||||||
|
unsigned long flags, addr, tval, mask;
|
||||||
|
+ void __iomem *base;
|
||||||
|
|
||||||
|
if (devfn)
|
||||||
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||||
|
@@ -31,25 +31,27 @@ static int ar724x_pci_read(struct pci_bu
|
||||||
|
if (where & (size - 1))
|
||||||
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||||
|
|
||||||
|
+ base = ar724x_pci_devcfg_base;
|
||||||
|
+
|
||||||
|
spin_lock_irqsave(&ar724x_pci_lock, flags);
|
||||||
|
|
||||||
|
switch (size) {
|
||||||
|
case 1:
|
||||||
|
addr = where & ~3;
|
||||||
|
mask = 0xff000000 >> ((where % 4) * 8);
|
||||||
|
- tval = reg_read(AR724X_PCI_DEV_BASE + addr);
|
||||||
|
+ tval = __raw_readl(base + addr);
|
||||||
|
tval = tval & ~mask;
|
||||||
|
*value = (tval >> ((4 - (where % 4))*8));
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
addr = where & ~3;
|
||||||
|
mask = 0xffff0000 >> ((where % 4)*8);
|
||||||
|
- tval = reg_read(AR724X_PCI_DEV_BASE + addr);
|
||||||
|
+ tval = __raw_readl(base + addr);
|
||||||
|
tval = tval & ~mask;
|
||||||
|
*value = (tval >> ((4 - (where % 4))*8));
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
- *value = reg_read(AR724X_PCI_DEV_BASE + where);
|
||||||
|
+ *value = __raw_readl(base + where);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
spin_unlock_irqrestore(&ar724x_pci_lock, flags);
|
||||||
|
@@ -66,6 +68,7 @@ static int ar724x_pci_write(struct pci_b
|
||||||
|
int size, uint32_t value)
|
||||||
|
{
|
||||||
|
unsigned long flags, tval, addr, mask;
|
||||||
|
+ void __iomem *base;
|
||||||
|
|
||||||
|
if (devfn)
|
||||||
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||||
|
@@ -73,27 +76,29 @@ static int ar724x_pci_write(struct pci_b
|
||||||
|
if (where & (size - 1))
|
||||||
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||||
|
|
||||||
|
+ base = ar724x_pci_devcfg_base;
|
||||||
|
+
|
||||||
|
spin_lock_irqsave(&ar724x_pci_lock, flags);
|
||||||
|
|
||||||
|
switch (size) {
|
||||||
|
case 1:
|
||||||
|
- addr = (AR724X_PCI_DEV_BASE + where) & ~3;
|
||||||
|
+ addr = where & ~3;
|
||||||
|
mask = 0xff000000 >> ((where % 4)*8);
|
||||||
|
- tval = reg_read(addr);
|
||||||
|
+ tval = __raw_readl(base + addr);
|
||||||
|
tval = tval & ~mask;
|
||||||
|
tval |= (value << ((4 - (where % 4))*8)) & mask;
|
||||||
|
- reg_write(addr, tval);
|
||||||
|
+ __raw_writel(tval, base + addr);
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
- addr = (AR724X_PCI_DEV_BASE + where) & ~3;
|
||||||
|
+ addr = where & ~3;
|
||||||
|
mask = 0xffff0000 >> ((where % 4)*8);
|
||||||
|
- tval = reg_read(addr);
|
||||||
|
+ tval = __raw_readl(base + addr);
|
||||||
|
tval = tval & ~mask;
|
||||||
|
tval |= (value << ((4 - (where % 4))*8)) & mask;
|
||||||
|
- reg_write(addr, tval);
|
||||||
|
+ __raw_writel(tval, base + addr);
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
- reg_write((AR724X_PCI_DEV_BASE + where), value);
|
||||||
|
+ __raw_writel(value, (base + where));
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
spin_unlock_irqrestore(&ar724x_pci_lock, flags);
|
||||||
|
@@ -133,6 +138,11 @@ static struct pci_controller ar724x_pci_
|
||||||
|
|
||||||
|
int __init ar724x_pcibios_init(void)
|
||||||
|
{
|
||||||
|
+ ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE,
|
||||||
|
+ AR724X_PCI_CFG_SIZE);
|
||||||
|
+ if (ar724x_pci_devcfg_base == NULL)
|
||||||
|
+ return -ENOMEM;
|
||||||
|
+
|
||||||
|
register_pci_controller(&ar724x_pci_controller);
|
||||||
|
|
||||||
|
return PCIBIOS_SUCCESSFUL;
|
||||||
|
|
@ -0,0 +1,37 @@
|
||||||
|
From 744ffdd4e90cd6671f46eadf9d7cf55b07618d73 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Fri, 18 Nov 2011 21:37:17 +0100
|
||||||
|
Subject: [PATCH 09/35] MIPS: ath79: remove superfluous alignment checks from pci-ar724x.c
|
||||||
|
|
||||||
|
The alignment of the 'where' parameters are checked
|
||||||
|
in the core PCI code already.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
|
||||||
|
v2: - no changes
|
||||||
|
---
|
||||||
|
arch/mips/pci/pci-ar724x.c | 6 ------
|
||||||
|
1 files changed, 0 insertions(+), 6 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/pci/pci-ar724x.c
|
||||||
|
+++ b/arch/mips/pci/pci-ar724x.c
|
||||||
|
@@ -28,9 +28,6 @@ static int ar724x_pci_read(struct pci_bu
|
||||||
|
if (devfn)
|
||||||
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||||
|
|
||||||
|
- if (where & (size - 1))
|
||||||
|
- return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||||
|
-
|
||||||
|
base = ar724x_pci_devcfg_base;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&ar724x_pci_lock, flags);
|
||||||
|
@@ -73,9 +70,6 @@ static int ar724x_pci_write(struct pci_b
|
||||||
|
if (devfn)
|
||||||
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||||
|
|
||||||
|
- if (where & (size - 1))
|
||||||
|
- return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||||
|
-
|
||||||
|
base = ar724x_pci_devcfg_base;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&ar724x_pci_lock, flags);
|
||||||
|
|
@ -0,0 +1,219 @@
|
||||||
|
From 2e535c334018d58b0bf6df583486abda5bfb2003 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Fri, 18 Nov 2011 22:25:30 +0100
|
||||||
|
Subject: [PATCH 10/35] MIPS: ath79: fix broken ar724x_pci_{read,write} functions
|
||||||
|
|
||||||
|
The current ar724x_pci_{read,write} functions are
|
||||||
|
broken. Due to that, pci_read_config_byte returns
|
||||||
|
with bogus values, and pci_write_config_{byte,word}
|
||||||
|
unconditionally clears the accessed PCI configuration
|
||||||
|
registers instead of changing the value of them.
|
||||||
|
|
||||||
|
The patch fixes the broken functions, thus the PCI
|
||||||
|
configuration space can be accessed correctly.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
|
||||||
|
v2: - no changes
|
||||||
|
|
||||||
|
Output of 'lspci -vv' without the patch:
|
||||||
|
|
||||||
|
00:00.0 Network controller: Atheros Communications Inc. AR9285 Wireless
|
||||||
|
Network Adapter (PCI-Express) (rev 01)
|
||||||
|
Subsystem: Atheros Communications Inc. Device a091
|
||||||
|
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
|
||||||
|
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
|
||||||
|
Latency: 0
|
||||||
|
Interrupt: pin A routed to IRQ 0
|
||||||
|
Region 0: Memory at 10000000 (64-bit, non-prefetchable) [size=64K]
|
||||||
|
Capabilities: [40] Power Management version 3
|
||||||
|
Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold-)
|
||||||
|
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
|
||||||
|
Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit-
|
||||||
|
Address: 00000000 Data: 0000
|
||||||
|
Capabilities: [60] Express (v2) Legacy Endpoint, MSI 00
|
||||||
|
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
|
||||||
|
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
|
||||||
|
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
|
||||||
|
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
|
||||||
|
MaxPayload 128 bytes, MaxReadReq 512 bytes
|
||||||
|
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
|
||||||
|
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM unknown, Latency L0 <512ns, L1 <64us
|
||||||
|
ClockPM- Surprise- LLActRep- BwNot-
|
||||||
|
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
|
||||||
|
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
|
||||||
|
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
|
||||||
|
DevCap2: Completion Timeout: Not Supported, TimeoutDis+
|
||||||
|
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
|
||||||
|
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
|
||||||
|
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
|
||||||
|
Compliance De-emphasis: -6dB
|
||||||
|
LnkSta2: Current De-emphasis Level: -6dB
|
||||||
|
|
||||||
|
Output of 'lspci -vv' with the patch:
|
||||||
|
|
||||||
|
00:00.0 Network controller: Atheros Communications Inc. AR9285 Wireless
|
||||||
|
Network Adapter (PCI-Express) (rev 01)
|
||||||
|
Subsystem: Atheros Communications Inc. Device a091
|
||||||
|
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
|
||||||
|
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
|
||||||
|
Latency: 0
|
||||||
|
Interrupt: pin A routed to IRQ 48
|
||||||
|
Region 0: Memory at 10000000 (64-bit, non-prefetchable) [size=64K]
|
||||||
|
Capabilities: [40] Power Management version 3
|
||||||
|
Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold-)
|
||||||
|
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
|
||||||
|
Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit-
|
||||||
|
Address: 00000000 Data: 0000
|
||||||
|
Capabilities: [60] Express (v2) Legacy Endpoint, MSI 00
|
||||||
|
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
|
||||||
|
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
|
||||||
|
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
|
||||||
|
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
|
||||||
|
MaxPayload 128 bytes, MaxReadReq 512 bytes
|
||||||
|
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
|
||||||
|
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM unknown, Latency L0 <512ns, L1 <64us
|
||||||
|
ClockPM- Surprise- LLActRep- BwNot-
|
||||||
|
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
|
||||||
|
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
|
||||||
|
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
|
||||||
|
DevCap2: Completion Timeout: Not Supported, TimeoutDis+
|
||||||
|
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
|
||||||
|
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
|
||||||
|
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
|
||||||
|
Compliance De-emphasis: -6dB
|
||||||
|
LnkSta2: Current De-emphasis Level: -6dB
|
||||||
|
Capabilities: [100 v1] Advanced Error Reporting
|
||||||
|
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
|
||||||
|
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
|
||||||
|
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
|
||||||
|
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
|
||||||
|
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
|
||||||
|
AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
|
||||||
|
Capabilities: [140 v1] Virtual Channel
|
||||||
|
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
|
||||||
|
Arb: Fixed- WRR32- WRR64- WRR128-
|
||||||
|
Ctrl: ArbSelect=Fixed
|
||||||
|
Status: InProgress-
|
||||||
|
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
|
||||||
|
Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
|
||||||
|
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
|
||||||
|
Status: NegoPending- InProgress-
|
||||||
|
Capabilities: [160 v1] Device Serial Number 00-15-17-ff-ff-24-14-12
|
||||||
|
Capabilities: [170 v1] Power Budgeting <?>
|
||||||
|
---
|
||||||
|
arch/mips/pci/pci-ar724x.c | 52 ++++++++++++++++++++++----------------------
|
||||||
|
1 files changed, 26 insertions(+), 26 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/pci/pci-ar724x.c
|
||||||
|
+++ b/arch/mips/pci/pci-ar724x.c
|
||||||
|
@@ -22,8 +22,9 @@ static void __iomem *ar724x_pci_devcfg_b
|
||||||
|
static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
|
||||||
|
int size, uint32_t *value)
|
||||||
|
{
|
||||||
|
- unsigned long flags, addr, tval, mask;
|
||||||
|
+ unsigned long flags;
|
||||||
|
void __iomem *base;
|
||||||
|
+ u32 data;
|
||||||
|
|
||||||
|
if (devfn)
|
||||||
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||||
|
@@ -31,24 +32,22 @@ static int ar724x_pci_read(struct pci_bu
|
||||||
|
base = ar724x_pci_devcfg_base;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&ar724x_pci_lock, flags);
|
||||||
|
+ data = __raw_readl(base + (where & ~3));
|
||||||
|
|
||||||
|
switch (size) {
|
||||||
|
case 1:
|
||||||
|
- addr = where & ~3;
|
||||||
|
- mask = 0xff000000 >> ((where % 4) * 8);
|
||||||
|
- tval = __raw_readl(base + addr);
|
||||||
|
- tval = tval & ~mask;
|
||||||
|
- *value = (tval >> ((4 - (where % 4))*8));
|
||||||
|
+ if (where & 1)
|
||||||
|
+ data >>= 8;
|
||||||
|
+ if (where & 2)
|
||||||
|
+ data >>= 16;
|
||||||
|
+ data &= 0xff;
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
- addr = where & ~3;
|
||||||
|
- mask = 0xffff0000 >> ((where % 4)*8);
|
||||||
|
- tval = __raw_readl(base + addr);
|
||||||
|
- tval = tval & ~mask;
|
||||||
|
- *value = (tval >> ((4 - (where % 4))*8));
|
||||||
|
+ if (where & 2)
|
||||||
|
+ data >>= 16;
|
||||||
|
+ data &= 0xffff;
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
- *value = __raw_readl(base + where);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
spin_unlock_irqrestore(&ar724x_pci_lock, flags);
|
||||||
|
@@ -57,6 +56,7 @@ static int ar724x_pci_read(struct pci_bu
|
||||||
|
}
|
||||||
|
|
||||||
|
spin_unlock_irqrestore(&ar724x_pci_lock, flags);
|
||||||
|
+ *value = data;
|
||||||
|
|
||||||
|
return PCIBIOS_SUCCESSFUL;
|
||||||
|
}
|
||||||
|
@@ -64,8 +64,10 @@ static int ar724x_pci_read(struct pci_bu
|
||||||
|
static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
|
||||||
|
int size, uint32_t value)
|
||||||
|
{
|
||||||
|
- unsigned long flags, tval, addr, mask;
|
||||||
|
+ unsigned long flags;
|
||||||
|
void __iomem *base;
|
||||||
|
+ u32 data;
|
||||||
|
+ int s;
|
||||||
|
|
||||||
|
if (devfn)
|
||||||
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||||
|
@@ -73,26 +75,21 @@ static int ar724x_pci_write(struct pci_b
|
||||||
|
base = ar724x_pci_devcfg_base;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&ar724x_pci_lock, flags);
|
||||||
|
+ data = __raw_readl(base + (where & ~3));
|
||||||
|
|
||||||
|
switch (size) {
|
||||||
|
case 1:
|
||||||
|
- addr = where & ~3;
|
||||||
|
- mask = 0xff000000 >> ((where % 4)*8);
|
||||||
|
- tval = __raw_readl(base + addr);
|
||||||
|
- tval = tval & ~mask;
|
||||||
|
- tval |= (value << ((4 - (where % 4))*8)) & mask;
|
||||||
|
- __raw_writel(tval, base + addr);
|
||||||
|
+ s = ((where & 3) * 8);
|
||||||
|
+ data &= ~(0xff << s);
|
||||||
|
+ data |= ((value & 0xff) << s);
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
- addr = where & ~3;
|
||||||
|
- mask = 0xffff0000 >> ((where % 4)*8);
|
||||||
|
- tval = __raw_readl(base + addr);
|
||||||
|
- tval = tval & ~mask;
|
||||||
|
- tval |= (value << ((4 - (where % 4))*8)) & mask;
|
||||||
|
- __raw_writel(tval, base + addr);
|
||||||
|
+ s = ((where & 2) * 8);
|
||||||
|
+ data &= ~(0xffff << s);
|
||||||
|
+ data |= ((value & 0xffff) << s);
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
- __raw_writel(value, (base + where));
|
||||||
|
+ data = value;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
spin_unlock_irqrestore(&ar724x_pci_lock, flags);
|
||||||
|
@@ -100,6 +97,9 @@ static int ar724x_pci_write(struct pci_b
|
||||||
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||||
|
}
|
||||||
|
|
||||||
|
+ __raw_writel(data, base + (where & ~3));
|
||||||
|
+ /* flush write */
|
||||||
|
+ __raw_readl(base + (where & ~3));
|
||||||
|
spin_unlock_irqrestore(&ar724x_pci_lock, flags);
|
||||||
|
|
||||||
|
return PCIBIOS_SUCCESSFUL;
|
||||||
|
|
@ -0,0 +1,134 @@
|
||||||
|
From b2ee3bd8706521c9bbf43405c767010927c101e5 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Mon, 21 Nov 2011 17:57:51 +0100
|
||||||
|
Subject: [PATCH 11/35] MIPS: ath79: add a workaround for a PCI controller bug in AR7240 SoCs
|
||||||
|
|
||||||
|
The PCI controller of the AR724X SoCs has a hardware
|
||||||
|
bag. If the BAR0 register of the PCI device is set to
|
||||||
|
the proper base address, the memory address space of
|
||||||
|
the device is not accessible.
|
||||||
|
|
||||||
|
When the device driver tries to access the memory
|
||||||
|
address space of the PCI device, it leads to data
|
||||||
|
bus error, similiar to this:
|
||||||
|
|
||||||
|
Data bus error, epc == 801f69a0, ra == 801f698c
|
||||||
|
Oops[#1]:
|
||||||
|
Cpu 0
|
||||||
|
$ 0 : 00000000 00000061 deadbeef 000000ff
|
||||||
|
$ 4 : 00000000 000000ff 00000014 00000000
|
||||||
|
$ 8 : ff000000 fffffffc 00000000 00000000
|
||||||
|
$12 : 000001f5 00000006 00000000 6e637920
|
||||||
|
$16 : 81ca4000 81ca0260 81ca4000 804d70f0
|
||||||
|
$20 : fffffff4 0000002b 803ad4c4 00000000
|
||||||
|
$24 : 00000003 00000000
|
||||||
|
$28 : 81c20000 81c21c60 00000000 801f698c
|
||||||
|
Hi : 00000000
|
||||||
|
Lo : 00000000
|
||||||
|
epc : 801f69a0 ath9k_hw_init+0xd0/0xa70
|
||||||
|
Not tainted
|
||||||
|
ra : 801f698c ath9k_hw_init+0xbc/0xa70
|
||||||
|
Status: 1000c103 KERNEL EXL IE
|
||||||
|
Cause : 1080001c
|
||||||
|
PrId : 00019374 (MIPS 24Kc)
|
||||||
|
Modules linked in:
|
||||||
|
Process swapper (pid: 1, threadinfo=81c20000, task=81c18000, tls=00000000)
|
||||||
|
Stack : 00000000 00000000 00000000 00000000 81c21c78 81ca0260 00000000 804d70f0
|
||||||
|
81ca0260 81c21cc0 81ca0e80 81ca0260 81ca4000 804d70f0 fffffff4 0000002b
|
||||||
|
803ad4c4 00000000 00000000 801e3ae8 81c9d080 81ca0e80 b0000000 800b9b9c
|
||||||
|
00000008 81c9d000 8031aeb0 802d38a0 00000000 81c14c00 81c14c60 00000000
|
||||||
|
81ca0e80 81ca0260 b0000000 801f08a4 81c9c820 81c21d48 81c9c820 80144320
|
||||||
|
...
|
||||||
|
Call Trace:
|
||||||
|
[<801f69a0>] ath9k_hw_init+0xd0/0xa70
|
||||||
|
[<801e3ae8>] ath9k_init_device+0x174/0x680
|
||||||
|
[<801f08a4>] ath_pci_probe+0x27c/0x380
|
||||||
|
[<8019e490>] pci_device_probe+0x74/0x9c
|
||||||
|
[<801bfadc>] driver_probe_device+0x9c/0x1b4
|
||||||
|
[<801bfcb0>] __driver_attach+0xbc/0xc4
|
||||||
|
[<801bea0c>] bus_for_each_dev+0x5c/0x98
|
||||||
|
[<801bf394>] bus_add_driver+0x1d0/0x2a4
|
||||||
|
[<801c0364>] driver_register+0x8c/0x16c
|
||||||
|
[<8019e72c>] __pci_register_driver+0x4c/0xe4
|
||||||
|
[<803d3d40>] ath9k_init+0x3c/0x88
|
||||||
|
[<80060930>] do_one_initcall+0x3c/0x1cc
|
||||||
|
[<803c297c>] kernel_init+0xa4/0x138
|
||||||
|
[<80063c04>] kernel_thread_helper+0x10/0x18
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
|
||||||
|
v2: - apply the workaround on AR7240 only
|
||||||
|
- remove unrelated defines
|
||||||
|
---
|
||||||
|
arch/mips/pci/pci-ar724x.c | 36 +++++++++++++++++++++++++++++++++++-
|
||||||
|
1 files changed, 35 insertions(+), 1 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/pci/pci-ar724x.c
|
||||||
|
+++ b/arch/mips/pci/pci-ar724x.c
|
||||||
|
@@ -9,6 +9,7 @@
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/pci.h>
|
||||||
|
+#include <asm/mach-ath79/ath79.h>
|
||||||
|
#include <asm/mach-ath79/pci.h>
|
||||||
|
|
||||||
|
#define AR724X_PCI_CFG_BASE 0x14000000
|
||||||
|
@@ -16,9 +17,14 @@
|
||||||
|
#define AR724X_PCI_MEM_BASE 0x10000000
|
||||||
|
#define AR724X_PCI_MEM_SIZE 0x08000000
|
||||||
|
|
||||||
|
+#define AR7240_BAR0_WAR_VALUE 0xffff
|
||||||
|
+
|
||||||
|
static DEFINE_SPINLOCK(ar724x_pci_lock);
|
||||||
|
static void __iomem *ar724x_pci_devcfg_base;
|
||||||
|
|
||||||
|
+static u32 ar724x_pci_bar0_value;
|
||||||
|
+static bool ar724x_pci_bar0_is_cached;
|
||||||
|
+
|
||||||
|
static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
|
||||||
|
int size, uint32_t *value)
|
||||||
|
{
|
||||||
|
@@ -56,7 +62,14 @@ static int ar724x_pci_read(struct pci_bu
|
||||||
|
}
|
||||||
|
|
||||||
|
spin_unlock_irqrestore(&ar724x_pci_lock, flags);
|
||||||
|
- *value = data;
|
||||||
|
+
|
||||||
|
+ if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
|
||||||
|
+ ar724x_pci_bar0_is_cached) {
|
||||||
|
+ /* use the cached value */
|
||||||
|
+ *value = ar724x_pci_bar0_value;
|
||||||
|
+ } else {
|
||||||
|
+ *value = data;
|
||||||
|
+ }
|
||||||
|
|
||||||
|
return PCIBIOS_SUCCESSFUL;
|
||||||
|
}
|
||||||
|
@@ -72,6 +85,27 @@ static int ar724x_pci_write(struct pci_b
|
||||||
|
if (devfn)
|
||||||
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||||
|
|
||||||
|
+ if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) {
|
||||||
|
+ if (value != 0xffffffff) {
|
||||||
|
+ /*
|
||||||
|
+ * WAR for a hw issue. If the BAR0 register of the
|
||||||
|
+ * device is set to the proper base address, the
|
||||||
|
+ * memory space of the device is not accessible.
|
||||||
|
+ *
|
||||||
|
+ * Cache the intended value so it can be read back,
|
||||||
|
+ * and write a SoC specific constant value to the
|
||||||
|
+ * BAR0 register in order to make the device memory
|
||||||
|
+ * accessible.
|
||||||
|
+ */
|
||||||
|
+ ar724x_pci_bar0_is_cached = true;
|
||||||
|
+ ar724x_pci_bar0_value = value;
|
||||||
|
+
|
||||||
|
+ value = AR7240_BAR0_WAR_VALUE;
|
||||||
|
+ } else {
|
||||||
|
+ ar724x_pci_bar0_is_cached = false;
|
||||||
|
+ }
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
base = ar724x_pci_devcfg_base;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&ar724x_pci_lock, flags);
|
||||||
|
|
@ -0,0 +1,75 @@
|
||||||
|
From cfb725275ea25857e8f0e3bf358fff7c84cc787c Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Tue, 22 Nov 2011 13:59:39 +0100
|
||||||
|
Subject: [PATCH 12/35] MIPS: ath79: fix a wrong IRQ number
|
||||||
|
|
||||||
|
The Ubiquiti XM board setup code uses an invalid
|
||||||
|
IRQ number, because it if above of NR_IRQS. This
|
||||||
|
leads to failed 'request_irq' calls:
|
||||||
|
|
||||||
|
ath9k 0000:00:00.0: request_irq failed
|
||||||
|
ath9k: probe of 0000:00:00.0 failed with error -22
|
||||||
|
|
||||||
|
Preserve some IRQ numbers for the built-in IRQ
|
||||||
|
controller of PCI host controllers in the
|
||||||
|
AR71XX/AR724X SoCs, and use the correct IRQ
|
||||||
|
number in the board setup code.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
|
||||||
|
v2: - no changes
|
||||||
|
|
||||||
|
The IRQ controller code is also missing, that will be
|
||||||
|
added in a separate patch.
|
||||||
|
---
|
||||||
|
arch/mips/ath79/mach-ubnt-xm.c | 5 +++--
|
||||||
|
arch/mips/include/asm/mach-ath79/irq.h | 6 +++++-
|
||||||
|
2 files changed, 8 insertions(+), 3 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
+++ b/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
@@ -17,6 +17,8 @@
|
||||||
|
#include <linux/ath9k_platform.h>
|
||||||
|
#endif /* CONFIG_PCI */
|
||||||
|
|
||||||
|
+#include <asm/mach-ath79/irq.h>
|
||||||
|
+
|
||||||
|
#include "machtypes.h"
|
||||||
|
#include "dev-gpio-buttons.h"
|
||||||
|
#include "dev-leds-gpio.h"
|
||||||
|
@@ -33,7 +35,6 @@
|
||||||
|
#define UBNT_XM_KEYS_POLL_INTERVAL 20
|
||||||
|
#define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL)
|
||||||
|
|
||||||
|
-#define UBNT_XM_PCI_IRQ 48
|
||||||
|
#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000)
|
||||||
|
|
||||||
|
static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
|
||||||
|
@@ -86,7 +87,7 @@ static struct ath9k_platform_data ubnt_x
|
||||||
|
|
||||||
|
static struct ar724x_pci_data ubnt_xm_pci_data[] = {
|
||||||
|
{
|
||||||
|
- .irq = UBNT_XM_PCI_IRQ,
|
||||||
|
+ .irq = ATH79_PCI_IRQ(0),
|
||||||
|
.pdata = &ubnt_xm_eeprom_data,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/irq.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/irq.h
|
||||||
|
@@ -10,11 +10,15 @@
|
||||||
|
#define __ASM_MACH_ATH79_IRQ_H
|
||||||
|
|
||||||
|
#define MIPS_CPU_IRQ_BASE 0
|
||||||
|
-#define NR_IRQS 40
|
||||||
|
+#define NR_IRQS 46
|
||||||
|
|
||||||
|
#define ATH79_MISC_IRQ_BASE 8
|
||||||
|
#define ATH79_MISC_IRQ_COUNT 32
|
||||||
|
|
||||||
|
+#define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
|
||||||
|
+#define ATH79_PCI_IRQ_COUNT 6
|
||||||
|
+#define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x))
|
||||||
|
+
|
||||||
|
#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
|
||||||
|
#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
|
||||||
|
#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
|
||||||
|
|
@ -0,0 +1,213 @@
|
||||||
|
From a4fbc2dec67a5d760e25e3c3a6c392191a5405c6 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Tue, 22 Nov 2011 14:11:19 +0100
|
||||||
|
Subject: [PATCH 13/35] MIPS: ath79: add PCI IRQ handling code for AR724X SoCs
|
||||||
|
|
||||||
|
The PCI Host Controller of the AR724x SoC has a
|
||||||
|
built-in IRQ controller. The current code does
|
||||||
|
not supports that, so the IRQ lines wired to this
|
||||||
|
controller are not usable. This leads to failed
|
||||||
|
'request_irq' calls:
|
||||||
|
|
||||||
|
ath9k 0000:00:00.0: request_irq failed
|
||||||
|
ath9k: probe of 0000:00:00.0 failed with error -89
|
||||||
|
|
||||||
|
This patch adds support for the IRQ controller
|
||||||
|
in order to make PCI IRQs work.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
|
||||||
|
v2: - move the interrupt controller related defines from
|
||||||
|
the workaround patch
|
||||||
|
---
|
||||||
|
arch/mips/ath79/pci.c | 3 +-
|
||||||
|
arch/mips/include/asm/mach-ath79/pci.h | 4 +-
|
||||||
|
arch/mips/pci/pci-ar724x.c | 118 +++++++++++++++++++++++++++++++-
|
||||||
|
3 files changed, 120 insertions(+), 5 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/pci.c
|
||||||
|
+++ b/arch/mips/ath79/pci.c
|
||||||
|
@@ -10,6 +10,7 @@
|
||||||
|
|
||||||
|
#include <linux/pci.h>
|
||||||
|
#include <asm/mach-ath79/ath79.h>
|
||||||
|
+#include <asm/mach-ath79/irq.h>
|
||||||
|
#include <asm/mach-ath79/pci.h>
|
||||||
|
#include "pci.h"
|
||||||
|
|
||||||
|
@@ -50,7 +51,7 @@ int pcibios_plat_dev_init(struct pci_dev
|
||||||
|
int __init ath79_register_pci(void)
|
||||||
|
{
|
||||||
|
if (soc_is_ar724x())
|
||||||
|
- return ar724x_pcibios_init();
|
||||||
|
+ return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
|
||||||
|
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/pci.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/pci.h
|
||||||
|
@@ -12,9 +12,9 @@
|
||||||
|
#define __ASM_MACH_ATH79_PCI_H
|
||||||
|
|
||||||
|
#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X)
|
||||||
|
-int ar724x_pcibios_init(void);
|
||||||
|
+int ar724x_pcibios_init(int irq);
|
||||||
|
#else
|
||||||
|
-static inline int ar724x_pcibios_init(void) { return 0 };
|
||||||
|
+static inline int ar724x_pcibios_init(int irq) { return 0 };
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __ASM_MACH_ATH79_PCI_H */
|
||||||
|
--- a/arch/mips/pci/pci-ar724x.c
|
||||||
|
+++ b/arch/mips/pci/pci-ar724x.c
|
||||||
|
@@ -8,19 +8,32 @@
|
||||||
|
* by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
|
||||||
|
+#include <linux/irq.h>
|
||||||
|
#include <linux/pci.h>
|
||||||
|
#include <asm/mach-ath79/ath79.h>
|
||||||
|
+#include <asm/mach-ath79/ar71xx_regs.h>
|
||||||
|
#include <asm/mach-ath79/pci.h>
|
||||||
|
|
||||||
|
#define AR724X_PCI_CFG_BASE 0x14000000
|
||||||
|
#define AR724X_PCI_CFG_SIZE 0x1000
|
||||||
|
+#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
|
||||||
|
+#define AR724X_PCI_CTRL_SIZE 0x100
|
||||||
|
+
|
||||||
|
#define AR724X_PCI_MEM_BASE 0x10000000
|
||||||
|
#define AR724X_PCI_MEM_SIZE 0x08000000
|
||||||
|
|
||||||
|
+#define AR724X_PCI_REG_INT_STATUS 0x4c
|
||||||
|
+#define AR724X_PCI_REG_INT_MASK 0x50
|
||||||
|
+
|
||||||
|
+#define AR724X_PCI_INT_DEV0 BIT(14)
|
||||||
|
+
|
||||||
|
+#define AR724X_PCI_IRQ_COUNT 1
|
||||||
|
+
|
||||||
|
#define AR7240_BAR0_WAR_VALUE 0xffff
|
||||||
|
|
||||||
|
static DEFINE_SPINLOCK(ar724x_pci_lock);
|
||||||
|
static void __iomem *ar724x_pci_devcfg_base;
|
||||||
|
+static void __iomem *ar724x_pci_ctrl_base;
|
||||||
|
|
||||||
|
static u32 ar724x_pci_bar0_value;
|
||||||
|
static bool ar724x_pci_bar0_is_cached;
|
||||||
|
@@ -164,14 +177,115 @@ static struct pci_controller ar724x_pci_
|
||||||
|
.mem_resource = &ar724x_mem_resource,
|
||||||
|
};
|
||||||
|
|
||||||
|
-int __init ar724x_pcibios_init(void)
|
||||||
|
+static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||||
|
+{
|
||||||
|
+ void __iomem *base;
|
||||||
|
+ u32 pending;
|
||||||
|
+
|
||||||
|
+ base = ar724x_pci_ctrl_base;
|
||||||
|
+
|
||||||
|
+ pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
|
||||||
|
+ __raw_readl(base + AR724X_PCI_REG_INT_MASK);
|
||||||
|
+
|
||||||
|
+ if (pending & AR724X_PCI_INT_DEV0)
|
||||||
|
+ generic_handle_irq(ATH79_PCI_IRQ(0));
|
||||||
|
+
|
||||||
|
+ else
|
||||||
|
+ spurious_interrupt();
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void ar724x_pci_irq_unmask(struct irq_data *d)
|
||||||
|
+{
|
||||||
|
+ void __iomem *base;
|
||||||
|
+ u32 t;
|
||||||
|
+
|
||||||
|
+ base = ar724x_pci_ctrl_base;
|
||||||
|
+
|
||||||
|
+ switch (d->irq) {
|
||||||
|
+ case ATH79_PCI_IRQ(0):
|
||||||
|
+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
|
||||||
|
+ __raw_writel(t | AR724X_PCI_INT_DEV0,
|
||||||
|
+ base + AR724X_PCI_REG_INT_MASK);
|
||||||
|
+ /* flush write */
|
||||||
|
+ __raw_readl(base + AR724X_PCI_REG_INT_MASK);
|
||||||
|
+ }
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void ar724x_pci_irq_mask(struct irq_data *d)
|
||||||
|
+{
|
||||||
|
+ void __iomem *base;
|
||||||
|
+ u32 t;
|
||||||
|
+
|
||||||
|
+ base = ar724x_pci_ctrl_base;
|
||||||
|
+
|
||||||
|
+ switch (d->irq) {
|
||||||
|
+ case ATH79_PCI_IRQ(0):
|
||||||
|
+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
|
||||||
|
+ __raw_writel(t & ~AR724X_PCI_INT_DEV0,
|
||||||
|
+ base + AR724X_PCI_REG_INT_MASK);
|
||||||
|
+
|
||||||
|
+ /* flush write */
|
||||||
|
+ __raw_readl(base + AR724X_PCI_REG_INT_MASK);
|
||||||
|
+
|
||||||
|
+ t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
|
||||||
|
+ __raw_writel(t | AR724X_PCI_INT_DEV0,
|
||||||
|
+ base + AR724X_PCI_REG_INT_STATUS);
|
||||||
|
+
|
||||||
|
+ /* flush write */
|
||||||
|
+ __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
|
||||||
|
+ }
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static struct irq_chip ar724x_pci_irq_chip = {
|
||||||
|
+ .name = "AR724X PCI ",
|
||||||
|
+ .irq_mask = ar724x_pci_irq_mask,
|
||||||
|
+ .irq_unmask = ar724x_pci_irq_unmask,
|
||||||
|
+ .irq_mask_ack = ar724x_pci_irq_mask,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static void __init ar724x_pci_irq_init(int irq)
|
||||||
|
+{
|
||||||
|
+ void __iomem *base;
|
||||||
|
+ int i;
|
||||||
|
+
|
||||||
|
+ base = ar724x_pci_ctrl_base;
|
||||||
|
+
|
||||||
|
+ __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
|
||||||
|
+ __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
|
||||||
|
+
|
||||||
|
+ BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT);
|
||||||
|
+
|
||||||
|
+ for (i = ATH79_PCI_IRQ_BASE;
|
||||||
|
+ i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++)
|
||||||
|
+ irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
|
||||||
|
+ handle_level_irq);
|
||||||
|
+
|
||||||
|
+ irq_set_chained_handler(irq, ar724x_pci_irq_handler);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+int __init ar724x_pcibios_init(int irq)
|
||||||
|
{
|
||||||
|
+ int ret;
|
||||||
|
+
|
||||||
|
+ ret = -ENOMEM;
|
||||||
|
+
|
||||||
|
ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE,
|
||||||
|
AR724X_PCI_CFG_SIZE);
|
||||||
|
if (ar724x_pci_devcfg_base == NULL)
|
||||||
|
- return -ENOMEM;
|
||||||
|
+ goto err;
|
||||||
|
|
||||||
|
+ ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE,
|
||||||
|
+ AR724X_PCI_CTRL_SIZE);
|
||||||
|
+ if (ar724x_pci_ctrl_base == NULL)
|
||||||
|
+ goto err_unmap_devcfg;
|
||||||
|
+
|
||||||
|
+ ar724x_pci_irq_init(irq);
|
||||||
|
register_pci_controller(&ar724x_pci_controller);
|
||||||
|
|
||||||
|
return PCIBIOS_SUCCESSFUL;
|
||||||
|
+
|
||||||
|
+err_unmap_devcfg:
|
||||||
|
+ iounmap(ar724x_pci_devcfg_base);
|
||||||
|
+err:
|
||||||
|
+ return ret;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,63 @@
|
||||||
|
From adeefb0860e92f44c7d66d5fccdb217fccfb8a81 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Sun, 20 Nov 2011 10:19:08 +0100
|
||||||
|
Subject: [PATCH 14/35] MIPS: ath79: get rid of some ifdefs in mach-ubnt-xm.c
|
||||||
|
|
||||||
|
Remove a superfluous ifdef around an include. Also
|
||||||
|
reorganize the board setup code a bit, so another
|
||||||
|
ifdef can be removed.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
|
||||||
|
v2: - no changes
|
||||||
|
---
|
||||||
|
arch/mips/ath79/mach-ubnt-xm.c | 23 ++++++++++++-----------
|
||||||
|
1 files changed, 12 insertions(+), 11 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
+++ b/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
@@ -12,10 +12,7 @@
|
||||||
|
|
||||||
|
#include <linux/init.h>
|
||||||
|
#include <linux/pci.h>
|
||||||
|
-
|
||||||
|
-#ifdef CONFIG_PCI
|
||||||
|
#include <linux/ath9k_platform.h>
|
||||||
|
-#endif /* CONFIG_PCI */
|
||||||
|
|
||||||
|
#include <asm/mach-ath79/irq.h>
|
||||||
|
|
||||||
|
@@ -91,6 +88,17 @@ static struct ar724x_pci_data ubnt_xm_pc
|
||||||
|
.pdata = &ubnt_xm_eeprom_data,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
+
|
||||||
|
+static void __init ubnt_xm_pci_init(void)
|
||||||
|
+{
|
||||||
|
+ memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
|
||||||
|
+ sizeof(ubnt_xm_eeprom_data.eeprom_data));
|
||||||
|
+
|
||||||
|
+ ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
|
||||||
|
+ ath79_register_pci();
|
||||||
|
+}
|
||||||
|
+#else
|
||||||
|
+static inline void ubnt_xm_pci_init(void) {}
|
||||||
|
#endif /* CONFIG_PCI */
|
||||||
|
|
||||||
|
static void __init ubnt_xm_init(void)
|
||||||
|
@@ -105,14 +113,7 @@ static void __init ubnt_xm_init(void)
|
||||||
|
ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
|
||||||
|
ARRAY_SIZE(ubnt_xm_spi_info));
|
||||||
|
|
||||||
|
-#ifdef CONFIG_PCI
|
||||||
|
- memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
|
||||||
|
- sizeof(ubnt_xm_eeprom_data.eeprom_data));
|
||||||
|
-
|
||||||
|
- ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
|
||||||
|
-#endif /* CONFIG_PCI */
|
||||||
|
-
|
||||||
|
- ath79_register_pci();
|
||||||
|
+ ubnt_xm_pci_init();
|
||||||
|
}
|
||||||
|
|
||||||
|
MIPS_MACHINE(ATH79_MACH_UBNT_XM,
|
||||||
|
|
@ -0,0 +1,143 @@
|
||||||
|
From 83d74abc7d549f5d6292b0474be080983239c0bd Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Sun, 20 Nov 2011 10:29:36 +0100
|
||||||
|
Subject: [PATCH 15/35] MIPS: ath79: allow to use board specific pci_plat_dev_init functions
|
||||||
|
|
||||||
|
Th current implementation causes NULL pointer dereference
|
||||||
|
if 'pci_data' is not set:
|
||||||
|
|
||||||
|
pci 0000:00:00.0: BAR 0: assigned [mem 0x10000000-0x1000ffff 64bit]
|
||||||
|
pci 0000:00:00.0: BAR 0: set to [mem 0x10000000-0x1000ffff 64bit] (PCI
|
||||||
|
address [0x10000000-0x1000ffff])
|
||||||
|
CPU 0 Unable to handle kernel paging request at virtual address 00000000, epc == 802daca0, ra == 802e78a4
|
||||||
|
Oops[#1]:
|
||||||
|
Cpu 0
|
||||||
|
$ 0 : 00000000 80420000 00000000 00000000
|
||||||
|
$ 4 : 00000000 00000000 00000001 00000001
|
||||||
|
$ 8 : 00000001 0000032c 81c54700 00000001
|
||||||
|
$12 : 0000032d 0000000f 00000000 ffffffff
|
||||||
|
$16 : 81c14c00 00000001 802dac74 80195f98
|
||||||
|
$20 : 802ea050 00000000 00000000 00000000
|
||||||
|
$24 : 00000003 800617f0
|
||||||
|
$28 : 81c20000 81c21e70 00000000 802e78a4
|
||||||
|
Hi : 00000000
|
||||||
|
Lo : 4190ab00
|
||||||
|
epc : 802daca0 0x802daca0
|
||||||
|
Not tainted
|
||||||
|
ra : 802e78a4 0x802e78a4
|
||||||
|
Status: 1000c003 KERNEL EXL IE
|
||||||
|
Cause : 00800008
|
||||||
|
BadVA : 00000000
|
||||||
|
PrId : 00019374 (MIPS 24Kc)
|
||||||
|
Modules linked in:
|
||||||
|
Process swapper (pid: 1, threadinfo=81c20000, task=81c18000, tls=00000000)
|
||||||
|
Stack : 00000000 8027d5d8 802e8ae0 00000000 01000000 802e8b5c 81c50600 00000000
|
||||||
|
802ff290 00000000 80420000 802ea0bc 00000000 00000000 80420000 802ff290
|
||||||
|
80420000 80060930 33390000 00000000 00002308 80140a80 00000028 802d0000
|
||||||
|
00000000 800ba024 802ff004 802ff0c8 802ff290 00000000 00000000 00000000
|
||||||
|
00000000 802d897c 01234567 7f827068 00000000 0045f798 00460000 00000000
|
||||||
|
|
||||||
|
This can be avoided by calling the 'ar724x_pci_add_data'
|
||||||
|
function from the board specific setup code. However it
|
||||||
|
makes no sense to use that function for every board,
|
||||||
|
especially when the board does not needs to set the
|
||||||
|
platform_data field of any PCI device.
|
||||||
|
|
||||||
|
The patch allows the board setup code to specify a board
|
||||||
|
specific function if that is required.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
|
||||||
|
v2: - no changes
|
||||||
|
|
||||||
|
The pci_irq_map function can throw another NULL pointer
|
||||||
|
dereference, that will be fixed in a subsequent patch.
|
||||||
|
---
|
||||||
|
arch/mips/ath79/mach-ubnt-xm.c | 13 ++++++++++++-
|
||||||
|
arch/mips/ath79/pci.c | 14 ++++++++------
|
||||||
|
arch/mips/ath79/pci.h | 4 +++-
|
||||||
|
3 files changed, 23 insertions(+), 8 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
+++ b/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
@@ -85,16 +85,27 @@ static struct ath9k_platform_data ubnt_x
|
||||||
|
static struct ar724x_pci_data ubnt_xm_pci_data[] = {
|
||||||
|
{
|
||||||
|
.irq = ATH79_PCI_IRQ(0),
|
||||||
|
- .pdata = &ubnt_xm_eeprom_data,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
+static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev)
|
||||||
|
+{
|
||||||
|
+ switch (PCI_SLOT(dev->devfn)) {
|
||||||
|
+ case 0:
|
||||||
|
+ dev->dev.platform_data = &ubnt_xm_eeprom_data;
|
||||||
|
+ break;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static void __init ubnt_xm_pci_init(void)
|
||||||
|
{
|
||||||
|
memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
|
||||||
|
sizeof(ubnt_xm_eeprom_data.eeprom_data));
|
||||||
|
|
||||||
|
ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
|
||||||
|
+ ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init);
|
||||||
|
ath79_register_pci();
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
--- a/arch/mips/ath79/pci.c
|
||||||
|
+++ b/arch/mips/ath79/pci.c
|
||||||
|
@@ -14,6 +14,7 @@
|
||||||
|
#include <asm/mach-ath79/pci.h>
|
||||||
|
#include "pci.h"
|
||||||
|
|
||||||
|
+static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
|
||||||
|
static struct ar724x_pci_data *pci_data;
|
||||||
|
static int pci_data_size;
|
||||||
|
|
||||||
|
@@ -38,14 +39,15 @@ int __init pcibios_map_irq(const struct
|
||||||
|
|
||||||
|
int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||||
|
{
|
||||||
|
- unsigned int devfn = dev->devfn;
|
||||||
|
-
|
||||||
|
- if (devfn > pci_data_size - 1)
|
||||||
|
- return PCIBIOS_DEVICE_NOT_FOUND;
|
||||||
|
+ if (ath79_pci_plat_dev_init)
|
||||||
|
+ return ath79_pci_plat_dev_init(dev);
|
||||||
|
|
||||||
|
- dev->dev.platform_data = pci_data[devfn].pdata;
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
|
||||||
|
- return PCIBIOS_SUCCESSFUL;
|
||||||
|
+void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev))
|
||||||
|
+{
|
||||||
|
+ ath79_pci_plat_dev_init = func;
|
||||||
|
}
|
||||||
|
|
||||||
|
int __init ath79_register_pci(void)
|
||||||
|
--- a/arch/mips/ath79/pci.h
|
||||||
|
+++ b/arch/mips/ath79/pci.h
|
||||||
|
@@ -13,14 +13,16 @@
|
||||||
|
|
||||||
|
struct ar724x_pci_data {
|
||||||
|
int irq;
|
||||||
|
- void *pdata;
|
||||||
|
};
|
||||||
|
|
||||||
|
void ar724x_pci_add_data(struct ar724x_pci_data *data, int size);
|
||||||
|
|
||||||
|
#ifdef CONFIG_PCI
|
||||||
|
+void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev));
|
||||||
|
int ath79_register_pci(void);
|
||||||
|
#else
|
||||||
|
+static inline void
|
||||||
|
+ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {}
|
||||||
|
static inline int ath79_register_pci(void) { return 0; }
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
@ -0,0 +1,435 @@
|
||||||
|
From 9f6d46372cf2a493eaeeffbefe0a796379f838fa Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Tue, 22 Nov 2011 22:54:32 +0100
|
||||||
|
Subject: [PATCH 16/35] MIPS: ath79: add support for the PCI host controller of the AR71XX SoCs
|
||||||
|
|
||||||
|
The Atheros AR71XX SoCs have a built-in PCI Host Controller.
|
||||||
|
This patch adds a driver for that, and modifies the relevant
|
||||||
|
files in order to allow to register the PCI controller from
|
||||||
|
board specific setup.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
|
||||||
|
|
||||||
|
v2: - add missing pci-ar71xx.c
|
||||||
|
---
|
||||||
|
arch/mips/ath79/Kconfig | 1 +
|
||||||
|
arch/mips/include/asm/mach-ath79/pci.h | 6 +
|
||||||
|
arch/mips/pci/Makefile | 1 +
|
||||||
|
arch/mips/pci/pci-ar71xx.c | 375 ++++++++++++++++++++++++++++++++
|
||||||
|
4 files changed, 383 insertions(+), 0 deletions(-)
|
||||||
|
create mode 100644 arch/mips/pci/pci-ar71xx.c
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/Kconfig
|
||||||
|
+++ b/arch/mips/ath79/Kconfig
|
||||||
|
@@ -52,6 +52,7 @@ endmenu
|
||||||
|
config SOC_AR71XX
|
||||||
|
select USB_ARCH_HAS_EHCI
|
||||||
|
select USB_ARCH_HAS_OHCI
|
||||||
|
+ select HW_HAS_PCI
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
config SOC_AR724X
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/pci.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/pci.h
|
||||||
|
@@ -11,6 +11,12 @@
|
||||||
|
#ifndef __ASM_MACH_ATH79_PCI_H
|
||||||
|
#define __ASM_MACH_ATH79_PCI_H
|
||||||
|
|
||||||
|
+#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
|
||||||
|
+int ar71xx_pcibios_init(void);
|
||||||
|
+#else
|
||||||
|
+static inline int ar71xx_pcibios_init(void) { return 0 };
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X)
|
||||||
|
int ar724x_pcibios_init(int irq);
|
||||||
|
#else
|
||||||
|
--- a/arch/mips/pci/Makefile
|
||||||
|
+++ b/arch/mips/pci/Makefile
|
||||||
|
@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
|
||||||
|
obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
|
||||||
|
ops-bcm63xx.o
|
||||||
|
obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
|
||||||
|
+obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
|
||||||
|
obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o
|
||||||
|
|
||||||
|
#
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/arch/mips/pci/pci-ar71xx.c
|
||||||
|
@@ -0,0 +1,375 @@
|
||||||
|
+/*
|
||||||
|
+ * Atheros AR71xx PCI host controller driver
|
||||||
|
+ *
|
||||||
|
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||||
|
+ *
|
||||||
|
+ * Parts of this file are based on Atheros' 2.6.15 BSP
|
||||||
|
+ *
|
||||||
|
+ * This program is free software; you can redistribute it and/or modify it
|
||||||
|
+ * under the terms of the GNU General Public License version 2 as published
|
||||||
|
+ * by the Free Software Foundation.
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+#include <linux/resource.h>
|
||||||
|
+#include <linux/types.h>
|
||||||
|
+#include <linux/delay.h>
|
||||||
|
+#include <linux/bitops.h>
|
||||||
|
+#include <linux/pci.h>
|
||||||
|
+#include <linux/pci_regs.h>
|
||||||
|
+#include <linux/interrupt.h>
|
||||||
|
+
|
||||||
|
+#include <asm/mach-ath79/ar71xx_regs.h>
|
||||||
|
+#include <asm/mach-ath79/ath79.h>
|
||||||
|
+#include <asm/mach-ath79/pci.h>
|
||||||
|
+
|
||||||
|
+#define AR71XX_PCI_MEM_BASE 0x10000000
|
||||||
|
+#define AR71XX_PCI_MEM_SIZE 0x08000000
|
||||||
|
+
|
||||||
|
+#define AR71XX_PCI_WIN0_OFFS 0x10000000
|
||||||
|
+#define AR71XX_PCI_WIN1_OFFS 0x11000000
|
||||||
|
+#define AR71XX_PCI_WIN2_OFFS 0x12000000
|
||||||
|
+#define AR71XX_PCI_WIN3_OFFS 0x13000000
|
||||||
|
+#define AR71XX_PCI_WIN4_OFFS 0x14000000
|
||||||
|
+#define AR71XX_PCI_WIN5_OFFS 0x15000000
|
||||||
|
+#define AR71XX_PCI_WIN6_OFFS 0x16000000
|
||||||
|
+#define AR71XX_PCI_WIN7_OFFS 0x07000000
|
||||||
|
+
|
||||||
|
+#define AR71XX_PCI_CFG_BASE \
|
||||||
|
+ (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
|
||||||
|
+#define AR71XX_PCI_CFG_SIZE 0x100
|
||||||
|
+
|
||||||
|
+#define AR71XX_PCI_REG_CRP_AD_CBE 0x00
|
||||||
|
+#define AR71XX_PCI_REG_CRP_WRDATA 0x04
|
||||||
|
+#define AR71XX_PCI_REG_CRP_RDDATA 0x08
|
||||||
|
+#define AR71XX_PCI_REG_CFG_AD 0x0c
|
||||||
|
+#define AR71XX_PCI_REG_CFG_CBE 0x10
|
||||||
|
+#define AR71XX_PCI_REG_CFG_WRDATA 0x14
|
||||||
|
+#define AR71XX_PCI_REG_CFG_RDDATA 0x18
|
||||||
|
+#define AR71XX_PCI_REG_PCI_ERR 0x1c
|
||||||
|
+#define AR71XX_PCI_REG_PCI_ERR_ADDR 0x20
|
||||||
|
+#define AR71XX_PCI_REG_AHB_ERR 0x24
|
||||||
|
+#define AR71XX_PCI_REG_AHB_ERR_ADDR 0x28
|
||||||
|
+
|
||||||
|
+#define AR71XX_PCI_CRP_CMD_WRITE 0x00010000
|
||||||
|
+#define AR71XX_PCI_CRP_CMD_READ 0x00000000
|
||||||
|
+#define AR71XX_PCI_CFG_CMD_READ 0x0000000a
|
||||||
|
+#define AR71XX_PCI_CFG_CMD_WRITE 0x0000000b
|
||||||
|
+
|
||||||
|
+#define AR71XX_PCI_INT_CORE BIT(4)
|
||||||
|
+#define AR71XX_PCI_INT_DEV2 BIT(2)
|
||||||
|
+#define AR71XX_PCI_INT_DEV1 BIT(1)
|
||||||
|
+#define AR71XX_PCI_INT_DEV0 BIT(0)
|
||||||
|
+
|
||||||
|
+#define AR71XX_PCI_IRQ_COUNT 5
|
||||||
|
+
|
||||||
|
+static DEFINE_SPINLOCK(ar71xx_pci_lock);
|
||||||
|
+static void __iomem *ar71xx_pcicfg_base;
|
||||||
|
+
|
||||||
|
+/* Byte lane enable bits */
|
||||||
|
+static const u8 ar71xx_pci_ble_table[4][4] = {
|
||||||
|
+ {0x0, 0xf, 0xf, 0xf},
|
||||||
|
+ {0xe, 0xd, 0xb, 0x7},
|
||||||
|
+ {0xc, 0xf, 0x3, 0xf},
|
||||||
|
+ {0xf, 0xf, 0xf, 0xf},
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const u32 ar71xx_pci_read_mask[8] = {
|
||||||
|
+ 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
|
||||||
|
+{
|
||||||
|
+ u32 t;
|
||||||
|
+
|
||||||
|
+ t = ar71xx_pci_ble_table[size & 3][where & 3];
|
||||||
|
+ BUG_ON(t == 0xf);
|
||||||
|
+ t <<= (local) ? 20 : 4;
|
||||||
|
+
|
||||||
|
+ return t;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
|
||||||
|
+ int where)
|
||||||
|
+{
|
||||||
|
+ u32 ret;
|
||||||
|
+
|
||||||
|
+ if (!bus->number) {
|
||||||
|
+ /* type 0 */
|
||||||
|
+ ret = (1 << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) |
|
||||||
|
+ (where & ~3);
|
||||||
|
+ } else {
|
||||||
|
+ /* type 1 */
|
||||||
|
+ ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) |
|
||||||
|
+ (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ return ret;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int ar71xx_pci_check_error(int quiet)
|
||||||
|
+{
|
||||||
|
+ void __iomem *base = ar71xx_pcicfg_base;
|
||||||
|
+ u32 pci_err;
|
||||||
|
+ u32 ahb_err;
|
||||||
|
+
|
||||||
|
+ pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3;
|
||||||
|
+ if (pci_err) {
|
||||||
|
+ if (!quiet) {
|
||||||
|
+ u32 addr;
|
||||||
|
+
|
||||||
|
+ addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR);
|
||||||
|
+ pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
|
||||||
|
+ "PCI", pci_err, addr);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ /* clear PCI error status */
|
||||||
|
+ __raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1;
|
||||||
|
+ if (ahb_err) {
|
||||||
|
+ if (!quiet) {
|
||||||
|
+ u32 addr;
|
||||||
|
+
|
||||||
|
+ addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR);
|
||||||
|
+ pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
|
||||||
|
+ "AHB", ahb_err, addr);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ /* clear AHB error status */
|
||||||
|
+ __raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ return !!(ahb_err | pci_err);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static inline void ar71xx_pci_local_write(int where, int size, u32 value)
|
||||||
|
+{
|
||||||
|
+ void __iomem *base = ar71xx_pcicfg_base;
|
||||||
|
+ u32 ad_cbe;
|
||||||
|
+
|
||||||
|
+ value = value << (8 * (where & 3));
|
||||||
|
+
|
||||||
|
+ ad_cbe = AR71XX_PCI_CRP_CMD_WRITE | (where & ~3);
|
||||||
|
+ ad_cbe |= ar71xx_pci_get_ble(where, size, 1);
|
||||||
|
+
|
||||||
|
+ __raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE);
|
||||||
|
+ __raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
|
||||||
|
+ unsigned int devfn,
|
||||||
|
+ int where, int size, u32 cmd)
|
||||||
|
+{
|
||||||
|
+ void __iomem *base = ar71xx_pcicfg_base;
|
||||||
|
+ u32 addr;
|
||||||
|
+
|
||||||
|
+ addr = ar71xx_pci_bus_addr(bus, devfn, where);
|
||||||
|
+
|
||||||
|
+ __raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD);
|
||||||
|
+ __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
|
||||||
|
+ base + AR71XX_PCI_REG_CFG_CBE);
|
||||||
|
+
|
||||||
|
+ return ar71xx_pci_check_error(1);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
|
||||||
|
+ int where, int size, u32 *value)
|
||||||
|
+{
|
||||||
|
+ void __iomem *base = ar71xx_pcicfg_base;
|
||||||
|
+ unsigned long flags;
|
||||||
|
+ u32 data;
|
||||||
|
+ int err;
|
||||||
|
+ int ret;
|
||||||
|
+
|
||||||
|
+ ret = PCIBIOS_SUCCESSFUL;
|
||||||
|
+ data = ~0;
|
||||||
|
+
|
||||||
|
+ spin_lock_irqsave(&ar71xx_pci_lock, flags);
|
||||||
|
+
|
||||||
|
+ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
|
||||||
|
+ AR71XX_PCI_CFG_CMD_READ);
|
||||||
|
+ if (err)
|
||||||
|
+ ret = PCIBIOS_DEVICE_NOT_FOUND;
|
||||||
|
+ else
|
||||||
|
+ data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
|
||||||
|
+
|
||||||
|
+ spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
|
||||||
|
+
|
||||||
|
+ *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
|
||||||
|
+
|
||||||
|
+ return ret;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
|
||||||
|
+ int where, int size, u32 value)
|
||||||
|
+{
|
||||||
|
+ void __iomem *base = ar71xx_pcicfg_base;
|
||||||
|
+ unsigned long flags;
|
||||||
|
+ int err;
|
||||||
|
+ int ret;
|
||||||
|
+
|
||||||
|
+ value = value << (8 * (where & 3));
|
||||||
|
+ ret = PCIBIOS_SUCCESSFUL;
|
||||||
|
+
|
||||||
|
+ spin_lock_irqsave(&ar71xx_pci_lock, flags);
|
||||||
|
+
|
||||||
|
+ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
|
||||||
|
+ AR71XX_PCI_CFG_CMD_WRITE);
|
||||||
|
+ if (err)
|
||||||
|
+ ret = PCIBIOS_DEVICE_NOT_FOUND;
|
||||||
|
+ else
|
||||||
|
+ __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
|
||||||
|
+
|
||||||
|
+ spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
|
||||||
|
+
|
||||||
|
+ return ret;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static struct pci_ops ar71xx_pci_ops = {
|
||||||
|
+ .read = ar71xx_pci_read_config,
|
||||||
|
+ .write = ar71xx_pci_write_config,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct resource ar71xx_pci_io_resource = {
|
||||||
|
+ .name = "PCI IO space",
|
||||||
|
+ .start = 0,
|
||||||
|
+ .end = 0,
|
||||||
|
+ .flags = IORESOURCE_IO,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct resource ar71xx_pci_mem_resource = {
|
||||||
|
+ .name = "PCI memory space",
|
||||||
|
+ .start = AR71XX_PCI_MEM_BASE,
|
||||||
|
+ .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
|
||||||
|
+ .flags = IORESOURCE_MEM
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct pci_controller ar71xx_pci_controller = {
|
||||||
|
+ .pci_ops = &ar71xx_pci_ops,
|
||||||
|
+ .mem_resource = &ar71xx_pci_mem_resource,
|
||||||
|
+ .io_resource = &ar71xx_pci_io_resource,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||||
|
+{
|
||||||
|
+ void __iomem *base = ath79_reset_base;
|
||||||
|
+ u32 pending;
|
||||||
|
+
|
||||||
|
+ pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
|
||||||
|
+ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
|
||||||
|
+
|
||||||
|
+ if (pending & AR71XX_PCI_INT_DEV0)
|
||||||
|
+ generic_handle_irq(ATH79_PCI_IRQ(0));
|
||||||
|
+
|
||||||
|
+ else if (pending & AR71XX_PCI_INT_DEV1)
|
||||||
|
+ generic_handle_irq(ATH79_PCI_IRQ(1));
|
||||||
|
+
|
||||||
|
+ else if (pending & AR71XX_PCI_INT_DEV2)
|
||||||
|
+ generic_handle_irq(ATH79_PCI_IRQ(2));
|
||||||
|
+
|
||||||
|
+ else if (pending & AR71XX_PCI_INT_CORE)
|
||||||
|
+ generic_handle_irq(ATH79_PCI_IRQ(4));
|
||||||
|
+
|
||||||
|
+ else
|
||||||
|
+ spurious_interrupt();
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void ar71xx_pci_irq_unmask(struct irq_data *d)
|
||||||
|
+{
|
||||||
|
+ unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
|
||||||
|
+ void __iomem *base = ath79_reset_base;
|
||||||
|
+ u32 t;
|
||||||
|
+
|
||||||
|
+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
|
||||||
|
+ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
|
||||||
|
+
|
||||||
|
+ /* flush write */
|
||||||
|
+ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void ar71xx_pci_irq_mask(struct irq_data *d)
|
||||||
|
+{
|
||||||
|
+ unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
|
||||||
|
+ void __iomem *base = ath79_reset_base;
|
||||||
|
+ u32 t;
|
||||||
|
+
|
||||||
|
+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
|
||||||
|
+ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
|
||||||
|
+
|
||||||
|
+ /* flush write */
|
||||||
|
+ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static struct irq_chip ar71xx_pci_irq_chip = {
|
||||||
|
+ .name = "AR71XX PCI",
|
||||||
|
+ .irq_mask = ar71xx_pci_irq_mask,
|
||||||
|
+ .irq_unmask = ar71xx_pci_irq_unmask,
|
||||||
|
+ .irq_mask_ack = ar71xx_pci_irq_mask,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static __init void ar71xx_pci_irq_init(void)
|
||||||
|
+{
|
||||||
|
+ void __iomem *base = ath79_reset_base;
|
||||||
|
+ int i;
|
||||||
|
+
|
||||||
|
+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
|
||||||
|
+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
|
||||||
|
+
|
||||||
|
+ BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
|
||||||
|
+
|
||||||
|
+ for (i = ATH79_PCI_IRQ_BASE;
|
||||||
|
+ i < ATH79_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++)
|
||||||
|
+ irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
|
||||||
|
+ handle_level_irq);
|
||||||
|
+
|
||||||
|
+ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar71xx_pci_irq_handler);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static __init void ar71xx_pci_reset(void)
|
||||||
|
+{
|
||||||
|
+ void __iomem *ddr_base = ath79_ddr_base;
|
||||||
|
+
|
||||||
|
+ ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
|
||||||
|
+ mdelay(100);
|
||||||
|
+
|
||||||
|
+ ath79_device_reset_clear(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
|
||||||
|
+ mdelay(100);
|
||||||
|
+
|
||||||
|
+ __raw_writel(AR71XX_PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0);
|
||||||
|
+ __raw_writel(AR71XX_PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1);
|
||||||
|
+ __raw_writel(AR71XX_PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2);
|
||||||
|
+ __raw_writel(AR71XX_PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3);
|
||||||
|
+ __raw_writel(AR71XX_PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4);
|
||||||
|
+ __raw_writel(AR71XX_PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5);
|
||||||
|
+ __raw_writel(AR71XX_PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6);
|
||||||
|
+ __raw_writel(AR71XX_PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7);
|
||||||
|
+
|
||||||
|
+ mdelay(100);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+__init int ar71xx_pcibios_init(void)
|
||||||
|
+{
|
||||||
|
+ u32 t;
|
||||||
|
+
|
||||||
|
+ ar71xx_pcicfg_base = ioremap(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE);
|
||||||
|
+ if (ar71xx_pcicfg_base == NULL)
|
||||||
|
+ return -ENOMEM;
|
||||||
|
+
|
||||||
|
+ ar71xx_pci_reset();
|
||||||
|
+
|
||||||
|
+ /* setup COMMAND register */
|
||||||
|
+ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
|
||||||
|
+ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
|
||||||
|
+ ar71xx_pci_local_write(PCI_COMMAND, 4, t);
|
||||||
|
+
|
||||||
|
+ /* clear bus errors */
|
||||||
|
+ ar71xx_pci_check_error(1);
|
||||||
|
+
|
||||||
|
+ ar71xx_pci_irq_init();
|
||||||
|
+
|
||||||
|
+ register_pci_controller(&ar71xx_pci_controller);
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
|
@ -0,0 +1,164 @@
|
||||||
|
From 8a1a5852aa7f8cfc027b2b0bb51cbbac4309e144 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Sun, 20 Nov 2011 14:32:09 +0100
|
||||||
|
Subject: [PATCH 17/35] MIPS: ath79: allow to use SoC specific PCI IRQ maps
|
||||||
|
|
||||||
|
The PCI controllers in the AR71XX and in the
|
||||||
|
AR724X SoCs are different, and both of them
|
||||||
|
uses different IRQ wiring.
|
||||||
|
|
||||||
|
The patch modifies the 'pcibios_map_irq' function
|
||||||
|
in order to allow to use different IRQ maps for
|
||||||
|
the different SoCs. The patch also adds a function,
|
||||||
|
which lets the board setup code to override the
|
||||||
|
default IRQ map.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
|
||||||
|
v2: - no changes
|
||||||
|
---
|
||||||
|
arch/mips/ath79/pci.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++---
|
||||||
|
arch/mips/ath79/pci.h | 9 ++++++
|
||||||
|
2 files changed, 77 insertions(+), 4 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/pci.c
|
||||||
|
+++ b/arch/mips/ath79/pci.c
|
||||||
|
@@ -8,6 +8,7 @@
|
||||||
|
* by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
|
||||||
|
+#include <linux/init.h>
|
||||||
|
#include <linux/pci.h>
|
||||||
|
#include <asm/mach-ath79/ath79.h>
|
||||||
|
#include <asm/mach-ath79/irq.h>
|
||||||
|
@@ -15,9 +16,35 @@
|
||||||
|
#include "pci.h"
|
||||||
|
|
||||||
|
static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
|
||||||
|
+static const struct ath79_pci_irq *ath79_pci_irq_map __initdata;
|
||||||
|
+static unsigned ath79_pci_nr_irqs __initdata;
|
||||||
|
static struct ar724x_pci_data *pci_data;
|
||||||
|
static int pci_data_size;
|
||||||
|
|
||||||
|
+static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = {
|
||||||
|
+ {
|
||||||
|
+ .slot = 17,
|
||||||
|
+ .pin = 1,
|
||||||
|
+ .irq = ATH79_PCI_IRQ(0),
|
||||||
|
+ }, {
|
||||||
|
+ .slot = 18,
|
||||||
|
+ .pin = 1,
|
||||||
|
+ .irq = ATH79_PCI_IRQ(1),
|
||||||
|
+ }, {
|
||||||
|
+ .slot = 19,
|
||||||
|
+ .pin = 1,
|
||||||
|
+ .irq = ATH79_PCI_IRQ(2),
|
||||||
|
+ }
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = {
|
||||||
|
+ {
|
||||||
|
+ .slot = 0,
|
||||||
|
+ .pin = 1,
|
||||||
|
+ .irq = ATH79_PCI_IRQ(0),
|
||||||
|
+ }
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
void ar724x_pci_add_data(struct ar724x_pci_data *data, int size)
|
||||||
|
{
|
||||||
|
pci_data = data;
|
||||||
|
@@ -26,13 +53,40 @@ void ar724x_pci_add_data(struct ar724x_p
|
||||||
|
|
||||||
|
int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
|
||||||
|
{
|
||||||
|
- unsigned int devfn = dev->devfn;
|
||||||
|
int irq = -1;
|
||||||
|
+ int i;
|
||||||
|
|
||||||
|
- if (devfn > pci_data_size - 1)
|
||||||
|
- return irq;
|
||||||
|
-
|
||||||
|
- irq = pci_data[devfn].irq;
|
||||||
|
+ if (ath79_pci_nr_irqs == 0 ||
|
||||||
|
+ ath79_pci_irq_map == NULL) {
|
||||||
|
+ if (soc_is_ar71xx()) {
|
||||||
|
+ ath79_pci_irq_map = ar71xx_pci_irq_map;
|
||||||
|
+ ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map);
|
||||||
|
+ } else if (soc_is_ar724x()) {
|
||||||
|
+ ath79_pci_irq_map = ar724x_pci_irq_map;
|
||||||
|
+ ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
|
||||||
|
+ } else {
|
||||||
|
+ pr_crit("pci %s: invalid irq map\n",
|
||||||
|
+ pci_name((struct pci_dev *) dev));
|
||||||
|
+ return irq;
|
||||||
|
+ }
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ for (i = 0; i < ath79_pci_nr_irqs; i++) {
|
||||||
|
+ const struct ath79_pci_irq *entry;
|
||||||
|
+
|
||||||
|
+ entry = &ath79_pci_irq_map[i];
|
||||||
|
+ if (entry->slot == slot && entry->pin == pin) {
|
||||||
|
+ irq = entry->irq;
|
||||||
|
+ break;
|
||||||
|
+ }
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ if (irq < 0)
|
||||||
|
+ pr_crit("pci %s: no irq found for pin %u\n",
|
||||||
|
+ pci_name((struct pci_dev *) dev), pin);
|
||||||
|
+ else
|
||||||
|
+ pr_info("pci %s: using irq %d for pin %u\n",
|
||||||
|
+ pci_name((struct pci_dev *) dev), irq, pin);
|
||||||
|
|
||||||
|
return irq;
|
||||||
|
}
|
||||||
|
@@ -45,6 +99,13 @@ int pcibios_plat_dev_init(struct pci_dev
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
+void __init ath79_pci_set_irq_map(unsigned nr_irqs,
|
||||||
|
+ const struct ath79_pci_irq *map)
|
||||||
|
+{
|
||||||
|
+ ath79_pci_nr_irqs = nr_irqs;
|
||||||
|
+ ath79_pci_irq_map = map;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev))
|
||||||
|
{
|
||||||
|
ath79_pci_plat_dev_init = func;
|
||||||
|
@@ -52,6 +113,9 @@ void __init ath79_pci_set_plat_dev_init(
|
||||||
|
|
||||||
|
int __init ath79_register_pci(void)
|
||||||
|
{
|
||||||
|
+ if (soc_is_ar71xx())
|
||||||
|
+ return ar71xx_pcibios_init();
|
||||||
|
+
|
||||||
|
if (soc_is_ar724x())
|
||||||
|
return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/pci.h
|
||||||
|
+++ b/arch/mips/ath79/pci.h
|
||||||
|
@@ -15,13 +15,22 @@ struct ar724x_pci_data {
|
||||||
|
int irq;
|
||||||
|
};
|
||||||
|
|
||||||
|
+struct ath79_pci_irq {
|
||||||
|
+ u8 slot;
|
||||||
|
+ u8 pin;
|
||||||
|
+ int irq;
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
void ar724x_pci_add_data(struct ar724x_pci_data *data, int size);
|
||||||
|
|
||||||
|
#ifdef CONFIG_PCI
|
||||||
|
+void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map);
|
||||||
|
void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev));
|
||||||
|
int ath79_register_pci(void);
|
||||||
|
#else
|
||||||
|
static inline void
|
||||||
|
+ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map) {}
|
||||||
|
+static inline void
|
||||||
|
ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {}
|
||||||
|
static inline int ath79_register_pci(void) { return 0; }
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,85 @@
|
||||||
|
From 0b026adc7a471edd018a060427e62d06e54be2bc Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Sun, 20 Nov 2011 15:50:32 +0100
|
||||||
|
Subject: [PATCH 18/35] MIPS: ath79: remove ar724x_pci_add_data function
|
||||||
|
|
||||||
|
The variables set by this function are not used anymore.
|
||||||
|
Remove the function and the relevant variables as well.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
|
||||||
|
v2: - no changes
|
||||||
|
---
|
||||||
|
arch/mips/ath79/mach-ubnt-xm.c | 7 -------
|
||||||
|
arch/mips/ath79/pci.c | 8 --------
|
||||||
|
arch/mips/ath79/pci.h | 6 ------
|
||||||
|
3 files changed, 0 insertions(+), 21 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
+++ b/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
@@ -82,12 +82,6 @@ static struct ath79_spi_platform_data ub
|
||||||
|
#ifdef CONFIG_PCI
|
||||||
|
static struct ath9k_platform_data ubnt_xm_eeprom_data;
|
||||||
|
|
||||||
|
-static struct ar724x_pci_data ubnt_xm_pci_data[] = {
|
||||||
|
- {
|
||||||
|
- .irq = ATH79_PCI_IRQ(0),
|
||||||
|
- },
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev)
|
||||||
|
{
|
||||||
|
switch (PCI_SLOT(dev->devfn)) {
|
||||||
|
@@ -104,7 +98,6 @@ static void __init ubnt_xm_pci_init(void
|
||||||
|
memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
|
||||||
|
sizeof(ubnt_xm_eeprom_data.eeprom_data));
|
||||||
|
|
||||||
|
- ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
|
||||||
|
ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init);
|
||||||
|
ath79_register_pci();
|
||||||
|
}
|
||||||
|
--- a/arch/mips/ath79/pci.c
|
||||||
|
+++ b/arch/mips/ath79/pci.c
|
||||||
|
@@ -18,8 +18,6 @@
|
||||||
|
static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
|
||||||
|
static const struct ath79_pci_irq *ath79_pci_irq_map __initdata;
|
||||||
|
static unsigned ath79_pci_nr_irqs __initdata;
|
||||||
|
-static struct ar724x_pci_data *pci_data;
|
||||||
|
-static int pci_data_size;
|
||||||
|
|
||||||
|
static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = {
|
||||||
|
{
|
||||||
|
@@ -45,12 +43,6 @@ static const struct ath79_pci_irq ar724x
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
-void ar724x_pci_add_data(struct ar724x_pci_data *data, int size)
|
||||||
|
-{
|
||||||
|
- pci_data = data;
|
||||||
|
- pci_data_size = size;
|
||||||
|
-}
|
||||||
|
-
|
||||||
|
int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
|
||||||
|
{
|
||||||
|
int irq = -1;
|
||||||
|
--- a/arch/mips/ath79/pci.h
|
||||||
|
+++ b/arch/mips/ath79/pci.h
|
||||||
|
@@ -11,18 +11,12 @@
|
||||||
|
#ifndef _ATH79_PCI_H
|
||||||
|
#define _ATH79_PCI_H
|
||||||
|
|
||||||
|
-struct ar724x_pci_data {
|
||||||
|
- int irq;
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
struct ath79_pci_irq {
|
||||||
|
u8 slot;
|
||||||
|
u8 pin;
|
||||||
|
int irq;
|
||||||
|
};
|
||||||
|
|
||||||
|
-void ar724x_pci_add_data(struct ar724x_pci_data *data, int size);
|
||||||
|
-
|
||||||
|
#ifdef CONFIG_PCI
|
||||||
|
void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map);
|
||||||
|
void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev));
|
||||||
|
|
@ -0,0 +1,33 @@
|
||||||
|
From 1759a5bc87d0eb8dbb0d8a9794b336813057eb88 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Thu, 25 Nov 2010 17:59:28 +0100
|
||||||
|
Subject: [PATCH 19/35] MIPS: ath79: register PCI controller on the PB44 board
|
||||||
|
|
||||||
|
The PB44 reference board has two miniPCI slots. Register
|
||||||
|
the PCI controller to make those usable.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
|
||||||
|
v2: - no changes
|
||||||
|
---
|
||||||
|
arch/mips/ath79/mach-pb44.c | 2 ++
|
||||||
|
1 files changed, 2 insertions(+), 0 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/mach-pb44.c
|
||||||
|
+++ b/arch/mips/ath79/mach-pb44.c
|
||||||
|
@@ -19,6 +19,7 @@
|
||||||
|
#include "dev-leds-gpio.h"
|
||||||
|
#include "dev-spi.h"
|
||||||
|
#include "dev-usb.h"
|
||||||
|
+#include "pci.h"
|
||||||
|
|
||||||
|
#define PB44_GPIO_I2C_SCL 0
|
||||||
|
#define PB44_GPIO_I2C_SDA 1
|
||||||
|
@@ -114,6 +115,7 @@ static void __init pb44_init(void)
|
||||||
|
ath79_register_spi(&pb44_spi_data, pb44_spi_info,
|
||||||
|
ARRAY_SIZE(pb44_spi_info));
|
||||||
|
ath79_register_usb();
|
||||||
|
+ ath79_register_pci();
|
||||||
|
}
|
||||||
|
|
||||||
|
MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
|
||||||
|
|
@ -0,0 +1,77 @@
|
||||||
|
From e83c294ff219ff709b8179cbff64f293199a6dad Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Tue, 22 Nov 2011 21:13:58 +0100
|
||||||
|
Subject: [PATCH 20/35] MIPS: ath79: update copyright headers of PCI related files
|
||||||
|
|
||||||
|
Add copyright records according to the recent changes in
|
||||||
|
the PCI code. Also fix up the descriptions.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
|
||||||
|
|
||||||
|
Just in case if someone is curious about why 2008 and 2009 years are
|
||||||
|
present in this change:
|
||||||
|
|
||||||
|
The recent PCI specific changes were based on an existing
|
||||||
|
code which can be found in the OpenWrt repository, and we
|
||||||
|
are working on that since 2008.
|
||||||
|
|
||||||
|
v2: - no changes
|
||||||
|
---
|
||||||
|
arch/mips/ath79/pci.c | 4 ++++
|
||||||
|
arch/mips/ath79/pci.h | 4 +++-
|
||||||
|
arch/mips/include/asm/mach-ath79/pci.h | 4 +++-
|
||||||
|
arch/mips/pci/pci-ar724x.c | 3 ++-
|
||||||
|
4 files changed, 12 insertions(+), 3 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/pci.c
|
||||||
|
+++ b/arch/mips/ath79/pci.c
|
||||||
|
@@ -2,6 +2,10 @@
|
||||||
|
* Atheros AR71XX/AR724X specific PCI setup code
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
|
||||||
|
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||||
|
+ *
|
||||||
|
+ * Parts of this file are based on Atheros' 2.6.15 BSP
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License version 2 as published
|
||||||
|
--- a/arch/mips/ath79/pci.h
|
||||||
|
+++ b/arch/mips/ath79/pci.h
|
||||||
|
@@ -1,7 +1,9 @@
|
||||||
|
/*
|
||||||
|
- * Atheros 724x PCI support
|
||||||
|
+ * Atheros AR71XX/AR724X PCI support
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
|
||||||
|
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License version 2 as published
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/pci.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/pci.h
|
||||||
|
@@ -1,7 +1,9 @@
|
||||||
|
/*
|
||||||
|
- * Atheros 724x PCI support
|
||||||
|
+ * Atheros AR71XX/AR724X PCI support
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
|
||||||
|
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License version 2 as published
|
||||||
|
--- a/arch/mips/pci/pci-ar724x.c
|
||||||
|
+++ b/arch/mips/pci/pci-ar724x.c
|
||||||
|
@@ -1,7 +1,8 @@
|
||||||
|
/*
|
||||||
|
- * Atheros 724x PCI support
|
||||||
|
+ * Atheros AR724X PCI host controller driver
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
|
||||||
|
+ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License version 2 as published
|
||||||
|
|
@ -0,0 +1,52 @@
|
||||||
|
From f60aed87f838ecfa4033ff1f63f97d05359b3b51 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Sun, 11 Dec 2011 17:36:08 +0100
|
||||||
|
Subject: [PATCH 21/35] MIPS: ath79: add early_printk support for AR934X
|
||||||
|
|
||||||
|
The patch allows to see kernel messages on AR934X SoCs in
|
||||||
|
early boot stage.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
|
||||||
|
---
|
||||||
|
arch/mips/ath79/early_printk.c | 3 +++
|
||||||
|
arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 6 +++++-
|
||||||
|
2 files changed, 8 insertions(+), 1 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/early_printk.c
|
||||||
|
+++ b/arch/mips/ath79/early_printk.c
|
||||||
|
@@ -71,6 +71,9 @@ static void prom_putchar_init(void)
|
||||||
|
case REV_ID_MAJOR_AR7241:
|
||||||
|
case REV_ID_MAJOR_AR7242:
|
||||||
|
case REV_ID_MAJOR_AR913X:
|
||||||
|
+ case REV_ID_MAJOR_AR9341:
|
||||||
|
+ case REV_ID_MAJOR_AR9342:
|
||||||
|
+ case REV_ID_MAJOR_AR9344:
|
||||||
|
_prom_putchar = prom_putchar_ar71xx;
|
||||||
|
break;
|
||||||
|
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
@@ -1,10 +1,11 @@
|
||||||
|
/*
|
||||||
|
* Atheros AR71XX/AR724X/AR913X SoC register definitions
|
||||||
|
*
|
||||||
|
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
|
||||||
|
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||||
|
*
|
||||||
|
- * Parts of this file are based on Atheros' 2.6.15 BSP
|
||||||
|
+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License version 2 as published
|
||||||
|
@@ -249,6 +250,9 @@
|
||||||
|
#define REV_ID_MAJOR_AR7242 0x1100
|
||||||
|
#define REV_ID_MAJOR_AR9330 0x0110
|
||||||
|
#define REV_ID_MAJOR_AR9331 0x1110
|
||||||
|
+#define REV_ID_MAJOR_AR9341 0x0120
|
||||||
|
+#define REV_ID_MAJOR_AR9342 0x1120
|
||||||
|
+#define REV_ID_MAJOR_AR9344 0x2120
|
||||||
|
|
||||||
|
#define AR71XX_REV_ID_MINOR_MASK 0x3
|
||||||
|
#define AR71XX_REV_ID_MINOR_AR7130 0x0
|
||||||
|
|
@ -0,0 +1,54 @@
|
||||||
|
From 655a57ed2df5e34c32645e08c3244facba70ae5f Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Fri, 9 Dec 2011 14:39:04 +0100
|
||||||
|
Subject: [PATCH 22/35] MIPS: ath79: sort case statements in ath79_detect_sys_type
|
||||||
|
|
||||||
|
Sort the case statements alphabetically in order to improve
|
||||||
|
readability.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
|
||||||
|
---
|
||||||
|
arch/mips/ath79/setup.c | 24 ++++++++++++------------
|
||||||
|
1 files changed, 12 insertions(+), 12 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/setup.c
|
||||||
|
+++ b/arch/mips/ath79/setup.c
|
||||||
|
@@ -116,18 +116,6 @@ static void __init ath79_detect_sys_type
|
||||||
|
rev = id & AR724X_REV_ID_REVISION_MASK;
|
||||||
|
break;
|
||||||
|
|
||||||
|
- case REV_ID_MAJOR_AR9330:
|
||||||
|
- ath79_soc = ATH79_SOC_AR9330;
|
||||||
|
- chip = "9330";
|
||||||
|
- rev = id & AR933X_REV_ID_REVISION_MASK;
|
||||||
|
- break;
|
||||||
|
-
|
||||||
|
- case REV_ID_MAJOR_AR9331:
|
||||||
|
- ath79_soc = ATH79_SOC_AR9331;
|
||||||
|
- chip = "9331";
|
||||||
|
- rev = id & AR933X_REV_ID_REVISION_MASK;
|
||||||
|
- break;
|
||||||
|
-
|
||||||
|
case REV_ID_MAJOR_AR913X:
|
||||||
|
minor = id & AR913X_REV_ID_MINOR_MASK;
|
||||||
|
rev = id >> AR913X_REV_ID_REVISION_SHIFT;
|
||||||
|
@@ -145,6 +133,18 @@ static void __init ath79_detect_sys_type
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
+ case REV_ID_MAJOR_AR9330:
|
||||||
|
+ ath79_soc = ATH79_SOC_AR9330;
|
||||||
|
+ chip = "9330";
|
||||||
|
+ rev = id & AR933X_REV_ID_REVISION_MASK;
|
||||||
|
+ break;
|
||||||
|
+
|
||||||
|
+ case REV_ID_MAJOR_AR9331:
|
||||||
|
+ ath79_soc = ATH79_SOC_AR9331;
|
||||||
|
+ chip = "9331";
|
||||||
|
+ rev = id & AR933X_REV_ID_REVISION_MASK;
|
||||||
|
+ break;
|
||||||
|
+
|
||||||
|
default:
|
||||||
|
panic("ath79: unknown SoC, id:0x%08x", id);
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,120 @@
|
||||||
|
From 9c19e86a7eccf8efd159ba213290830164f33a71 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Sun, 11 Dec 2011 17:36:42 +0100
|
||||||
|
Subject: [PATCH 23/35] MIPS: ath79: add SoC detection code for AR934X
|
||||||
|
|
||||||
|
Also add 'soc_is_ar934[124x]' helper functions and a Kconfig
|
||||||
|
symbol for the AR934X SoCs.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
|
||||||
|
---
|
||||||
|
arch/mips/ath79/Kconfig | 4 ++++
|
||||||
|
arch/mips/ath79/setup.c | 21 ++++++++++++++++++++-
|
||||||
|
arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++
|
||||||
|
arch/mips/include/asm/mach-ath79/ath79.h | 23 +++++++++++++++++++++++
|
||||||
|
4 files changed, 49 insertions(+), 1 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/Kconfig
|
||||||
|
+++ b/arch/mips/ath79/Kconfig
|
||||||
|
@@ -69,6 +69,10 @@ config SOC_AR933X
|
||||||
|
select USB_ARCH_HAS_EHCI
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
+config SOC_AR934X
|
||||||
|
+ select USB_ARCH_HAS_EHCI
|
||||||
|
+ def_bool n
|
||||||
|
+
|
||||||
|
config ATH79_DEV_GPIO_BUTTONS
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/setup.c
|
||||||
|
+++ b/arch/mips/ath79/setup.c
|
||||||
|
@@ -1,10 +1,11 @@
|
||||||
|
/*
|
||||||
|
* Atheros AR71XX/AR724X/AR913X specific setup
|
||||||
|
*
|
||||||
|
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
|
||||||
|
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||||
|
*
|
||||||
|
- * Parts of this file are based on Atheros' 2.6.15 BSP
|
||||||
|
+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License version 2 as published
|
||||||
|
@@ -145,6 +146,24 @@ static void __init ath79_detect_sys_type
|
||||||
|
rev = id & AR933X_REV_ID_REVISION_MASK;
|
||||||
|
break;
|
||||||
|
|
||||||
|
+ case REV_ID_MAJOR_AR9341:
|
||||||
|
+ ath79_soc = ATH79_SOC_AR9341;
|
||||||
|
+ chip = "9341";
|
||||||
|
+ rev = id & AR934X_REV_ID_REVISION_MASK;
|
||||||
|
+ break;
|
||||||
|
+
|
||||||
|
+ case REV_ID_MAJOR_AR9342:
|
||||||
|
+ ath79_soc = ATH79_SOC_AR9342;
|
||||||
|
+ chip = "9342";
|
||||||
|
+ rev = id & AR934X_REV_ID_REVISION_MASK;
|
||||||
|
+ break;
|
||||||
|
+
|
||||||
|
+ case REV_ID_MAJOR_AR9344:
|
||||||
|
+ ath79_soc = ATH79_SOC_AR9344;
|
||||||
|
+ chip = "9344";
|
||||||
|
+ rev = id & AR934X_REV_ID_REVISION_MASK;
|
||||||
|
+ break;
|
||||||
|
+
|
||||||
|
default:
|
||||||
|
panic("ath79: unknown SoC, id:0x%08x", id);
|
||||||
|
}
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
@@ -271,6 +271,8 @@
|
||||||
|
|
||||||
|
#define AR724X_REV_ID_REVISION_MASK 0x3
|
||||||
|
|
||||||
|
+#define AR934X_REV_ID_REVISION_MASK 0xf
|
||||||
|
+
|
||||||
|
/*
|
||||||
|
* SPI block
|
||||||
|
*/
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/ath79.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
|
||||||
|
@@ -29,6 +29,9 @@ enum ath79_soc_type {
|
||||||
|
ATH79_SOC_AR9132,
|
||||||
|
ATH79_SOC_AR9330,
|
||||||
|
ATH79_SOC_AR9331,
|
||||||
|
+ ATH79_SOC_AR9341,
|
||||||
|
+ ATH79_SOC_AR9342,
|
||||||
|
+ ATH79_SOC_AR9344,
|
||||||
|
};
|
||||||
|
|
||||||
|
extern enum ath79_soc_type ath79_soc;
|
||||||
|
@@ -75,6 +78,26 @@ static inline int soc_is_ar933x(void)
|
||||||
|
ath79_soc == ATH79_SOC_AR9331);
|
||||||
|
}
|
||||||
|
|
||||||
|
+static inline int soc_is_ar9341(void)
|
||||||
|
+{
|
||||||
|
+ return (ath79_soc == ATH79_SOC_AR9341);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static inline int soc_is_ar9342(void)
|
||||||
|
+{
|
||||||
|
+ return (ath79_soc == ATH79_SOC_AR9342);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static inline int soc_is_ar9344(void)
|
||||||
|
+{
|
||||||
|
+ return (ath79_soc == ATH79_SOC_AR9344);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static inline int soc_is_ar934x(void)
|
||||||
|
+{
|
||||||
|
+ return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
extern void __iomem *ath79_ddr_base;
|
||||||
|
extern void __iomem *ath79_pll_base;
|
||||||
|
extern void __iomem *ath79_reset_base;
|
||||||
|
|
@ -0,0 +1,194 @@
|
||||||
|
From 783addfa256e79892f889e95ec5cda34f4e91eb7 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Fri, 9 Dec 2011 20:36:32 +0100
|
||||||
|
Subject: [PATCH 24/35] MIPS: ath79: add clock initialization code for AR934X
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
|
||||||
|
---
|
||||||
|
arch/mips/ath79/clock.c | 81 ++++++++++++++++++++++++
|
||||||
|
arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 53 +++++++++++++++
|
||||||
|
2 files changed, 134 insertions(+), 0 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/clock.c
|
||||||
|
+++ b/arch/mips/ath79/clock.c
|
||||||
|
@@ -1,8 +1,11 @@
|
||||||
|
/*
|
||||||
|
* Atheros AR71XX/AR724X/AR913X common routines
|
||||||
|
*
|
||||||
|
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
|
||||||
|
* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
*
|
||||||
|
+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
|
||||||
|
+ *
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License version 2 as published
|
||||||
|
* by the Free Software Foundation.
|
||||||
|
@@ -163,6 +166,82 @@ static void __init ar933x_clocks_init(vo
|
||||||
|
ath79_uart_clk.rate = ath79_ref_clk.rate;
|
||||||
|
}
|
||||||
|
|
||||||
|
+static void __init ar934x_clocks_init(void)
|
||||||
|
+{
|
||||||
|
+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
|
||||||
|
+ u32 cpu_pll, ddr_pll;
|
||||||
|
+ u32 bootstrap;
|
||||||
|
+
|
||||||
|
+ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
|
||||||
|
+ if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
|
||||||
|
+ ath79_ref_clk.rate = 40 * 1000 * 1000;
|
||||||
|
+ else
|
||||||
|
+ ath79_ref_clk.rate = 25 * 1000 * 1000;
|
||||||
|
+
|
||||||
|
+ pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
|
||||||
|
+ out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
|
||||||
|
+ AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
|
||||||
|
+ ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
|
||||||
|
+ AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
|
||||||
|
+ nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
|
||||||
|
+ AR934X_PLL_CPU_CONFIG_NINT_MASK;
|
||||||
|
+ frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
|
||||||
|
+ AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
|
||||||
|
+
|
||||||
|
+ cpu_pll = nint * ath79_ref_clk.rate / ref_div;
|
||||||
|
+ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6));
|
||||||
|
+ cpu_pll /= (1 << out_div);
|
||||||
|
+
|
||||||
|
+ pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
|
||||||
|
+ out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
|
||||||
|
+ AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
|
||||||
|
+ ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
|
||||||
|
+ AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
|
||||||
|
+ nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
|
||||||
|
+ AR934X_PLL_DDR_CONFIG_NINT_MASK;
|
||||||
|
+ frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
|
||||||
|
+ AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
|
||||||
|
+
|
||||||
|
+ ddr_pll = nint * ath79_ref_clk.rate / ref_div;
|
||||||
|
+ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10));
|
||||||
|
+ ddr_pll /= (1 << out_div);
|
||||||
|
+
|
||||||
|
+ clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
|
||||||
|
+
|
||||||
|
+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
|
||||||
|
+ AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
|
||||||
|
+
|
||||||
|
+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
|
||||||
|
+ ath79_cpu_clk.rate = ath79_ref_clk.rate;
|
||||||
|
+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
|
||||||
|
+ ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
|
||||||
|
+ else
|
||||||
|
+ ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
|
||||||
|
+
|
||||||
|
+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
|
||||||
|
+ AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
|
||||||
|
+
|
||||||
|
+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
|
||||||
|
+ ath79_ddr_clk.rate = ath79_ref_clk.rate;
|
||||||
|
+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
|
||||||
|
+ ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
|
||||||
|
+ else
|
||||||
|
+ ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
|
||||||
|
+
|
||||||
|
+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
|
||||||
|
+ AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
|
||||||
|
+
|
||||||
|
+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
|
||||||
|
+ ath79_ahb_clk.rate = ath79_ref_clk.rate;
|
||||||
|
+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
|
||||||
|
+ ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
|
||||||
|
+ else
|
||||||
|
+ ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
|
||||||
|
+
|
||||||
|
+ ath79_wdt_clk.rate = ath79_ref_clk.rate;
|
||||||
|
+ ath79_uart_clk.rate = ath79_ref_clk.rate;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
void __init ath79_clocks_init(void)
|
||||||
|
{
|
||||||
|
if (soc_is_ar71xx())
|
||||||
|
@@ -173,6 +252,8 @@ void __init ath79_clocks_init(void)
|
||||||
|
ar913x_clocks_init();
|
||||||
|
else if (soc_is_ar933x())
|
||||||
|
ar933x_clocks_init();
|
||||||
|
+ else if (soc_is_ar934x())
|
||||||
|
+ ar934x_clocks_init();
|
||||||
|
else
|
||||||
|
BUG();
|
||||||
|
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
@@ -151,6 +151,41 @@
|
||||||
|
#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
|
||||||
|
#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
|
||||||
|
|
||||||
|
+#define AR934X_PLL_CPU_CONFIG_REG 0x00
|
||||||
|
+#define AR934X_PLL_DDR_CONFIG_REG 0x04
|
||||||
|
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
|
||||||
|
+
|
||||||
|
+#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
|
||||||
|
+#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
|
||||||
|
+#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6
|
||||||
|
+#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
|
||||||
|
+#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
|
||||||
|
+#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
|
||||||
|
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
|
||||||
|
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
|
||||||
|
+
|
||||||
|
+#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
|
||||||
|
+#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
|
||||||
|
+#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10
|
||||||
|
+#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
|
||||||
|
+#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
|
||||||
|
+#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
|
||||||
|
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
|
||||||
|
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
|
||||||
|
+
|
||||||
|
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
|
||||||
|
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
|
||||||
|
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
|
||||||
|
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
|
||||||
|
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
|
||||||
|
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
|
||||||
|
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
|
||||||
|
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
|
||||||
|
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
|
||||||
|
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
|
||||||
|
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
|
||||||
|
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
|
||||||
|
+
|
||||||
|
/*
|
||||||
|
* USB_CONFIG block
|
||||||
|
*/
|
||||||
|
@@ -186,6 +221,8 @@
|
||||||
|
#define AR933X_RESET_REG_RESET_MODULE 0x1c
|
||||||
|
#define AR933X_RESET_REG_BOOTSTRAP 0xac
|
||||||
|
|
||||||
|
+#define AR934X_RESET_REG_BOOTSTRAP 0xb0
|
||||||
|
+
|
||||||
|
#define MISC_INT_ETHSW BIT(12)
|
||||||
|
#define MISC_INT_TIMER4 BIT(10)
|
||||||
|
#define MISC_INT_TIMER3 BIT(9)
|
||||||
|
@@ -242,6 +279,22 @@
|
||||||
|
|
||||||
|
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
|
||||||
|
|
||||||
|
+#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
|
||||||
|
+#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
|
||||||
|
+#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
|
||||||
|
+#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
|
||||||
|
+#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
|
||||||
|
+#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
|
||||||
|
+#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
|
||||||
|
+#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
|
||||||
|
+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
|
||||||
|
+#define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
|
||||||
|
+#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
|
||||||
|
+#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
|
||||||
|
+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
|
||||||
|
+#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
|
||||||
|
+#define AR934X_BOOTSTRAP_DDR1 BIT(0)
|
||||||
|
+
|
||||||
|
#define REV_ID_MAJOR_MASK 0xfff0
|
||||||
|
#define REV_ID_MAJOR_AR71XX 0x00a0
|
||||||
|
#define REV_ID_MAJOR_AR913X 0x00b0
|
||||||
|
|
@ -0,0 +1,98 @@
|
||||||
|
From c01b6005cfa2d762c2de33d5be2e82f91afaa66f Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Fri, 9 Dec 2011 20:53:47 +0100
|
||||||
|
Subject: [PATCH 25/35] MIPS: ath79: add GPIO support code for AR934X
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
|
||||||
|
---
|
||||||
|
arch/mips/ath79/gpio.c | 47 +++++++++++++++++++++++-
|
||||||
|
arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
|
||||||
|
2 files changed, 47 insertions(+), 1 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/gpio.c
|
||||||
|
+++ b/arch/mips/ath79/gpio.c
|
||||||
|
@@ -1,9 +1,12 @@
|
||||||
|
/*
|
||||||
|
* Atheros AR71XX/AR724X/AR913X GPIO API support
|
||||||
|
*
|
||||||
|
- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
|
||||||
|
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||||
|
*
|
||||||
|
+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
|
||||||
|
+ *
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License version 2 as published
|
||||||
|
* by the Free Software Foundation.
|
||||||
|
@@ -89,6 +92,42 @@ static int ath79_gpio_direction_output(s
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
+static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
||||||
|
+{
|
||||||
|
+ void __iomem *base = ath79_gpio_base;
|
||||||
|
+ unsigned long flags;
|
||||||
|
+
|
||||||
|
+ spin_lock_irqsave(&ath79_gpio_lock, flags);
|
||||||
|
+
|
||||||
|
+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
|
||||||
|
+ base + AR71XX_GPIO_REG_OE);
|
||||||
|
+
|
||||||
|
+ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
|
||||||
|
+ int value)
|
||||||
|
+{
|
||||||
|
+ void __iomem *base = ath79_gpio_base;
|
||||||
|
+ unsigned long flags;
|
||||||
|
+
|
||||||
|
+ spin_lock_irqsave(&ath79_gpio_lock, flags);
|
||||||
|
+
|
||||||
|
+ if (value)
|
||||||
|
+ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
|
||||||
|
+ else
|
||||||
|
+ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
|
||||||
|
+
|
||||||
|
+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
|
||||||
|
+ base + AR71XX_GPIO_REG_OE);
|
||||||
|
+
|
||||||
|
+ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static struct gpio_chip ath79_gpio_chip = {
|
||||||
|
.label = "ath79",
|
||||||
|
.get = ath79_gpio_get_value,
|
||||||
|
@@ -155,11 +194,17 @@ void __init ath79_gpio_init(void)
|
||||||
|
ath79_gpio_count = AR913X_GPIO_COUNT;
|
||||||
|
else if (soc_is_ar933x())
|
||||||
|
ath79_gpio_count = AR933X_GPIO_COUNT;
|
||||||
|
+ else if (soc_is_ar934x())
|
||||||
|
+ ath79_gpio_count = AR934X_GPIO_COUNT;
|
||||||
|
else
|
||||||
|
BUG();
|
||||||
|
|
||||||
|
ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
|
||||||
|
ath79_gpio_chip.ngpio = ath79_gpio_count;
|
||||||
|
+ if (soc_is_ar934x()) {
|
||||||
|
+ ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
|
||||||
|
+ ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
|
||||||
|
+ }
|
||||||
|
|
||||||
|
err = gpiochip_add(&ath79_gpio_chip);
|
||||||
|
if (err)
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
@@ -367,5 +367,6 @@
|
||||||
|
#define AR724X_GPIO_COUNT 18
|
||||||
|
#define AR913X_GPIO_COUNT 22
|
||||||
|
#define AR933X_GPIO_COUNT 30
|
||||||
|
+#define AR934X_GPIO_COUNT 23
|
||||||
|
|
||||||
|
#endif /* __ASM_MACH_AR71XX_REGS_H */
|
||||||
|
|
@ -0,0 +1,154 @@
|
||||||
|
From e69d89040d4884ea4069352338f555694e65fe70 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Fri, 9 Dec 2011 21:30:03 +0100
|
||||||
|
Subject: [PATCH 26/35] MIPS: ath79: rework IP2/IP3 interrupt handling
|
||||||
|
|
||||||
|
The current implementation assumes that flushing the
|
||||||
|
DDR writeback buffer is required for IP2/IP3 interrupts,
|
||||||
|
however this is not true for all SoCs.
|
||||||
|
|
||||||
|
Use SoC specific IP2/IP3 handlers instead of flushing
|
||||||
|
the buffers in the dispatcher code.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
|
||||||
|
---
|
||||||
|
arch/mips/ath79/irq.c | 92 ++++++++++++++++++++++++++++++++++++++-----------
|
||||||
|
1 files changed, 72 insertions(+), 20 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/irq.c
|
||||||
|
+++ b/arch/mips/ath79/irq.c
|
||||||
|
@@ -1,7 +1,7 @@
|
||||||
|
/*
|
||||||
|
* Atheros AR71xx/AR724x/AR913x specific interrupt handling
|
||||||
|
*
|
||||||
|
- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||||
|
*
|
||||||
|
* Parts of this file are based on Atheros' 2.6.15 BSP
|
||||||
|
@@ -23,8 +23,8 @@
|
||||||
|
#include <asm/mach-ath79/ar71xx_regs.h>
|
||||||
|
#include "common.h"
|
||||||
|
|
||||||
|
-static unsigned int ath79_ip2_flush_reg;
|
||||||
|
-static unsigned int ath79_ip3_flush_reg;
|
||||||
|
+static void (*ath79_ip2_handler)(void);
|
||||||
|
+static void (*ath79_ip3_handler)(void);
|
||||||
|
|
||||||
|
static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||||
|
{
|
||||||
|
@@ -152,10 +152,8 @@ asmlinkage void plat_irq_dispatch(void)
|
||||||
|
if (pending & STATUSF_IP7)
|
||||||
|
do_IRQ(ATH79_CPU_IRQ_TIMER);
|
||||||
|
|
||||||
|
- else if (pending & STATUSF_IP2) {
|
||||||
|
- ath79_ddr_wb_flush(ath79_ip2_flush_reg);
|
||||||
|
- do_IRQ(ATH79_CPU_IRQ_IP2);
|
||||||
|
- }
|
||||||
|
+ else if (pending & STATUSF_IP2)
|
||||||
|
+ ath79_ip2_handler();
|
||||||
|
|
||||||
|
else if (pending & STATUSF_IP4)
|
||||||
|
do_IRQ(ATH79_CPU_IRQ_GE0);
|
||||||
|
@@ -163,10 +161,8 @@ asmlinkage void plat_irq_dispatch(void)
|
||||||
|
else if (pending & STATUSF_IP5)
|
||||||
|
do_IRQ(ATH79_CPU_IRQ_GE1);
|
||||||
|
|
||||||
|
- else if (pending & STATUSF_IP3) {
|
||||||
|
- ath79_ddr_wb_flush(ath79_ip3_flush_reg);
|
||||||
|
- do_IRQ(ATH79_CPU_IRQ_USB);
|
||||||
|
- }
|
||||||
|
+ else if (pending & STATUSF_IP3)
|
||||||
|
+ ath79_ip3_handler();
|
||||||
|
|
||||||
|
else if (pending & STATUSF_IP6)
|
||||||
|
do_IRQ(ATH79_CPU_IRQ_MISC);
|
||||||
|
@@ -175,22 +171,78 @@ asmlinkage void plat_irq_dispatch(void)
|
||||||
|
spurious_interrupt();
|
||||||
|
}
|
||||||
|
|
||||||
|
+/*
|
||||||
|
+ * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
|
||||||
|
+ * these devices typically allocate coherent DMA memory, however the
|
||||||
|
+ * DMA controller may still have some unsynchronized data in the FIFO.
|
||||||
|
+ * Issue a flush in the handlers to ensure that the driver sees
|
||||||
|
+ * the update.
|
||||||
|
+ */
|
||||||
|
+static void ar71xx_ip2_handler(void)
|
||||||
|
+{
|
||||||
|
+ ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
|
||||||
|
+ do_IRQ(ATH79_CPU_IRQ_IP2);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void ar724x_ip2_handler(void)
|
||||||
|
+{
|
||||||
|
+ ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE);
|
||||||
|
+ do_IRQ(ATH79_CPU_IRQ_IP2);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void ar913x_ip2_handler(void)
|
||||||
|
+{
|
||||||
|
+ ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC);
|
||||||
|
+ do_IRQ(ATH79_CPU_IRQ_IP2);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void ar933x_ip2_handler(void)
|
||||||
|
+{
|
||||||
|
+ ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC);
|
||||||
|
+ do_IRQ(ATH79_CPU_IRQ_IP2);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void ar71xx_ip3_handler(void)
|
||||||
|
+{
|
||||||
|
+ ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
|
||||||
|
+ do_IRQ(ATH79_CPU_IRQ_USB);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void ar724x_ip3_handler(void)
|
||||||
|
+{
|
||||||
|
+ ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB);
|
||||||
|
+ do_IRQ(ATH79_CPU_IRQ_USB);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void ar913x_ip3_handler(void)
|
||||||
|
+{
|
||||||
|
+ ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB);
|
||||||
|
+ do_IRQ(ATH79_CPU_IRQ_USB);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void ar933x_ip3_handler(void)
|
||||||
|
+{
|
||||||
|
+ ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB);
|
||||||
|
+ do_IRQ(ATH79_CPU_IRQ_USB);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
void __init arch_init_irq(void)
|
||||||
|
{
|
||||||
|
if (soc_is_ar71xx()) {
|
||||||
|
- ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI;
|
||||||
|
- ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB;
|
||||||
|
+ ath79_ip2_handler = ar71xx_ip2_handler;
|
||||||
|
+ ath79_ip3_handler = ar71xx_ip3_handler;
|
||||||
|
} else if (soc_is_ar724x()) {
|
||||||
|
- ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE;
|
||||||
|
- ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB;
|
||||||
|
+ ath79_ip2_handler = ar724x_ip2_handler;
|
||||||
|
+ ath79_ip3_handler = ar724x_ip3_handler;
|
||||||
|
} else if (soc_is_ar913x()) {
|
||||||
|
- ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
|
||||||
|
- ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
|
||||||
|
+ ath79_ip2_handler = ar913x_ip2_handler;
|
||||||
|
+ ath79_ip3_handler = ar913x_ip3_handler;
|
||||||
|
} else if (soc_is_ar933x()) {
|
||||||
|
- ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC;
|
||||||
|
- ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB;
|
||||||
|
- } else
|
||||||
|
+ ath79_ip2_handler = ar933x_ip2_handler;
|
||||||
|
+ ath79_ip3_handler = ar933x_ip3_handler;
|
||||||
|
+ } else {
|
||||||
|
BUG();
|
||||||
|
+ }
|
||||||
|
|
||||||
|
cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
|
||||||
|
mips_cpu_irq_init();
|
||||||
|
|
@ -0,0 +1,190 @@
|
||||||
|
From 9db6021011556948d2d28d6957cee451bc2985aa Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Fri, 9 Dec 2011 21:59:50 +0100
|
||||||
|
Subject: [PATCH 27/35] MIPS: ath79: add IRQ handling code for AR934X
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
|
||||||
|
---
|
||||||
|
arch/mips/ath79/irq.c | 55 +++++++++++++++++++++++-
|
||||||
|
arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 25 +++++++++++
|
||||||
|
arch/mips/include/asm/mach-ath79/irq.h | 6 ++-
|
||||||
|
3 files changed, 83 insertions(+), 3 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/irq.c
|
||||||
|
+++ b/arch/mips/ath79/irq.c
|
||||||
|
@@ -1,10 +1,11 @@
|
||||||
|
/*
|
||||||
|
* Atheros AR71xx/AR724x/AR913x specific interrupt handling
|
||||||
|
*
|
||||||
|
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
|
||||||
|
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||||
|
*
|
||||||
|
- * Parts of this file are based on Atheros' 2.6.15 BSP
|
||||||
|
+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License version 2 as published
|
||||||
|
@@ -129,7 +130,7 @@ static void __init ath79_misc_irq_init(v
|
||||||
|
|
||||||
|
if (soc_is_ar71xx() || soc_is_ar913x())
|
||||||
|
ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
|
||||||
|
- else if (soc_is_ar724x() || soc_is_ar933x())
|
||||||
|
+ else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x())
|
||||||
|
ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
|
||||||
|
else
|
||||||
|
BUG();
|
||||||
|
@@ -143,6 +144,39 @@ static void __init ath79_misc_irq_init(v
|
||||||
|
irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
|
||||||
|
}
|
||||||
|
|
||||||
|
+static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
|
||||||
|
+{
|
||||||
|
+ u32 status;
|
||||||
|
+
|
||||||
|
+ disable_irq_nosync(irq);
|
||||||
|
+
|
||||||
|
+ status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
|
||||||
|
+
|
||||||
|
+ if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
|
||||||
|
+ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_PCIE);
|
||||||
|
+ generic_handle_irq(ATH79_IP2_IRQ(0));
|
||||||
|
+ } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
|
||||||
|
+ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_WMAC);
|
||||||
|
+ generic_handle_irq(ATH79_IP2_IRQ(1));
|
||||||
|
+ } else {
|
||||||
|
+ spurious_interrupt();
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ enable_irq(irq);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void ar934x_ip2_irq_init(void)
|
||||||
|
+{
|
||||||
|
+ int i;
|
||||||
|
+
|
||||||
|
+ for (i = ATH79_IP2_IRQ_BASE;
|
||||||
|
+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
|
||||||
|
+ irq_set_chip_and_handler(i, &dummy_irq_chip,
|
||||||
|
+ handle_level_irq);
|
||||||
|
+
|
||||||
|
+ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
asmlinkage void plat_irq_dispatch(void)
|
||||||
|
{
|
||||||
|
unsigned long pending;
|
||||||
|
@@ -202,6 +236,11 @@ static void ar933x_ip2_handler(void)
|
||||||
|
do_IRQ(ATH79_CPU_IRQ_IP2);
|
||||||
|
}
|
||||||
|
|
||||||
|
+static void ar934x_ip2_handler(void)
|
||||||
|
+{
|
||||||
|
+ do_IRQ(ATH79_CPU_IRQ_IP2);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static void ar71xx_ip3_handler(void)
|
||||||
|
{
|
||||||
|
ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
|
||||||
|
@@ -226,6 +265,12 @@ static void ar933x_ip3_handler(void)
|
||||||
|
do_IRQ(ATH79_CPU_IRQ_USB);
|
||||||
|
}
|
||||||
|
|
||||||
|
+static void ar934x_ip3_handler(void)
|
||||||
|
+{
|
||||||
|
+ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB);
|
||||||
|
+ do_IRQ(ATH79_CPU_IRQ_USB);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
void __init arch_init_irq(void)
|
||||||
|
{
|
||||||
|
if (soc_is_ar71xx()) {
|
||||||
|
@@ -240,6 +285,9 @@ void __init arch_init_irq(void)
|
||||||
|
} else if (soc_is_ar933x()) {
|
||||||
|
ath79_ip2_handler = ar933x_ip2_handler;
|
||||||
|
ath79_ip3_handler = ar933x_ip3_handler;
|
||||||
|
+ } else if (soc_is_ar934x()) {
|
||||||
|
+ ath79_ip2_handler = ar934x_ip2_handler;
|
||||||
|
+ ath79_ip3_handler = ar934x_ip3_handler;
|
||||||
|
} else {
|
||||||
|
BUG();
|
||||||
|
}
|
||||||
|
@@ -247,4 +295,7 @@ void __init arch_init_irq(void)
|
||||||
|
cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
|
||||||
|
mips_cpu_irq_init();
|
||||||
|
ath79_misc_irq_init();
|
||||||
|
+
|
||||||
|
+ if (soc_is_ar934x())
|
||||||
|
+ ar934x_ip2_irq_init();
|
||||||
|
}
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
@@ -92,6 +92,12 @@
|
||||||
|
#define AR933X_DDR_REG_FLUSH_USB 0x84
|
||||||
|
#define AR933X_DDR_REG_FLUSH_WMAC 0x88
|
||||||
|
|
||||||
|
+#define AR934X_DDR_REG_FLUSH_GE0 0x9c
|
||||||
|
+#define AR934X_DDR_REG_FLUSH_GE1 0xa0
|
||||||
|
+#define AR934X_DDR_REG_FLUSH_USB 0xa4
|
||||||
|
+#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
|
||||||
|
+#define AR934X_DDR_REG_FLUSH_WMAC 0xac
|
||||||
|
+
|
||||||
|
/*
|
||||||
|
* PLL block
|
||||||
|
*/
|
||||||
|
@@ -222,6 +228,7 @@
|
||||||
|
#define AR933X_RESET_REG_BOOTSTRAP 0xac
|
||||||
|
|
||||||
|
#define AR934X_RESET_REG_BOOTSTRAP 0xb0
|
||||||
|
+#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
|
||||||
|
|
||||||
|
#define MISC_INT_ETHSW BIT(12)
|
||||||
|
#define MISC_INT_TIMER4 BIT(10)
|
||||||
|
@@ -295,6 +302,24 @@
|
||||||
|
#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
|
||||||
|
#define AR934X_BOOTSTRAP_DDR1 BIT(0)
|
||||||
|
|
||||||
|
+#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
|
||||||
|
+#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
|
||||||
|
+#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
|
||||||
|
+#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
|
||||||
|
+#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
|
||||||
|
+#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
|
||||||
|
+#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
|
||||||
|
+#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
|
||||||
|
+#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
|
||||||
|
+#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
|
||||||
|
+ (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
|
||||||
|
+ AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
|
||||||
|
+
|
||||||
|
+#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
|
||||||
|
+ (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
|
||||||
|
+ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
|
||||||
|
+ AR934X_PCIE_WMAC_INT_PCIE_RC3)
|
||||||
|
+
|
||||||
|
#define REV_ID_MAJOR_MASK 0xfff0
|
||||||
|
#define REV_ID_MAJOR_AR71XX 0x00a0
|
||||||
|
#define REV_ID_MAJOR_AR913X 0x00b0
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/irq.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/irq.h
|
||||||
|
@@ -10,7 +10,7 @@
|
||||||
|
#define __ASM_MACH_ATH79_IRQ_H
|
||||||
|
|
||||||
|
#define MIPS_CPU_IRQ_BASE 0
|
||||||
|
-#define NR_IRQS 46
|
||||||
|
+#define NR_IRQS 48
|
||||||
|
|
||||||
|
#define ATH79_MISC_IRQ_BASE 8
|
||||||
|
#define ATH79_MISC_IRQ_COUNT 32
|
||||||
|
@@ -19,6 +19,10 @@
|
||||||
|
#define ATH79_PCI_IRQ_COUNT 6
|
||||||
|
#define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x))
|
||||||
|
|
||||||
|
+#define ATH79_IP2_IRQ_BASE (ATH79_PCI_IRQ_BASE + ATH79_PCI_IRQ_COUNT)
|
||||||
|
+#define ATH79_IP2_IRQ_COUNT 2
|
||||||
|
+#define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x))
|
||||||
|
+
|
||||||
|
#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
|
||||||
|
#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
|
||||||
|
#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
|
||||||
|
|
@ -0,0 +1,56 @@
|
||||||
|
From da0f20f8a99de9193fc484a25d1f9edc913c98fd Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Sat, 10 Dec 2011 20:09:39 +0100
|
||||||
|
Subject: [PATCH 28/35] MIPS: ath79: add AR934X specific glue to ath79_device_reset_{clear,set}
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
|
||||||
|
---
|
||||||
|
arch/mips/ath79/common.c | 9 ++++++++-
|
||||||
|
arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
|
||||||
|
2 files changed, 9 insertions(+), 1 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/common.c
|
||||||
|
+++ b/arch/mips/ath79/common.c
|
||||||
|
@@ -1,9 +1,12 @@
|
||||||
|
/*
|
||||||
|
* Atheros AR71XX/AR724X/AR913X common routines
|
||||||
|
*
|
||||||
|
- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
|
||||||
|
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||||
|
*
|
||||||
|
+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
|
||||||
|
+ *
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License version 2 as published
|
||||||
|
* by the Free Software Foundation.
|
||||||
|
@@ -67,6 +70,8 @@ void ath79_device_reset_set(u32 mask)
|
||||||
|
reg = AR913X_RESET_REG_RESET_MODULE;
|
||||||
|
else if (soc_is_ar933x())
|
||||||
|
reg = AR933X_RESET_REG_RESET_MODULE;
|
||||||
|
+ else if (soc_is_ar934x())
|
||||||
|
+ reg = AR934X_RESET_REG_RESET_MODULE;
|
||||||
|
else
|
||||||
|
BUG();
|
||||||
|
|
||||||
|
@@ -91,6 +96,8 @@ void ath79_device_reset_clear(u32 mask)
|
||||||
|
reg = AR913X_RESET_REG_RESET_MODULE;
|
||||||
|
else if (soc_is_ar933x())
|
||||||
|
reg = AR933X_RESET_REG_RESET_MODULE;
|
||||||
|
+ else if (soc_is_ar934x())
|
||||||
|
+ reg = AR934X_RESET_REG_RESET_MODULE;
|
||||||
|
else
|
||||||
|
BUG();
|
||||||
|
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
@@ -227,6 +227,7 @@
|
||||||
|
#define AR933X_RESET_REG_RESET_MODULE 0x1c
|
||||||
|
#define AR933X_RESET_REG_BOOTSTRAP 0xac
|
||||||
|
|
||||||
|
+#define AR934X_RESET_REG_RESET_MODULE 0x1c
|
||||||
|
#define AR934X_RESET_REG_BOOTSTRAP 0xb0
|
||||||
|
#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
|
||||||
|
|
||||||
|
|
@ -0,0 +1,23 @@
|
||||||
|
From 6b6803a249a27aa708bc5f24aa15270e30f3de61 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Sat, 10 Dec 2011 19:55:05 +0100
|
||||||
|
Subject: [PATCH 29/35] MIPS: ath79: register UART device for AR934X SoCs
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
|
||||||
|
---
|
||||||
|
arch/mips/ath79/dev-common.c | 3 ++-
|
||||||
|
1 files changed, 2 insertions(+), 1 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/dev-common.c
|
||||||
|
+++ b/arch/mips/ath79/dev-common.c
|
||||||
|
@@ -89,7 +89,8 @@ void __init ath79_register_uart(void)
|
||||||
|
|
||||||
|
if (soc_is_ar71xx() ||
|
||||||
|
soc_is_ar724x() ||
|
||||||
|
- soc_is_ar913x()) {
|
||||||
|
+ soc_is_ar913x() ||
|
||||||
|
+ soc_is_ar934x()) {
|
||||||
|
ath79_uart_data[0].uartclk = clk_get_rate(clk);
|
||||||
|
platform_device_register(&ath79_uart_device);
|
||||||
|
} else if (soc_is_ar933x()) {
|
||||||
|
|
@ -0,0 +1,112 @@
|
||||||
|
From 58b69cf52387a7351ec13b52d3d6a495fe611c29 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Fri, 9 Dec 2011 22:07:23 +0100
|
||||||
|
Subject: [PATCH 30/35] MIPS: ath79: add WMAC registration code for AR934X
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
|
||||||
|
---
|
||||||
|
arch/mips/ath79/Kconfig | 2 +-
|
||||||
|
arch/mips/ath79/dev-wmac.c | 30 ++++++++++++++++++++++-
|
||||||
|
arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 ++
|
||||||
|
3 files changed, 32 insertions(+), 3 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/Kconfig
|
||||||
|
+++ b/arch/mips/ath79/Kconfig
|
||||||
|
@@ -86,7 +86,7 @@ config ATH79_DEV_USB
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
config ATH79_DEV_WMAC
|
||||||
|
- depends on (SOC_AR913X || SOC_AR933X)
|
||||||
|
+ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X)
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
endif
|
||||||
|
--- a/arch/mips/ath79/dev-wmac.c
|
||||||
|
+++ b/arch/mips/ath79/dev-wmac.c
|
||||||
|
@@ -1,9 +1,12 @@
|
||||||
|
/*
|
||||||
|
* Atheros AR913X/AR933X SoC built-in WMAC device support
|
||||||
|
*
|
||||||
|
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
|
||||||
|
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||||
|
*
|
||||||
|
+ * Parts of this file are based on Atheros 2.6.15/2.6.31 BSP
|
||||||
|
+ *
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License version 2 as published
|
||||||
|
* by the Free Software Foundation.
|
||||||
|
@@ -26,8 +29,7 @@ static struct resource ath79_wmac_resour
|
||||||
|
/* .start and .end fields are filled dynamically */
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
}, {
|
||||||
|
- .start = ATH79_CPU_IRQ_IP2,
|
||||||
|
- .end = ATH79_CPU_IRQ_IP2,
|
||||||
|
+ /* .start and .end fields are filled dynamically */
|
||||||
|
.flags = IORESOURCE_IRQ,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
@@ -53,6 +55,8 @@ static void __init ar913x_wmac_setup(voi
|
||||||
|
|
||||||
|
ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
|
||||||
|
ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
|
||||||
|
+ ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
|
||||||
|
+ ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@@ -79,6 +83,8 @@ static void __init ar933x_wmac_setup(voi
|
||||||
|
|
||||||
|
ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
|
||||||
|
ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
|
||||||
|
+ ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
|
||||||
|
+ ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
|
||||||
|
|
||||||
|
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
|
||||||
|
if (t & AR933X_BOOTSTRAP_REF_CLK_40)
|
||||||
|
@@ -92,12 +98,32 @@ static void __init ar933x_wmac_setup(voi
|
||||||
|
ath79_wmac_data.external_reset = ar933x_wmac_reset;
|
||||||
|
}
|
||||||
|
|
||||||
|
+static void ar934x_wmac_setup(void)
|
||||||
|
+{
|
||||||
|
+ u32 t;
|
||||||
|
+
|
||||||
|
+ ath79_wmac_device.name = "ar934x_wmac";
|
||||||
|
+
|
||||||
|
+ ath79_wmac_resources[0].start = AR934X_WMAC_BASE;
|
||||||
|
+ ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1;
|
||||||
|
+ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
|
||||||
|
+ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
|
||||||
|
+
|
||||||
|
+ t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
|
||||||
|
+ if (t & AR934X_BOOTSTRAP_REF_CLK_40)
|
||||||
|
+ ath79_wmac_data.is_clk_25mhz = false;
|
||||||
|
+ else
|
||||||
|
+ ath79_wmac_data.is_clk_25mhz = true;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
void __init ath79_register_wmac(u8 *cal_data)
|
||||||
|
{
|
||||||
|
if (soc_is_ar913x())
|
||||||
|
ar913x_wmac_setup();
|
||||||
|
else if (soc_is_ar933x())
|
||||||
|
ar933x_wmac_setup();
|
||||||
|
+ else if (soc_is_ar934x())
|
||||||
|
+ ar934x_wmac_setup();
|
||||||
|
else
|
||||||
|
BUG();
|
||||||
|
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
@@ -61,6 +61,9 @@
|
||||||
|
#define AR933X_EHCI_BASE 0x1b000000
|
||||||
|
#define AR933X_EHCI_SIZE 0x1000
|
||||||
|
|
||||||
|
+#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
|
||||||
|
+#define AR934X_WMAC_SIZE 0x20000
|
||||||
|
+
|
||||||
|
/*
|
||||||
|
* DDR_CTRL block
|
||||||
|
*/
|
||||||
|
|
@ -0,0 +1,107 @@
|
||||||
|
From 2d832612094b5592641364773c5ab2a3658f7120 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Sun, 11 Dec 2011 18:34:13 +0100
|
||||||
|
Subject: [PATCH 31/35] MIPS: ath79: add USB platform setup code for AR934X
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
|
||||||
|
---
|
||||||
|
arch/mips/ath79/dev-usb.c | 28 +++++++++++++++++++
|
||||||
|
arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 35 ++++++++++++++++++++++++
|
||||||
|
2 files changed, 63 insertions(+), 0 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/dev-usb.c
|
||||||
|
+++ b/arch/mips/ath79/dev-usb.c
|
||||||
|
@@ -180,6 +180,32 @@ static void __init ar933x_usb_setup(void
|
||||||
|
platform_device_register(&ath79_ehci_device);
|
||||||
|
}
|
||||||
|
|
||||||
|
+static void __init ar934x_usb_setup(void)
|
||||||
|
+{
|
||||||
|
+ u32 bootstrap;
|
||||||
|
+
|
||||||
|
+ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
|
||||||
|
+ if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
|
||||||
|
+ return;
|
||||||
|
+
|
||||||
|
+ ath79_device_reset_clear(AR934X_RESET_USBSUS_OVERRIDE);
|
||||||
|
+ udelay(1000);
|
||||||
|
+
|
||||||
|
+ ath79_device_reset_set(AR934X_RESET_USB_PHY);
|
||||||
|
+ udelay(1000);
|
||||||
|
+
|
||||||
|
+ ath79_device_reset_set(AR934X_RESET_USB_PHY_ANALOG);
|
||||||
|
+ udelay(1000);
|
||||||
|
+
|
||||||
|
+ ath79_device_reset_set(AR934X_RESET_USB_HOST);
|
||||||
|
+ udelay(1000);
|
||||||
|
+
|
||||||
|
+ ath79_ehci_resources[0].start = AR934X_EHCI_BASE;
|
||||||
|
+ ath79_ehci_resources[0].end = AR934X_EHCI_BASE + AR934X_EHCI_SIZE - 1;
|
||||||
|
+ ath79_ehci_device.name = "ar934x-ehci";
|
||||||
|
+ platform_device_register(&ath79_ehci_device);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
void __init ath79_register_usb(void)
|
||||||
|
{
|
||||||
|
if (soc_is_ar71xx())
|
||||||
|
@@ -192,6 +218,8 @@ void __init ath79_register_usb(void)
|
||||||
|
ar913x_usb_setup();
|
||||||
|
else if (soc_is_ar933x())
|
||||||
|
ar933x_usb_setup();
|
||||||
|
+ else if (soc_is_ar934x())
|
||||||
|
+ ar934x_usb_setup();
|
||||||
|
else
|
||||||
|
BUG();
|
||||||
|
}
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
@@ -63,6 +63,8 @@
|
||||||
|
|
||||||
|
#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
|
||||||
|
#define AR934X_WMAC_SIZE 0x20000
|
||||||
|
+#define AR934X_EHCI_BASE 0x1b000000
|
||||||
|
+#define AR934X_EHCI_SIZE 0x1000
|
||||||
|
|
||||||
|
/*
|
||||||
|
* DDR_CTRL block
|
||||||
|
@@ -288,6 +290,39 @@
|
||||||
|
#define AR933X_RESET_USB_PHY BIT(4)
|
||||||
|
#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
|
||||||
|
|
||||||
|
+#define AR934X_RESET_HOST BIT(31)
|
||||||
|
+#define AR934X_RESET_SLIC BIT(30)
|
||||||
|
+#define AR934X_RESET_HDMA BIT(29)
|
||||||
|
+#define AR934X_RESET_EXTERNAL BIT(28)
|
||||||
|
+#define AR934X_RESET_RTC BIT(27)
|
||||||
|
+#define AR934X_RESET_PCIE_EP_INT BIT(26)
|
||||||
|
+#define AR934X_RESET_CHKSUM_ACC BIT(25)
|
||||||
|
+#define AR934X_RESET_FULL_CHIP BIT(24)
|
||||||
|
+#define AR934X_RESET_GE1_MDIO BIT(23)
|
||||||
|
+#define AR934X_RESET_GE0_MDIO BIT(22)
|
||||||
|
+#define AR934X_RESET_CPU_NMI BIT(21)
|
||||||
|
+#define AR934X_RESET_CPU_COLD BIT(20)
|
||||||
|
+#define AR934X_RESET_HOST_RESET_INT BIT(19)
|
||||||
|
+#define AR934X_RESET_PCIE_EP BIT(18)
|
||||||
|
+#define AR934X_RESET_UART1 BIT(17)
|
||||||
|
+#define AR934X_RESET_DDR BIT(16)
|
||||||
|
+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
|
||||||
|
+#define AR934X_RESET_NANDF BIT(14)
|
||||||
|
+#define AR934X_RESET_GE1_MAC BIT(13)
|
||||||
|
+#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
|
||||||
|
+#define AR934X_RESET_USB_PHY_ANALOG BIT(11)
|
||||||
|
+#define AR934X_RESET_HOST_DMA_INT BIT(10)
|
||||||
|
+#define AR934X_RESET_GE0_MAC BIT(9)
|
||||||
|
+#define AR934X_RESET_ETH_SIWTCH BIT(8)
|
||||||
|
+#define AR934X_RESET_PCIE_PHY BIT(7)
|
||||||
|
+#define AR934X_RESET_PCIE BIT(6)
|
||||||
|
+#define AR934X_RESET_USB_HOST BIT(5)
|
||||||
|
+#define AR934X_RESET_USB_PHY BIT(4)
|
||||||
|
+#define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
|
||||||
|
+#define AR934X_RESET_LUT BIT(2)
|
||||||
|
+#define AR934X_RESET_MBOX BIT(1)
|
||||||
|
+#define AR934X_RESET_I2S BIT(0)
|
||||||
|
+
|
||||||
|
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
|
||||||
|
|
||||||
|
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
|
||||||
|
|
@ -0,0 +1,62 @@
|
||||||
|
From f299f36542f81f05cff7cdebb50abde202faf6df Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Sat, 17 Dec 2011 10:04:18 +0100
|
||||||
|
Subject: [PATCH 32/35] MIPS: ath79: add PCI_AR724X Kconfig symbol
|
||||||
|
|
||||||
|
The AR724X specific PCI code can be used for the
|
||||||
|
AR934X SoCs, however it can be selected only if
|
||||||
|
SOC_AR724X is set.
|
||||||
|
|
||||||
|
Introduce a new Kconfig symbol in order to be able
|
||||||
|
to use the code for AR934X as well.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
|
||||||
|
---
|
||||||
|
arch/mips/ath79/Kconfig | 4 ++++
|
||||||
|
arch/mips/include/asm/mach-ath79/pci.h | 2 +-
|
||||||
|
arch/mips/pci/Makefile | 2 +-
|
||||||
|
3 files changed, 6 insertions(+), 2 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/Kconfig
|
||||||
|
+++ b/arch/mips/ath79/Kconfig
|
||||||
|
@@ -59,6 +59,7 @@ config SOC_AR724X
|
||||||
|
select USB_ARCH_HAS_EHCI
|
||||||
|
select USB_ARCH_HAS_OHCI
|
||||||
|
select HW_HAS_PCI
|
||||||
|
+ select PCI_AR724X if PCI
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
config SOC_AR913X
|
||||||
|
@@ -73,6 +74,9 @@ config SOC_AR934X
|
||||||
|
select USB_ARCH_HAS_EHCI
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
+config PCI_AR724X
|
||||||
|
+ def_bool n
|
||||||
|
+
|
||||||
|
config ATH79_DEV_GPIO_BUTTONS
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/pci.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/pci.h
|
||||||
|
@@ -19,7 +19,7 @@ int ar71xx_pcibios_init(void);
|
||||||
|
static inline int ar71xx_pcibios_init(void) { return 0 };
|
||||||
|
#endif
|
||||||
|
|
||||||
|
-#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X)
|
||||||
|
+#if defined(CONFIG_PCI_AR724X)
|
||||||
|
int ar724x_pcibios_init(int irq);
|
||||||
|
#else
|
||||||
|
static inline int ar724x_pcibios_init(int irq) { return 0 };
|
||||||
|
--- a/arch/mips/pci/Makefile
|
||||||
|
+++ b/arch/mips/pci/Makefile
|
||||||
|
@@ -20,7 +20,7 @@ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o
|
||||||
|
ops-bcm63xx.o
|
||||||
|
obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
|
||||||
|
obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
|
||||||
|
-obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o
|
||||||
|
+obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
|
||||||
|
|
||||||
|
#
|
||||||
|
# These are still pretty much in the old state, watch, go blind.
|
||||||
|
|
@ -0,0 +1,58 @@
|
||||||
|
From e30d942814a606c5258c7adafc6bbb49836573e9 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Sat, 17 Dec 2011 10:13:08 +0100
|
||||||
|
Subject: [PATCH 33/35] MIPS: ath79: add PCI registration code for AR934X
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
|
||||||
|
---
|
||||||
|
arch/mips/ath79/Kconfig | 2 ++
|
||||||
|
arch/mips/ath79/pci.c | 13 ++++++++++++-
|
||||||
|
2 files changed, 14 insertions(+), 1 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/Kconfig
|
||||||
|
+++ b/arch/mips/ath79/Kconfig
|
||||||
|
@@ -72,6 +72,8 @@ config SOC_AR933X
|
||||||
|
|
||||||
|
config SOC_AR934X
|
||||||
|
select USB_ARCH_HAS_EHCI
|
||||||
|
+ select HW_HAS_PCI
|
||||||
|
+ select PCI_AR724X if PCI
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
config PCI_AR724X
|
||||||
|
--- a/arch/mips/ath79/pci.c
|
||||||
|
+++ b/arch/mips/ath79/pci.c
|
||||||
|
@@ -14,6 +14,7 @@
|
||||||
|
|
||||||
|
#include <linux/init.h>
|
||||||
|
#include <linux/pci.h>
|
||||||
|
+#include <asm/mach-ath79/ar71xx_regs.h>
|
||||||
|
#include <asm/mach-ath79/ath79.h>
|
||||||
|
#include <asm/mach-ath79/irq.h>
|
||||||
|
#include <asm/mach-ath79/pci.h>
|
||||||
|
@@ -57,7 +58,9 @@ int __init pcibios_map_irq(const struct
|
||||||
|
if (soc_is_ar71xx()) {
|
||||||
|
ath79_pci_irq_map = ar71xx_pci_irq_map;
|
||||||
|
ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map);
|
||||||
|
- } else if (soc_is_ar724x()) {
|
||||||
|
+ } else if (soc_is_ar724x() ||
|
||||||
|
+ soc_is_ar9342() ||
|
||||||
|
+ soc_is_ar9344()) {
|
||||||
|
ath79_pci_irq_map = ar724x_pci_irq_map;
|
||||||
|
ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
|
||||||
|
} else {
|
||||||
|
@@ -115,5 +118,13 @@ int __init ath79_register_pci(void)
|
||||||
|
if (soc_is_ar724x())
|
||||||
|
return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
|
||||||
|
|
||||||
|
+ if (soc_is_ar9342() || soc_is_ar9344()) {
|
||||||
|
+ u32 bootstrap;
|
||||||
|
+
|
||||||
|
+ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
|
||||||
|
+ if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC)
|
||||||
|
+ return ar724x_pcibios_init(ATH79_IP2_IRQ(0));
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,213 @@
|
||||||
|
From a01e8727327cf0fb6382ca8700a3a3f73d93202a Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Fri, 9 Dec 2011 22:23:02 +0100
|
||||||
|
Subject: [PATCH 34/35] MIPS: ath79: add initial support for the Atheros DB120 board
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
|
||||||
|
---
|
||||||
|
arch/mips/ath79/Kconfig | 12 +++
|
||||||
|
arch/mips/ath79/Makefile | 1 +
|
||||||
|
arch/mips/ath79/mach-db120.c | 155 ++++++++++++++++++++++++++++++++++++++++++
|
||||||
|
arch/mips/ath79/machtypes.h | 1 +
|
||||||
|
4 files changed, 169 insertions(+), 0 deletions(-)
|
||||||
|
create mode 100644 arch/mips/ath79/mach-db120.c
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/Kconfig
|
||||||
|
+++ b/arch/mips/ath79/Kconfig
|
||||||
|
@@ -26,6 +26,18 @@ config ATH79_MACH_AP81
|
||||||
|
Say 'Y' here if you want your kernel to support the
|
||||||
|
Atheros AP81 reference board.
|
||||||
|
|
||||||
|
+config ATH79_MACH_DB120
|
||||||
|
+ bool "Atheros DB120 reference board"
|
||||||
|
+ select SOC_AR934X
|
||||||
|
+ select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
+ select ATH79_DEV_LEDS_GPIO
|
||||||
|
+ select ATH79_DEV_SPI
|
||||||
|
+ select ATH79_DEV_USB
|
||||||
|
+ select ATH79_DEV_WMAC
|
||||||
|
+ help
|
||||||
|
+ Say 'Y' here if you want your kernel to support the
|
||||||
|
+ Atheros DB120 reference board.
|
||||||
|
+
|
||||||
|
config ATH79_MACH_PB44
|
||||||
|
bool "Atheros PB44 reference board"
|
||||||
|
select SOC_AR71XX
|
||||||
|
--- a/arch/mips/ath79/Makefile
|
||||||
|
+++ b/arch/mips/ath79/Makefile
|
||||||
|
@@ -28,5 +28,6 @@ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wma
|
||||||
|
#
|
||||||
|
obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
|
||||||
|
obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o
|
||||||
|
obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
|
||||||
|
obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/arch/mips/ath79/mach-db120.c
|
||||||
|
@@ -0,0 +1,155 @@
|
||||||
|
+/*
|
||||||
|
+ * Atheros DB120 reference board support
|
||||||
|
+ *
|
||||||
|
+ * Copyright (c) 2011 Qualcomm Atheros
|
||||||
|
+ * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
+ *
|
||||||
|
+ * All rights reserved.
|
||||||
|
+ *
|
||||||
|
+ * Redistribution and use in source and binary forms, with or without
|
||||||
|
+ * modification, are permitted (subject to the limitations in the
|
||||||
|
+ * disclaimer below) provided that the following conditions are met:
|
||||||
|
+ *
|
||||||
|
+ * * Redistributions of source code must retain the above copyright
|
||||||
|
+ * notice, this list of conditions and the following disclaimer.
|
||||||
|
+ *
|
||||||
|
+ * * Redistributions in binary form must reproduce the above copyright
|
||||||
|
+ * notice, this list of conditions and the following disclaimer in the
|
||||||
|
+ * documentation and/or other materials provided with the
|
||||||
|
+ * distribution.
|
||||||
|
+ *
|
||||||
|
+ * * Neither the name of Qualcomm Atheros nor the names of its
|
||||||
|
+ * contributors may be used to endorse or promote products derived
|
||||||
|
+ * from this software without specific prior written permission.
|
||||||
|
+ *
|
||||||
|
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
|
||||||
|
+ * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
|
||||||
|
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||||
|
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||||
|
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||||
|
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||||
|
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||||
|
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||||
|
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+#include <linux/pci.h>
|
||||||
|
+#include <linux/ath9k_platform.h>
|
||||||
|
+
|
||||||
|
+#include "machtypes.h"
|
||||||
|
+#include "dev-gpio-buttons.h"
|
||||||
|
+#include "dev-leds-gpio.h"
|
||||||
|
+#include "dev-spi.h"
|
||||||
|
+#include "dev-usb.h"
|
||||||
|
+#include "dev-wmac.h"
|
||||||
|
+#include "pci.h"
|
||||||
|
+
|
||||||
|
+#define DB120_GPIO_LED_WLAN_5G 12
|
||||||
|
+#define DB120_GPIO_LED_WLAN_2G 13
|
||||||
|
+#define DB120_GPIO_LED_STATUS 14
|
||||||
|
+#define DB120_GPIO_LED_WPS 15
|
||||||
|
+
|
||||||
|
+#define DB120_GPIO_BTN_WPS 16
|
||||||
|
+
|
||||||
|
+#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */
|
||||||
|
+#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL)
|
||||||
|
+
|
||||||
|
+#define DB120_WMAC_CALDATA_OFFSET 0x1000
|
||||||
|
+#define DB120_PCIE_CALDATA_OFFSET 0x5000
|
||||||
|
+
|
||||||
|
+static struct gpio_led db120_leds_gpio[] __initdata = {
|
||||||
|
+ {
|
||||||
|
+ .name = "db120:green:status",
|
||||||
|
+ .gpio = DB120_GPIO_LED_STATUS,
|
||||||
|
+ .active_low = 1,
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
+ .name = "db120:green:wps",
|
||||||
|
+ .gpio = DB120_GPIO_LED_WPS,
|
||||||
|
+ .active_low = 1,
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
+ .name = "db120:green:wlan-5g",
|
||||||
|
+ .gpio = DB120_GPIO_LED_WLAN_5G,
|
||||||
|
+ .active_low = 1,
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
+ .name = "db120:green:wlan-2g",
|
||||||
|
+ .gpio = DB120_GPIO_LED_WLAN_2G,
|
||||||
|
+ .active_low = 1,
|
||||||
|
+ },
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct gpio_keys_button db120_gpio_keys[] __initdata = {
|
||||||
|
+ {
|
||||||
|
+ .desc = "WPS button",
|
||||||
|
+ .type = EV_KEY,
|
||||||
|
+ .code = KEY_WPS_BUTTON,
|
||||||
|
+ .debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL,
|
||||||
|
+ .gpio = DB120_GPIO_BTN_WPS,
|
||||||
|
+ .active_low = 1,
|
||||||
|
+ },
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct spi_board_info db120_spi_info[] = {
|
||||||
|
+ {
|
||||||
|
+ .bus_num = 0,
|
||||||
|
+ .chip_select = 0,
|
||||||
|
+ .max_speed_hz = 25000000,
|
||||||
|
+ .modalias = "s25sl064a",
|
||||||
|
+ }
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct ath79_spi_platform_data db120_spi_data = {
|
||||||
|
+ .bus_num = 0,
|
||||||
|
+ .num_chipselect = 1,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+#ifdef CONFIG_PCI
|
||||||
|
+static struct ath9k_platform_data db120_ath9k_data;
|
||||||
|
+
|
||||||
|
+static int db120_pci_plat_dev_init(struct pci_dev *dev)
|
||||||
|
+{
|
||||||
|
+ switch (PCI_SLOT(dev->devfn)) {
|
||||||
|
+ case 0:
|
||||||
|
+ dev->dev.platform_data = &db120_ath9k_data;
|
||||||
|
+ break;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void __init db120_pci_init(u8 *eeprom)
|
||||||
|
+{
|
||||||
|
+ memcpy(db120_ath9k_data.eeprom_data, eeprom,
|
||||||
|
+ sizeof(db120_ath9k_data.eeprom_data));
|
||||||
|
+
|
||||||
|
+ ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
|
||||||
|
+ ath79_register_pci();
|
||||||
|
+}
|
||||||
|
+#else
|
||||||
|
+static inline void db120_pci_init(void) {}
|
||||||
|
+#endif /* CONFIG_PCI */
|
||||||
|
+
|
||||||
|
+static void __init db120_setup(void)
|
||||||
|
+{
|
||||||
|
+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
|
||||||
|
+
|
||||||
|
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
|
||||||
|
+ db120_leds_gpio);
|
||||||
|
+ ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
|
||||||
|
+ ARRAY_SIZE(db120_gpio_keys),
|
||||||
|
+ db120_gpio_keys);
|
||||||
|
+ ath79_register_spi(&db120_spi_data, db120_spi_info,
|
||||||
|
+ ARRAY_SIZE(db120_spi_info));
|
||||||
|
+ ath79_register_usb();
|
||||||
|
+ ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
|
||||||
|
+ db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
|
||||||
|
+ db120_setup);
|
||||||
|
--- a/arch/mips/ath79/machtypes.h
|
||||||
|
+++ b/arch/mips/ath79/machtypes.h
|
||||||
|
@@ -18,6 +18,7 @@ enum ath79_mach_type {
|
||||||
|
ATH79_MACH_GENERIC = 0,
|
||||||
|
ATH79_MACH_AP121, /* Atheros AP121 reference board */
|
||||||
|
ATH79_MACH_AP81, /* Atheros AP81 reference board */
|
||||||
|
+ ATH79_MACH_DB120, /* Atheros DB120 reference board */
|
||||||
|
ATH79_MACH_PB44, /* Atheros PB44 reference board */
|
||||||
|
ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,41 @@
|
||||||
|
From cbf8930fe259777fb746f0387bf821729061c122 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Sun, 11 Dec 2011 22:09:20 +0100
|
||||||
|
Subject: [PATCH 35/35] USB: ehci-ath79: add device_id entry for the AR934X SoCs
|
||||||
|
|
||||||
|
Also make the USB_EHCI_ATH79 selectable for the AR934X SoCs.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
|
||||||
|
Cc: Alan Stern <stern@rowland.harvard.edu>
|
||||||
|
Cc: Greg Kroah-Hartman <gregkh@suse.de>
|
||||||
|
Cc: linux-usb@vger.kernel.org
|
||||||
|
---
|
||||||
|
drivers/usb/host/Kconfig | 2 +-
|
||||||
|
drivers/usb/host/ehci-ath79.c | 4 ++++
|
||||||
|
2 files changed, 5 insertions(+), 1 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/usb/host/Kconfig
|
||||||
|
+++ b/drivers/usb/host/Kconfig
|
||||||
|
@@ -219,7 +219,7 @@ config USB_CNS3XXX_EHCI
|
||||||
|
|
||||||
|
config USB_EHCI_ATH79
|
||||||
|
bool "EHCI support for AR7XXX/AR9XXX SoCs"
|
||||||
|
- depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X)
|
||||||
|
+ depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X || SOC_AR934X)
|
||||||
|
select USB_EHCI_ROOT_HUB_TT
|
||||||
|
default y
|
||||||
|
---help---
|
||||||
|
--- a/drivers/usb/host/ehci-ath79.c
|
||||||
|
+++ b/drivers/usb/host/ehci-ath79.c
|
||||||
|
@@ -37,6 +37,10 @@ static const struct platform_device_id e
|
||||||
|
.driver_data = EHCI_ATH79_IP_V2,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
+ .name = "ar934x-ehci",
|
||||||
|
+ .driver_data = EHCI_ATH79_IP_V2,
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
/* terminating entry */
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,42 @@
|
||||||
|
From 48b7e765e6e097d20d809fadd17a4355d26ad6d5 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Wed, 11 Jan 2012 20:06:35 +0100
|
||||||
|
Subject: [PATCH 1/7] spi/ath79: add delay between SCK changes
|
||||||
|
|
||||||
|
The driver uses the "as fast as it can" approach
|
||||||
|
to drive the SCK signal. However this does not
|
||||||
|
work with certain low speed SPI chips (e.g. the
|
||||||
|
PCF2123 RTC chip). Add per-bit slowdowns in order
|
||||||
|
to be able to use the driver with such chips as
|
||||||
|
well.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
---
|
||||||
|
drivers/spi/spi-ath79.c | 8 ++++++++
|
||||||
|
1 files changed, 8 insertions(+), 0 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/spi/spi-ath79.c
|
||||||
|
+++ b/drivers/spi/spi-ath79.c
|
||||||
|
@@ -52,6 +52,12 @@ static inline struct ath79_spi *ath79_sp
|
||||||
|
return spi_master_get_devdata(spi->master);
|
||||||
|
}
|
||||||
|
|
||||||
|
+static inline void ath79_spi_delay(unsigned nsecs)
|
||||||
|
+{
|
||||||
|
+ if (nsecs)
|
||||||
|
+ ndelay(nsecs);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
|
||||||
|
{
|
||||||
|
struct ath79_spi *sp = ath79_spidev_to_sp(spi);
|
||||||
|
@@ -184,7 +190,9 @@ static u32 ath79_spi_txrx_mode0(struct s
|
||||||
|
|
||||||
|
/* setup MSB (to slave) on trailing edge */
|
||||||
|
ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
|
||||||
|
+ ath79_spi_delay(nsecs);
|
||||||
|
ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
|
||||||
|
+ ath79_spi_delay(nsecs);
|
||||||
|
|
||||||
|
word <<= 1;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
From 0ad8cbbb978bc01de08eadd3357ea188302b83ce Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Wed, 11 Jan 2012 20:33:41 +0100
|
||||||
|
Subject: [PATCH 2/7] spi/ath79: add missing HIGH->LOW SCK transition
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
---
|
||||||
|
drivers/spi/spi-ath79.c | 1 +
|
||||||
|
1 files changed, 1 insertions(+), 0 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/spi/spi-ath79.c
|
||||||
|
+++ b/drivers/spi/spi-ath79.c
|
||||||
|
@@ -193,6 +193,7 @@ static u32 ath79_spi_txrx_mode0(struct s
|
||||||
|
ath79_spi_delay(nsecs);
|
||||||
|
ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
|
||||||
|
ath79_spi_delay(nsecs);
|
||||||
|
+ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
|
||||||
|
|
||||||
|
word <<= 1;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,30 @@
|
||||||
|
From 7385ff2cb72d6a0107890760466b9564aa5204c1 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Mon, 9 Jan 2012 15:03:28 +0100
|
||||||
|
Subject: [PATCH 3/7] spi/ath79: remove superfluous chip select code
|
||||||
|
|
||||||
|
The spi_bitbang driver calls the chipselect function
|
||||||
|
of the driver from spi_bitbang_setup in order to
|
||||||
|
deselect the given SPI chip, so we don't have to
|
||||||
|
initialize the CS line here.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
---
|
||||||
|
drivers/spi/spi-ath79.c | 6 ------
|
||||||
|
1 files changed, 0 insertions(+), 6 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/spi/spi-ath79.c
|
||||||
|
+++ b/drivers/spi/spi-ath79.c
|
||||||
|
@@ -121,12 +121,6 @@ static int ath79_spi_setup_cs(struct spi
|
||||||
|
gpio_free(cdata->gpio);
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
- } else {
|
||||||
|
- if (spi->mode & SPI_CS_HIGH)
|
||||||
|
- sp->ioc_base |= AR71XX_SPI_IOC_CS0;
|
||||||
|
- else
|
||||||
|
- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
|
||||||
|
- ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
|
@ -0,0 +1,56 @@
|
||||||
|
From c5bfb0c760a5d8de7ffc3a6acfb8c782be6af1a5 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Mon, 9 Jan 2012 15:04:21 +0100
|
||||||
|
Subject: [PATCH 4/7] spi/ath79: use gpio_request_one
|
||||||
|
|
||||||
|
Use gpio_request_one() instead of multiple gpiolib calls.
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
---
|
||||||
|
drivers/spi/spi-ath79.c | 26 +++++++++++++-------------
|
||||||
|
1 files changed, 13 insertions(+), 13 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/spi/spi-ath79.c
|
||||||
|
+++ b/drivers/spi/spi-ath79.c
|
||||||
|
@@ -93,6 +93,7 @@ static int ath79_spi_setup_cs(struct spi
|
||||||
|
{
|
||||||
|
struct ath79_spi *sp = ath79_spidev_to_sp(spi);
|
||||||
|
struct ath79_spi_controller_data *cdata;
|
||||||
|
+ int status;
|
||||||
|
|
||||||
|
cdata = spi->controller_data;
|
||||||
|
if (spi->chip_select && !cdata)
|
||||||
|
@@ -108,22 +109,21 @@ static int ath79_spi_setup_cs(struct spi
|
||||||
|
/* TODO: setup speed? */
|
||||||
|
ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
|
||||||
|
|
||||||
|
+ status = 0;
|
||||||
|
if (spi->chip_select) {
|
||||||
|
- int status = 0;
|
||||||
|
+ unsigned long flags;
|
||||||
|
|
||||||
|
- status = gpio_request(cdata->gpio, dev_name(&spi->dev));
|
||||||
|
- if (status)
|
||||||
|
- return status;
|
||||||
|
-
|
||||||
|
- status = gpio_direction_output(cdata->gpio,
|
||||||
|
- spi->mode & SPI_CS_HIGH);
|
||||||
|
- if (status) {
|
||||||
|
- gpio_free(cdata->gpio);
|
||||||
|
- return status;
|
||||||
|
- }
|
||||||
|
+ flags = GPIOF_DIR_OUT;
|
||||||
|
+ if (spi->mode & SPI_CS_HIGH)
|
||||||
|
+ flags |= GPIOF_INIT_HIGH;
|
||||||
|
+ else
|
||||||
|
+ flags |= GPIOF_INIT_LOW;
|
||||||
|
+
|
||||||
|
+ status = gpio_request_one(cdata->gpio, flags,
|
||||||
|
+ dev_name(&spi->dev));
|
||||||
|
}
|
||||||
|
|
||||||
|
- return 0;
|
||||||
|
+ return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void ath79_spi_cleanup_cs(struct spi_device *spi)
|
||||||
|
|
@ -0,0 +1,98 @@
|
||||||
|
From 4518ae06e5fc953abfd9c2b66c6155fc2b2696ce Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Mon, 9 Jan 2012 15:00:46 +0100
|
||||||
|
Subject: [PATCH 5/7] spi/ath79: introduce ath79_spi_{en,dis}able helpers
|
||||||
|
|
||||||
|
---
|
||||||
|
drivers/spi/spi-ath79.c | 41 +++++++++++++++++++++++++----------------
|
||||||
|
1 files changed, 25 insertions(+), 16 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/spi/spi-ath79.c
|
||||||
|
+++ b/drivers/spi/spi-ath79.c
|
||||||
|
@@ -89,16 +89,8 @@ static void ath79_spi_chipselect(struct
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
-static int ath79_spi_setup_cs(struct spi_device *spi)
|
||||||
|
+static void ath79_spi_enable(struct ath79_spi *sp)
|
||||||
|
{
|
||||||
|
- struct ath79_spi *sp = ath79_spidev_to_sp(spi);
|
||||||
|
- struct ath79_spi_controller_data *cdata;
|
||||||
|
- int status;
|
||||||
|
-
|
||||||
|
- cdata = spi->controller_data;
|
||||||
|
- if (spi->chip_select && !cdata)
|
||||||
|
- return -EINVAL;
|
||||||
|
-
|
||||||
|
/* enable GPIO mode */
|
||||||
|
ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
|
||||||
|
|
||||||
|
@@ -108,6 +100,24 @@ static int ath79_spi_setup_cs(struct spi
|
||||||
|
|
||||||
|
/* TODO: setup speed? */
|
||||||
|
ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void ath79_spi_disable(struct ath79_spi *sp)
|
||||||
|
+{
|
||||||
|
+ /* restore CTRL register */
|
||||||
|
+ ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
|
||||||
|
+ /* disable GPIO mode */
|
||||||
|
+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int ath79_spi_setup_cs(struct spi_device *spi)
|
||||||
|
+{
|
||||||
|
+ struct ath79_spi_controller_data *cdata;
|
||||||
|
+ int status;
|
||||||
|
+
|
||||||
|
+ cdata = spi->controller_data;
|
||||||
|
+ if (spi->chip_select && !cdata)
|
||||||
|
+ return -EINVAL;
|
||||||
|
|
||||||
|
status = 0;
|
||||||
|
if (spi->chip_select) {
|
||||||
|
@@ -128,17 +138,10 @@ static int ath79_spi_setup_cs(struct spi
|
||||||
|
|
||||||
|
static void ath79_spi_cleanup_cs(struct spi_device *spi)
|
||||||
|
{
|
||||||
|
- struct ath79_spi *sp = ath79_spidev_to_sp(spi);
|
||||||
|
-
|
||||||
|
if (spi->chip_select) {
|
||||||
|
struct ath79_spi_controller_data *cdata = spi->controller_data;
|
||||||
|
gpio_free(cdata->gpio);
|
||||||
|
}
|
||||||
|
-
|
||||||
|
- /* restore CTRL register */
|
||||||
|
- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
|
||||||
|
- /* disable GPIO mode */
|
||||||
|
- ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int ath79_spi_setup(struct spi_device *spi)
|
||||||
|
@@ -242,13 +245,15 @@ static __devinit int ath79_spi_probe(str
|
||||||
|
goto err_put_master;
|
||||||
|
}
|
||||||
|
|
||||||
|
+ ath79_spi_enable(sp);
|
||||||
|
ret = spi_bitbang_start(&sp->bitbang);
|
||||||
|
if (ret)
|
||||||
|
- goto err_unmap;
|
||||||
|
+ goto err_disable;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
-err_unmap:
|
||||||
|
+err_disable:
|
||||||
|
+ ath79_spi_disable(sp);
|
||||||
|
iounmap(sp->base);
|
||||||
|
err_put_master:
|
||||||
|
platform_set_drvdata(pdev, NULL);
|
||||||
|
@@ -262,6 +267,7 @@ static __devexit int ath79_spi_remove(st
|
||||||
|
struct ath79_spi *sp = platform_get_drvdata(pdev);
|
||||||
|
|
||||||
|
spi_bitbang_stop(&sp->bitbang);
|
||||||
|
+ ath79_spi_disable(sp);
|
||||||
|
iounmap(sp->base);
|
||||||
|
platform_set_drvdata(pdev, NULL);
|
||||||
|
spi_master_put(sp->bitbang.master);
|
||||||
|
|
@ -0,0 +1,45 @@
|
||||||
|
From 1025bfbe327b3f9f7227e781c71751d5251803cb Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Wed, 11 Jan 2012 22:19:32 +0100
|
||||||
|
Subject: [PATCH 6/7] spi/ath79: add shutdown handler
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
---
|
||||||
|
drivers/spi/spi-ath79.c | 12 +++++++++++-
|
||||||
|
1 files changed, 11 insertions(+), 1 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/spi/spi-ath79.c
|
||||||
|
+++ b/drivers/spi/spi-ath79.c
|
||||||
|
@@ -262,7 +262,7 @@ err_put_master:
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
-static __devexit int ath79_spi_remove(struct platform_device *pdev)
|
||||||
|
+static void __ath79_spi_remove(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct ath79_spi *sp = platform_get_drvdata(pdev);
|
||||||
|
|
||||||
|
@@ -271,13 +271,23 @@ static __devexit int ath79_spi_remove(st
|
||||||
|
iounmap(sp->base);
|
||||||
|
platform_set_drvdata(pdev, NULL);
|
||||||
|
spi_master_put(sp->bitbang.master);
|
||||||
|
+}
|
||||||
|
|
||||||
|
+static __devexit int ath79_spi_remove(struct platform_device *pdev)
|
||||||
|
+{
|
||||||
|
+ __ath79_spi_remove(pdev);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
+static void ath79_spi_shutdown(struct platform_device *pdev)
|
||||||
|
+{
|
||||||
|
+ __ath79_spi_remove(pdev);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static struct platform_driver ath79_spi_driver = {
|
||||||
|
.probe = ath79_spi_probe,
|
||||||
|
.remove = __devexit_p(ath79_spi_remove),
|
||||||
|
+ .shutdown = ath79_spi_shutdown,
|
||||||
|
.driver = {
|
||||||
|
.name = DRV_NAME,
|
||||||
|
.owner = THIS_MODULE,
|
||||||
|
|
@ -0,0 +1,164 @@
|
||||||
|
From b875f877d06acb852342636db4c3d1e6c9fe01ba Mon Sep 17 00:00:00 2001
|
||||||
|
From: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
Date: Wed, 11 Jan 2012 22:25:11 +0100
|
||||||
|
Subject: [PATCH 7/7] spi/ath79: make chipselect logic more flexible
|
||||||
|
|
||||||
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
---
|
||||||
|
.../include/asm/mach-ath79/ath79_spi_platform.h | 8 ++-
|
||||||
|
drivers/spi/spi-ath79.c | 65 +++++++++++--------
|
||||||
|
2 files changed, 45 insertions(+), 28 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
|
||||||
|
@@ -16,8 +16,14 @@ struct ath79_spi_platform_data {
|
||||||
|
unsigned num_chipselect;
|
||||||
|
};
|
||||||
|
|
||||||
|
+enum ath79_spi_cs_type {
|
||||||
|
+ ATH79_SPI_CS_TYPE_INTERNAL,
|
||||||
|
+ ATH79_SPI_CS_TYPE_GPIO,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
struct ath79_spi_controller_data {
|
||||||
|
- unsigned gpio;
|
||||||
|
+ enum ath79_spi_cs_type cs_type;
|
||||||
|
+ unsigned cs_line;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* _ATH79_SPI_PLATFORM_H */
|
||||||
|
--- a/drivers/spi/spi-ath79.c
|
||||||
|
+++ b/drivers/spi/spi-ath79.c
|
||||||
|
@@ -30,6 +30,8 @@
|
||||||
|
|
||||||
|
#define DRV_NAME "ath79-spi"
|
||||||
|
|
||||||
|
+#define ATH79_SPI_CS_LINE_MAX 2
|
||||||
|
+
|
||||||
|
struct ath79_spi {
|
||||||
|
struct spi_bitbang bitbang;
|
||||||
|
u32 ioc_base;
|
||||||
|
@@ -62,6 +64,7 @@ static void ath79_spi_chipselect(struct
|
||||||
|
{
|
||||||
|
struct ath79_spi *sp = ath79_spidev_to_sp(spi);
|
||||||
|
int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
|
||||||
|
+ struct ath79_spi_controller_data *cdata = spi->controller_data;
|
||||||
|
|
||||||
|
if (is_active) {
|
||||||
|
/* set initial clock polarity */
|
||||||
|
@@ -73,20 +76,21 @@ static void ath79_spi_chipselect(struct
|
||||||
|
ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
|
||||||
|
}
|
||||||
|
|
||||||
|
- if (spi->chip_select) {
|
||||||
|
- struct ath79_spi_controller_data *cdata = spi->controller_data;
|
||||||
|
-
|
||||||
|
- /* SPI is normally active-low */
|
||||||
|
- gpio_set_value(cdata->gpio, cs_high);
|
||||||
|
- } else {
|
||||||
|
+ switch (cdata->cs_type) {
|
||||||
|
+ case ATH79_SPI_CS_TYPE_INTERNAL:
|
||||||
|
if (cs_high)
|
||||||
|
- sp->ioc_base |= AR71XX_SPI_IOC_CS0;
|
||||||
|
+ sp->ioc_base |= AR71XX_SPI_IOC_CS(cdata->cs_line);
|
||||||
|
else
|
||||||
|
- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
|
||||||
|
+ sp->ioc_base &= ~AR71XX_SPI_IOC_CS(cdata->cs_line);
|
||||||
|
|
||||||
|
ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
|
||||||
|
- }
|
||||||
|
+ break;
|
||||||
|
|
||||||
|
+ case ATH79_SPI_CS_TYPE_GPIO:
|
||||||
|
+ /* SPI is normally active-low */
|
||||||
|
+ gpio_set_value(cdata->cs_line, cs_high);
|
||||||
|
+ break;
|
||||||
|
+ }
|
||||||
|
}
|
||||||
|
|
||||||
|
static void ath79_spi_enable(struct ath79_spi *sp)
|
||||||
|
@@ -113,24 +117,30 @@ static void ath79_spi_disable(struct ath
|
||||||
|
static int ath79_spi_setup_cs(struct spi_device *spi)
|
||||||
|
{
|
||||||
|
struct ath79_spi_controller_data *cdata;
|
||||||
|
+ unsigned long flags;
|
||||||
|
int status;
|
||||||
|
|
||||||
|
cdata = spi->controller_data;
|
||||||
|
- if (spi->chip_select && !cdata)
|
||||||
|
+ if (!cdata)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
status = 0;
|
||||||
|
- if (spi->chip_select) {
|
||||||
|
- unsigned long flags;
|
||||||
|
+ switch (cdata->cs_type) {
|
||||||
|
+ case ATH79_SPI_CS_TYPE_INTERNAL:
|
||||||
|
+ if (cdata->cs_line > ATH79_SPI_CS_LINE_MAX)
|
||||||
|
+ status = -EINVAL;
|
||||||
|
+ break;
|
||||||
|
|
||||||
|
+ case ATH79_SPI_CS_TYPE_GPIO:
|
||||||
|
flags = GPIOF_DIR_OUT;
|
||||||
|
if (spi->mode & SPI_CS_HIGH)
|
||||||
|
flags |= GPIOF_INIT_HIGH;
|
||||||
|
else
|
||||||
|
flags |= GPIOF_INIT_LOW;
|
||||||
|
|
||||||
|
- status = gpio_request_one(cdata->gpio, flags,
|
||||||
|
+ status = gpio_request_one(cdata->cs_line, flags,
|
||||||
|
dev_name(&spi->dev));
|
||||||
|
+ break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
|
@@ -138,9 +148,15 @@ static int ath79_spi_setup_cs(struct spi
|
||||||
|
|
||||||
|
static void ath79_spi_cleanup_cs(struct spi_device *spi)
|
||||||
|
{
|
||||||
|
- if (spi->chip_select) {
|
||||||
|
- struct ath79_spi_controller_data *cdata = spi->controller_data;
|
||||||
|
- gpio_free(cdata->gpio);
|
||||||
|
+ struct ath79_spi_controller_data *cdata = spi->controller_data;
|
||||||
|
+
|
||||||
|
+ switch (cdata->cs_type) {
|
||||||
|
+ case ATH79_SPI_CS_TYPE_INTERNAL:
|
||||||
|
+ /* nothing to do */
|
||||||
|
+ break;
|
||||||
|
+ case ATH79_SPI_CS_TYPE_GPIO:
|
||||||
|
+ gpio_free(cdata->cs_line);
|
||||||
|
+ break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -206,6 +222,10 @@ static __devinit int ath79_spi_probe(str
|
||||||
|
struct resource *r;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
+ pdata = pdev->dev.platform_data;
|
||||||
|
+ if (!pdata)
|
||||||
|
+ return -EINVAL;
|
||||||
|
+
|
||||||
|
master = spi_alloc_master(&pdev->dev, sizeof(*sp));
|
||||||
|
if (master == NULL) {
|
||||||
|
dev_err(&pdev->dev, "failed to allocate spi master\n");
|
||||||
|
@@ -215,17 +235,10 @@ static __devinit int ath79_spi_probe(str
|
||||||
|
sp = spi_master_get_devdata(master);
|
||||||
|
platform_set_drvdata(pdev, sp);
|
||||||
|
|
||||||
|
- pdata = pdev->dev.platform_data;
|
||||||
|
-
|
||||||
|
master->setup = ath79_spi_setup;
|
||||||
|
master->cleanup = ath79_spi_cleanup;
|
||||||
|
- if (pdata) {
|
||||||
|
- master->bus_num = pdata->bus_num;
|
||||||
|
- master->num_chipselect = pdata->num_chipselect;
|
||||||
|
- } else {
|
||||||
|
- master->bus_num = -1;
|
||||||
|
- master->num_chipselect = 1;
|
||||||
|
- }
|
||||||
|
+ master->bus_num = pdata->bus_num;
|
||||||
|
+ master->num_chipselect = pdata->num_chipselect;
|
||||||
|
|
||||||
|
sp->bitbang.master = spi_master_get(master);
|
||||||
|
sp->bitbang.chipselect = ath79_spi_chipselect;
|
||||||
|
|
@ -0,0 +1,105 @@
|
||||||
|
--- a/arch/mips/ath79/mach-ap121.c
|
||||||
|
+++ b/arch/mips/ath79/mach-ap121.c
|
||||||
|
@@ -58,12 +58,18 @@ static struct gpio_keys_button ap121_gpi
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
+static struct ath79_spi_controller_data ap121_spi0_data = {
|
||||||
|
+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
|
||||||
|
+ .cs_line = 0,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
static struct spi_board_info ap121_spi_info[] = {
|
||||||
|
{
|
||||||
|
.bus_num = 0,
|
||||||
|
.chip_select = 0,
|
||||||
|
.max_speed_hz = 25000000,
|
||||||
|
.modalias = "mx25l1606e",
|
||||||
|
+ .controller_data = &ap121_spi0_data,
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/mach-ap81.c
|
||||||
|
+++ b/arch/mips/ath79/mach-ap81.c
|
||||||
|
@@ -67,12 +67,18 @@ static struct gpio_keys_button ap81_gpio
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
+static struct ath79_spi_controller_data ap81_spi0_data = {
|
||||||
|
+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
|
||||||
|
+ .cs_line = 0,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
static struct spi_board_info ap81_spi_info[] = {
|
||||||
|
{
|
||||||
|
.bus_num = 0,
|
||||||
|
.chip_select = 0,
|
||||||
|
.max_speed_hz = 25000000,
|
||||||
|
.modalias = "m25p64",
|
||||||
|
+ .controller_data = &ap81_spi0_data,
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/mach-db120.c
|
||||||
|
+++ b/arch/mips/ath79/mach-db120.c
|
||||||
|
@@ -95,12 +95,18 @@ static struct gpio_keys_button db120_gpi
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
+static struct ath79_spi_controller_data db120_spi0_data = {
|
||||||
|
+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
|
||||||
|
+ .cs_line = 0,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
static struct spi_board_info db120_spi_info[] = {
|
||||||
|
{
|
||||||
|
.bus_num = 0,
|
||||||
|
.chip_select = 0,
|
||||||
|
.max_speed_hz = 25000000,
|
||||||
|
.modalias = "s25sl064a",
|
||||||
|
+ .controller_data = &db120_spi0_data,
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/mach-pb44.c
|
||||||
|
+++ b/arch/mips/ath79/mach-pb44.c
|
||||||
|
@@ -87,12 +87,18 @@ static struct gpio_keys_button pb44_gpio
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
+static struct ath79_spi_controller_data pb44_spi0_data = {
|
||||||
|
+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
|
||||||
|
+ .cs_line = 0,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
static struct spi_board_info pb44_spi_info[] = {
|
||||||
|
{
|
||||||
|
.bus_num = 0,
|
||||||
|
.chip_select = 0,
|
||||||
|
.max_speed_hz = 25000000,
|
||||||
|
.modalias = "m25p64",
|
||||||
|
+ .controller_data = &pb44_spi0_data,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
+++ b/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
@@ -65,12 +65,18 @@ static struct gpio_keys_button ubnt_xm_g
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
+static struct ath79_spi_controller_data ubnt_xm_spi0_data = {
|
||||||
|
+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
|
||||||
|
+ .cs_line = 0,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
static struct spi_board_info ubnt_xm_spi_info[] = {
|
||||||
|
{
|
||||||
|
.bus_num = 0,
|
||||||
|
.chip_select = 0,
|
||||||
|
.max_speed_hz = 25000000,
|
||||||
|
.modalias = "mx25l6405d",
|
||||||
|
+ .controller_data = &ubnt_xm_spi0_data,
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
|
@ -0,0 +1,27 @@
|
||||||
|
--- a/arch/mips/ath79/gpio.c
|
||||||
|
+++ b/arch/mips/ath79/gpio.c
|
||||||
|
@@ -188,8 +188,10 @@ void __init ath79_gpio_init(void)
|
||||||
|
|
||||||
|
if (soc_is_ar71xx())
|
||||||
|
ath79_gpio_count = AR71XX_GPIO_COUNT;
|
||||||
|
- else if (soc_is_ar724x())
|
||||||
|
- ath79_gpio_count = AR724X_GPIO_COUNT;
|
||||||
|
+ else if (soc_is_ar7240())
|
||||||
|
+ ath79_gpio_count = AR7240_GPIO_COUNT;
|
||||||
|
+ else if (soc_is_ar7241() || soc_is_ar7242())
|
||||||
|
+ ath79_gpio_count = AR7241_GPIO_COUNT;
|
||||||
|
else if (soc_is_ar913x())
|
||||||
|
ath79_gpio_count = AR913X_GPIO_COUNT;
|
||||||
|
else if (soc_is_ar933x())
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
@@ -428,7 +428,8 @@
|
||||||
|
#define AR71XX_GPIO_REG_FUNC 0x28
|
||||||
|
|
||||||
|
#define AR71XX_GPIO_COUNT 16
|
||||||
|
-#define AR724X_GPIO_COUNT 18
|
||||||
|
+#define AR7240_GPIO_COUNT 18
|
||||||
|
+#define AR7241_GPIO_COUNT 20
|
||||||
|
#define AR913X_GPIO_COUNT 22
|
||||||
|
#define AR933X_GPIO_COUNT 30
|
||||||
|
#define AR934X_GPIO_COUNT 23
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
--- a/arch/mips/ath79/dev-wmac.c
|
||||||
|
+++ b/arch/mips/ath79/dev-wmac.c
|
||||||
|
@@ -62,8 +62,8 @@ static void __init ar913x_wmac_setup(voi
|
||||||
|
|
||||||
|
static int ar933x_wmac_reset(void)
|
||||||
|
{
|
||||||
|
- ath79_device_reset_clear(AR933X_RESET_WMAC);
|
||||||
|
ath79_device_reset_set(AR933X_RESET_WMAC);
|
||||||
|
+ ath79_device_reset_clear(AR933X_RESET_WMAC);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,18 @@
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/pci.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/pci.h
|
||||||
|
@@ -16,13 +16,13 @@
|
||||||
|
#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
|
||||||
|
int ar71xx_pcibios_init(void);
|
||||||
|
#else
|
||||||
|
-static inline int ar71xx_pcibios_init(void) { return 0 };
|
||||||
|
+static inline int ar71xx_pcibios_init(void) { return 0; }
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_PCI_AR724X)
|
||||||
|
int ar724x_pcibios_init(int irq);
|
||||||
|
#else
|
||||||
|
-static inline int ar724x_pcibios_init(int irq) { return 0 };
|
||||||
|
+static inline int ar724x_pcibios_init(int irq) { return 0; }
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __ASM_MACH_ATH79_PCI_H */
|
||||||
|
|
@ -0,0 +1,94 @@
|
||||||
|
--- a/drivers/mtd/maps/physmap.c
|
||||||
|
+++ b/drivers/mtd/maps/physmap.c
|
||||||
|
@@ -29,6 +29,66 @@ struct physmap_flash_info {
|
||||||
|
struct map_info map[MAX_RESOURCES];
|
||||||
|
};
|
||||||
|
|
||||||
|
+static struct platform_device *physmap_map2pdev(struct map_info *map)
|
||||||
|
+{
|
||||||
|
+ return (struct platform_device *) map->map_priv_1;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void physmap_lock(struct map_info *map)
|
||||||
|
+{
|
||||||
|
+ struct platform_device *pdev;
|
||||||
|
+ struct physmap_flash_data *physmap_data;
|
||||||
|
+
|
||||||
|
+ pdev = physmap_map2pdev(map);
|
||||||
|
+ physmap_data = pdev->dev.platform_data;
|
||||||
|
+ physmap_data->lock(pdev);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void physmap_unlock(struct map_info *map)
|
||||||
|
+{
|
||||||
|
+ struct platform_device *pdev;
|
||||||
|
+ struct physmap_flash_data *physmap_data;
|
||||||
|
+
|
||||||
|
+ pdev = physmap_map2pdev(map);
|
||||||
|
+ physmap_data = pdev->dev.platform_data;
|
||||||
|
+ physmap_data->unlock(pdev);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static map_word physmap_flash_read_lock(struct map_info *map, unsigned long ofs)
|
||||||
|
+{
|
||||||
|
+ map_word ret;
|
||||||
|
+
|
||||||
|
+ physmap_lock(map);
|
||||||
|
+ ret = inline_map_read(map, ofs);
|
||||||
|
+ physmap_unlock(map);
|
||||||
|
+
|
||||||
|
+ return ret;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void physmap_flash_write_lock(struct map_info *map, map_word d,
|
||||||
|
+ unsigned long ofs)
|
||||||
|
+{
|
||||||
|
+ physmap_lock(map);
|
||||||
|
+ inline_map_write(map, d, ofs);
|
||||||
|
+ physmap_unlock(map);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void physmap_flash_copy_from_lock(struct map_info *map, void *to,
|
||||||
|
+ unsigned long from, ssize_t len)
|
||||||
|
+{
|
||||||
|
+ physmap_lock(map);
|
||||||
|
+ inline_map_copy_from(map, to, from, len);
|
||||||
|
+ physmap_unlock(map);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void physmap_flash_copy_to_lock(struct map_info *map, unsigned long to,
|
||||||
|
+ const void *from, ssize_t len)
|
||||||
|
+{
|
||||||
|
+ physmap_lock(map);
|
||||||
|
+ inline_map_copy_to(map, to, from, len);
|
||||||
|
+ physmap_unlock(map);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static int physmap_flash_remove(struct platform_device *dev)
|
||||||
|
{
|
||||||
|
struct physmap_flash_info *info;
|
||||||
|
@@ -141,6 +201,13 @@ static int physmap_flash_probe(struct pl
|
||||||
|
|
||||||
|
simple_map_init(&info->map[i]);
|
||||||
|
|
||||||
|
+ if (physmap_data->lock && physmap_data->unlock) {
|
||||||
|
+ info->map[i].read = physmap_flash_read_lock;
|
||||||
|
+ info->map[i].write = physmap_flash_write_lock;
|
||||||
|
+ info->map[i].copy_from = physmap_flash_copy_from_lock;
|
||||||
|
+ info->map[i].copy_to = physmap_flash_copy_to_lock;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
probe_type = rom_probe_types;
|
||||||
|
if (physmap_data->probe_type == NULL) {
|
||||||
|
for (; info->mtd[i] == NULL && *probe_type != NULL; probe_type++)
|
||||||
|
--- a/include/linux/mtd/physmap.h
|
||||||
|
+++ b/include/linux/mtd/physmap.h
|
||||||
|
@@ -26,6 +26,8 @@ struct physmap_flash_data {
|
||||||
|
unsigned int width;
|
||||||
|
int (*init)(struct platform_device *);
|
||||||
|
void (*exit)(struct platform_device *);
|
||||||
|
+ void (*lock)(struct platform_device *);
|
||||||
|
+ void (*unlock)(struct platform_device *);
|
||||||
|
void (*set_vpp)(struct platform_device *, int);
|
||||||
|
unsigned int nr_parts;
|
||||||
|
unsigned int pfow_base;
|
||||||
|
|
@ -0,0 +1,29 @@
|
||||||
|
--- a/drivers/mtd/chips/jedec_probe.c
|
||||||
|
+++ b/drivers/mtd/chips/jedec_probe.c
|
||||||
|
@@ -148,6 +148,7 @@
|
||||||
|
#define SST39LF160 0x2782
|
||||||
|
#define SST39VF1601 0x234b
|
||||||
|
#define SST39VF3201 0x235b
|
||||||
|
+#define SST39VF6401B 0x236d
|
||||||
|
#define SST39WF1601 0x274b
|
||||||
|
#define SST39WF1602 0x274a
|
||||||
|
#define SST39LF512 0x00D4
|
||||||
|
@@ -1568,6 +1569,18 @@ static const struct amd_flash_info jedec
|
||||||
|
ERASEINFO(0x10000,64),
|
||||||
|
}
|
||||||
|
}, {
|
||||||
|
+ .mfr_id = CFI_MFR_SST,
|
||||||
|
+ .dev_id = SST39VF6401B,
|
||||||
|
+ .name = "SST 39VF6401B",
|
||||||
|
+ .devtypes = CFI_DEVICETYPE_X16,
|
||||||
|
+ .uaddr = MTD_UADDR_0xAAAA_0x5555,
|
||||||
|
+ .dev_size = SIZE_8MiB,
|
||||||
|
+ .cmd_set = P_ID_AMD_STD,
|
||||||
|
+ .nr_regions = 1,
|
||||||
|
+ .regions = {
|
||||||
|
+ ERASEINFO(0x10000,128)
|
||||||
|
+ }
|
||||||
|
+ }, {
|
||||||
|
.mfr_id = CFI_MFR_ST,
|
||||||
|
.dev_id = M29F800AB,
|
||||||
|
.name = "ST M29F800AB",
|
||||||
|
|
@ -0,0 +1,69 @@
|
||||||
|
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
|
||||||
|
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
|
||||||
|
@@ -1214,8 +1214,8 @@ static int __xipram do_write_oneword(str
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
- if (chip_ready(map, adr))
|
||||||
|
- break;
|
||||||
|
+ if (chip_good(map, adr, datum))
|
||||||
|
+ goto enable_xip;
|
||||||
|
|
||||||
|
/* Latency issues. Drop the lock, wait a while and retry */
|
||||||
|
UDELAY(map, chip, adr, 1);
|
||||||
|
@@ -1231,6 +1231,8 @@ static int __xipram do_write_oneword(str
|
||||||
|
|
||||||
|
ret = -EIO;
|
||||||
|
}
|
||||||
|
+
|
||||||
|
+ enable_xip:
|
||||||
|
xip_enable(map, chip, adr);
|
||||||
|
op_done:
|
||||||
|
chip->state = FL_READY;
|
||||||
|
@@ -1563,7 +1565,6 @@ static int cfi_amdstd_write_buffers(stru
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
-
|
||||||
|
/*
|
||||||
|
* Handle devices with one erase region, that only implement
|
||||||
|
* the chip erase command.
|
||||||
|
@@ -1627,8 +1628,8 @@ static int __xipram do_erase_chip(struct
|
||||||
|
chip->erase_suspended = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
- if (chip_ready(map, adr))
|
||||||
|
- break;
|
||||||
|
+ if (chip_good(map, adr, map_word_ff(map)))
|
||||||
|
+ goto op_done;
|
||||||
|
|
||||||
|
if (time_after(jiffies, timeo)) {
|
||||||
|
printk(KERN_WARNING "MTD %s(): software timeout\n",
|
||||||
|
@@ -1648,6 +1649,7 @@ static int __xipram do_erase_chip(struct
|
||||||
|
ret = -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
+ op_done:
|
||||||
|
chip->state = FL_READY;
|
||||||
|
xip_enable(map, chip, adr);
|
||||||
|
put_chip(map, chip, adr);
|
||||||
|
@@ -1715,9 +1717,9 @@ static int __xipram do_erase_oneblock(st
|
||||||
|
chip->erase_suspended = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
- if (chip_ready(map, adr)) {
|
||||||
|
+ if (chip_good(map, adr, map_word_ff(map))) {
|
||||||
|
xip_enable(map, chip, adr);
|
||||||
|
- break;
|
||||||
|
+ goto op_done;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (time_after(jiffies, timeo)) {
|
||||||
|
@@ -1739,6 +1741,7 @@ static int __xipram do_erase_oneblock(st
|
||||||
|
ret = -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
+ op_done:
|
||||||
|
chip->state = FL_READY;
|
||||||
|
put_chip(map, chip, adr);
|
||||||
|
mutex_unlock(&chip->mutex);
|
||||||
|
|
@ -0,0 +1,25 @@
|
||||||
|
--- a/drivers/mtd/Kconfig
|
||||||
|
+++ b/drivers/mtd/Kconfig
|
||||||
|
@@ -156,6 +156,12 @@ config MTD_BCM63XX_PARTS
|
||||||
|
This provides partions parsing for BCM63xx devices with CFE
|
||||||
|
bootloaders.
|
||||||
|
|
||||||
|
+config MTD_WRT160NL_PARTS
|
||||||
|
+ tristate "Linksys WRT160NL partitioning support"
|
||||||
|
+ depends on MTD_PARTITIONS && ATH79_MACH_WRT160NL
|
||||||
|
+ ---help---
|
||||||
|
+ Linksys WRT160NL partitioning support
|
||||||
|
+
|
||||||
|
config MTD_MYLOADER_PARTS
|
||||||
|
tristate "MyLoader partition parsing"
|
||||||
|
depends on ADM5120 || ATHEROS_AR231X || ATHEROS_AR71XX || ATH79
|
||||||
|
--- a/drivers/mtd/Makefile
|
||||||
|
+++ b/drivers/mtd/Makefile
|
||||||
|
@@ -13,6 +13,7 @@ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
|
||||||
|
obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
|
||||||
|
obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o
|
||||||
|
obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
|
||||||
|
+obj-$(CONFIG_MTD_WRT160NL_PARTS) += wrt160nl_part.o
|
||||||
|
|
||||||
|
# 'Users' - code which presents functionality to userspace.
|
||||||
|
obj-$(CONFIG_MTD_CHAR) += mtdchar.o
|
||||||
|
|
@ -0,0 +1,34 @@
|
||||||
|
--- a/drivers/mtd/Kconfig
|
||||||
|
+++ b/drivers/mtd/Kconfig
|
||||||
|
@@ -158,7 +158,7 @@ config MTD_BCM63XX_PARTS
|
||||||
|
|
||||||
|
config MTD_WRT160NL_PARTS
|
||||||
|
tristate "Linksys WRT160NL partitioning support"
|
||||||
|
- depends on MTD_PARTITIONS && ATH79_MACH_WRT160NL
|
||||||
|
+ depends on ATH79_MACH_WRT160NL
|
||||||
|
---help---
|
||||||
|
Linksys WRT160NL partitioning support
|
||||||
|
|
||||||
|
@@ -178,6 +178,12 @@ config MTD_MYLOADER_PARTS
|
||||||
|
You will still need the parsing functions to be called by the driver
|
||||||
|
for your particular device. It won't happen automatically.
|
||||||
|
|
||||||
|
+config MTD_TPLINK_PARTS
|
||||||
|
+ tristate "TP-Link AR7XXX/AR9XXX partitioning support"
|
||||||
|
+ depends on ATH79
|
||||||
|
+ ---help---
|
||||||
|
+ TBD.
|
||||||
|
+
|
||||||
|
comment "User Modules And Translation Layers"
|
||||||
|
|
||||||
|
config MTD_CHAR
|
||||||
|
--- a/drivers/mtd/Makefile
|
||||||
|
+++ b/drivers/mtd/Makefile
|
||||||
|
@@ -13,6 +13,7 @@ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
|
||||||
|
obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
|
||||||
|
obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o
|
||||||
|
obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
|
||||||
|
+obj-$(CONFIG_MTD_TPLINK_PARTS) += tplinkpart.o
|
||||||
|
obj-$(CONFIG_MTD_WRT160NL_PARTS) += wrt160nl_part.o
|
||||||
|
|
||||||
|
# 'Users' - code which presents functionality to userspace.
|
||||||
|
|
@ -0,0 +1,112 @@
|
||||||
|
--- a/drivers/mtd/devices/m25p80.c
|
||||||
|
+++ b/drivers/mtd/devices/m25p80.c
|
||||||
|
@@ -100,6 +100,7 @@ struct m25p {
|
||||||
|
u16 addr_width;
|
||||||
|
u8 erase_opcode;
|
||||||
|
u8 *command;
|
||||||
|
+ size_t max_read_len;
|
||||||
|
};
|
||||||
|
|
||||||
|
static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
|
||||||
|
@@ -352,6 +353,7 @@ static int m25p80_read(struct mtd_info *
|
||||||
|
struct m25p *flash = mtd_to_m25p(mtd);
|
||||||
|
struct spi_transfer t[2];
|
||||||
|
struct spi_message m;
|
||||||
|
+ loff_t ofs;
|
||||||
|
|
||||||
|
pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
|
||||||
|
__func__, (u32)from, len);
|
||||||
|
@@ -374,8 +376,6 @@ static int m25p80_read(struct mtd_info *
|
||||||
|
t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE;
|
||||||
|
spi_message_add_tail(&t[0], &m);
|
||||||
|
|
||||||
|
- t[1].rx_buf = buf;
|
||||||
|
- t[1].len = len;
|
||||||
|
spi_message_add_tail(&t[1], &m);
|
||||||
|
|
||||||
|
/* Byte count starts at zero. */
|
||||||
|
@@ -383,13 +383,6 @@ static int m25p80_read(struct mtd_info *
|
||||||
|
|
||||||
|
mutex_lock(&flash->lock);
|
||||||
|
|
||||||
|
- /* Wait till previous write/erase is done. */
|
||||||
|
- if (wait_till_ready(flash)) {
|
||||||
|
- /* REVISIT status return?? */
|
||||||
|
- mutex_unlock(&flash->lock);
|
||||||
|
- return 1;
|
||||||
|
- }
|
||||||
|
-
|
||||||
|
/* FIXME switch to OPCODE_FAST_READ. It's required for higher
|
||||||
|
* clocks; and at this writing, every chip this driver handles
|
||||||
|
* supports that opcode.
|
||||||
|
@@ -397,11 +390,44 @@ static int m25p80_read(struct mtd_info *
|
||||||
|
|
||||||
|
/* Set up the write data buffer. */
|
||||||
|
flash->command[0] = OPCODE_READ;
|
||||||
|
- m25p_addr2cmd(flash, from, flash->command);
|
||||||
|
|
||||||
|
- spi_sync(flash->spi, &m);
|
||||||
|
+ ofs = 0;
|
||||||
|
+ while (len) {
|
||||||
|
+ size_t readlen;
|
||||||
|
+ size_t done;
|
||||||
|
+ int ret;
|
||||||
|
+
|
||||||
|
+ ret = wait_till_ready(flash);
|
||||||
|
+ if (ret) {
|
||||||
|
+ mutex_unlock(&flash->lock);
|
||||||
|
+ return 1;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ if (flash->max_read_len > 0 &&
|
||||||
|
+ flash->max_read_len < len)
|
||||||
|
+ readlen = flash->max_read_len;
|
||||||
|
+ else
|
||||||
|
+ readlen = len;
|
||||||
|
+
|
||||||
|
+ t[1].rx_buf = buf + ofs;
|
||||||
|
+ t[1].len = readlen;
|
||||||
|
+
|
||||||
|
+ m25p_addr2cmd(flash, from + ofs, flash->command);
|
||||||
|
+
|
||||||
|
+ spi_sync(flash->spi, &m);
|
||||||
|
|
||||||
|
- *retlen = m.actual_length - m25p_cmdsz(flash) - FAST_READ_DUMMY_BYTE;
|
||||||
|
+ done = m.actual_length - m25p_cmdsz(flash) -
|
||||||
|
+ FAST_READ_DUMMY_BYTE;
|
||||||
|
+ if (done != readlen) {
|
||||||
|
+ mutex_unlock(&flash->lock);
|
||||||
|
+ return 1;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ ofs += done;
|
||||||
|
+ len -= done;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ *retlen = ofs;
|
||||||
|
|
||||||
|
mutex_unlock(&flash->lock);
|
||||||
|
|
||||||
|
@@ -924,6 +950,12 @@ static int __devinit m25p_probe(struct s
|
||||||
|
flash->mtd.erase = m25p80_erase;
|
||||||
|
flash->mtd.read = m25p80_read;
|
||||||
|
|
||||||
|
+ if (data && data->max_read_len) {
|
||||||
|
+ flash->max_read_len = data->max_read_len;
|
||||||
|
+ dev_warn(&spi->dev, "max_read_len set to %d bytes\n",
|
||||||
|
+ flash->max_read_len);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
/* sst flash chips use AAI word program */
|
||||||
|
if (JEDEC_MFR(info->jedec_id) == CFI_MFR_SST)
|
||||||
|
flash->mtd.write = sst_write;
|
||||||
|
--- a/include/linux/spi/flash.h
|
||||||
|
+++ b/include/linux/spi/flash.h
|
||||||
|
@@ -25,6 +25,7 @@ struct flash_platform_data {
|
||||||
|
|
||||||
|
char *type;
|
||||||
|
|
||||||
|
+ size_t max_read_len;
|
||||||
|
/* we'll likely add more ... use JEDEC IDs, etc */
|
||||||
|
};
|
||||||
|
|
||||||
|
|
@ -0,0 +1,23 @@
|
||||||
|
--- a/drivers/mtd/devices/m25p80.c
|
||||||
|
+++ b/drivers/mtd/devices/m25p80.c
|
||||||
|
@@ -1016,7 +1016,9 @@ static int __devinit m25p_probe(struct s
|
||||||
|
/* partitions should match sector boundaries; and it may be good to
|
||||||
|
* use readonly partitions for writeprotected sectors (BP2..BP0).
|
||||||
|
*/
|
||||||
|
- return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
|
||||||
|
+ return mtd_device_parse_register(&flash->mtd,
|
||||||
|
+ data ? data->part_probes : NULL,
|
||||||
|
+ &ppdata,
|
||||||
|
data ? data->parts : NULL,
|
||||||
|
data ? data->nr_parts : 0);
|
||||||
|
}
|
||||||
|
--- a/include/linux/spi/flash.h
|
||||||
|
+++ b/include/linux/spi/flash.h
|
||||||
|
@@ -24,6 +24,7 @@ struct flash_platform_data {
|
||||||
|
unsigned int nr_parts;
|
||||||
|
|
||||||
|
char *type;
|
||||||
|
+ const char **part_probes;
|
||||||
|
|
||||||
|
size_t max_read_len;
|
||||||
|
/* we'll likely add more ... use JEDEC IDs, etc */
|
||||||
|
|
@ -0,0 +1,45 @@
|
||||||
|
--- a/drivers/mtd/redboot.c
|
||||||
|
+++ b/drivers/mtd/redboot.c
|
||||||
|
@@ -79,6 +79,11 @@ static int parse_redboot_partitions(stru
|
||||||
|
static char nullstring[] = "unallocated";
|
||||||
|
#endif
|
||||||
|
|
||||||
|
+ buf = vmalloc(master->erasesize);
|
||||||
|
+ if (!buf)
|
||||||
|
+ return -ENOMEM;
|
||||||
|
+
|
||||||
|
+ restart:
|
||||||
|
if ( directory < 0 ) {
|
||||||
|
offset = master->size + directory * master->erasesize;
|
||||||
|
while (mtd_can_have_bb(master) &&
|
||||||
|
@@ -86,6 +91,7 @@ static int parse_redboot_partitions(stru
|
||||||
|
if (!offset) {
|
||||||
|
nogood:
|
||||||
|
printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
|
||||||
|
+ vfree(buf);
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
offset -= master->erasesize;
|
||||||
|
@@ -99,10 +105,6 @@ static int parse_redboot_partitions(stru
|
||||||
|
goto nogood;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
- buf = vmalloc(master->erasesize);
|
||||||
|
-
|
||||||
|
- if (!buf)
|
||||||
|
- return -ENOMEM;
|
||||||
|
|
||||||
|
printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
|
||||||
|
master->name, offset);
|
||||||
|
@@ -175,6 +177,11 @@ static int parse_redboot_partitions(stru
|
||||||
|
}
|
||||||
|
if (i == numslots) {
|
||||||
|
/* Didn't find it */
|
||||||
|
+ if (offset + master->erasesize < master->size) {
|
||||||
|
+ /* not at the end of the flash yet, maybe next block :) */
|
||||||
|
+ directory++;
|
||||||
|
+ goto restart;
|
||||||
|
+ }
|
||||||
|
printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
|
||||||
|
master->name);
|
||||||
|
ret = 0;
|
||||||
|
|
@ -0,0 +1,21 @@
|
||||||
|
--- a/drivers/mtd/nand/Kconfig
|
||||||
|
+++ b/drivers/mtd/nand/Kconfig
|
||||||
|
@@ -536,4 +536,8 @@ config MTD_NAND_FSMC
|
||||||
|
Enables support for NAND Flash chips on the ST Microelectronics
|
||||||
|
Flexible Static Memory Controller (FSMC)
|
||||||
|
|
||||||
|
+config MTD_NAND_RB4XX
|
||||||
|
+ tristate "NAND flash driver for RouterBoard 4xx series"
|
||||||
|
+ depends on MTD_NAND && ATH79_MACH_RB4XX
|
||||||
|
+
|
||||||
|
endif # MTD_NAND
|
||||||
|
--- a/drivers/mtd/nand/Makefile
|
||||||
|
+++ b/drivers/mtd/nand/Makefile
|
||||||
|
@@ -33,6 +33,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx27
|
||||||
|
obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
|
||||||
|
obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
|
||||||
|
obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
|
||||||
|
+obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
|
||||||
|
obj-$(CONFIG_MTD_ALAUDA) += alauda.o
|
||||||
|
obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
|
||||||
|
obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
|
||||||
|
|
@ -0,0 +1,21 @@
|
||||||
|
--- a/drivers/mtd/nand/Kconfig
|
||||||
|
+++ b/drivers/mtd/nand/Kconfig
|
||||||
|
@@ -540,4 +540,8 @@ config MTD_NAND_RB4XX
|
||||||
|
tristate "NAND flash driver for RouterBoard 4xx series"
|
||||||
|
depends on MTD_NAND && ATH79_MACH_RB4XX
|
||||||
|
|
||||||
|
+config MTD_NAND_RB750
|
||||||
|
+ tristate "NAND flash driver for the RouterBoard 750"
|
||||||
|
+ depends on MTD_NAND && ATH79_MACH_RB750
|
||||||
|
+
|
||||||
|
endif # MTD_NAND
|
||||||
|
--- a/drivers/mtd/nand/Makefile
|
||||||
|
+++ b/drivers/mtd/nand/Makefile
|
||||||
|
@@ -34,6 +34,7 @@ obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx
|
||||||
|
obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
|
||||||
|
obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
|
||||||
|
obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
|
||||||
|
+obj-$(CONFIG_MTD_NAND_RB750) += rb750_nand.o
|
||||||
|
obj-$(CONFIG_MTD_ALAUDA) += alauda.o
|
||||||
|
obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
|
||||||
|
obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
|
||||||
|
|
@ -0,0 +1,61 @@
|
||||||
|
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
|
||||||
|
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
|
||||||
|
@@ -39,7 +39,7 @@
|
||||||
|
#include <linux/mtd/xip.h>
|
||||||
|
|
||||||
|
#define AMD_BOOTLOC_BUG
|
||||||
|
-#define FORCE_WORD_WRITE 0
|
||||||
|
+#define FORCE_WORD_WRITE 1
|
||||||
|
|
||||||
|
#define MAX_WORD_RETRIES 3
|
||||||
|
|
||||||
|
@@ -50,7 +50,9 @@
|
||||||
|
|
||||||
|
static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
|
||||||
|
static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
|
||||||
|
+#if !FORCE_WORD_WRITE
|
||||||
|
static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
|
||||||
|
+#endif
|
||||||
|
static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
|
||||||
|
static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
|
||||||
|
static void cfi_amdstd_sync (struct mtd_info *);
|
||||||
|
@@ -183,6 +185,7 @@ static void fixup_amd_bootblock(struct m
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
+#if !FORCE_WORD_WRITE
|
||||||
|
static void fixup_use_write_buffers(struct mtd_info *mtd)
|
||||||
|
{
|
||||||
|
struct map_info *map = mtd->priv;
|
||||||
|
@@ -192,6 +195,7 @@ static void fixup_use_write_buffers(stru
|
||||||
|
mtd->write = cfi_amdstd_write_buffers;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
+#endif /* !FORCE_WORD_WRITE */
|
||||||
|
|
||||||
|
/* Atmel chips don't use the same PRI format as AMD chips */
|
||||||
|
static void fixup_convert_atmel_pri(struct mtd_info *mtd)
|
||||||
|
@@ -1374,6 +1378,7 @@ static int cfi_amdstd_write_words(struct
|
||||||
|
/*
|
||||||
|
* FIXME: interleaved mode not tested, and probably not supported!
|
||||||
|
*/
|
||||||
|
+#if !FORCE_WORD_WRITE
|
||||||
|
static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
|
||||||
|
unsigned long adr, const u_char *buf,
|
||||||
|
int len)
|
||||||
|
@@ -1485,7 +1490,6 @@ static int __xipram do_write_buffer(stru
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
-
|
||||||
|
static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
|
||||||
|
size_t *retlen, const u_char *buf)
|
||||||
|
{
|
||||||
|
@@ -1564,6 +1568,7 @@ static int cfi_amdstd_write_buffers(stru
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
+#endif /* !FORCE_WORD_WRITE */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Handle devices with one erase region, that only implement
|
||||||
|
|
@ -0,0 +1,28 @@
|
||||||
|
--- a/drivers/net/ethernet/atheros/Kconfig
|
||||||
|
+++ b/drivers/net/ethernet/atheros/Kconfig
|
||||||
|
@@ -5,7 +5,7 @@
|
||||||
|
config NET_VENDOR_ATHEROS
|
||||||
|
bool "Atheros devices"
|
||||||
|
default y
|
||||||
|
- depends on PCI
|
||||||
|
+ depends on (PCI || ATH79)
|
||||||
|
---help---
|
||||||
|
If you have a network (Ethernet) card belonging to this class, say Y
|
||||||
|
and read the Ethernet-HOWTO, available from
|
||||||
|
@@ -67,4 +67,6 @@ config ATL1C
|
||||||
|
To compile this driver as a module, choose M here. The module
|
||||||
|
will be called atl1c.
|
||||||
|
|
||||||
|
+source drivers/net/ethernet/atheros/ag71xx/Kconfig
|
||||||
|
+
|
||||||
|
endif # NET_VENDOR_ATHEROS
|
||||||
|
--- a/drivers/net/ethernet/atheros/Makefile
|
||||||
|
+++ b/drivers/net/ethernet/atheros/Makefile
|
||||||
|
@@ -2,6 +2,7 @@
|
||||||
|
# Makefile for the Atheros network device drivers.
|
||||||
|
#
|
||||||
|
|
||||||
|
+obj-$(CONFIG_AG71XX) += ag71xx/
|
||||||
|
obj-$(CONFIG_ATL1) += atlx/
|
||||||
|
obj-$(CONFIG_ATL2) += atlx/
|
||||||
|
obj-$(CONFIG_ATL1E) += atl1e/
|
||||||
|
|
@ -0,0 +1,24 @@
|
||||||
|
--- a/drivers/net/phy/Kconfig
|
||||||
|
+++ b/drivers/net/phy/Kconfig
|
||||||
|
@@ -124,6 +124,11 @@ config RTL8306_PHY
|
||||||
|
tristate "Driver for Realtek RTL8306S switches"
|
||||||
|
select SWCONFIG
|
||||||
|
|
||||||
|
+config MICREL_PHY
|
||||||
|
+ tristate "Drivers for Micrel/Kendin PHYs"
|
||||||
|
+ ---help---
|
||||||
|
+ Currently has a driver for the KSZ8041
|
||||||
|
+
|
||||||
|
config FIXED_PHY
|
||||||
|
bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
|
||||||
|
depends on PHYLIB=y
|
||||||
|
--- a/drivers/net/phy/Makefile
|
||||||
|
+++ b/drivers/net/phy/Makefile
|
||||||
|
@@ -25,6 +25,7 @@ obj-$(CONFIG_RTL8366S_PHY) += rtl8366s.o
|
||||||
|
obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb.o
|
||||||
|
obj-$(CONFIG_RTL8367_PHY) += rtl8367.o
|
||||||
|
obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o
|
||||||
|
+obj-$(CONFIG_MICREL_PHY) += micrel.o
|
||||||
|
obj-$(CONFIG_FIXED_PHY) += fixed.o
|
||||||
|
obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
|
||||||
|
obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
|
||||||
|
|
@ -0,0 +1,11 @@
|
||||||
|
--- a/net/dsa/tag_trailer.c
|
||||||
|
+++ b/net/dsa/tag_trailer.c
|
||||||
|
@@ -87,7 +87,7 @@ static int trailer_rcv(struct sk_buff *s
|
||||||
|
|
||||||
|
trailer = skb_tail_pointer(skb) - 4;
|
||||||
|
if (trailer[0] != 0x80 || (trailer[1] & 0xf8) != 0x00 ||
|
||||||
|
- (trailer[3] & 0xef) != 0x00 || trailer[3] != 0x00)
|
||||||
|
+ (trailer[2] & 0xef) != 0x00 || (trailer[3] & 0xfe) != 0x00)
|
||||||
|
goto out_drop;
|
||||||
|
|
||||||
|
source_port = trailer[1] & 7;
|
||||||
|
|
@ -0,0 +1,24 @@
|
||||||
|
--- a/drivers/net/dsa/Kconfig
|
||||||
|
+++ b/drivers/net/dsa/Kconfig
|
||||||
|
@@ -12,6 +12,13 @@ config NET_DSA_MV88E6060
|
||||||
|
This enables support for the Marvell 88E6060 ethernet switch
|
||||||
|
chip.
|
||||||
|
|
||||||
|
+config NET_DSA_MV88E6063
|
||||||
|
+ bool "Marvell 88E6063 ethernet switch chip support"
|
||||||
|
+ select NET_DSA_TAG_TRAILER
|
||||||
|
+ ---help---
|
||||||
|
+ This enables support for the Marvell 88E6063 ethernet switch
|
||||||
|
+ chip
|
||||||
|
+
|
||||||
|
config NET_DSA_MV88E6XXX_NEED_PPU
|
||||||
|
bool
|
||||||
|
default n
|
||||||
|
--- a/drivers/net/dsa/Makefile
|
||||||
|
+++ b/drivers/net/dsa/Makefile
|
||||||
|
@@ -1,4 +1,5 @@
|
||||||
|
obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
|
||||||
|
+obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o
|
||||||
|
obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx_drv.o
|
||||||
|
mv88e6xxx_drv-y += mv88e6xxx.o
|
||||||
|
ifdef CONFIG_NET_DSA_MV88E6123_61_65
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
--- a/drivers/Makefile
|
||||||
|
+++ b/drivers/Makefile
|
||||||
|
@@ -51,8 +51,8 @@ obj-$(CONFIG_IDE) += ide/
|
||||||
|
obj-$(CONFIG_SCSI) += scsi/
|
||||||
|
obj-$(CONFIG_ATA) += ata/
|
||||||
|
obj-$(CONFIG_TARGET_CORE) += target/
|
||||||
|
-obj-$(CONFIG_MTD) += mtd/
|
||||||
|
obj-$(CONFIG_SPI) += spi/
|
||||||
|
+obj-$(CONFIG_MTD) += mtd/
|
||||||
|
obj-y += net/
|
||||||
|
obj-$(CONFIG_ATM) += atm/
|
||||||
|
obj-$(CONFIG_FUSION) += message/
|
||||||
|
|
@ -0,0 +1,19 @@
|
||||||
|
--- a/include/linux/spi/spi.h
|
||||||
|
+++ b/include/linux/spi/spi.h
|
||||||
|
@@ -452,6 +452,8 @@ struct spi_transfer {
|
||||||
|
dma_addr_t rx_dma;
|
||||||
|
|
||||||
|
unsigned cs_change:1;
|
||||||
|
+ unsigned verify:1;
|
||||||
|
+ unsigned fast_write:1;
|
||||||
|
u8 bits_per_word;
|
||||||
|
u16 delay_usecs;
|
||||||
|
u32 speed_hz;
|
||||||
|
@@ -493,6 +495,7 @@ struct spi_message {
|
||||||
|
struct spi_device *spi;
|
||||||
|
|
||||||
|
unsigned is_dma_mapped:1;
|
||||||
|
+ unsigned fast_read:1;
|
||||||
|
|
||||||
|
/* REVISIT: we might want a flag affecting the behavior of the
|
||||||
|
* last transfer ... allowing things like "read 16 bit length L"
|
||||||
|
|
@ -0,0 +1,25 @@
|
||||||
|
--- a/drivers/spi/Kconfig
|
||||||
|
+++ b/drivers/spi/Kconfig
|
||||||
|
@@ -288,6 +288,12 @@ config SPI_PXA2XX
|
||||||
|
config SPI_PXA2XX_PCI
|
||||||
|
def_bool SPI_PXA2XX && X86_32 && PCI
|
||||||
|
|
||||||
|
+config SPI_RB4XX
|
||||||
|
+ tristate "Mikrotik RB4XX SPI master"
|
||||||
|
+ depends on SPI_MASTER && ATH79_MACH_RB4XX
|
||||||
|
+ help
|
||||||
|
+ SPI controller driver for the Mikrotik RB4xx series boards.
|
||||||
|
+
|
||||||
|
config SPI_S3C24XX
|
||||||
|
tristate "Samsung S3C24XX series SPI"
|
||||||
|
depends on ARCH_S3C2410 && EXPERIMENTAL
|
||||||
|
--- a/drivers/spi/Makefile
|
||||||
|
+++ b/drivers/spi/Makefile
|
||||||
|
@@ -45,6 +45,7 @@ obj-$(CONFIG_SPI_PL022) += spi-pl022.o
|
||||||
|
obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
|
||||||
|
obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx.o
|
||||||
|
obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
|
||||||
|
+obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
|
||||||
|
obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
|
||||||
|
spi-s3c24xx-hw-y := spi-s3c24xx.o
|
||||||
|
spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
|
||||||
|
|
@ -0,0 +1,26 @@
|
||||||
|
--- a/drivers/spi/Kconfig
|
||||||
|
+++ b/drivers/spi/Kconfig
|
||||||
|
@@ -439,6 +439,13 @@ config SPI_TLE62X0
|
||||||
|
sysfs interface, with each line presented as a kind of GPIO
|
||||||
|
exposing both switch control and diagnostic feedback.
|
||||||
|
|
||||||
|
+config SPI_RB4XX_CPLD
|
||||||
|
+ tristate "MikroTik RB4XX CPLD driver"
|
||||||
|
+ depends on ATH79_MACH_RB4XX
|
||||||
|
+ help
|
||||||
|
+ SPI driver for the Xilinx CPLD chip present on the
|
||||||
|
+ MikroTik RB4xx boards.
|
||||||
|
+
|
||||||
|
#
|
||||||
|
# Add new SPI protocol masters in alphabetical order above this line
|
||||||
|
#
|
||||||
|
--- a/drivers/spi/Makefile
|
||||||
|
+++ b/drivers/spi/Makefile
|
||||||
|
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.
|
||||||
|
obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx.o
|
||||||
|
obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
|
||||||
|
obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
|
||||||
|
+obj-$(CONFIG_SPI_RB4XX_CPLD) += spi-rb4xx-cpld.o
|
||||||
|
obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
|
||||||
|
spi-s3c24xx-hw-y := spi-s3c24xx.o
|
||||||
|
spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
|
||||||
|
|
@ -0,0 +1,27 @@
|
||||||
|
--- a/drivers/spi/Makefile
|
||||||
|
+++ b/drivers/spi/Makefile
|
||||||
|
@@ -12,6 +12,7 @@ obj-$(CONFIG_SPI_SPIDEV) += spidev.o
|
||||||
|
# SPI master controller drivers (bus)
|
||||||
|
obj-$(CONFIG_SPI_ALTERA) += spi-altera.o
|
||||||
|
obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
|
||||||
|
+obj-$(CONFIG_SPI_AP83) += spi-ap83.o
|
||||||
|
obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
|
||||||
|
obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
|
||||||
|
obj-$(CONFIG_SPI_BFIN) += spi-bfin5xx.o
|
||||||
|
--- a/drivers/spi/Kconfig
|
||||||
|
+++ b/drivers/spi/Kconfig
|
||||||
|
@@ -59,6 +59,14 @@ config SPI_ALTERA
|
||||||
|
help
|
||||||
|
This is the driver for the Altera SPI Controller.
|
||||||
|
|
||||||
|
+config SPI_AP83
|
||||||
|
+ tristate "Atheros AP83 specific SPI Controller"
|
||||||
|
+ depends on SPI_MASTER && ATH79_MACH_AP83
|
||||||
|
+ select SPI_BITBANG
|
||||||
|
+ help
|
||||||
|
+ This is a specific SPI controller driver for the Atheros AP83
|
||||||
|
+ reference board.
|
||||||
|
+
|
||||||
|
config SPI_ATH79
|
||||||
|
tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver"
|
||||||
|
depends on ATH79 && GENERIC_GPIO
|
||||||
|
|
@ -0,0 +1,23 @@
|
||||||
|
--- a/drivers/spi/Kconfig
|
||||||
|
+++ b/drivers/spi/Kconfig
|
||||||
|
@@ -454,6 +454,11 @@ config SPI_RB4XX_CPLD
|
||||||
|
SPI driver for the Xilinx CPLD chip present on the
|
||||||
|
MikroTik RB4xx boards.
|
||||||
|
|
||||||
|
+config SPI_VSC7385
|
||||||
|
+ tristate "Vitesse VSC7385 ethernet switch driver"
|
||||||
|
+ help
|
||||||
|
+ SPI driver for the Vitesse VSC7385 ethernet switch.
|
||||||
|
+
|
||||||
|
#
|
||||||
|
# Add new SPI protocol masters in alphabetical order above this line
|
||||||
|
#
|
||||||
|
--- a/drivers/spi/Makefile
|
||||||
|
+++ b/drivers/spi/Makefile
|
||||||
|
@@ -61,5 +61,5 @@ obj-$(CONFIG_SPI_TI_SSP) += spi-ti-ssp.
|
||||||
|
obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o
|
||||||
|
obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
|
||||||
|
obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
|
||||||
|
+obj-$(CONFIG_SPI_VSC7385) += spi-vsc7385.o
|
||||||
|
obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
|
||||||
|
-
|
||||||
|
|
@ -0,0 +1,26 @@
|
||||||
|
--- a/drivers/leds/Kconfig
|
||||||
|
+++ b/drivers/leds/Kconfig
|
||||||
|
@@ -418,6 +418,13 @@ config LEDS_TRIGGERS
|
||||||
|
These triggers allow kernel events to drive the LEDs and can
|
||||||
|
be configured via sysfs. If unsure, say Y.
|
||||||
|
|
||||||
|
+config LEDS_WNDR3700_USB
|
||||||
|
+ tristate "NETGEAR WNDR3700 USB LED driver"
|
||||||
|
+ depends on LEDS_CLASS && ATH79_MACH_WNDR3700
|
||||||
|
+ help
|
||||||
|
+ This option enables support for the USB LED found on the
|
||||||
|
+ NETGEAR WNDR3700 board.
|
||||||
|
+
|
||||||
|
comment "LED Triggers"
|
||||||
|
|
||||||
|
config LEDS_TRIGGER_TIMER
|
||||||
|
--- a/drivers/leds/Makefile
|
||||||
|
+++ b/drivers/leds/Makefile
|
||||||
|
@@ -35,6 +35,7 @@ obj-$(CONFIG_LEDS_DA903X) += leds-da903
|
||||||
|
obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o
|
||||||
|
obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o
|
||||||
|
obj-$(CONFIG_LEDS_PWM) += leds-pwm.o
|
||||||
|
+obj-${CONFIG_LEDS_WNDR3700_USB} += leds-wndr3700-usb.o
|
||||||
|
obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o
|
||||||
|
obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o
|
||||||
|
obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o
|
||||||
|
|
@ -0,0 +1,23 @@
|
||||||
|
--- a/drivers/leds/Kconfig
|
||||||
|
+++ b/drivers/leds/Kconfig
|
||||||
|
@@ -425,6 +425,10 @@ config LEDS_WNDR3700_USB
|
||||||
|
This option enables support for the USB LED found on the
|
||||||
|
NETGEAR WNDR3700 board.
|
||||||
|
|
||||||
|
+config LEDS_RB750
|
||||||
|
+ tristate "LED driver for the Mikrotik RouterBOARD 750"
|
||||||
|
+ depends on LEDS_CLASS && ATH79_MACH_RB750
|
||||||
|
+
|
||||||
|
comment "LED Triggers"
|
||||||
|
|
||||||
|
config LEDS_TRIGGER_TIMER
|
||||||
|
--- a/drivers/leds/Makefile
|
||||||
|
+++ b/drivers/leds/Makefile
|
||||||
|
@@ -42,6 +42,7 @@ obj-$(CONFIG_LEDS_LT3593) += leds-lt359
|
||||||
|
obj-$(CONFIG_LEDS_ADP5520) += leds-adp5520.o
|
||||||
|
obj-$(CONFIG_LEDS_DELL_NETBOOKS) += dell-led.o
|
||||||
|
obj-$(CONFIG_LEDS_MC13783) += leds-mc13783.o
|
||||||
|
+obj-$(CONFIG_LEDS_RB750) += leds-rb750.o
|
||||||
|
obj-$(CONFIG_LEDS_NS2) += leds-ns2.o
|
||||||
|
obj-$(CONFIG_LEDS_NETXBIG) += leds-netxbig.o
|
||||||
|
obj-$(CONFIG_LEDS_ASIC3) += leds-asic3.o
|
||||||
|
|
@ -0,0 +1,26 @@
|
||||||
|
--- a/drivers/gpio/Kconfig
|
||||||
|
+++ b/drivers/gpio/Kconfig
|
||||||
|
@@ -489,4 +489,13 @@ config GPIO_TPS65910
|
||||||
|
help
|
||||||
|
Select this option to enable GPIO driver for the TPS65910
|
||||||
|
chip family.
|
||||||
|
+
|
||||||
|
+comment "Other GPIO expanders"
|
||||||
|
+
|
||||||
|
+config GPIO_NXP_74HC153
|
||||||
|
+ tristate "NXP 74HC153 Dual 4-input multiplexer"
|
||||||
|
+ help
|
||||||
|
+ Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This
|
||||||
|
+ provides a GPIO interface supporting input mode only.
|
||||||
|
+
|
||||||
|
endif
|
||||||
|
--- a/drivers/gpio/Makefile
|
||||||
|
+++ b/drivers/gpio/Makefile
|
||||||
|
@@ -35,6 +35,7 @@ obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2
|
||||||
|
obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o
|
||||||
|
obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o
|
||||||
|
obj-$(CONFIG_PLAT_NOMADIK) += gpio-nomadik.o
|
||||||
|
+obj-$(CONFIG_GPIO_NXP_74HC153) += gpio-nxp-74hc153.o
|
||||||
|
obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o
|
||||||
|
obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o
|
||||||
|
obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o
|
||||||
|
|
@ -0,0 +1,22 @@
|
||||||
|
--- a/arch/mips/Makefile
|
||||||
|
+++ b/arch/mips/Makefile
|
||||||
|
@@ -175,6 +175,7 @@ endif
|
||||||
|
#
|
||||||
|
libs-$(CONFIG_ARC) += arch/mips/fw/arc/
|
||||||
|
libs-$(CONFIG_CFE) += arch/mips/fw/cfe/
|
||||||
|
+libs-$(CONFIG_MYLOADER) += arch/mips/fw/myloader/
|
||||||
|
libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/
|
||||||
|
libs-y += arch/mips/fw/lib/
|
||||||
|
|
||||||
|
--- a/arch/mips/Kconfig
|
||||||
|
+++ b/arch/mips/Kconfig
|
||||||
|
@@ -981,6 +981,9 @@ config MIPS_NILE4
|
||||||
|
config MIPS_DISABLE_OBSOLETE_IDE
|
||||||
|
bool
|
||||||
|
|
||||||
|
+config MYLOADER
|
||||||
|
+ bool
|
||||||
|
+
|
||||||
|
config SYNC_R4K
|
||||||
|
bool
|
||||||
|
|
||||||
|
|
@ -0,0 +1,81 @@
|
||||||
|
--- a/arch/mips/ath79/dev-wmac.c
|
||||||
|
+++ b/arch/mips/ath79/dev-wmac.c
|
||||||
|
@@ -15,6 +15,7 @@
|
||||||
|
#include <linux/init.h>
|
||||||
|
#include <linux/delay.h>
|
||||||
|
#include <linux/irq.h>
|
||||||
|
+#include <linux/etherdevice.h>
|
||||||
|
#include <linux/platform_device.h>
|
||||||
|
#include <linux/ath9k_platform.h>
|
||||||
|
|
||||||
|
@@ -22,6 +23,7 @@
|
||||||
|
#include <asm/mach-ath79/ar71xx_regs.h>
|
||||||
|
#include "dev-wmac.h"
|
||||||
|
|
||||||
|
+static u8 ath79_wmac_mac[ETH_ALEN];
|
||||||
|
static struct ath9k_platform_data ath79_wmac_data;
|
||||||
|
|
||||||
|
static struct resource ath79_wmac_resources[] = {
|
||||||
|
@@ -116,7 +118,7 @@ static void ar934x_wmac_setup(void)
|
||||||
|
ath79_wmac_data.is_clk_25mhz = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
-void __init ath79_register_wmac(u8 *cal_data)
|
||||||
|
+void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
|
||||||
|
{
|
||||||
|
if (soc_is_ar913x())
|
||||||
|
ar913x_wmac_setup();
|
||||||
|
@@ -131,5 +133,10 @@ void __init ath79_register_wmac(u8 *cal_
|
||||||
|
memcpy(ath79_wmac_data.eeprom_data, cal_data,
|
||||||
|
sizeof(ath79_wmac_data.eeprom_data));
|
||||||
|
|
||||||
|
+ if (mac_addr) {
|
||||||
|
+ memcpy(ath79_wmac_mac, mac_addr, sizeof(ath79_wmac_mac));
|
||||||
|
+ ath79_wmac_data.macaddr = ath79_wmac_mac;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
platform_device_register(&ath79_wmac_device);
|
||||||
|
}
|
||||||
|
--- a/arch/mips/ath79/dev-wmac.h
|
||||||
|
+++ b/arch/mips/ath79/dev-wmac.h
|
||||||
|
@@ -12,6 +12,6 @@
|
||||||
|
#ifndef _ATH79_DEV_WMAC_H
|
||||||
|
#define _ATH79_DEV_WMAC_H
|
||||||
|
|
||||||
|
-void ath79_register_wmac(u8 *cal_data);
|
||||||
|
+void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
|
||||||
|
|
||||||
|
#endif /* _ATH79_DEV_WMAC_H */
|
||||||
|
--- a/arch/mips/ath79/mach-ap81.c
|
||||||
|
+++ b/arch/mips/ath79/mach-ap81.c
|
||||||
|
@@ -98,7 +98,7 @@ static void __init ap81_setup(void)
|
||||||
|
ap81_gpio_keys);
|
||||||
|
ath79_register_spi(&ap81_spi_data, ap81_spi_info,
|
||||||
|
ARRAY_SIZE(ap81_spi_info));
|
||||||
|
- ath79_register_wmac(cal_data);
|
||||||
|
+ ath79_register_wmac(cal_data, NULL);
|
||||||
|
ath79_register_usb();
|
||||||
|
}
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/mach-db120.c
|
||||||
|
+++ b/arch/mips/ath79/mach-db120.c
|
||||||
|
@@ -153,7 +153,7 @@ static void __init db120_setup(void)
|
||||||
|
ath79_register_spi(&db120_spi_data, db120_spi_info,
|
||||||
|
ARRAY_SIZE(db120_spi_info));
|
||||||
|
ath79_register_usb();
|
||||||
|
- ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
|
||||||
|
+ ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
|
||||||
|
db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
|
||||||
|
}
|
||||||
|
|
||||||
|
--- a/arch/mips/ath79/mach-ap121.c
|
||||||
|
+++ b/arch/mips/ath79/mach-ap121.c
|
||||||
|
@@ -91,7 +91,7 @@ static void __init ap121_setup(void)
|
||||||
|
ath79_register_spi(&ap121_spi_data, ap121_spi_info,
|
||||||
|
ARRAY_SIZE(ap121_spi_info));
|
||||||
|
ath79_register_usb();
|
||||||
|
- ath79_register_wmac(cal_data);
|
||||||
|
+ ath79_register_wmac(cal_data, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
|
||||||
|
|
@ -0,0 +1,23 @@
|
||||||
|
--- a/arch/mips/ath79/gpio.c
|
||||||
|
+++ b/arch/mips/ath79/gpio.c
|
||||||
|
@@ -25,7 +25,9 @@
|
||||||
|
#include <asm/mach-ath79/ath79.h>
|
||||||
|
#include "common.h"
|
||||||
|
|
||||||
|
-static void __iomem *ath79_gpio_base;
|
||||||
|
+void __iomem *ath79_gpio_base;
|
||||||
|
+EXPORT_SYMBOL_GPL(ath79_gpio_base);
|
||||||
|
+
|
||||||
|
static unsigned long ath79_gpio_count;
|
||||||
|
static DEFINE_SPINLOCK(ath79_gpio_lock);
|
||||||
|
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/ath79.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
|
||||||
|
@@ -99,6 +99,7 @@ static inline int soc_is_ar934x(void)
|
||||||
|
}
|
||||||
|
|
||||||
|
extern void __iomem *ath79_ddr_base;
|
||||||
|
+extern void __iomem *ath79_gpio_base;
|
||||||
|
extern void __iomem *ath79_pll_base;
|
||||||
|
extern void __iomem *ath79_reset_base;
|
||||||
|
|
||||||
|
|
@ -0,0 +1,37 @@
|
||||||
|
--- a/arch/mips/ath79/common.c
|
||||||
|
+++ b/arch/mips/ath79/common.c
|
||||||
|
@@ -22,6 +22,7 @@
|
||||||
|
#include "common.h"
|
||||||
|
|
||||||
|
static DEFINE_SPINLOCK(ath79_device_reset_lock);
|
||||||
|
+static DEFINE_MUTEX(ath79_flash_mutex);
|
||||||
|
|
||||||
|
u32 ath79_cpu_freq;
|
||||||
|
EXPORT_SYMBOL_GPL(ath79_cpu_freq);
|
||||||
|
@@ -107,3 +108,16 @@ void ath79_device_reset_clear(u32 mask)
|
||||||
|
spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
|
||||||
|
+
|
||||||
|
+void ath79_flash_acquire(void)
|
||||||
|
+{
|
||||||
|
+ mutex_lock(&ath79_flash_mutex);
|
||||||
|
+}
|
||||||
|
+EXPORT_SYMBOL_GPL(ath79_flash_acquire);
|
||||||
|
+
|
||||||
|
+void ath79_flash_release(void)
|
||||||
|
+{
|
||||||
|
+ mutex_unlock(&ath79_flash_mutex);
|
||||||
|
+}
|
||||||
|
+EXPORT_SYMBOL_GPL(ath79_flash_release);
|
||||||
|
+
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/ath79.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
|
||||||
|
@@ -126,4 +126,7 @@ static inline u32 ath79_reset_rr(unsigne
|
||||||
|
void ath79_device_reset_set(u32 mask);
|
||||||
|
void ath79_device_reset_clear(u32 mask);
|
||||||
|
|
||||||
|
+void ath79_flash_acquire(void);
|
||||||
|
+void ath79_flash_release(void);
|
||||||
|
+
|
||||||
|
#endif /* __ASM_MACH_ATH79_H */
|
||||||
|
|
@ -0,0 +1,45 @@
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/ath79.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
|
||||||
|
@@ -125,6 +125,7 @@ static inline u32 ath79_reset_rr(unsigne
|
||||||
|
|
||||||
|
void ath79_device_reset_set(u32 mask);
|
||||||
|
void ath79_device_reset_clear(u32 mask);
|
||||||
|
+u32 ath79_device_reset_get(u32 mask);
|
||||||
|
|
||||||
|
void ath79_flash_acquire(void);
|
||||||
|
void ath79_flash_release(void);
|
||||||
|
--- a/arch/mips/ath79/common.c
|
||||||
|
+++ b/arch/mips/ath79/common.c
|
||||||
|
@@ -109,6 +109,32 @@ void ath79_device_reset_clear(u32 mask)
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
|
||||||
|
|
||||||
|
+u32 ath79_device_reset_get(u32 mask)
|
||||||
|
+{
|
||||||
|
+ unsigned long flags;
|
||||||
|
+ u32 reg;
|
||||||
|
+ u32 ret;
|
||||||
|
+
|
||||||
|
+ if (soc_is_ar71xx())
|
||||||
|
+ reg = AR71XX_RESET_REG_RESET_MODULE;
|
||||||
|
+ else if (soc_is_ar724x())
|
||||||
|
+ reg = AR724X_RESET_REG_RESET_MODULE;
|
||||||
|
+ else if (soc_is_ar913x())
|
||||||
|
+ reg = AR913X_RESET_REG_RESET_MODULE;
|
||||||
|
+ else if (soc_is_ar933x())
|
||||||
|
+ reg = AR933X_RESET_REG_RESET_MODULE;
|
||||||
|
+ else if (soc_is_ar934x())
|
||||||
|
+ reg = AR934X_RESET_REG_RESET_MODULE;
|
||||||
|
+ else
|
||||||
|
+ BUG();
|
||||||
|
+
|
||||||
|
+ spin_lock_irqsave(&ath79_device_reset_lock, flags);
|
||||||
|
+ ret = ath79_reset_rr(reg);
|
||||||
|
+ spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
|
||||||
|
+ return ret;
|
||||||
|
+}
|
||||||
|
+EXPORT_SYMBOL_GPL(ath79_device_reset_get);
|
||||||
|
+
|
||||||
|
void ath79_flash_acquire(void)
|
||||||
|
{
|
||||||
|
mutex_lock(&ath79_flash_mutex);
|
||||||
|
|
@ -0,0 +1,47 @@
|
||||||
|
--- a/arch/mips/ath79/common.h
|
||||||
|
+++ b/arch/mips/ath79/common.h
|
||||||
|
@@ -26,6 +26,7 @@ void ath79_ddr_wb_flush(unsigned int reg
|
||||||
|
void ath79_gpio_function_enable(u32 mask);
|
||||||
|
void ath79_gpio_function_disable(u32 mask);
|
||||||
|
void ath79_gpio_function_setup(u32 set, u32 clear);
|
||||||
|
+void ath79_gpio_output_select(unsigned gpio, u8 val);
|
||||||
|
void ath79_gpio_init(void);
|
||||||
|
|
||||||
|
#endif /* __ATH79_COMMON_H */
|
||||||
|
--- a/arch/mips/ath79/gpio.c
|
||||||
|
+++ b/arch/mips/ath79/gpio.c
|
||||||
|
@@ -184,6 +184,34 @@ void ath79_gpio_function_setup(u32 set,
|
||||||
|
spin_unlock_irqrestore(&ath79_gpio_lock, flags);
|
||||||
|
}
|
||||||
|
|
||||||
|
+void __init ath79_gpio_output_select(unsigned gpio, u8 val)
|
||||||
|
+{
|
||||||
|
+ void __iomem *base = ath79_gpio_base;
|
||||||
|
+ unsigned long flags;
|
||||||
|
+ unsigned int reg;
|
||||||
|
+ u32 t, s;
|
||||||
|
+
|
||||||
|
+ BUG_ON(!soc_is_ar934x());
|
||||||
|
+
|
||||||
|
+ if (gpio >= AR934X_GPIO_COUNT)
|
||||||
|
+ return;
|
||||||
|
+
|
||||||
|
+ reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
|
||||||
|
+ s = 8 * (gpio % 4);
|
||||||
|
+
|
||||||
|
+ spin_lock_irqsave(&ath79_gpio_lock, flags);
|
||||||
|
+
|
||||||
|
+ t = __raw_readl(base + reg);
|
||||||
|
+ t &= ~(0xff << s);
|
||||||
|
+ t |= val << s;
|
||||||
|
+ __raw_writel(t, base + reg);
|
||||||
|
+
|
||||||
|
+ /* flush write */
|
||||||
|
+ (void) __raw_readl(base + reg);
|
||||||
|
+
|
||||||
|
+ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
void __init ath79_gpio_init(void)
|
||||||
|
{
|
||||||
|
int err;
|
||||||
|
|
@ -0,0 +1,86 @@
|
||||||
|
--- a/arch/mips/ath79/prom.c
|
||||||
|
+++ b/arch/mips/ath79/prom.c
|
||||||
|
@@ -19,6 +19,8 @@
|
||||||
|
|
||||||
|
#include "common.h"
|
||||||
|
|
||||||
|
+static char ath79_cmdline_buf[COMMAND_LINE_SIZE] __initdata;
|
||||||
|
+
|
||||||
|
static inline int is_valid_ram_addr(void *addr)
|
||||||
|
{
|
||||||
|
if (((u32) addr > KSEG0) &&
|
||||||
|
@@ -32,6 +34,41 @@ static inline int is_valid_ram_addr(void
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
+static void __init ath79_prom_append_cmdline(const char *name,
|
||||||
|
+ const char *value)
|
||||||
|
+{
|
||||||
|
+ snprintf(ath79_cmdline_buf, sizeof(ath79_cmdline_buf),
|
||||||
|
+ " %s=%s", name, value);
|
||||||
|
+ strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline));
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static const char * __init ath79_prom_find_env(char **envp, const char *name)
|
||||||
|
+{
|
||||||
|
+ const char *ret = NULL;
|
||||||
|
+ int len;
|
||||||
|
+ char **p;
|
||||||
|
+
|
||||||
|
+ if (!is_valid_ram_addr(envp))
|
||||||
|
+ return NULL;
|
||||||
|
+
|
||||||
|
+ len = strlen(name);
|
||||||
|
+ for (p = envp; is_valid_ram_addr(*p); p++) {
|
||||||
|
+ if (strncmp(name, *p, len) == 0 && (*p)[len] == '=') {
|
||||||
|
+ ret = *p + len + 1;
|
||||||
|
+ break;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ /* RedBoot env comes in pointer pairs - key, value */
|
||||||
|
+ if (strncmp(name, *p, len) == 0 && (*p)[len] == 0)
|
||||||
|
+ if (is_valid_ram_addr(*(++p))) {
|
||||||
|
+ ret = *p;
|
||||||
|
+ break;
|
||||||
|
+ }
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ return ret;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static __init void ath79_prom_init_cmdline(int argc, char **argv)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
@@ -48,7 +85,32 @@ static __init void ath79_prom_init_cmdli
|
||||||
|
|
||||||
|
void __init prom_init(void)
|
||||||
|
{
|
||||||
|
+ const char *env;
|
||||||
|
+ char **envp;
|
||||||
|
+
|
||||||
|
ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1);
|
||||||
|
+
|
||||||
|
+ envp = (char **)fw_arg2;
|
||||||
|
+ if (!strstr(arcs_cmdline, "ethaddr=")) {
|
||||||
|
+ env = ath79_prom_find_env(envp, "ethaddr");
|
||||||
|
+ if (env)
|
||||||
|
+ ath79_prom_append_cmdline("ethaddr", env);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ if (!strstr(arcs_cmdline, "board=")) {
|
||||||
|
+ env = ath79_prom_find_env(envp, "board");
|
||||||
|
+ if (env) {
|
||||||
|
+ /* Workaround for buggy bootloaders */
|
||||||
|
+ if (strcmp(env, "RouterStation") == 0 ||
|
||||||
|
+ strcmp(env, "Ubiquiti AR71xx-based board") == 0)
|
||||||
|
+ env = "UBNT-RS";
|
||||||
|
+
|
||||||
|
+ if (strcmp(env, "RouterStation PRO") == 0)
|
||||||
|
+ env = "UBNT-RSPRO";
|
||||||
|
+
|
||||||
|
+ ath79_prom_append_cmdline("board", env);
|
||||||
|
+ }
|
||||||
|
+ }
|
||||||
|
}
|
||||||
|
|
||||||
|
void __init prom_free_prom_memory(void)
|
||||||
|
|
@ -0,0 +1,55 @@
|
||||||
|
--- a/arch/mips/ath79/prom.c
|
||||||
|
+++ b/arch/mips/ath79/prom.c
|
||||||
|
@@ -16,6 +16,7 @@
|
||||||
|
|
||||||
|
#include <asm/bootinfo.h>
|
||||||
|
#include <asm/addrspace.h>
|
||||||
|
+#include <asm/fw/myloader/myloader.h>
|
||||||
|
|
||||||
|
#include "common.h"
|
||||||
|
|
||||||
|
@@ -69,6 +70,34 @@ static const char * __init ath79_prom_fi
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
+static int __init ath79_prom_init_myloader(void)
|
||||||
|
+{
|
||||||
|
+ struct myloader_info *mylo;
|
||||||
|
+ char mac_buf[32];
|
||||||
|
+ unsigned char *mac;
|
||||||
|
+
|
||||||
|
+ mylo = myloader_get_info();
|
||||||
|
+ if (!mylo)
|
||||||
|
+ return 0;
|
||||||
|
+
|
||||||
|
+ switch (mylo->did) {
|
||||||
|
+ case DEVID_COMPEX_WP543:
|
||||||
|
+ ath79_prom_append_cmdline("board", "WP543");
|
||||||
|
+ break;
|
||||||
|
+ default:
|
||||||
|
+ pr_warn("prom: unknown device id: %x\n", mylo->did);
|
||||||
|
+ return 0;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ mac = mylo->macs[0];
|
||||||
|
+ snprintf(mac_buf, sizeof(mac_buf), "%02x:%02x:%02x:%02x:%02x:%02x",
|
||||||
|
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
|
||||||
|
+
|
||||||
|
+ ath79_prom_append_cmdline("ethaddr", mac_buf);
|
||||||
|
+
|
||||||
|
+ return 1;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static __init void ath79_prom_init_cmdline(int argc, char **argv)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
@@ -88,6 +117,9 @@ void __init prom_init(void)
|
||||||
|
const char *env;
|
||||||
|
char **envp;
|
||||||
|
|
||||||
|
+ if (ath79_prom_init_myloader())
|
||||||
|
+ return;
|
||||||
|
+
|
||||||
|
ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1);
|
||||||
|
|
||||||
|
envp = (char **)fw_arg2;
|
||||||
|
|
@ -0,0 +1,57 @@
|
||||||
|
--- a/arch/mips/ath79/prom.c
|
||||||
|
+++ b/arch/mips/ath79/prom.c
|
||||||
|
@@ -70,6 +70,35 @@ static const char * __init ath79_prom_fi
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
+#ifdef CONFIG_IMAGE_CMDLINE_HACK
|
||||||
|
+extern char __image_cmdline[];
|
||||||
|
+
|
||||||
|
+static int __init ath79_use_image_cmdline(void)
|
||||||
|
+{
|
||||||
|
+ char *p = __image_cmdline;
|
||||||
|
+ int replace = 0;
|
||||||
|
+
|
||||||
|
+ if (*p == '-') {
|
||||||
|
+ replace = 1;
|
||||||
|
+ p++;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ if (*p == '\0')
|
||||||
|
+ return 0;
|
||||||
|
+
|
||||||
|
+ if (replace) {
|
||||||
|
+ strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline));
|
||||||
|
+ } else {
|
||||||
|
+ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
|
||||||
|
+ strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ return 1;
|
||||||
|
+}
|
||||||
|
+#else
|
||||||
|
+static inline int ath79_use_image_cmdline(void) { return 0; }
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
static int __init ath79_prom_init_myloader(void)
|
||||||
|
{
|
||||||
|
struct myloader_info *mylo;
|
||||||
|
@@ -95,6 +124,8 @@ static int __init ath79_prom_init_myload
|
||||||
|
|
||||||
|
ath79_prom_append_cmdline("ethaddr", mac_buf);
|
||||||
|
|
||||||
|
+ ath79_use_image_cmdline();
|
||||||
|
+
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -102,6 +133,9 @@ static __init void ath79_prom_init_cmdli
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
+ if (ath79_use_image_cmdline())
|
||||||
|
+ return;
|
||||||
|
+
|
||||||
|
if (!is_valid_ram_addr(argv))
|
||||||
|
return;
|
||||||
|
|
||||||
|
|
@ -0,0 +1,11 @@
|
||||||
|
--- a/arch/mips/ath79/setup.c
|
||||||
|
+++ b/arch/mips/ath79/setup.c
|
||||||
|
@@ -215,6 +215,8 @@ void __init plat_time_init(void)
|
||||||
|
mips_hpt_frequency = clk_get_rate(clk) / 2;
|
||||||
|
}
|
||||||
|
|
||||||
|
+__setup("board=", mips_machtype_setup);
|
||||||
|
+
|
||||||
|
static int __init ath79_setup(void)
|
||||||
|
{
|
||||||
|
ath79_gpio_init();
|
||||||
|
|
@ -0,0 +1,14 @@
|
||||||
|
--- a/arch/mips/ath79/dev-wmac.c
|
||||||
|
+++ b/arch/mips/ath79/dev-wmac.c
|
||||||
|
@@ -24,7 +24,10 @@
|
||||||
|
#include "dev-wmac.h"
|
||||||
|
|
||||||
|
static u8 ath79_wmac_mac[ETH_ALEN];
|
||||||
|
-static struct ath9k_platform_data ath79_wmac_data;
|
||||||
|
+
|
||||||
|
+static struct ath9k_platform_data ath79_wmac_data = {
|
||||||
|
+ .led_pin = -1,
|
||||||
|
+};
|
||||||
|
|
||||||
|
static struct resource ath79_wmac_resources[] = {
|
||||||
|
{
|
||||||
|
|
@ -0,0 +1,231 @@
|
||||||
|
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||||
|
@@ -20,7 +20,13 @@
|
||||||
|
#include <linux/io.h>
|
||||||
|
#include <linux/bitops.h>
|
||||||
|
|
||||||
|
+#define AR71XX_PCI_MEM_BASE 0x10000000
|
||||||
|
+#define AR71XX_PCI_MEM_SIZE 0x08000000
|
||||||
|
#define AR71XX_APB_BASE 0x18000000
|
||||||
|
+#define AR71XX_GE0_BASE 0x19000000
|
||||||
|
+#define AR71XX_GE0_SIZE 0x10000
|
||||||
|
+#define AR71XX_GE1_BASE 0x1a000000
|
||||||
|
+#define AR71XX_GE1_SIZE 0x10000
|
||||||
|
#define AR71XX_EHCI_BASE 0x1b000000
|
||||||
|
#define AR71XX_EHCI_SIZE 0x1000
|
||||||
|
#define AR71XX_OHCI_BASE 0x1c000000
|
||||||
|
@@ -40,6 +46,8 @@
|
||||||
|
#define AR71XX_PLL_SIZE 0x100
|
||||||
|
#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
|
||||||
|
#define AR71XX_RESET_SIZE 0x100
|
||||||
|
+#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
|
||||||
|
+#define AR71XX_MII_SIZE 0x100
|
||||||
|
|
||||||
|
#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
|
||||||
|
#define AR7240_USB_CTRL_SIZE 0x100
|
||||||
|
@@ -56,11 +64,15 @@
|
||||||
|
|
||||||
|
#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
|
||||||
|
#define AR933X_UART_SIZE 0x14
|
||||||
|
+#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
|
||||||
|
+#define AR933X_GMAC_SIZE 0x04
|
||||||
|
#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
|
||||||
|
#define AR933X_WMAC_SIZE 0x20000
|
||||||
|
#define AR933X_EHCI_BASE 0x1b000000
|
||||||
|
#define AR933X_EHCI_SIZE 0x1000
|
||||||
|
|
||||||
|
+#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
|
||||||
|
+#define AR934X_GMAC_SIZE 0x14
|
||||||
|
#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
|
||||||
|
#define AR934X_WMAC_SIZE 0x20000
|
||||||
|
#define AR934X_EHCI_BASE 0x1b000000
|
||||||
|
@@ -120,6 +132,9 @@
|
||||||
|
#define AR71XX_AHB_DIV_SHIFT 20
|
||||||
|
#define AR71XX_AHB_DIV_MASK 0x7
|
||||||
|
|
||||||
|
+#define AR71XX_ETH0_PLL_SHIFT 17
|
||||||
|
+#define AR71XX_ETH1_PLL_SHIFT 19
|
||||||
|
+
|
||||||
|
#define AR724X_PLL_REG_CPU_CONFIG 0x00
|
||||||
|
#define AR724X_PLL_REG_PCIE_CONFIG 0x18
|
||||||
|
|
||||||
|
@@ -132,6 +147,8 @@
|
||||||
|
#define AR724X_DDR_DIV_SHIFT 22
|
||||||
|
#define AR724X_DDR_DIV_MASK 0x3
|
||||||
|
|
||||||
|
+#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
|
||||||
|
+
|
||||||
|
#define AR913X_PLL_REG_CPU_CONFIG 0x00
|
||||||
|
#define AR913X_PLL_REG_ETH_CONFIG 0x04
|
||||||
|
#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
|
||||||
|
@@ -144,6 +161,9 @@
|
||||||
|
#define AR913X_AHB_DIV_SHIFT 19
|
||||||
|
#define AR913X_AHB_DIV_MASK 0x1
|
||||||
|
|
||||||
|
+#define AR913X_ETH0_PLL_SHIFT 20
|
||||||
|
+#define AR913X_ETH1_PLL_SHIFT 22
|
||||||
|
+
|
||||||
|
#define AR933X_PLL_CPU_CONFIG_REG 0x00
|
||||||
|
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
|
||||||
|
|
||||||
|
@@ -285,7 +305,11 @@
|
||||||
|
#define AR913X_RESET_USB_HOST BIT(5)
|
||||||
|
#define AR913X_RESET_USB_PHY BIT(4)
|
||||||
|
|
||||||
|
+#define AR933X_RESET_GE1_MDIO BIT(23)
|
||||||
|
+#define AR933X_RESET_GE0_MDIO BIT(22)
|
||||||
|
+#define AR933X_RESET_GE1_MAC BIT(13)
|
||||||
|
#define AR933X_RESET_WMAC BIT(11)
|
||||||
|
+#define AR933X_RESET_GE0_MAC BIT(9)
|
||||||
|
#define AR933X_RESET_USB_HOST BIT(5)
|
||||||
|
#define AR933X_RESET_USB_PHY BIT(4)
|
||||||
|
#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
|
||||||
|
@@ -323,6 +347,8 @@
|
||||||
|
#define AR934X_RESET_MBOX BIT(1)
|
||||||
|
#define AR934X_RESET_I2S BIT(0)
|
||||||
|
|
||||||
|
+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
|
||||||
|
+#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
|
||||||
|
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
|
||||||
|
|
||||||
|
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
|
||||||
|
@@ -427,6 +453,14 @@
|
||||||
|
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
|
||||||
|
#define AR71XX_GPIO_REG_FUNC 0x28
|
||||||
|
|
||||||
|
+#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
|
||||||
|
+#define AR934X_GPIO_REG_OUT_FUNC1 0x30
|
||||||
|
+#define AR934X_GPIO_REG_OUT_FUNC2 0x34
|
||||||
|
+#define AR934X_GPIO_REG_OUT_FUNC3 0x38
|
||||||
|
+#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
|
||||||
|
+#define AR934X_GPIO_REG_OUT_FUNC5 0x40
|
||||||
|
+#define AR934X_GPIO_REG_FUNC 0x6c
|
||||||
|
+
|
||||||
|
#define AR71XX_GPIO_COUNT 16
|
||||||
|
#define AR7240_GPIO_COUNT 18
|
||||||
|
#define AR7241_GPIO_COUNT 20
|
||||||
|
@@ -434,4 +468,124 @@
|
||||||
|
#define AR933X_GPIO_COUNT 30
|
||||||
|
#define AR934X_GPIO_COUNT 23
|
||||||
|
|
||||||
|
+#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
|
||||||
|
+#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
|
||||||
|
+#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
|
||||||
|
+#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
|
||||||
|
+#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
|
||||||
|
+#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
|
||||||
|
+#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
|
||||||
|
+
|
||||||
|
+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
|
||||||
|
+#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
|
||||||
|
+#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
|
||||||
|
+#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
|
||||||
|
+#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
|
||||||
|
+#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
|
||||||
|
+#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
|
||||||
|
+#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
|
||||||
|
+#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
|
||||||
|
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
|
||||||
|
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
|
||||||
|
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
|
||||||
|
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
|
||||||
|
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
|
||||||
|
+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
|
||||||
|
+#define AR724X_GPIO_FUNC_UART_EN BIT(1)
|
||||||
|
+#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
|
||||||
|
+
|
||||||
|
+#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
|
||||||
|
+#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
|
||||||
|
+#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
|
||||||
|
+#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
|
||||||
|
+#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
|
||||||
|
+#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
|
||||||
|
+#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
|
||||||
|
+#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
|
||||||
|
+#define AR913X_GPIO_FUNC_UART_EN BIT(8)
|
||||||
|
+#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
|
||||||
|
+
|
||||||
|
+#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
|
||||||
|
+#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
|
||||||
|
+#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
|
||||||
|
+#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
|
||||||
|
+#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
|
||||||
|
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
|
||||||
|
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
|
||||||
|
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
|
||||||
|
+#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
|
||||||
|
+#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
|
||||||
|
+#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
|
||||||
|
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
|
||||||
|
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
|
||||||
|
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
|
||||||
|
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
|
||||||
|
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
|
||||||
|
+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
|
||||||
|
+#define AR933X_GPIO_FUNC_UART_EN BIT(1)
|
||||||
|
+#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
|
||||||
|
+
|
||||||
|
+#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17)
|
||||||
|
+#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14)
|
||||||
|
+#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13)
|
||||||
|
+
|
||||||
|
+#define AR934X_GPIO_OUT_GPIO 0x00
|
||||||
|
+
|
||||||
|
+/*
|
||||||
|
+ * MII_CTRL block
|
||||||
|
+ */
|
||||||
|
+#define AR71XX_MII_REG_MII0_CTRL 0x00
|
||||||
|
+#define AR71XX_MII_REG_MII1_CTRL 0x04
|
||||||
|
+
|
||||||
|
+#define AR71XX_MII_CTRL_IF_MASK 3
|
||||||
|
+#define AR71XX_MII_CTRL_SPEED_SHIFT 4
|
||||||
|
+#define AR71XX_MII_CTRL_SPEED_MASK 3
|
||||||
|
+#define AR71XX_MII_CTRL_SPEED_10 0
|
||||||
|
+#define AR71XX_MII_CTRL_SPEED_100 1
|
||||||
|
+#define AR71XX_MII_CTRL_SPEED_1000 2
|
||||||
|
+
|
||||||
|
+#define AR71XX_MII0_CTRL_IF_GMII 0
|
||||||
|
+#define AR71XX_MII0_CTRL_IF_MII 1
|
||||||
|
+#define AR71XX_MII0_CTRL_IF_RGMII 2
|
||||||
|
+#define AR71XX_MII0_CTRL_IF_RMII 3
|
||||||
|
+
|
||||||
|
+#define AR71XX_MII1_CTRL_IF_RGMII 0
|
||||||
|
+#define AR71XX_MII1_CTRL_IF_RMII 1
|
||||||
|
+
|
||||||
|
+/*
|
||||||
|
+ * AR933X GMAC interface
|
||||||
|
+ */
|
||||||
|
+#define AR933X_GMAC_REG_ETH_CFG 0x00
|
||||||
|
+
|
||||||
|
+#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
|
||||||
|
+#define AR933X_ETH_CFG_MII_GE0 BIT(1)
|
||||||
|
+#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
|
||||||
|
+#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
|
||||||
|
+#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
|
||||||
|
+#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
|
||||||
|
+#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
|
||||||
|
+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
|
||||||
|
+#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
|
||||||
|
+#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
|
||||||
|
+#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
|
||||||
|
+
|
||||||
|
+/*
|
||||||
|
+ * AR934X GMAC Interface
|
||||||
|
+ */
|
||||||
|
+#define AR934X_GMAC_REG_ETH_CFG 0x00
|
||||||
|
+
|
||||||
|
+#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
|
||||||
|
+#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
|
||||||
|
+#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
|
||||||
|
+#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
|
||||||
|
+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
|
||||||
|
+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
|
||||||
|
+#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
|
||||||
|
+#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
|
||||||
|
+#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
|
||||||
|
+#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
|
||||||
|
+#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
|
||||||
|
+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
|
||||||
|
+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
|
||||||
|
+
|
||||||
|
#endif /* __ASM_MACH_AR71XX_REGS_H */
|
||||||
|
|
@ -0,0 +1,60 @@
|
||||||
|
--- a/arch/mips/ath79/Kconfig
|
||||||
|
+++ b/arch/mips/ath79/Kconfig
|
||||||
|
@@ -88,6 +88,20 @@ config SOC_AR934X
|
||||||
|
select PCI_AR724X if PCI
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
+config ATH79_DEV_M25P80
|
||||||
|
+ select ATH79_DEV_SPI
|
||||||
|
+ def_bool n
|
||||||
|
+
|
||||||
|
+config ATH79_DEV_AP9X_PCI
|
||||||
|
+ select ATH79_PCI_ATH9K_FIXUP
|
||||||
|
+ def_bool n
|
||||||
|
+
|
||||||
|
+config ATH79_DEV_DSA
|
||||||
|
+ def_bool n
|
||||||
|
+
|
||||||
|
+config ATH79_DEV_ETH
|
||||||
|
+ def_bool n
|
||||||
|
+
|
||||||
|
config PCI_AR724X
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
@@ -107,4 +121,10 @@ config ATH79_DEV_WMAC
|
||||||
|
depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X)
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
+config ATH79_NVRAM
|
||||||
|
+ def_bool n
|
||||||
|
+
|
||||||
|
+config ATH79_PCI_ATH9K_FIXUP
|
||||||
|
+ def_bool n
|
||||||
|
+
|
||||||
|
endif
|
||||||
|
--- a/arch/mips/ath79/Makefile
|
||||||
|
+++ b/arch/mips/ath79/Makefile
|
||||||
|
@@ -17,13 +17,23 @@ obj-$(CONFIG_PCI) += pci.o
|
||||||
|
# Devices
|
||||||
|
#
|
||||||
|
obj-y += dev-common.o
|
||||||
|
+obj-$(CONFIG_ATH79_DEV_AP9X_PCI) += dev-ap9x-pci.o
|
||||||
|
+obj-$(CONFIG_ATH79_DEV_DSA) += dev-dsa.o
|
||||||
|
+obj-$(CONFIG_ATH79_DEV_ETH) += dev-eth.o
|
||||||
|
obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o
|
||||||
|
obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o
|
||||||
|
+obj-$(CONFIG_ATH79_DEV_M25P80) += dev-m25p80.o
|
||||||
|
obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
|
||||||
|
obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
|
||||||
|
obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o
|
||||||
|
|
||||||
|
#
|
||||||
|
+# Miscellaneous objects
|
||||||
|
+#
|
||||||
|
+obj-$(CONFIG_ATH79_NVRAM) += nvram.o
|
||||||
|
+obj-$(CONFIG_ATH79_PCI_ATH9K_FIXUP) += pci-ath9k-fixup.o
|
||||||
|
+
|
||||||
|
+#
|
||||||
|
# Machines
|
||||||
|
#
|
||||||
|
obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
|
||||||
|
|
@ -0,0 +1,240 @@
|
||||||
|
--- a/arch/mips/ath79/mach-ap121.c
|
||||||
|
+++ b/arch/mips/ath79/mach-ap121.c
|
||||||
|
@@ -1,19 +1,23 @@
|
||||||
|
/*
|
||||||
|
* Atheros AP121 board support
|
||||||
|
*
|
||||||
|
- * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License version 2 as published
|
||||||
|
* by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
+#include <linux/mtd/mtd.h>
|
||||||
|
+#include <linux/mtd/partitions.h>
|
||||||
|
|
||||||
|
-#include "machtypes.h"
|
||||||
|
+#include "dev-eth.h"
|
||||||
|
#include "dev-gpio-buttons.h"
|
||||||
|
#include "dev-leds-gpio.h"
|
||||||
|
+#include "dev-m25p80.h"
|
||||||
|
#include "dev-spi.h"
|
||||||
|
#include "dev-usb.h"
|
||||||
|
#include "dev-wmac.h"
|
||||||
|
+#include "machtypes.h"
|
||||||
|
|
||||||
|
#define AP121_GPIO_LED_WLAN 0
|
||||||
|
#define AP121_GPIO_LED_USB 1
|
||||||
|
@@ -24,7 +28,82 @@
|
||||||
|
#define AP121_KEYS_POLL_INTERVAL 20 /* msecs */
|
||||||
|
#define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL)
|
||||||
|
|
||||||
|
-#define AP121_CAL_DATA_ADDR 0x1fff1000
|
||||||
|
+#define AP121_MAC0_OFFSET 0x0000
|
||||||
|
+#define AP121_MAC1_OFFSET 0x0006
|
||||||
|
+#define AP121_CALDATA_OFFSET 0x1000
|
||||||
|
+#define AP121_WMAC_MAC_OFFSET 0x1002
|
||||||
|
+
|
||||||
|
+#define AP121_MINI_GPIO_LED_WLAN 0
|
||||||
|
+#define AP121_MINI_GPIO_BTN_JUMPSTART 12
|
||||||
|
+#define AP121_MINI_GPIO_BTN_RESET 11
|
||||||
|
+
|
||||||
|
+static struct mtd_partition ap121_parts[] = {
|
||||||
|
+ {
|
||||||
|
+ .name = "u-boot",
|
||||||
|
+ .offset = 0,
|
||||||
|
+ .size = 0x010000,
|
||||||
|
+ .mask_flags = MTD_WRITEABLE,
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
+ .name = "rootfs",
|
||||||
|
+ .offset = 0x010000,
|
||||||
|
+ .size = 0x130000,
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
+ .name = "uImage",
|
||||||
|
+ .offset = 0x140000,
|
||||||
|
+ .size = 0x0a0000,
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
+ .name = "NVRAM",
|
||||||
|
+ .offset = 0x1e0000,
|
||||||
|
+ .size = 0x010000,
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
+ .name = "ART",
|
||||||
|
+ .offset = 0x1f0000,
|
||||||
|
+ .size = 0x010000,
|
||||||
|
+ .mask_flags = MTD_WRITEABLE,
|
||||||
|
+ },
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct mtd_partition ap121_mini_parts[] = {
|
||||||
|
+ {
|
||||||
|
+ .name = "u-boot",
|
||||||
|
+ .offset = 0,
|
||||||
|
+ .size = 0x040000,
|
||||||
|
+ .mask_flags = MTD_WRITEABLE,
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
+ .name = "u-boot-env",
|
||||||
|
+ .offset = 0x040000,
|
||||||
|
+ .size = 0x010000,
|
||||||
|
+ .mask_flags = MTD_WRITEABLE,
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
+ .name = "rootfs",
|
||||||
|
+ .offset = 0x050000,
|
||||||
|
+ .size = 0x2b0000,
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
+ .name = "uImage",
|
||||||
|
+ .offset = 0x300000,
|
||||||
|
+ .size = 0x0e0000,
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
+ .name = "NVRAM",
|
||||||
|
+ .offset = 0x3e0000,
|
||||||
|
+ .size = 0x010000,
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
+ .name = "ART",
|
||||||
|
+ .offset = 0x3f0000,
|
||||||
|
+ .size = 0x010000,
|
||||||
|
+ .mask_flags = MTD_WRITEABLE,
|
||||||
|
+ },
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct flash_platform_data ap121_flash_data;
|
||||||
|
|
||||||
|
static struct gpio_led ap121_leds_gpio[] __initdata = {
|
||||||
|
{
|
||||||
|
@@ -58,41 +137,84 @@ static struct gpio_keys_button ap121_gpi
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
-static struct ath79_spi_controller_data ap121_spi0_data = {
|
||||||
|
- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
|
||||||
|
- .cs_line = 0,
|
||||||
|
+static struct gpio_led ap121_mini_leds_gpio[] __initdata = {
|
||||||
|
+ {
|
||||||
|
+ .name = "ap121:green:wlan",
|
||||||
|
+ .gpio = AP121_MINI_GPIO_LED_WLAN,
|
||||||
|
+ .active_low = 0,
|
||||||
|
+ },
|
||||||
|
};
|
||||||
|
|
||||||
|
-static struct spi_board_info ap121_spi_info[] = {
|
||||||
|
- {
|
||||||
|
- .bus_num = 0,
|
||||||
|
- .chip_select = 0,
|
||||||
|
- .max_speed_hz = 25000000,
|
||||||
|
- .modalias = "mx25l1606e",
|
||||||
|
- .controller_data = &ap121_spi0_data,
|
||||||
|
+static struct gpio_keys_button ap121_mini_gpio_keys[] __initdata = {
|
||||||
|
+ {
|
||||||
|
+ .desc = "jumpstart button",
|
||||||
|
+ .type = EV_KEY,
|
||||||
|
+ .code = KEY_WPS_BUTTON,
|
||||||
|
+ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
|
||||||
|
+ .gpio = AP121_MINI_GPIO_BTN_JUMPSTART,
|
||||||
|
+ .active_low = 1,
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
+ .desc = "reset button",
|
||||||
|
+ .type = EV_KEY,
|
||||||
|
+ .code = KEY_RESTART,
|
||||||
|
+ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
|
||||||
|
+ .gpio = AP121_MINI_GPIO_BTN_RESET,
|
||||||
|
+ .active_low = 1,
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
-static struct ath79_spi_platform_data ap121_spi_data = {
|
||||||
|
- .bus_num = 0,
|
||||||
|
- .num_chipselect = 1,
|
||||||
|
-};
|
||||||
|
+static void __init ap121_common_setup(void)
|
||||||
|
+{
|
||||||
|
+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
|
||||||
|
+
|
||||||
|
+ ath79_register_m25p80(&ap121_flash_data);
|
||||||
|
+ ath79_register_wmac(art + AP121_CALDATA_OFFSET,
|
||||||
|
+ art + AP121_WMAC_MAC_OFFSET);
|
||||||
|
+
|
||||||
|
+ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP121_MAC0_OFFSET, 0);
|
||||||
|
+ ath79_init_mac(ath79_eth1_data.mac_addr, art + AP121_MAC1_OFFSET, 0);
|
||||||
|
+
|
||||||
|
+ ath79_register_mdio(0, 0x0);
|
||||||
|
+
|
||||||
|
+ /* LAN ports */
|
||||||
|
+ ath79_register_eth(1);
|
||||||
|
+
|
||||||
|
+ /* WAN port */
|
||||||
|
+ ath79_register_eth(0);
|
||||||
|
+}
|
||||||
|
|
||||||
|
static void __init ap121_setup(void)
|
||||||
|
{
|
||||||
|
- u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR);
|
||||||
|
+ ap121_flash_data.parts = ap121_parts;
|
||||||
|
+ ap121_flash_data.nr_parts = ARRAY_SIZE(ap121_parts);
|
||||||
|
+
|
||||||
|
+ ap121_common_setup();
|
||||||
|
|
||||||
|
ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
|
||||||
|
ap121_leds_gpio);
|
||||||
|
ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
|
||||||
|
ARRAY_SIZE(ap121_gpio_keys),
|
||||||
|
ap121_gpio_keys);
|
||||||
|
-
|
||||||
|
- ath79_register_spi(&ap121_spi_data, ap121_spi_info,
|
||||||
|
- ARRAY_SIZE(ap121_spi_info));
|
||||||
|
ath79_register_usb();
|
||||||
|
- ath79_register_wmac(cal_data, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
|
||||||
|
ap121_setup);
|
||||||
|
+
|
||||||
|
+static void __init ap121_mini_setup(void)
|
||||||
|
+{
|
||||||
|
+ ap121_flash_data.parts = ap121_mini_parts;
|
||||||
|
+ ap121_flash_data.nr_parts = ARRAY_SIZE(ap121_mini_parts);
|
||||||
|
+
|
||||||
|
+ ap121_common_setup();
|
||||||
|
+
|
||||||
|
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_mini_leds_gpio),
|
||||||
|
+ ap121_mini_leds_gpio);
|
||||||
|
+ ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
|
||||||
|
+ ARRAY_SIZE(ap121_mini_gpio_keys),
|
||||||
|
+ ap121_mini_gpio_keys);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+MIPS_MACHINE(ATH79_MACH_AP121_MINI, "AP121-MINI", "Atheros AP121-MINI",
|
||||||
|
+ ap121_mini_setup);
|
||||||
|
--- a/arch/mips/ath79/Kconfig
|
||||||
|
+++ b/arch/mips/ath79/Kconfig
|
||||||
|
@@ -5,9 +5,10 @@ menu "Atheros AR71XX/AR724X/AR913X machi
|
||||||
|
config ATH79_MACH_AP121
|
||||||
|
bool "Atheros AP121 reference board"
|
||||||
|
select SOC_AR933X
|
||||||
|
+ select ATH79_DEV_ETH
|
||||||
|
select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
select ATH79_DEV_LEDS_GPIO
|
||||||
|
- select ATH79_DEV_SPI
|
||||||
|
+ select ATH79_DEV_M25P80
|
||||||
|
select ATH79_DEV_USB
|
||||||
|
select ATH79_DEV_WMAC
|
||||||
|
help
|
||||||
|
--- a/arch/mips/ath79/machtypes.h
|
||||||
|
+++ b/arch/mips/ath79/machtypes.h
|
||||||
|
@@ -17,6 +17,7 @@
|
||||||
|
enum ath79_mach_type {
|
||||||
|
ATH79_MACH_GENERIC = 0,
|
||||||
|
ATH79_MACH_AP121, /* Atheros AP121 reference board */
|
||||||
|
+ ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */
|
||||||
|
ATH79_MACH_AP81, /* Atheros AP81 reference board */
|
||||||
|
ATH79_MACH_DB120, /* Atheros DB120 reference board */
|
||||||
|
ATH79_MACH_PB44, /* Atheros PB44 reference board */
|
||||||
|
|
@ -0,0 +1,128 @@
|
||||||
|
--- a/arch/mips/ath79/mach-ap81.c
|
||||||
|
+++ b/arch/mips/ath79/mach-ap81.c
|
||||||
|
@@ -9,12 +9,16 @@
|
||||||
|
* by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
|
||||||
|
-#include "machtypes.h"
|
||||||
|
-#include "dev-wmac.h"
|
||||||
|
+#include <linux/mtd/mtd.h>
|
||||||
|
+#include <linux/mtd/partitions.h>
|
||||||
|
+
|
||||||
|
+#include "dev-eth.h"
|
||||||
|
#include "dev-gpio-buttons.h"
|
||||||
|
#include "dev-leds-gpio.h"
|
||||||
|
-#include "dev-spi.h"
|
||||||
|
+#include "dev-m25p80.h"
|
||||||
|
#include "dev-usb.h"
|
||||||
|
+#include "dev-wmac.h"
|
||||||
|
+#include "machtypes.h"
|
||||||
|
|
||||||
|
#define AP81_GPIO_LED_STATUS 1
|
||||||
|
#define AP81_GPIO_LED_AOSS 3
|
||||||
|
@@ -29,6 +33,37 @@
|
||||||
|
|
||||||
|
#define AP81_CAL_DATA_ADDR 0x1fff1000
|
||||||
|
|
||||||
|
+static struct mtd_partition ap81_partitions[] = {
|
||||||
|
+ {
|
||||||
|
+ .name = "u-boot",
|
||||||
|
+ .offset = 0,
|
||||||
|
+ .size = 0x040000,
|
||||||
|
+ .mask_flags = MTD_WRITEABLE,
|
||||||
|
+ }, {
|
||||||
|
+ .name = "u-boot-env",
|
||||||
|
+ .offset = 0x040000,
|
||||||
|
+ .size = 0x010000,
|
||||||
|
+ }, {
|
||||||
|
+ .name = "rootfs",
|
||||||
|
+ .offset = 0x050000,
|
||||||
|
+ .size = 0x500000,
|
||||||
|
+ }, {
|
||||||
|
+ .name = "uImage",
|
||||||
|
+ .offset = 0x550000,
|
||||||
|
+ .size = 0x100000,
|
||||||
|
+ }, {
|
||||||
|
+ .name = "ART",
|
||||||
|
+ .offset = 0x650000,
|
||||||
|
+ .size = 0x1b0000,
|
||||||
|
+ .mask_flags = MTD_WRITEABLE,
|
||||||
|
+ }
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct flash_platform_data ap81_flash_data = {
|
||||||
|
+ .parts = ap81_partitions,
|
||||||
|
+ .nr_parts = ARRAY_SIZE(ap81_partitions),
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
static struct gpio_led ap81_leds_gpio[] __initdata = {
|
||||||
|
{
|
||||||
|
.name = "ap81:green:status",
|
||||||
|
@@ -67,26 +102,6 @@ static struct gpio_keys_button ap81_gpio
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
-static struct ath79_spi_controller_data ap81_spi0_data = {
|
||||||
|
- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
|
||||||
|
- .cs_line = 0,
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static struct spi_board_info ap81_spi_info[] = {
|
||||||
|
- {
|
||||||
|
- .bus_num = 0,
|
||||||
|
- .chip_select = 0,
|
||||||
|
- .max_speed_hz = 25000000,
|
||||||
|
- .modalias = "m25p64",
|
||||||
|
- .controller_data = &ap81_spi0_data,
|
||||||
|
- }
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static struct ath79_spi_platform_data ap81_spi_data = {
|
||||||
|
- .bus_num = 0,
|
||||||
|
- .num_chipselect = 1,
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
static void __init ap81_setup(void)
|
||||||
|
{
|
||||||
|
u8 *cal_data = (u8 *) KSEG1ADDR(AP81_CAL_DATA_ADDR);
|
||||||
|
@@ -96,10 +111,24 @@ static void __init ap81_setup(void)
|
||||||
|
ath79_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL,
|
||||||
|
ARRAY_SIZE(ap81_gpio_keys),
|
||||||
|
ap81_gpio_keys);
|
||||||
|
- ath79_register_spi(&ap81_spi_data, ap81_spi_info,
|
||||||
|
- ARRAY_SIZE(ap81_spi_info));
|
||||||
|
+ ath79_register_m25p80(&ap81_flash_data);
|
||||||
|
ath79_register_wmac(cal_data, NULL);
|
||||||
|
ath79_register_usb();
|
||||||
|
+
|
||||||
|
+ ath79_register_mdio(0, 0x0);
|
||||||
|
+
|
||||||
|
+ ath79_init_mac(ath79_eth0_data.mac_addr, cal_data, 0);
|
||||||
|
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
|
||||||
|
+ ath79_eth0_data.speed = SPEED_100;
|
||||||
|
+ ath79_eth0_data.duplex = DUPLEX_FULL;
|
||||||
|
+ ath79_eth0_data.has_ar8216 = 1;
|
||||||
|
+
|
||||||
|
+ ath79_init_mac(ath79_eth1_data.mac_addr, cal_data, 1);
|
||||||
|
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
|
||||||
|
+ ath79_eth1_data.phy_mask = 0x10;
|
||||||
|
+
|
||||||
|
+ ath79_register_eth(0);
|
||||||
|
+ ath79_register_eth(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",
|
||||||
|
--- a/arch/mips/ath79/Kconfig
|
||||||
|
+++ b/arch/mips/ath79/Kconfig
|
||||||
|
@@ -18,9 +18,10 @@ config ATH79_MACH_AP121
|
||||||
|
config ATH79_MACH_AP81
|
||||||
|
bool "Atheros AP81 reference board"
|
||||||
|
select SOC_AR913X
|
||||||
|
+ select ATH79_DEV_ETH
|
||||||
|
select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
select ATH79_DEV_LEDS_GPIO
|
||||||
|
- select ATH79_DEV_SPI
|
||||||
|
+ select ATH79_DEV_M25P80
|
||||||
|
select ATH79_DEV_USB
|
||||||
|
select ATH79_DEV_WMAC
|
||||||
|
help
|
||||||
|
|
@ -0,0 +1,220 @@
|
||||||
|
--- a/arch/mips/ath79/mach-db120.c
|
||||||
|
+++ b/arch/mips/ath79/mach-db120.c
|
||||||
|
@@ -37,17 +37,26 @@
|
||||||
|
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
+#include <linux/mtd/mtd.h>
|
||||||
|
+#include <linux/mtd/partitions.h>
|
||||||
|
#include <linux/pci.h>
|
||||||
|
+#include <linux/platform_device.h>
|
||||||
|
#include <linux/ath9k_platform.h>
|
||||||
|
|
||||||
|
-#include "machtypes.h"
|
||||||
|
+#include <asm/mach-ath79/ar71xx_regs.h>
|
||||||
|
+
|
||||||
|
+#include "common.h"
|
||||||
|
+#include "dev-ap9x-pci.h"
|
||||||
|
+#include "dev-eth.h"
|
||||||
|
#include "dev-gpio-buttons.h"
|
||||||
|
#include "dev-leds-gpio.h"
|
||||||
|
+#include "dev-m25p80.h"
|
||||||
|
#include "dev-spi.h"
|
||||||
|
#include "dev-usb.h"
|
||||||
|
#include "dev-wmac.h"
|
||||||
|
-#include "pci.h"
|
||||||
|
+#include "machtypes.h"
|
||||||
|
|
||||||
|
+#define DB120_GPIO_LED_USB 11
|
||||||
|
#define DB120_GPIO_LED_WLAN_5G 12
|
||||||
|
#define DB120_GPIO_LED_WLAN_2G 13
|
||||||
|
#define DB120_GPIO_LED_STATUS 14
|
||||||
|
@@ -58,8 +67,50 @@
|
||||||
|
#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */
|
||||||
|
#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL)
|
||||||
|
|
||||||
|
-#define DB120_WMAC_CALDATA_OFFSET 0x1000
|
||||||
|
-#define DB120_PCIE_CALDATA_OFFSET 0x5000
|
||||||
|
+#define DB120_MAC0_OFFSET 0
|
||||||
|
+#define DB120_MAC1_OFFSET 6
|
||||||
|
+#define DB120_WMAC_CALDATA_OFFSET 0x1000
|
||||||
|
+#define DB120_PCIE_CALDATA_OFFSET 0x5000
|
||||||
|
+
|
||||||
|
+static struct mtd_partition db120_partitions[] = {
|
||||||
|
+ {
|
||||||
|
+ .name = "u-boot",
|
||||||
|
+ .offset = 0,
|
||||||
|
+ .size = 0x040000,
|
||||||
|
+ .mask_flags = MTD_WRITEABLE,
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
+ .name = "u-boot-env",
|
||||||
|
+ .offset = 0x040000,
|
||||||
|
+ .size = 0x010000,
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
+ .name = "rootfs",
|
||||||
|
+ .offset = 0x050000,
|
||||||
|
+ .size = 0x630000,
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
+ .name = "uImage",
|
||||||
|
+ .offset = 0x680000,
|
||||||
|
+ .size = 0x160000,
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
+ .name = "NVRAM",
|
||||||
|
+ .offset = 0x7E0000,
|
||||||
|
+ .size = 0x010000,
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
+ .name = "ART",
|
||||||
|
+ .offset = 0x7F0000,
|
||||||
|
+ .size = 0x010000,
|
||||||
|
+ .mask_flags = MTD_WRITEABLE,
|
||||||
|
+ }
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct flash_platform_data db120_flash_data = {
|
||||||
|
+ .parts = db120_partitions,
|
||||||
|
+ .nr_parts = ARRAY_SIZE(db120_partitions),
|
||||||
|
+};
|
||||||
|
|
||||||
|
static struct gpio_led db120_leds_gpio[] __initdata = {
|
||||||
|
{
|
||||||
|
@@ -82,6 +133,11 @@ static struct gpio_led db120_leds_gpio[]
|
||||||
|
.gpio = DB120_GPIO_LED_WLAN_2G,
|
||||||
|
.active_low = 1,
|
||||||
|
},
|
||||||
|
+ {
|
||||||
|
+ .name = "db120:green:usb",
|
||||||
|
+ .gpio = DB120_GPIO_LED_USB,
|
||||||
|
+ .active_low = 1,
|
||||||
|
+ }
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct gpio_keys_button db120_gpio_keys[] __initdata = {
|
||||||
|
@@ -95,66 +151,65 @@ static struct gpio_keys_button db120_gpi
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
-static struct ath79_spi_controller_data db120_spi0_data = {
|
||||||
|
- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
|
||||||
|
- .cs_line = 0,
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static struct spi_board_info db120_spi_info[] = {
|
||||||
|
- {
|
||||||
|
- .bus_num = 0,
|
||||||
|
- .chip_select = 0,
|
||||||
|
- .max_speed_hz = 25000000,
|
||||||
|
- .modalias = "s25sl064a",
|
||||||
|
- .controller_data = &db120_spi0_data,
|
||||||
|
- }
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static struct ath79_spi_platform_data db120_spi_data = {
|
||||||
|
- .bus_num = 0,
|
||||||
|
- .num_chipselect = 1,
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-#ifdef CONFIG_PCI
|
||||||
|
-static struct ath9k_platform_data db120_ath9k_data;
|
||||||
|
-
|
||||||
|
-static int db120_pci_plat_dev_init(struct pci_dev *dev)
|
||||||
|
+static void __init db120_gmac_setup(void)
|
||||||
|
{
|
||||||
|
- switch (PCI_SLOT(dev->devfn)) {
|
||||||
|
- case 0:
|
||||||
|
- dev->dev.platform_data = &db120_ath9k_data;
|
||||||
|
- break;
|
||||||
|
- }
|
||||||
|
+ void __iomem *base;
|
||||||
|
+ u32 t;
|
||||||
|
|
||||||
|
- return 0;
|
||||||
|
-}
|
||||||
|
+ base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
|
||||||
|
|
||||||
|
-static void __init db120_pci_init(u8 *eeprom)
|
||||||
|
-{
|
||||||
|
- memcpy(db120_ath9k_data.eeprom_data, eeprom,
|
||||||
|
- sizeof(db120_ath9k_data.eeprom_data));
|
||||||
|
+ t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
|
||||||
|
+ t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
|
||||||
|
+ AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
|
||||||
|
+ __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
|
||||||
|
|
||||||
|
- ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
|
||||||
|
- ath79_register_pci();
|
||||||
|
+ iounmap(base);
|
||||||
|
}
|
||||||
|
-#else
|
||||||
|
-static inline void db120_pci_init(void) {}
|
||||||
|
-#endif /* CONFIG_PCI */
|
||||||
|
|
||||||
|
static void __init db120_setup(void)
|
||||||
|
{
|
||||||
|
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
|
||||||
|
|
||||||
|
+ ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO);
|
||||||
|
+ ath79_register_m25p80(&db120_flash_data);
|
||||||
|
+
|
||||||
|
ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
|
||||||
|
db120_leds_gpio);
|
||||||
|
ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
|
||||||
|
ARRAY_SIZE(db120_gpio_keys),
|
||||||
|
db120_gpio_keys);
|
||||||
|
- ath79_register_spi(&db120_spi_data, db120_spi_info,
|
||||||
|
- ARRAY_SIZE(db120_spi_info));
|
||||||
|
ath79_register_usb();
|
||||||
|
ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
|
||||||
|
- db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
|
||||||
|
+ ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL);
|
||||||
|
+
|
||||||
|
+ db120_gmac_setup();
|
||||||
|
+
|
||||||
|
+ ath79_register_mdio(0, 0x0);
|
||||||
|
+ ath79_register_mdio(1, 0x0);
|
||||||
|
+
|
||||||
|
+ ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0);
|
||||||
|
+#if 0
|
||||||
|
+ /* GMAC0 is connected to an AR8327 switch */
|
||||||
|
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
|
||||||
|
+ ath79_eth0_data.speed = SPEED_1000;
|
||||||
|
+ ath79_eth0_data.duplex = DUPLEX_FULL;
|
||||||
|
+#else
|
||||||
|
+ /* GMAC0 is connected to PHY4 of the internal switch */
|
||||||
|
+ ath79_switch_data.phy4_mii_en = 1;
|
||||||
|
+
|
||||||
|
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
|
||||||
|
+ ath79_eth0_data.phy_mask = BIT(4);
|
||||||
|
+ ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
|
||||||
|
+#endif
|
||||||
|
+ ath79_register_eth(0);
|
||||||
|
+
|
||||||
|
+ /* GMAC1 is connected to the internal switch */
|
||||||
|
+ ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0);
|
||||||
|
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
|
||||||
|
+ ath79_eth1_data.speed = SPEED_1000;
|
||||||
|
+ ath79_eth1_data.duplex = DUPLEX_FULL;
|
||||||
|
+
|
||||||
|
+ ath79_register_eth(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
|
||||||
|
--- a/arch/mips/ath79/Kconfig
|
||||||
|
+++ b/arch/mips/ath79/Kconfig
|
||||||
|
@@ -31,9 +31,11 @@ config ATH79_MACH_AP81
|
||||||
|
config ATH79_MACH_DB120
|
||||||
|
bool "Atheros DB120 reference board"
|
||||||
|
select SOC_AR934X
|
||||||
|
+ select ATH79_DEV_AP9X_PCI if PCI
|
||||||
|
+ select ATH79_DEV_ETH
|
||||||
|
select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
select ATH79_DEV_LEDS_GPIO
|
||||||
|
- select ATH79_DEV_SPI
|
||||||
|
+ select ATH79_DEV_M25P80
|
||||||
|
select ATH79_DEV_USB
|
||||||
|
select ATH79_DEV_WMAC
|
||||||
|
help
|
||||||
|
|
@ -0,0 +1,153 @@
|
||||||
|
--- a/arch/mips/ath79/mach-pb44.c
|
||||||
|
+++ b/arch/mips/ath79/mach-pb44.c
|
||||||
|
@@ -8,23 +8,48 @@
|
||||||
|
* by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
|
||||||
|
+#include <linux/delay.h>
|
||||||
|
#include <linux/init.h>
|
||||||
|
#include <linux/platform_device.h>
|
||||||
|
#include <linux/i2c.h>
|
||||||
|
#include <linux/i2c-gpio.h>
|
||||||
|
#include <linux/i2c/pcf857x.h>
|
||||||
|
+#include <linux/i2c/pcf857x.h>
|
||||||
|
+#include <linux/spi/flash.h>
|
||||||
|
+#include <linux/spi/vsc7385.h>
|
||||||
|
|
||||||
|
-#include "machtypes.h"
|
||||||
|
+#include <asm/mach-ath79/ar71xx_regs.h>
|
||||||
|
+#include <asm/mach-ath79/ath79.h>
|
||||||
|
+
|
||||||
|
+#include "dev-eth.h"
|
||||||
|
#include "dev-gpio-buttons.h"
|
||||||
|
#include "dev-leds-gpio.h"
|
||||||
|
#include "dev-spi.h"
|
||||||
|
#include "dev-usb.h"
|
||||||
|
+#include "machtypes.h"
|
||||||
|
#include "pci.h"
|
||||||
|
|
||||||
|
#define PB44_GPIO_I2C_SCL 0
|
||||||
|
#define PB44_GPIO_I2C_SDA 1
|
||||||
|
|
||||||
|
+#define PB44_PCF8757_VSC7395_CS 0
|
||||||
|
+#define PB44_PCF8757_STEREO_CS 1
|
||||||
|
+#define PB44_PCF8757_SLIC_CS0 2
|
||||||
|
+#define PB44_PCF8757_SLIC_TEST 3
|
||||||
|
+#define PB44_PCF8757_SLIC_INT0 4
|
||||||
|
+#define PB44_PCF8757_SLIC_INT1 5
|
||||||
|
+#define PB44_PCF8757_SW_RESET 6
|
||||||
|
+#define PB44_PCF8757_SW_JUMP 8
|
||||||
|
+#define PB44_PCF8757_LED_JUMP1 9
|
||||||
|
+#define PB44_PCF8757_LED_JUMP2 10
|
||||||
|
+#define PB44_PCF8757_TP24 11
|
||||||
|
+#define PB44_PCF8757_TP25 12
|
||||||
|
+#define PB44_PCF8757_TP26 13
|
||||||
|
+#define PB44_PCF8757_TP27 14
|
||||||
|
+#define PB44_PCF8757_TP28 15
|
||||||
|
+
|
||||||
|
#define PB44_GPIO_EXP_BASE 16
|
||||||
|
+#define PB44_GPIO_VSC7395_CS (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS)
|
||||||
|
#define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6)
|
||||||
|
#define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8)
|
||||||
|
#define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9)
|
||||||
|
@@ -92,21 +117,66 @@ static struct ath79_spi_controller_data
|
||||||
|
.cs_line = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
+static struct ath79_spi_controller_data pb44_spi1_data = {
|
||||||
|
+ .cs_type = ATH79_SPI_CS_TYPE_GPIO,
|
||||||
|
+ .cs_line = PB44_GPIO_VSC7395_CS,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static void pb44_vsc7395_reset(void)
|
||||||
|
+{
|
||||||
|
+ ath79_device_reset_set(AR71XX_RESET_GE1_PHY);
|
||||||
|
+ udelay(10);
|
||||||
|
+ ath79_device_reset_clear(AR71XX_RESET_GE1_PHY);
|
||||||
|
+ mdelay(50);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static struct vsc7385_platform_data pb44_vsc7395_data = {
|
||||||
|
+ .reset = pb44_vsc7395_reset,
|
||||||
|
+ .ucode_name = "vsc7395_ucode_pb44.bin",
|
||||||
|
+ .mac_cfg = {
|
||||||
|
+ .tx_ipg = 6,
|
||||||
|
+ .bit2 = 1,
|
||||||
|
+ .clk_sel = 0,
|
||||||
|
+ },
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const char *pb44_part_probes[] = {
|
||||||
|
+ "RedBoot",
|
||||||
|
+ NULL,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct flash_platform_data pb44_flash_data = {
|
||||||
|
+ .part_probes = pb44_part_probes,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
static struct spi_board_info pb44_spi_info[] = {
|
||||||
|
{
|
||||||
|
.bus_num = 0,
|
||||||
|
.chip_select = 0,
|
||||||
|
.max_speed_hz = 25000000,
|
||||||
|
.modalias = "m25p64",
|
||||||
|
+ .platform_data = &pb44_flash_data,
|
||||||
|
.controller_data = &pb44_spi0_data,
|
||||||
|
},
|
||||||
|
+ {
|
||||||
|
+ .bus_num = 0,
|
||||||
|
+ .chip_select = 1,
|
||||||
|
+ .max_speed_hz = 25000000,
|
||||||
|
+ .modalias = "spi-vsc7385",
|
||||||
|
+ .platform_data = &pb44_vsc7395_data,
|
||||||
|
+ .controller_data = &pb44_spi1_data,
|
||||||
|
+ }
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct ath79_spi_platform_data pb44_spi_data = {
|
||||||
|
.bus_num = 0,
|
||||||
|
- .num_chipselect = 1,
|
||||||
|
+ .num_chipselect = 2,
|
||||||
|
};
|
||||||
|
|
||||||
|
+#define PB44_WAN_PHYMASK BIT(0)
|
||||||
|
+#define PB44_LAN_PHYMASK 0
|
||||||
|
+#define PB44_MDIO_PHYMASK (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK)
|
||||||
|
+
|
||||||
|
static void __init pb44_init(void)
|
||||||
|
{
|
||||||
|
i2c_register_board_info(0, pb44_i2c_board_info,
|
||||||
|
@@ -122,6 +192,22 @@ static void __init pb44_init(void)
|
||||||
|
ARRAY_SIZE(pb44_spi_info));
|
||||||
|
ath79_register_usb();
|
||||||
|
ath79_register_pci();
|
||||||
|
+
|
||||||
|
+ ath79_register_mdio(0, ~PB44_MDIO_PHYMASK);
|
||||||
|
+
|
||||||
|
+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
|
||||||
|
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
|
||||||
|
+ ath79_eth0_data.phy_mask = PB44_WAN_PHYMASK;
|
||||||
|
+
|
||||||
|
+ ath79_register_eth(0);
|
||||||
|
+
|
||||||
|
+ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
|
||||||
|
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
|
||||||
|
+ ath79_eth1_data.speed = SPEED_1000;
|
||||||
|
+ ath79_eth1_data.duplex = DUPLEX_FULL;
|
||||||
|
+ ath79_eth1_pll_data.pll_1000 = 0x110000;
|
||||||
|
+
|
||||||
|
+ ath79_register_eth(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
|
||||||
|
--- a/arch/mips/ath79/Kconfig
|
||||||
|
+++ b/arch/mips/ath79/Kconfig
|
||||||
|
@@ -45,6 +45,7 @@ config ATH79_MACH_DB120
|
||||||
|
config ATH79_MACH_PB44
|
||||||
|
bool "Atheros PB44 reference board"
|
||||||
|
select SOC_AR71XX
|
||||||
|
+ select ATH79_DEV_ETH
|
||||||
|
select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
select ATH79_DEV_LEDS_GPIO
|
||||||
|
select ATH79_DEV_SPI
|
||||||
|
|
@ -0,0 +1,109 @@
|
||||||
|
--- a/arch/mips/ath79/Kconfig
|
||||||
|
+++ b/arch/mips/ath79/Kconfig
|
||||||
|
@@ -57,9 +57,10 @@ config ATH79_MACH_PB44
|
||||||
|
config ATH79_MACH_UBNT_XM
|
||||||
|
bool "Ubiquiti Networks XM (rev 1.0) board"
|
||||||
|
select SOC_AR724X
|
||||||
|
+ select ATH79_DEV_AP9X_PCI if PCI
|
||||||
|
select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
select ATH79_DEV_LEDS_GPIO
|
||||||
|
- select ATH79_DEV_SPI
|
||||||
|
+ select ATH79_DEV_M25P80
|
||||||
|
help
|
||||||
|
Say 'Y' here if you want your kernel to support the
|
||||||
|
Ubiquiti Networks XM (rev 1.0) board.
|
||||||
|
--- a/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
+++ b/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
@@ -16,10 +16,11 @@
|
||||||
|
|
||||||
|
#include <asm/mach-ath79/irq.h>
|
||||||
|
|
||||||
|
-#include "machtypes.h"
|
||||||
|
+#include "dev-ap9x-pci.h"
|
||||||
|
#include "dev-gpio-buttons.h"
|
||||||
|
#include "dev-leds-gpio.h"
|
||||||
|
-#include "dev-spi.h"
|
||||||
|
+#include "dev-m25p80.h"
|
||||||
|
+#include "machtypes.h"
|
||||||
|
#include "pci.h"
|
||||||
|
|
||||||
|
#define UBNT_XM_GPIO_LED_L1 0
|
||||||
|
@@ -32,7 +33,7 @@
|
||||||
|
#define UBNT_XM_KEYS_POLL_INTERVAL 20
|
||||||
|
#define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL)
|
||||||
|
|
||||||
|
-#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000)
|
||||||
|
+#define UBNT_XM_EEPROM_ADDR 0x1fff1000
|
||||||
|
|
||||||
|
static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
|
||||||
|
{
|
||||||
|
@@ -65,54 +66,10 @@ static struct gpio_keys_button ubnt_xm_g
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
-static struct ath79_spi_controller_data ubnt_xm_spi0_data = {
|
||||||
|
- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
|
||||||
|
- .cs_line = 0,
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static struct spi_board_info ubnt_xm_spi_info[] = {
|
||||||
|
- {
|
||||||
|
- .bus_num = 0,
|
||||||
|
- .chip_select = 0,
|
||||||
|
- .max_speed_hz = 25000000,
|
||||||
|
- .modalias = "mx25l6405d",
|
||||||
|
- .controller_data = &ubnt_xm_spi0_data,
|
||||||
|
- }
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static struct ath79_spi_platform_data ubnt_xm_spi_data = {
|
||||||
|
- .bus_num = 0,
|
||||||
|
- .num_chipselect = 1,
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-#ifdef CONFIG_PCI
|
||||||
|
-static struct ath9k_platform_data ubnt_xm_eeprom_data;
|
||||||
|
-
|
||||||
|
-static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev)
|
||||||
|
-{
|
||||||
|
- switch (PCI_SLOT(dev->devfn)) {
|
||||||
|
- case 0:
|
||||||
|
- dev->dev.platform_data = &ubnt_xm_eeprom_data;
|
||||||
|
- break;
|
||||||
|
- }
|
||||||
|
-
|
||||||
|
- return 0;
|
||||||
|
-}
|
||||||
|
-
|
||||||
|
-static void __init ubnt_xm_pci_init(void)
|
||||||
|
-{
|
||||||
|
- memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
|
||||||
|
- sizeof(ubnt_xm_eeprom_data.eeprom_data));
|
||||||
|
-
|
||||||
|
- ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init);
|
||||||
|
- ath79_register_pci();
|
||||||
|
-}
|
||||||
|
-#else
|
||||||
|
-static inline void ubnt_xm_pci_init(void) {}
|
||||||
|
-#endif /* CONFIG_PCI */
|
||||||
|
-
|
||||||
|
static void __init ubnt_xm_init(void)
|
||||||
|
{
|
||||||
|
+ u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR);
|
||||||
|
+
|
||||||
|
ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
|
||||||
|
ubnt_xm_leds_gpio);
|
||||||
|
|
||||||
|
@@ -120,10 +77,8 @@ static void __init ubnt_xm_init(void)
|
||||||
|
ARRAY_SIZE(ubnt_xm_gpio_keys),
|
||||||
|
ubnt_xm_gpio_keys);
|
||||||
|
|
||||||
|
- ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
|
||||||
|
- ARRAY_SIZE(ubnt_xm_spi_info));
|
||||||
|
-
|
||||||
|
- ubnt_xm_pci_init();
|
||||||
|
+ ath79_register_m25p80(NULL);
|
||||||
|
+ ap91_pci_init(eeprom, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
MIPS_MACHINE(ATH79_MACH_UBNT_XM,
|
||||||
|
|
@ -0,0 +1,187 @@
|
||||||
|
--- a/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
+++ b/arch/mips/ath79/mach-ubnt-xm.c
|
||||||
|
@@ -13,15 +13,17 @@
|
||||||
|
#include <linux/init.h>
|
||||||
|
#include <linux/pci.h>
|
||||||
|
#include <linux/ath9k_platform.h>
|
||||||
|
+#include <linux/etherdevice.h>
|
||||||
|
|
||||||
|
#include <asm/mach-ath79/irq.h>
|
||||||
|
|
||||||
|
#include "dev-ap9x-pci.h"
|
||||||
|
+#include "dev-eth.h"
|
||||||
|
#include "dev-gpio-buttons.h"
|
||||||
|
#include "dev-leds-gpio.h"
|
||||||
|
#include "dev-m25p80.h"
|
||||||
|
+#include "dev-usb.h"
|
||||||
|
#include "machtypes.h"
|
||||||
|
-#include "pci.h"
|
||||||
|
|
||||||
|
#define UBNT_XM_GPIO_LED_L1 0
|
||||||
|
#define UBNT_XM_GPIO_LED_L2 1
|
||||||
|
@@ -37,19 +39,19 @@
|
||||||
|
|
||||||
|
static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
|
||||||
|
{
|
||||||
|
- .name = "ubnt-xm:red:link1",
|
||||||
|
+ .name = "ubnt:red:link1",
|
||||||
|
.gpio = UBNT_XM_GPIO_LED_L1,
|
||||||
|
.active_low = 0,
|
||||||
|
}, {
|
||||||
|
- .name = "ubnt-xm:orange:link2",
|
||||||
|
+ .name = "ubnt:orange:link2",
|
||||||
|
.gpio = UBNT_XM_GPIO_LED_L2,
|
||||||
|
.active_low = 0,
|
||||||
|
}, {
|
||||||
|
- .name = "ubnt-xm:green:link3",
|
||||||
|
+ .name = "ubnt:green:link3",
|
||||||
|
.gpio = UBNT_XM_GPIO_LED_L3,
|
||||||
|
.active_low = 0,
|
||||||
|
}, {
|
||||||
|
- .name = "ubnt-xm:green:link4",
|
||||||
|
+ .name = "ubnt:green:link4",
|
||||||
|
.gpio = UBNT_XM_GPIO_LED_L4,
|
||||||
|
.active_low = 0,
|
||||||
|
},
|
||||||
|
@@ -66,9 +68,13 @@ static struct gpio_keys_button ubnt_xm_g
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
+#define UBNT_M_WAN_PHYMASK BIT(4)
|
||||||
|
+
|
||||||
|
static void __init ubnt_xm_init(void)
|
||||||
|
{
|
||||||
|
u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR);
|
||||||
|
+ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
|
||||||
|
+ u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN);
|
||||||
|
|
||||||
|
ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
|
||||||
|
ubnt_xm_leds_gpio);
|
||||||
|
@@ -79,9 +85,99 @@ static void __init ubnt_xm_init(void)
|
||||||
|
|
||||||
|
ath79_register_m25p80(NULL);
|
||||||
|
ap91_pci_init(eeprom, NULL);
|
||||||
|
+
|
||||||
|
+ ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
|
||||||
|
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
|
||||||
|
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
|
||||||
|
+ ath79_register_eth(0);
|
||||||
|
}
|
||||||
|
|
||||||
|
MIPS_MACHINE(ATH79_MACH_UBNT_XM,
|
||||||
|
"UBNT-XM",
|
||||||
|
"Ubiquiti Networks XM (rev 1.0) board",
|
||||||
|
ubnt_xm_init);
|
||||||
|
+
|
||||||
|
+MIPS_MACHINE(ATH79_MACH_UBNT_BULLET_M, "UBNT-BM", "Ubiquiti Bullet M",
|
||||||
|
+ ubnt_xm_init);
|
||||||
|
+
|
||||||
|
+static void __init ubnt_rocket_m_setup(void)
|
||||||
|
+{
|
||||||
|
+ ubnt_xm_init();
|
||||||
|
+ ath79_register_usb();
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M, "UBNT-RM", "Ubiquiti Rocket M",
|
||||||
|
+ ubnt_rocket_m_setup);
|
||||||
|
+
|
||||||
|
+static void __init ubnt_nano_m_setup(void)
|
||||||
|
+{
|
||||||
|
+ ubnt_xm_init();
|
||||||
|
+ ath79_register_eth(1);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+MIPS_MACHINE(ATH79_MACH_UBNT_NANO_M, "UBNT-NM", "Ubiquiti Nanostation M",
|
||||||
|
+ ubnt_nano_m_setup);
|
||||||
|
+
|
||||||
|
+static struct gpio_led ubnt_airrouter_leds_gpio[] __initdata = {
|
||||||
|
+ {
|
||||||
|
+ .name = "ubnt:green:globe",
|
||||||
|
+ .gpio = 0,
|
||||||
|
+ .active_low = 1,
|
||||||
|
+ }
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static void __init ubnt_airrouter_setup(void)
|
||||||
|
+{
|
||||||
|
+ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
|
||||||
|
+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
|
||||||
|
+
|
||||||
|
+ ath79_register_m25p80(NULL);
|
||||||
|
+ ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
|
||||||
|
+
|
||||||
|
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
|
||||||
|
+ ath79_init_local_mac(ath79_eth1_data.mac_addr, mac1);
|
||||||
|
+
|
||||||
|
+ ath79_register_eth(1);
|
||||||
|
+ ath79_register_eth(0);
|
||||||
|
+ ath79_register_usb();
|
||||||
|
+
|
||||||
|
+ ap91_pci_init(ee, NULL);
|
||||||
|
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airrouter_leds_gpio),
|
||||||
|
+ ubnt_airrouter_leds_gpio);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+MIPS_MACHINE(ATH79_MACH_UBNT_AIRROUTER, "UBNT-AR", "Ubiquiti AirRouter",
|
||||||
|
+ ubnt_airrouter_setup);
|
||||||
|
+
|
||||||
|
+static struct gpio_led ubnt_unifi_leds_gpio[] __initdata = {
|
||||||
|
+ {
|
||||||
|
+ .name = "ubnt:orange:dome",
|
||||||
|
+ .gpio = 1,
|
||||||
|
+ .active_low = 0,
|
||||||
|
+ }, {
|
||||||
|
+ .name = "ubnt:green:dome",
|
||||||
|
+ .gpio = 0,
|
||||||
|
+ .active_low = 0,
|
||||||
|
+ }
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static void __init ubnt_unifi_setup(void)
|
||||||
|
+{
|
||||||
|
+ u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000);
|
||||||
|
+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
|
||||||
|
+
|
||||||
|
+ ath79_register_m25p80(NULL);
|
||||||
|
+
|
||||||
|
+ ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
|
||||||
|
+
|
||||||
|
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
|
||||||
|
+ ath79_register_eth(0);
|
||||||
|
+
|
||||||
|
+ ap91_pci_init(ee, NULL);
|
||||||
|
+
|
||||||
|
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_leds_gpio),
|
||||||
|
+ ubnt_unifi_leds_gpio);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI, "UBNT-UF", "Ubiquiti UniFi",
|
||||||
|
+ ubnt_unifi_setup);
|
||||||
|
--- a/arch/mips/ath79/Kconfig
|
||||||
|
+++ b/arch/mips/ath79/Kconfig
|
||||||
|
@@ -58,9 +58,11 @@ config ATH79_MACH_UBNT_XM
|
||||||
|
bool "Ubiquiti Networks XM (rev 1.0) board"
|
||||||
|
select SOC_AR724X
|
||||||
|
select ATH79_DEV_AP9X_PCI if PCI
|
||||||
|
+ select ATH79_DEV_ETH
|
||||||
|
select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
select ATH79_DEV_LEDS_GPIO
|
||||||
|
select ATH79_DEV_M25P80
|
||||||
|
+ select ATH79_DEV_USB
|
||||||
|
help
|
||||||
|
Say 'Y' here if you want your kernel to support the
|
||||||
|
Ubiquiti Networks XM (rev 1.0) board.
|
||||||
|
--- a/arch/mips/ath79/machtypes.h
|
||||||
|
+++ b/arch/mips/ath79/machtypes.h
|
||||||
|
@@ -21,6 +21,11 @@ enum ath79_mach_type {
|
||||||
|
ATH79_MACH_AP81, /* Atheros AP81 reference board */
|
||||||
|
ATH79_MACH_DB120, /* Atheros DB120 reference board */
|
||||||
|
ATH79_MACH_PB44, /* Atheros PB44 reference board */
|
||||||
|
+ ATH79_MACH_UBNT_AIRROUTER, /* Ubiquiti AirRouter */
|
||||||
|
+ ATH79_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */
|
||||||
|
+ ATH79_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */
|
||||||
|
+ ATH79_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */
|
||||||
|
+ ATH79_MACH_UBNT_UNIFI, /* Ubiquiti Unifi */
|
||||||
|
ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */
|
||||||
|
};
|
||||||
|
|
||||||
|
|
@ -0,0 +1,679 @@
|
||||||
|
--- a/arch/mips/ath79/machtypes.h
|
||||||
|
+++ b/arch/mips/ath79/machtypes.h
|
||||||
|
@@ -16,17 +16,81 @@
|
||||||
|
|
||||||
|
enum ath79_mach_type {
|
||||||
|
ATH79_MACH_GENERIC = 0,
|
||||||
|
+ ATH79_MACH_ALFA_AP96, /* ALFA Network AP96 board */
|
||||||
|
+ ATH79_MACH_ALFA_NX, /* ALFA Network N2/N5 board */
|
||||||
|
+ ATH79_MACH_ALL0258N, /* Allnet ALL0258N */
|
||||||
|
+ ATH79_MACH_AP113, /* Atheros AP113 reference board */
|
||||||
|
ATH79_MACH_AP121, /* Atheros AP121 reference board */
|
||||||
|
ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */
|
||||||
|
ATH79_MACH_AP81, /* Atheros AP81 reference board */
|
||||||
|
+ ATH79_MACH_AP83, /* Atheros AP83 */
|
||||||
|
+ ATH79_MACH_AP96, /* Atheros AP96 */
|
||||||
|
+ ATH79_MACH_AW_NR580, /* AzureWave AW-NR580 */
|
||||||
|
ATH79_MACH_DB120, /* Atheros DB120 reference board */
|
||||||
|
ATH79_MACH_PB44, /* Atheros PB44 reference board */
|
||||||
|
+ ATH79_MACH_DIR_600_A1, /* D-Link DIR-600 rev. A1 */
|
||||||
|
+ ATH79_MACH_DIR_615_C1, /* D-Link DIR-615 rev. C1 */
|
||||||
|
+ ATH79_MACH_DIR_615_E4, /* D-Link DIR-615 rev. E4 */
|
||||||
|
+ ATH79_MACH_DIR_825_B1, /* D-Link DIR-825 rev. B1 */
|
||||||
|
+ ATH79_MACH_EAP7660D, /* Senao EAP7660D */
|
||||||
|
+ ATH79_MACH_JA76PF, /* jjPlus JA76PF */
|
||||||
|
+ ATH79_MACH_JWAP003, /* jjPlus JWAP003 */
|
||||||
|
+ ATH79_MACH_HORNET_UB, /* ALFA Networks Hornet-UB */
|
||||||
|
+ ATH79_MACH_MZK_W04NU, /* Planex MZK-W04NU */
|
||||||
|
+ ATH79_MACH_MZK_W300NH, /* Planex MZK-W300NH */
|
||||||
|
+ ATH79_MACH_NBG460N, /* Zyxel NBG460N/550N/550NH */
|
||||||
|
+ ATH79_MACH_OM2P, /* OpenMesh OM2P */
|
||||||
|
+ ATH79_MACH_PB42, /* Atheros PB42 */
|
||||||
|
+ ATH79_MACH_PB92, /* Atheros PB92 */
|
||||||
|
+ ATH79_MACH_RB_411, /* MikroTik RouterBOARD 411/411A/411AH */
|
||||||
|
+ ATH79_MACH_RB_411U, /* MikroTik RouterBOARD 411U */
|
||||||
|
+ ATH79_MACH_RB_433, /* MikroTik RouterBOARD 433/433AH */
|
||||||
|
+ ATH79_MACH_RB_433U, /* MikroTik RouterBOARD 433UAH */
|
||||||
|
+ ATH79_MACH_RB_450G, /* MikroTik RouterBOARD 450G */
|
||||||
|
+ ATH79_MACH_RB_450, /* MikroTik RouterBOARD 450 */
|
||||||
|
+ ATH79_MACH_RB_493, /* Mikrotik RouterBOARD 493/493AH */
|
||||||
|
+ ATH79_MACH_RB_493G, /* Mikrotik RouterBOARD 493G */
|
||||||
|
+ ATH79_MACH_RB_750, /* MikroTik RouterBOARD 750 */
|
||||||
|
+ ATH79_MACH_RW2458N, /* Redwave RW2458N */
|
||||||
|
+ ATH79_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */
|
||||||
|
+ ATH79_MACH_TL_MR11U, /* TP-LINK TL-MR11U */
|
||||||
|
+ ATH79_MACH_TL_MR3020, /* TP-LINK TL-MR3020 */
|
||||||
|
+ ATH79_MACH_TL_MR3220, /* TP-LINK TL-MR3220 */
|
||||||
|
+ ATH79_MACH_TL_MR3420, /* TP-LINK TL-MR3420 */
|
||||||
|
+ ATH79_MACH_TL_WA901ND, /* TP-LINK TL-WA901ND */
|
||||||
|
+ ATH79_MACH_TL_WA901ND_V2, /* TP-LINK TL-WA901ND v2 */
|
||||||
|
+ ATH79_MACH_TL_WR1043ND, /* TP-LINK TL-WR1041ND */
|
||||||
|
+ ATH79_MACH_TL_WR2543N, /* TP-LINK TL-WR2543N/ND */
|
||||||
|
+ ATH79_MACH_TL_WR703N, /* TP-LINK TL-WR703N */
|
||||||
|
+ ATH79_MACH_TL_WR741ND, /* TP-LINK TL-WR741ND */
|
||||||
|
+ ATH79_MACH_TL_WR741ND_V4, /* TP-LINK TL-WR741ND v4*/
|
||||||
|
+ ATH79_MACH_TL_WR841N_V1, /* TP-LINK TL-WR841N v1 */
|
||||||
|
+ ATH79_MACH_TL_WR841N_V7, /* TP-LINK TL-WR841N/ND v7 */
|
||||||
|
+ ATH79_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */
|
||||||
|
ATH79_MACH_UBNT_AIRROUTER, /* Ubiquiti AirRouter */
|
||||||
|
ATH79_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */
|
||||||
|
+ ATH79_MACH_UBNT_LSSR71, /* Ubiquiti LS-SR71 */
|
||||||
|
+ ATH79_MACH_UBNT_LSX, /* Ubiquiti LSX */
|
||||||
|
ATH79_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */
|
||||||
|
ATH79_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */
|
||||||
|
+ ATH79_MACH_UBNT_RSPRO, /* Ubiquiti RouterStation Pro */
|
||||||
|
+ ATH79_MACH_UBNT_RS, /* Ubiquiti RouterStation */
|
||||||
|
ATH79_MACH_UBNT_UNIFI, /* Ubiquiti Unifi */
|
||||||
|
ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */
|
||||||
|
+ ATH79_MACH_WHR_G301N, /* Buffalo WHR-G301N */
|
||||||
|
+ ATH79_MACH_WHR_HP_G300N, /* Buffalo WHR-HP-G300N */
|
||||||
|
+ ATH79_MACH_WHR_HP_GN, /* Buffalo WHR-HP-GN */
|
||||||
|
+ ATH79_MACH_WNDR3700, /* NETGEAR WNDR3700/WNDR3800/WNDRMAC */
|
||||||
|
+ ATH79_MACH_WNR2000, /* NETGEAR WNR2000 */
|
||||||
|
+ ATH79_MACH_WP543, /* Compex WP543 */
|
||||||
|
+ ATH79_MACH_WPE72, /* Compex WPE72 */
|
||||||
|
+ ATH79_MACH_WRT160NL, /* Linksys WRT160NL */
|
||||||
|
+ ATH79_MACH_WRT400N, /* Linksys WRT400N */
|
||||||
|
+ ATH79_MACH_WZR_HP_AG300H, /* Buffalo WZR-HP-AG300H */
|
||||||
|
+ ATH79_MACH_WZR_HP_G300NH, /* Buffalo WZR-HP-G300NH */
|
||||||
|
+ ATH79_MACH_WZR_HP_G300NH2, /* Buffalo WZR-HP-G300NH2 */
|
||||||
|
+ ATH79_MACH_WZR_HP_G450H, /* Buffalo WZR-HP-G450H */
|
||||||
|
+ ATH79_MACH_ZCN_1523H_2, /* Zcomax ZCN-1523H-2-xx */
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* _ATH79_MACHTYPE_H */
|
||||||
|
--- a/arch/mips/ath79/Kconfig
|
||||||
|
+++ b/arch/mips/ath79/Kconfig
|
||||||
|
@@ -2,6 +2,52 @@ if ATH79
|
||||||
|
|
||||||
|
menu "Atheros AR71XX/AR724X/AR913X machine selection"
|
||||||
|
|
||||||
|
+config ATH79_MACH_ALFA_AP96
|
||||||
|
+ bool "ALFA Network AP96 board support"
|
||||||
|
+ select SOC_AR71XX
|
||||||
|
+ select ATH79_DEV_ETH
|
||||||
|
+ select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
+ select ATH79_DEV_SPI
|
||||||
|
+ select ATH79_DEV_USB
|
||||||
|
+
|
||||||
|
+config ATH79_MACH_HORNET_UB
|
||||||
|
+ bool "ALFA Network Hornet-UB board support"
|
||||||
|
+ select SOC_AR933X
|
||||||
|
+ select ATH79_DEV_ETH
|
||||||
|
+ select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
+ select ATH79_DEV_LEDS_GPIO
|
||||||
|
+ select ATH79_DEV_M25P80
|
||||||
|
+ select ATH79_DEV_USB
|
||||||
|
+ select ATH79_DEV_WMAC
|
||||||
|
+
|
||||||
|
+config ATH79_MACH_ALFA_NX
|
||||||
|
+ bool "ALFA Network N2/N5 board support"
|
||||||
|
+ select SOC_AR724X
|
||||||
|
+ select ATH79_DEV_AP9X_PCI if PCI
|
||||||
|
+ select ATH79_DEV_ETH
|
||||||
|
+ select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
+ select ATH79_DEV_LEDS_GPIO
|
||||||
|
+ select ATH79_DEV_M25P80
|
||||||
|
+
|
||||||
|
+config ATH79_MACH_ALL0258N
|
||||||
|
+ bool "Allnet ALL0258N support"
|
||||||
|
+ select SOC_AR724X
|
||||||
|
+ select ATH79_DEV_AP9X_PCI if PCI
|
||||||
|
+ select ATH79_DEV_ETH
|
||||||
|
+ select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
+ select ATH79_DEV_LEDS_GPIO
|
||||||
|
+ select ATH79_DEV_M25P80
|
||||||
|
+
|
||||||
|
+config ATH79_MACH_AP113
|
||||||
|
+ bool "Atheros AP113 board support"
|
||||||
|
+ select SOC_AR724X
|
||||||
|
+ select ATH79_DEV_M25P80
|
||||||
|
+ select ATH79_DEV_PB9X_PCI if PCI
|
||||||
|
+ select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
+ select ATH79_DEV_LEDS_GPIO
|
||||||
|
+ select ATH79_DEV_USB
|
||||||
|
+ select ATH79_DEV_ETH
|
||||||
|
+
|
||||||
|
config ATH79_MACH_AP121
|
||||||
|
bool "Atheros AP121 reference board"
|
||||||
|
select SOC_AR933X
|
||||||
|
@@ -28,6 +74,36 @@ config ATH79_MACH_AP81
|
||||||
|
Say 'Y' here if you want your kernel to support the
|
||||||
|
Atheros AP81 reference board.
|
||||||
|
|
||||||
|
+config ATH79_MACH_AP83
|
||||||
|
+ bool "Atheros AP83 board support"
|
||||||
|
+ select SOC_AR913X
|
||||||
|
+ select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
+ select ATH79_DEV_LEDS_GPIO
|
||||||
|
+ select ATH79_DEV_USB
|
||||||
|
+ select ATH79_DEV_WMAC
|
||||||
|
+
|
||||||
|
+config ATH79_MACH_AP96
|
||||||
|
+ bool "Atheros AP96 board support"
|
||||||
|
+ select SOC_AR71XX
|
||||||
|
+ select ATH79_DEV_ETH
|
||||||
|
+ select ATH79_DEV_AP9X_PCI if PCI
|
||||||
|
+ select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
+ select ATH79_DEV_LEDS_GPIO
|
||||||
|
+ select ATH79_DEV_M25P80
|
||||||
|
+ select ATH79_DEV_USB
|
||||||
|
+
|
||||||
|
+config ATH79_MACH_AP121
|
||||||
|
+ bool "Atheros AP121 reference board"
|
||||||
|
+ select SOC_AR933X
|
||||||
|
+ select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
+ select ATH79_DEV_LEDS_GPIO
|
||||||
|
+ select ATH79_DEV_SPI
|
||||||
|
+ select ATH79_DEV_USB
|
||||||
|
+ select ATH79_DEV_WMAC
|
||||||
|
+ help
|
||||||
|
+ Say 'Y' here if you want your kernel to support the
|
||||||
|
+ Atheros AP121 reference board.
|
||||||
|
+
|
||||||
|
config ATH79_MACH_DB120
|
||||||
|
bool "Atheros DB120 reference board"
|
||||||
|
select SOC_AR934X
|
||||||
|
@@ -42,6 +118,13 @@ config ATH79_MACH_DB120
|
||||||
|
Say 'Y' here if you want your kernel to support the
|
||||||
|
Atheros DB120 reference board.
|
||||||
|
|
||||||
|
+config ATH79_MACH_PB42
|
||||||
|
+ bool "Atheros PB42 board support"
|
||||||
|
+ select SOC_AR71XX
|
||||||
|
+ select ATH79_DEV_ETH
|
||||||
|
+ select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
+ select ATH79_DEV_M25P80
|
||||||
|
+
|
||||||
|
config ATH79_MACH_PB44
|
||||||
|
bool "Atheros PB44 reference board"
|
||||||
|
select SOC_AR71XX
|
||||||
|
@@ -54,6 +137,369 @@ config ATH79_MACH_PB44
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Say 'Y' here if you want your kernel to support the
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Atheros PB44 reference board.
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+config ATH79_MACH_PB92
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+ bool "Atheros PB92 board support"
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+ select SOC_AR724X
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_PB9X_PCI if PCI
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+ select ATH79_DEV_USB
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+
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+config ATH79_MACH_AW_NR580
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+ bool "AzureWave AW-NR580 board support"
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+ select SOC_AR71XX
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+
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+config ATH79_MACH_WHR_HP_G300N
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+ bool "Buffalo WHR-HP-G300N board support"
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+ select SOC_AR724X
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_AP9X_PCI if PCI
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+
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+config ATH79_MACH_WZR_HP_AG300H
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+ bool "Buffalo WZR-HP-AG300H board support"
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+ select SOC_AR71XX
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_USB
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+
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+config ATH79_MACH_WZR_HP_G300NH
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+ bool "Buffalo WZR-HP-G300NH board support"
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+ select SOC_AR913X
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_USB
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+ select ATH79_DEV_WMAC
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+ select RTL8366_SMI
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+
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+config ATH79_MACH_WZR_HP_G300NH2
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+ bool "Buffalo WZR-HP-G300NH2 board support"
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+ select SOC_AR724X
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+ select ATH79_DEV_AP9X_PCI if PCI
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_USB
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+
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+config ATH79_MACH_WZR_HP_G450H
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+ bool "Buffalo WZR-HP-G450H board support"
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+ select SOC_AR724X
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_AP9X_PCI if PCI
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_USB
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+
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+config ATH79_MACH_WP543
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+ bool "Compex WP543/WPJ543 board support"
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+ select SOC_AR71XX
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_USB
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+ select MYLOADER
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+
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+config ATH79_MACH_WPE72
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+ bool "Compex WPE72/WPE72NX board support"
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+ select SOC_AR724X
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_USB
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+ select MYLOADER
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+
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+config ATH79_MACH_DIR_600_A1
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+ bool "D-Link DIR-600 A1/DIR-615 E4 support"
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+ select SOC_AR724X
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+ select ATH79_DEV_AP9X_PCI if PCI
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_NVRAM
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+
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+config ATH79_MACH_DIR_615_C1
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+ bool "D-Link DIR-615 rev. C1 support"
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+ select SOC_AR913X
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_WMAC
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+ select ATH79_NVRAM
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+
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+config ATH79_MACH_DIR_825_B1
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+ bool "D-Link DIR-825 rev. B1 board support"
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+ select SOC_AR71XX
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_AP9X_PCI if PCI
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_USB
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+
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+config ATH79_MACH_JA76PF
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+ bool "jjPlus JA76PF board support"
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+ select SOC_AR71XX
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_USB
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+
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+config ATH79_MACH_JWAP003
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+ bool "jjPlus JWAP003 board support"
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+ select SOC_AR71XX
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_USB
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+
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+config ATH79_MACH_WRT160NL
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+ bool "Linksys WRT160NL board support"
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+ select SOC_AR913X
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_USB
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+ select ATH79_DEV_WMAC
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+ select ATH79_NVRAM
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+
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+config ATH79_MACH_WRT400N
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+ bool "Linksys WRT400N board support"
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+ select SOC_AR71XX
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_AP9X_PCI if PCI
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+
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+config ATH79_MACH_RB4XX
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+ bool "MikroTik RouterBOARD 4xx series support"
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+ select SOC_AR71XX
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_USB
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+
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+config ATH79_MACH_RB750
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+ bool "MikroTik RouterBOARD 750 support"
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+ select SOC_AR724X
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+ select ATH79_DEV_ETH
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+
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+config ATH79_MACH_WNDR3700
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+ bool "NETGEAR WNDR3700 board support"
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+ select SOC_AR71XX
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+ select ATH79_DEV_AP9X_PCI if PCI
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_USB
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+
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+config ATH79_MACH_WNR2000
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+ bool "NETGEAR WNR2000 board support"
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+ select SOC_AR913X
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_WMAC
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+
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+config ATH79_MACH_OM2P
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+ bool "OpenMesh OM2P board support"
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+ select SOC_AR724X
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+ select ATH79_DEV_AP9X_PCI if PCI
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+
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+config ATH79_MACH_MZK_W04NU
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+ bool "Planex MZK-W04NU board support"
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+ select SOC_AR913X
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_USB
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+ select ATH79_DEV_WMAC
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+
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+config ATH79_MACH_MZK_W300NH
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+ bool "Planex MZK-W300NH board support"
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+ select SOC_AR913X
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_WMAC
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+
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+config ATH79_MACH_RW2458N
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+ bool "Redwave RW2458N board support"
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+ select SOC_AR724X
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_AP9X_PCI if PCI
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_USB
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+
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+config ATH79_MACH_EAP7660D
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+ bool "Senao EAP7660D support"
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+ select SOC_AR71XX
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+
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+config ATH79_MACH_TL_MR11U
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+ bool "TP-LINK TL-MR11U support"
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+ select SOC_AR933X
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_USB
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+ select ATH79_DEV_WMAC
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+
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+config ATH79_MACH_TL_MR3020
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+ bool "TP-LINK TL-MR3020 support"
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+ select SOC_AR933X
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_USB
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+ select ATH79_DEV_WMAC
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+
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+config ATH79_MACH_TL_MR3X20
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+ bool "TP-LINK TL-MR3220/3420 support"
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+ select SOC_AR724X
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+ select ATH79_DEV_AP9X_PCI if PCI
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_USB
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+
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+config ATH79_MACH_TL_WA901ND
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+ bool "TP-LINK TL-WA901ND support"
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+ select SOC_AR724X
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+ select ATH79_DEV_AP9X_PCI if PCI
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+
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+config ATH79_MACH_TL_WA901ND_V2
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+ bool "TP-LINK TL-WA901ND v2 support"
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+ select SOC_AR913X
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_WMAC
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+
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+config ATH79_MACH_TL_WR703N
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+ bool "TP-LINK TL-WR703N support"
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+ select SOC_AR933X
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_USB
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+ select ATH79_DEV_WMAC
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+
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+config ATH79_MACH_TL_WR741ND
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+ bool "TP-LINK TL-WR741ND support"
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+ select SOC_AR724X
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+ select ATH79_DEV_AP9X_PCI if PCI
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+
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+config ATH79_MACH_TL_WR741ND_V4
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+ bool "TP-LINK TL-WR741ND v4 support"
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+ select SOC_AR933X
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_WMAC
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+
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+config ATH79_MACH_TL_WR841N_V1
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+ bool "TP-LINK TL-WR841N v1 support"
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+ select SOC_AR71XX
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+ select ATH79_DEV_DSA
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+
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+config ATH79_MACH_TL_WR941ND
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+ bool "TP-LINK TL-WR941ND support"
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+ select SOC_AR913X
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+ select ATH79_DEV_DSA
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_WMAC
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+
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+config ATH79_MACH_TL_WR1043ND
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+ bool "TP-LINK TL-WR1043ND support"
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+ select SOC_AR913X
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_M25P80
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+ select ATH79_DEV_USB
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+ select ATH79_DEV_WMAC
|
||||||
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+
|
||||||
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+config ATH79_MACH_TL_WR2543N
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||||||
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+ bool "TP-LINK TL-WR2543N/ND support"
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||||||
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+ select SOC_AR724X
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||||||
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+ select ATH79_DEV_AP9X_PCI if PCI
|
||||||
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+ select ATH79_DEV_ETH
|
||||||
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+ select ATH79_DEV_GPIO_BUTTONS
|
||||||
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+ select ATH79_DEV_LEDS_GPIO
|
||||||
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+ select ATH79_DEV_M25P80
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||||||
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+ select ATH79_DEV_USB
|
||||||
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+
|
||||||
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+config ATH79_MACH_TEW_632BRP
|
||||||
|
+ bool "TRENDnet TEW-632BRP support"
|
||||||
|
+ select SOC_AR913X
|
||||||
|
+ select ATH79_DEV_ETH
|
||||||
|
+ select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
+ select ATH79_DEV_LEDS_GPIO
|
||||||
|
+ select ATH79_DEV_M25P80
|
||||||
|
+ select ATH79_DEV_WMAC
|
||||||
|
+ select ATH79_NVRAM
|
||||||
|
+
|
||||||
|
+config ATH79_MACH_UBNT
|
||||||
|
+ bool "Ubiquiti AR71xx based boards support"
|
||||||
|
+ select SOC_AR71XX
|
||||||
|
+ select ATH79_DEV_ETH
|
||||||
|
+ select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
+ select ATH79_DEV_LEDS_GPIO
|
||||||
|
+ select ATH79_DEV_M25P80
|
||||||
|
+ select ATH79_DEV_USB
|
||||||
|
+
|
||||||
|
config ATH79_MACH_UBNT_XM
|
||||||
|
bool "Ubiquiti Networks XM (rev 1.0) board"
|
||||||
|
select SOC_AR724X
|
||||||
|
@@ -67,6 +513,24 @@ config ATH79_MACH_UBNT_XM
|
||||||
|
Say 'Y' here if you want your kernel to support the
|
||||||
|
Ubiquiti Networks XM (rev 1.0) board.
|
||||||
|
|
||||||
|
+config ATH79_MACH_ZCN_1523H
|
||||||
|
+ bool "Zcomax ZCN-1523H support"
|
||||||
|
+ select SOC_AR724X
|
||||||
|
+ select ATH79_DEV_AP9X_PCI if PCI
|
||||||
|
+ select ATH79_DEV_ETH
|
||||||
|
+ select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
+ select ATH79_DEV_LEDS_GPIO
|
||||||
|
+ select ATH79_DEV_M25P80
|
||||||
|
+
|
||||||
|
+config ATH79_MACH_NBG460N
|
||||||
|
+ bool "Zyxel NBG460N/550N/550NH board support"
|
||||||
|
+ select SOC_AR913X
|
||||||
|
+ select ATH79_DEV_ETH
|
||||||
|
+ select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
+ select ATH79_DEV_LEDS_GPIO
|
||||||
|
+ select ATH79_DEV_M25P80
|
||||||
|
+ select ATH79_DEV_WMAC
|
||||||
|
+
|
||||||
|
endmenu
|
||||||
|
|
||||||
|
config SOC_AR71XX
|
||||||
|
@@ -96,10 +560,6 @@ config SOC_AR934X
|
||||||
|
select PCI_AR724X if PCI
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
-config ATH79_DEV_M25P80
|
||||||
|
- select ATH79_DEV_SPI
|
||||||
|
- def_bool n
|
||||||
|
-
|
||||||
|
config ATH79_DEV_AP9X_PCI
|
||||||
|
select ATH79_PCI_ATH9K_FIXUP
|
||||||
|
def_bool n
|
||||||
|
@@ -110,7 +570,14 @@ config ATH79_DEV_DSA
|
||||||
|
config ATH79_DEV_ETH
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
-config PCI_AR724X
|
||||||
|
+config ATH79_DEV_M25P80
|
||||||
|
+ select ATH79_DEV_SPI
|
||||||
|
+ def_bool n
|
||||||
|
+
|
||||||
|
+config ATH79_DEV_DSA
|
||||||
|
+ def_bool n
|
||||||
|
+
|
||||||
|
+config ATH79_DEV_ETH
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
config ATH79_DEV_GPIO_BUTTONS
|
||||||
|
@@ -135,4 +602,7 @@ config ATH79_NVRAM
|
||||||
|
config ATH79_PCI_ATH9K_FIXUP
|
||||||
|
def_bool n
|
||||||
|
|
||||||
|
+config PCI_AR724X
|
||||||
|
+ def_bool n
|
||||||
|
+
|
||||||
|
endif
|
||||||
|
--- a/arch/mips/ath79/Makefile
|
||||||
|
+++ b/arch/mips/ath79/Makefile
|
||||||
|
@@ -36,8 +36,56 @@ obj-$(CONFIG_ATH79_PCI_ATH9K_FIXUP) += p
|
||||||
|
#
|
||||||
|
# Machines
|
||||||
|
#
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_ALFA_AP96) += mach-alfa-ap96.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_ALFA_NX) += mach-alfa-nx.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_ALL0258N) += mach-all0258n.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_AP113) += mach-ap113.o
|
||||||
|
obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
|
||||||
|
obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_AP83) += mach-ap83.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_AP96) += mach-ap96.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_AW_NR580) += mach-aw-nr580.o
|
||||||
|
obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_DIR_600_A1) += mach-dir-600-a1.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_DIR_615_C1) += mach-dir-615-c1.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_DIR_825_B1) += mach-dir-825-b1.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_EAP7660D) += mach-eap7660d.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_JA76PF) += mach-ja76pf.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_JWAP003) += mach-jwap003.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_HORNET_UB) += mach-hornet-ub.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_MZK_W04NU) += mach-mzk-w04nu.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_MZK_W300NH) += mach-mzk-w300nh.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_NBG460N) += mach-nbg460n.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_OM2P) += mach-om2p.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_PB42) += mach-pb42.o
|
||||||
|
obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_PB92) += mach-pb92.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_RB4XX) += mach-rb4xx.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_RB750) += mach-rb750.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_RW2458N) += mach-rw2458n.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_TEW_632BRP) += mach-tew-632brp.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_TL_MR11U) += mach-tl-mr11u.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_TL_MR3020) += mach-tl-mr3020.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_TL_MR3X20) += mach-tl-mr3x20.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_TL_WA901ND) += mach-tl-wa901nd.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V2) += mach-tl-wa901nd-v2.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_TL_WR741ND) += mach-tl-wr741nd.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_TL_WR741ND_V4) += mach-tl-wr741nd-v4.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_TL_WR841N_V1) += mach-tl-wr841n.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_TL_WR941ND) += mach-tl-wr941nd.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_TL_WR1043ND) += mach-tl-wr1043nd.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_TL_WR2543N) += mach-tl-wr2543n.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_TL_WR703N) += mach-tl-wr703n.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_UBNT) += mach-ubnt.o
|
||||||
|
obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_WHR_HP_G300N) += mach-whr-hp-g300n.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_WNDR3700) += mach-wndr3700.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_WNR2000) += mach-wnr2000.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_WP543) += mach-wp543.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_WPE72) += mach-wpe72.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_WRT160NL) += mach-wrt160nl.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_WRT400N) += mach-wrt400n.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH) += mach-wzr-hp-g300nh.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH2) += mach-wzr-hp-g300nh2.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_WZR_HP_AG300H) += mach-wzr-hp-ag300h.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_WZR_HP_G450H) += mach-wzr-hp-g450h.o
|
||||||
|
|
@ -0,0 +1,40 @@
|
||||||
|
--- a/arch/mips/ath79/Kconfig
|
||||||
|
+++ b/arch/mips/ath79/Kconfig
|
||||||
|
@@ -491,6 +491,17 @@ config ATH79_MACH_TEW_632BRP
|
||||||
|
select ATH79_DEV_WMAC
|
||||||
|
select ATH79_NVRAM
|
||||||
|
|
||||||
|
+config ATH79_MACH_TEW_673GRU
|
||||||
|
+ bool "TRENDnet TEW-673GRU support"
|
||||||
|
+ select SOC_AR71XX
|
||||||
|
+ select ATH79_DEV_AP9X_PCI if PCI
|
||||||
|
+ select ATH79_DEV_ETH
|
||||||
|
+ select ATH79_DEV_GPIO_BUTTONS
|
||||||
|
+ select ATH79_DEV_LEDS_GPIO
|
||||||
|
+ select ATH79_DEV_M25P80
|
||||||
|
+ select ATH79_DEV_USB
|
||||||
|
+ select ATH79_NVRAM
|
||||||
|
+
|
||||||
|
config ATH79_MACH_UBNT
|
||||||
|
bool "Ubiquiti AR71xx based boards support"
|
||||||
|
select SOC_AR71XX
|
||||||
|
--- a/arch/mips/ath79/machtypes.h
|
||||||
|
+++ b/arch/mips/ath79/machtypes.h
|
||||||
|
@@ -53,6 +53,7 @@ enum ath79_mach_type {
|
||||||
|
ATH79_MACH_RB_750, /* MikroTik RouterBOARD 750 */
|
||||||
|
ATH79_MACH_RW2458N, /* Redwave RW2458N */
|
||||||
|
ATH79_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */
|
||||||
|
+ ATH79_MACH_TEW_673GRU, /* TRENDnet TEW-673GRU */
|
||||||
|
ATH79_MACH_TL_MR11U, /* TP-LINK TL-MR11U */
|
||||||
|
ATH79_MACH_TL_MR3020, /* TP-LINK TL-MR3020 */
|
||||||
|
ATH79_MACH_TL_MR3220, /* TP-LINK TL-MR3220 */
|
||||||
|
--- a/arch/mips/ath79/Makefile
|
||||||
|
+++ b/arch/mips/ath79/Makefile
|
||||||
|
@@ -64,6 +64,7 @@ obj-$(CONFIG_ATH79_MACH_RB4XX) += mach-
|
||||||
|
obj-$(CONFIG_ATH79_MACH_RB750) += mach-rb750.o
|
||||||
|
obj-$(CONFIG_ATH79_MACH_RW2458N) += mach-rw2458n.o
|
||||||
|
obj-$(CONFIG_ATH79_MACH_TEW_632BRP) += mach-tew-632brp.o
|
||||||
|
+obj-$(CONFIG_ATH79_MACH_TEW_673GRU) += mach-tew-673gru.o
|
||||||
|
obj-$(CONFIG_ATH79_MACH_TL_MR11U) += mach-tl-mr11u.o
|
||||||
|
obj-$(CONFIG_ATH79_MACH_TL_MR3020) += mach-tl-mr3020.o
|
||||||
|
obj-$(CONFIG_ATH79_MACH_TL_MR3X20) += mach-tl-mr3x20.o
|
||||||
|
|
@ -0,0 +1,23 @@
|
||||||
|
--- a/arch/mips/ath79/dev-usb.c
|
||||||
|
+++ b/arch/mips/ath79/dev-usb.c
|
||||||
|
@@ -188,16 +188,16 @@ static void __init ar934x_usb_setup(void
|
||||||
|
if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
|
||||||
|
return;
|
||||||
|
|
||||||
|
- ath79_device_reset_clear(AR934X_RESET_USBSUS_OVERRIDE);
|
||||||
|
+ ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE);
|
||||||
|
udelay(1000);
|
||||||
|
|
||||||
|
- ath79_device_reset_set(AR934X_RESET_USB_PHY);
|
||||||
|
+ ath79_device_reset_clear(AR934X_RESET_USB_PHY);
|
||||||
|
udelay(1000);
|
||||||
|
|
||||||
|
- ath79_device_reset_set(AR934X_RESET_USB_PHY_ANALOG);
|
||||||
|
+ ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG);
|
||||||
|
udelay(1000);
|
||||||
|
|
||||||
|
- ath79_device_reset_set(AR934X_RESET_USB_HOST);
|
||||||
|
+ ath79_device_reset_clear(AR934X_RESET_USB_HOST);
|
||||||
|
udelay(1000);
|
||||||
|
|
||||||
|
ath79_ehci_resources[0].start = AR934X_EHCI_BASE;
|
||||||
|
|
@ -0,0 +1,49 @@
|
||||||
|
--- a/arch/mips/ath79/dev-eth.c
|
||||||
|
+++ b/arch/mips/ath79/dev-eth.c
|
||||||
|
@@ -331,6 +331,10 @@ static void ar934x_set_speed_ge1(int spe
|
||||||
|
/* TODO */
|
||||||
|
}
|
||||||
|
|
||||||
|
+static void ath79_ddr_no_flush(void)
|
||||||
|
+{
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static void ath79_ddr_flush_ge0(void)
|
||||||
|
{
|
||||||
|
ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
|
||||||
|
@@ -371,16 +375,6 @@ static void ar933x_ddr_flush_ge1(void)
|
||||||
|
ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
|
||||||
|
}
|
||||||
|
|
||||||
|
-static void ar934x_ddr_flush_ge0(void)
|
||||||
|
-{
|
||||||
|
- ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_GE0);
|
||||||
|
-}
|
||||||
|
-
|
||||||
|
-static void ar934x_ddr_flush_ge1(void)
|
||||||
|
-{
|
||||||
|
- ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_GE1);
|
||||||
|
-}
|
||||||
|
-
|
||||||
|
static struct resource ath79_eth0_resources[] = {
|
||||||
|
{
|
||||||
|
.name = "mac_base",
|
||||||
|
@@ -817,17 +811,16 @@ void __init ath79_register_eth(unsigned
|
||||||
|
if (id == 0) {
|
||||||
|
pdata->reset_bit = AR934X_RESET_GE0_MAC |
|
||||||
|
AR934X_RESET_GE0_MDIO;
|
||||||
|
- pdata->ddr_flush =ar934x_ddr_flush_ge0;
|
||||||
|
pdata->set_speed = ar934x_set_speed_ge0;
|
||||||
|
} else {
|
||||||
|
pdata->reset_bit = AR934X_RESET_GE1_MAC |
|
||||||
|
AR934X_RESET_GE1_MDIO;
|
||||||
|
- pdata->ddr_flush = ar934x_ddr_flush_ge1;
|
||||||
|
pdata->set_speed = ar934x_set_speed_ge1;
|
||||||
|
|
||||||
|
pdata->switch_data = &ath79_switch_data;
|
||||||
|
}
|
||||||
|
|
||||||
|
+ pdata->ddr_flush = ath79_ddr_no_flush;
|
||||||
|
pdata->has_gbit = 1;
|
||||||
|
pdata->is_ar724x = 1;
|
||||||
|
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
--- a/drivers/net/phy/mdio-bitbang.c
|
||||||
|
+++ b/drivers/net/phy/mdio-bitbang.c
|
||||||
|
@@ -165,16 +165,7 @@ static int mdiobb_read(struct mii_bus *b
|
||||||
|
|
||||||
|
ctrl->ops->set_mdio_dir(ctrl, 0);
|
||||||
|
|
||||||
|
- /* check the turnaround bit: the PHY should be driving it to zero */
|
||||||
|
- if (mdiobb_get_bit(ctrl) != 0) {
|
||||||
|
- /* PHY didn't drive TA low -- flush any bits it
|
||||||
|
- * may be trying to send.
|
||||||
|
- */
|
||||||
|
- for (i = 0; i < 32; i++)
|
||||||
|
- mdiobb_get_bit(ctrl);
|
||||||
|
-
|
||||||
|
- return 0xffff;
|
||||||
|
- }
|
||||||
|
+ mdiobb_get_bit(ctrl);
|
||||||
|
|
||||||
|
ret = mdiobb_get_num(ctrl, 16);
|
||||||
|
mdiobb_get_bit(ctrl);
|
||||||
|
|
@ -0,0 +1,117 @@
|
||||||
|
--- a/arch/mips/include/asm/checksum.h
|
||||||
|
+++ b/arch/mips/include/asm/checksum.h
|
||||||
|
@@ -12,6 +12,7 @@
|
||||||
|
#define _ASM_CHECKSUM_H
|
||||||
|
|
||||||
|
#include <linux/in6.h>
|
||||||
|
+#include <linux/unaligned/packed_struct.h>
|
||||||
|
|
||||||
|
#include <asm/uaccess.h>
|
||||||
|
|
||||||
|
@@ -104,26 +105,30 @@ static inline __sum16 ip_fast_csum(const
|
||||||
|
const unsigned int *stop = word + ihl;
|
||||||
|
unsigned int csum;
|
||||||
|
int carry;
|
||||||
|
+ unsigned int w;
|
||||||
|
|
||||||
|
- csum = word[0];
|
||||||
|
- csum += word[1];
|
||||||
|
- carry = (csum < word[1]);
|
||||||
|
+ csum = __get_unaligned_cpu32(word++);
|
||||||
|
+
|
||||||
|
+ w = __get_unaligned_cpu32(word++);
|
||||||
|
+ csum += w;
|
||||||
|
+ carry = (csum < w);
|
||||||
|
csum += carry;
|
||||||
|
|
||||||
|
- csum += word[2];
|
||||||
|
- carry = (csum < word[2]);
|
||||||
|
+ w = __get_unaligned_cpu32(word++);
|
||||||
|
+ csum += w;
|
||||||
|
+ carry = (csum < w);
|
||||||
|
csum += carry;
|
||||||
|
|
||||||
|
- csum += word[3];
|
||||||
|
- carry = (csum < word[3]);
|
||||||
|
+ w = __get_unaligned_cpu32(word++);
|
||||||
|
+ csum += w;
|
||||||
|
+ carry = (csum < w);
|
||||||
|
csum += carry;
|
||||||
|
|
||||||
|
- word += 4;
|
||||||
|
do {
|
||||||
|
- csum += *word;
|
||||||
|
- carry = (csum < *word);
|
||||||
|
+ w = __get_unaligned_cpu32(word++);
|
||||||
|
+ csum += w;
|
||||||
|
+ carry = (csum < w);
|
||||||
|
csum += carry;
|
||||||
|
- word++;
|
||||||
|
} while (word != stop);
|
||||||
|
|
||||||
|
return csum_fold(csum);
|
||||||
|
--- a/include/linux/ip.h
|
||||||
|
+++ b/include/linux/ip.h
|
||||||
|
@@ -102,7 +102,7 @@ struct iphdr {
|
||||||
|
__be32 saddr;
|
||||||
|
__be32 daddr;
|
||||||
|
/*The options start here. */
|
||||||
|
-};
|
||||||
|
+} __packed;
|
||||||
|
|
||||||
|
#ifdef __KERNEL__
|
||||||
|
#include <linux/skbuff.h>
|
||||||
|
--- a/include/linux/ipv6.h
|
||||||
|
+++ b/include/linux/ipv6.h
|
||||||
|
@@ -126,7 +126,7 @@ struct ipv6hdr {
|
||||||
|
|
||||||
|
struct in6_addr saddr;
|
||||||
|
struct in6_addr daddr;
|
||||||
|
-};
|
||||||
|
+} __packed;
|
||||||
|
|
||||||
|
#ifdef __KERNEL__
|
||||||
|
/*
|
||||||
|
--- a/include/linux/tcp.h
|
||||||
|
+++ b/include/linux/tcp.h
|
||||||
|
@@ -54,7 +54,7 @@ struct tcphdr {
|
||||||
|
__be16 window;
|
||||||
|
__sum16 check;
|
||||||
|
__be16 urg_ptr;
|
||||||
|
-};
|
||||||
|
+} __packed;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The union cast uses a gcc extension to avoid aliasing problems
|
||||||
|
--- a/include/linux/udp.h
|
||||||
|
+++ b/include/linux/udp.h
|
||||||
|
@@ -24,7 +24,7 @@ struct udphdr {
|
||||||
|
__be16 dest;
|
||||||
|
__be16 len;
|
||||||
|
__sum16 check;
|
||||||
|
-};
|
||||||
|
+} __packed;
|
||||||
|
|
||||||
|
/* UDP socket options */
|
||||||
|
#define UDP_CORK 1 /* Never send partially complete segments */
|
||||||
|
--- a/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c
|
||||||
|
+++ b/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c
|
||||||
|
@@ -14,6 +14,7 @@
|
||||||
|
#include <linux/skbuff.h>
|
||||||
|
#include <linux/icmp.h>
|
||||||
|
#include <linux/sysctl.h>
|
||||||
|
+#include <linux/unaligned/packed_struct.h>
|
||||||
|
#include <net/route.h>
|
||||||
|
#include <net/ip.h>
|
||||||
|
|
||||||
|
@@ -44,8 +45,8 @@ static bool ipv4_pkt_to_tuple(const stru
|
||||||
|
if (ap == NULL)
|
||||||
|
return false;
|
||||||
|
|
||||||
|
- tuple->src.u3.ip = ap[0];
|
||||||
|
- tuple->dst.u3.ip = ap[1];
|
||||||
|
+ tuple->src.u3.ip = __get_unaligned_cpu32(ap++);
|
||||||
|
+ tuple->dst.u3.ip = __get_unaligned_cpu32(ap);
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue