mirror of https://github.com/hak5/openwrt-owl.git
imx6: add flexcan support
backport upstream changes to 3.10: - 0060-flexcan.patch: - add flexcan pinctrl and devicetree config - 0061-can-flexcan-use-correct-clock-as-base-for-bit-rate-c.patch - fix a clock issue - 0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch - fix a clock issue Signed-off-by: Tim Harvey <tharvey@gateworks.com> SVN-Revision: 39033owl
Luka Perkov
parent
bda5d40721
commit
2bbd43d065
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@ -0,0 +1,92 @@
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--- a/arch/arm/boot/dts/imx6q.dtsi
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+++ b/arch/arm/boot/dts/imx6q.dtsi
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@@ -163,6 +163,31 @@
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};
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};
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+ flexcan1 {
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+ pinctrl_flexcan1_1: flexcan1grp-1 {
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+ fsl,pins = <
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+ MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
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+ MX6Q_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
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+ >;
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+ };
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+
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+ pinctrl_flexcan1_2: flexcan1grp-2 {
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+ fsl,pins = <
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+ MX6Q_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
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+ MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
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+ >;
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+ };
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+ };
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+
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+ flexcan2 {
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+ pinctrl_flexcan2_1: flexcan2grp-1 {
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+ fsl,pins = <
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+ MX6Q_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
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+ MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
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+ >;
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+ };
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+ };
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+
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gpmi-nand {
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pinctrl_gpmi_nand_1: gpmi-nand-1 {
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fsl,pins = <
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--- a/arch/arm/boot/dts/imx6qdl.dtsi
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+++ b/arch/arm/boot/dts/imx6qdl.dtsi
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@@ -292,13 +292,21 @@
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};
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can1: flexcan@02090000 {
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+ compatible = "fsl,imx6q-flexcan";
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reg = <0x02090000 0x4000>;
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interrupts = <0 110 0x04>;
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+ clocks = <&clks 108>, <&clks 109>;
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+ clock-names = "ipg", "per";
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+ status = "disabled";
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};
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can2: flexcan@02094000 {
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+ compatible = "fsl,imx6q-flexcan";
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reg = <0x02094000 0x4000>;
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interrupts = <0 111 0x04>;
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+ clocks = <&clks 110>, <&clks 111>;
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+ clock-names = "ipg", "per";
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+ status = "disabled";
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};
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gpt: gpt@02098000 {
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--- a/arch/arm/boot/dts/imx6dl.dtsi
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+++ b/arch/arm/boot/dts/imx6dl.dtsi
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@@ -80,6 +80,31 @@
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};
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};
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+ flexcan1 {
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+ pinctrl_flexcan1_1: flexcan1grp-1 {
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+ fsl,pins = <
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+ MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
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+ MX6DL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
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+ >;
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+ };
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+
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+ pinctrl_flexcan1_2: flexcan1grp-2 {
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+ fsl,pins = <
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+ MX6DL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
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+ MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
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+ >;
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+ };
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+ };
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+
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+ flexcan2 {
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+ pinctrl_flexcan2_1: flexcan2grp-1 {
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+ fsl,pins = <
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+ MX6DL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
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+ MX6DL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
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+ >;
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+ };
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+ };
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+
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uart1 {
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pinctrl_uart1_1: uart1grp-1 {
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fsl,pins = <
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@ -0,0 +1,37 @@
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From 1a3e5173f5e72cbf7f0c8927b33082e361c16d72 Mon Sep 17 00:00:00 2001
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From: Marc Kleine-Budde <mkl@pengutronix.de>
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Date: Mon, 25 Nov 2013 22:15:20 +0100
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Subject: [PATCH] can: flexcan: use correct clock as base for bit rate
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calculation
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The flexcan IP core uses the peripheral clock ("per") as basic clock for the
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bit timing calculation. However the driver uses the the wrong clock ("ipg").
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This leads to wrong bit rates if the rates on both clock are different.
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This patch fixes the problem by using the correct clock for the bit rate
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calculation.
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Cc: linux-stable <stable@vger.kernel.org>
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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---
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drivers/net/can/flexcan.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/net/can/flexcan.c
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+++ b/drivers/net/can/flexcan.c
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@@ -1025,7 +1025,6 @@ static int flexcan_probe(struct platform
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err = PTR_ERR(clk_ipg);
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goto failed_clock;
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}
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- clock_freq = clk_get_rate(clk_ipg);
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clk_per = devm_clk_get(&pdev->dev, "per");
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if (IS_ERR(clk_per)) {
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@@ -1033,6 +1032,7 @@ static int flexcan_probe(struct platform
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err = PTR_ERR(clk_per);
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goto failed_clock;
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}
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+ clock_freq = clk_get_rate(clk_per);
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}
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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@ -0,0 +1,25 @@
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From 9b3d423707c3b1f6633be1be7e959623e10c596b Mon Sep 17 00:00:00 2001
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From: Jiada Wang <jiada_wang@mentor.com>
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Date: Wed, 30 Oct 2013 04:25:51 -0700
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Subject: [PATCH] ARM: i.MX6q: fix the wrong parent of can_root clock
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instead of pll3_usb_otg the parent of can_root clock
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should be pll3_60m.
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Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
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Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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---
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arch/arm/mach-imx/clk-imx6q.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/arch/arm/mach-imx/clk-imx6q.c
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+++ b/arch/arm/mach-imx/clk-imx6q.c
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@@ -442,7 +442,7 @@ int __init mx6q_clocks_init(void)
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clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
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clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
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clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
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- clk[can_root] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6);
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+ clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
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clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
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clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
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clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
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