mirror of https://github.com/hak5/openwrt-owl.git
imx6: backport ahci support
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 37936owl
Luka Perkov
parent
b2c852e685
commit
2964a11933
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@ -0,0 +1,306 @@
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From 9e54eae23bc9cca0d8a955018c35b1250e09a73a Mon Sep 17 00:00:00 2001
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From: Richard Zhu <r65037@freescale.com>
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Date: Wed, 24 Jul 2013 14:15:29 +0800
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Subject: [PATCH] ahci_imx: add ahci sata support on imx platforms
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imx6q contains one Synopsys AHCI SATA controller, But it can't share
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ahci_platform driver with other controllers because there are some
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misalignments of the generic AHCI controller - the bits definitions of
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the HBA registers, the Vendor Specific registers, the AHCI PHY clock
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and the AHCI signals adjustment window(GPR13 register).
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- CAP_SSS(bit20) of the HOST_CAP is writable, default value is '0',
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should be configured to be '1'
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- bit0 (only one AHCI SATA port on imx6q) of the HOST_PORTS_IMPL
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should be set to be '1'.(default 0)
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- One Vendor Specific register HOST_TIMER1MS(offset:0xe0) should be
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configured regarding to the frequency of AHB bus clock.
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- Configurations of the AHCI PHY clock, and the signal parameters of
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the GPR13
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Setup its own ahci sata driver, contained the imx6q specific
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initialized codes, re-use the generic ahci_platform driver, and keep
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the generic ahci_platform driver clean as much as possible.
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tj: patch description reformatted
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Signed-off-by: Richard Zhu <r65037@freescale.com>
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Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
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Signed-off-by: Tejun Heo <tj@kernel.org>
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---
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drivers/ata/Kconfig | 9 ++
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drivers/ata/Makefile | 1 +
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drivers/ata/ahci_imx.c | 236 +++++++++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 246 insertions(+)
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create mode 100644 drivers/ata/ahci_imx.c
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--- a/drivers/ata/Kconfig
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+++ b/drivers/ata/Kconfig
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@@ -97,6 +97,15 @@ config SATA_AHCI_PLATFORM
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If unsure, say N.
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+config AHCI_IMX
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+ tristate "Freescale i.MX AHCI SATA support"
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+ depends on SATA_AHCI_PLATFORM
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+ help
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+ This option enables support for the Freescale i.MX SoC's
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+ onboard AHCI SATA.
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+
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+ If unsure, say N.
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+
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config SATA_FSL
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tristate "Freescale 3.0Gbps SATA support"
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depends on FSL_SOC
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--- a/drivers/ata/Makefile
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+++ b/drivers/ata/Makefile
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@@ -10,6 +10,7 @@ obj-$(CONFIG_SATA_INIC162X) += sata_inic
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obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
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obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
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obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
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+obj-$(CONFIG_AHCI_IMX) += ahci_imx.o
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# SFF w/ custom DMA
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obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
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--- /dev/null
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+++ b/drivers/ata/ahci_imx.c
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@@ -0,0 +1,236 @@
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+/*
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+ * Freescale IMX AHCI SATA platform driver
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+ * Copyright 2013 Freescale Semiconductor, Inc.
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+ *
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+ * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms and conditions of the GNU General Public License,
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+ * version 2, as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope it will be useful, but WITHOUT
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+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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+ * more details.
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+ *
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+ * You should have received a copy of the GNU General Public License along with
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+ * this program. If not, see <http://www.gnu.org/licenses/>.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/regmap.h>
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+#include <linux/ahci_platform.h>
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+#include <linux/of_device.h>
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+#include <linux/mfd/syscon.h>
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+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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+#include "ahci.h"
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+
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+enum {
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+ HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
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+};
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+
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+struct imx_ahci_priv {
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+ struct platform_device *ahci_pdev;
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+ struct clk *sata_ref_clk;
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+ struct clk *ahb_clk;
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+ struct regmap *gpr;
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+};
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+
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+static int imx6q_sata_init(struct device *dev, void __iomem *mmio)
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+{
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+ int ret = 0;
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+ unsigned int reg_val;
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+ struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
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+
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+ imxpriv->gpr =
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+ syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
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+ if (IS_ERR(imxpriv->gpr)) {
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+ dev_err(dev, "failed to find fsl,imx6q-iomux-gpr regmap\n");
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+ return PTR_ERR(imxpriv->gpr);
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+ }
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+
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+ ret = clk_prepare_enable(imxpriv->sata_ref_clk);
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+ if (ret < 0) {
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+ dev_err(dev, "prepare-enable sata_ref clock err:%d\n", ret);
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+ return ret;
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+ }
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+
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+ /*
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+ * set PHY Paremeters, two steps to configure the GPR13,
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+ * one write for rest of parameters, mask of first write
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+ * is 0x07fffffd, and the other one write for setting
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+ * the mpll_clk_en.
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+ */
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+ regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK
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+ | IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK
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+ | IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK
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+ | IMX6Q_GPR13_SATA_SPD_MODE_MASK
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+ | IMX6Q_GPR13_SATA_MPLL_SS_EN
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+ | IMX6Q_GPR13_SATA_TX_ATTEN_MASK
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+ | IMX6Q_GPR13_SATA_TX_BOOST_MASK
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+ | IMX6Q_GPR13_SATA_TX_LVL_MASK
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+ | IMX6Q_GPR13_SATA_TX_EDGE_RATE
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+ , IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB
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+ | IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M
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+ | IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F
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+ | IMX6Q_GPR13_SATA_SPD_MODE_3P0G
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+ | IMX6Q_GPR13_SATA_MPLL_SS_EN
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+ | IMX6Q_GPR13_SATA_TX_ATTEN_9_16
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+ | IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB
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+ | IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
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+ regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
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+ IMX6Q_GPR13_SATA_MPLL_CLK_EN);
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+ usleep_range(100, 200);
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+
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+ /*
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+ * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
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+ * and IP vendor specific register HOST_TIMER1MS.
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+ * Configure CAP_SSS (support stagered spin up).
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+ * Implement the port0.
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+ * Get the ahb clock rate, and configure the TIMER1MS register.
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+ */
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+ reg_val = readl(mmio + HOST_CAP);
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+ if (!(reg_val & HOST_CAP_SSS)) {
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+ reg_val |= HOST_CAP_SSS;
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+ writel(reg_val, mmio + HOST_CAP);
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+ }
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+ reg_val = readl(mmio + HOST_PORTS_IMPL);
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+ if (!(reg_val & 0x1)) {
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+ reg_val |= 0x1;
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+ writel(reg_val, mmio + HOST_PORTS_IMPL);
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+ }
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+
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+ reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
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+ writel(reg_val, mmio + HOST_TIMER1MS);
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+
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+ return 0;
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+}
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+
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+static void imx6q_sata_exit(struct device *dev)
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+{
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+ struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
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+
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+ regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
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+ !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
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+ clk_disable_unprepare(imxpriv->sata_ref_clk);
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+}
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+
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+static struct ahci_platform_data imx6q_sata_pdata = {
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+ .init = imx6q_sata_init,
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+ .exit = imx6q_sata_exit,
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+};
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+
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+static const struct of_device_id imx_ahci_of_match[] = {
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+ { .compatible = "fsl,imx6q-ahci", .data = &imx6q_sata_pdata},
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
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+
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+static int imx_ahci_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct resource *mem, *irq, res[2];
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+ const struct of_device_id *of_id;
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+ const struct ahci_platform_data *pdata = NULL;
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+ struct imx_ahci_priv *imxpriv;
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+ struct device *ahci_dev;
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+ struct platform_device *ahci_pdev;
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+ int ret;
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+
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+ imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
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+ if (!imxpriv) {
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+ dev_err(dev, "can't alloc ahci_host_priv\n");
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+ return -ENOMEM;
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+ }
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+
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+ ahci_pdev = platform_device_alloc("ahci", -1);
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+ if (!ahci_pdev)
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+ return -ENODEV;
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+
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+ ahci_dev = &ahci_pdev->dev;
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+ ahci_dev->parent = dev;
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+
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+ imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
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+ if (IS_ERR(imxpriv->ahb_clk)) {
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+ dev_err(dev, "can't get ahb clock.\n");
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+ ret = PTR_ERR(imxpriv->ahb_clk);
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+ goto err_out;
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+ }
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+
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+ imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
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+ if (IS_ERR(imxpriv->sata_ref_clk)) {
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+ dev_err(dev, "can't get sata_ref clock.\n");
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+ ret = PTR_ERR(imxpriv->sata_ref_clk);
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+ goto err_out;
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+ }
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+
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+ imxpriv->ahci_pdev = ahci_pdev;
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+ platform_set_drvdata(pdev, imxpriv);
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+
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+ of_id = of_match_device(imx_ahci_of_match, dev);
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+ if (of_id) {
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+ pdata = of_id->data;
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+ } else {
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+ ret = -EINVAL;
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+ goto err_out;
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+ }
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+
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+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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+ if (!mem || !irq) {
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+ dev_err(dev, "no mmio/irq resource\n");
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+ ret = -ENOMEM;
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+ goto err_out;
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+ }
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+
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+ res[0] = *mem;
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+ res[1] = *irq;
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+
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+ ahci_dev->coherent_dma_mask = DMA_BIT_MASK(32);
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+ ahci_dev->dma_mask = &ahci_dev->coherent_dma_mask;
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+ ahci_dev->of_node = dev->of_node;
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+
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+ ret = platform_device_add_resources(ahci_pdev, res, 2);
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+ if (ret)
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+ goto err_out;
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+
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+ ret = platform_device_add_data(ahci_pdev, pdata, sizeof(*pdata));
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+ if (ret)
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+ goto err_out;
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+
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+ ret = platform_device_add(ahci_pdev);
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+ if (ret) {
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+err_out:
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+ platform_device_put(ahci_pdev);
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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+static int imx_ahci_remove(struct platform_device *pdev)
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+{
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+ struct imx_ahci_priv *imxpriv = platform_get_drvdata(pdev);
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+ struct platform_device *ahci_pdev = imxpriv->ahci_pdev;
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+
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+ platform_device_unregister(ahci_pdev);
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+ return 0;
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+}
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+
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+static struct platform_driver imx_ahci_driver = {
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+ .probe = imx_ahci_probe,
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+ .remove = imx_ahci_remove,
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+ .driver = {
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+ .name = "ahci-imx",
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+ .owner = THIS_MODULE,
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+ .of_match_table = imx_ahci_of_match,
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+ },
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+};
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+module_platform_driver(imx_ahci_driver);
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+
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+MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
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+MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
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+MODULE_LICENSE("GPL");
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+MODULE_ALIAS("ahci:imx");
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@ -0,0 +1,145 @@
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From 6a6c21ef487be47b300a0b24cd6afeb69d8b9a1a Mon Sep 17 00:00:00 2001
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From: Richard Zhu <r65037@freescale.com>
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Date: Wed, 24 Jul 2013 14:15:28 +0800
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Subject: [PATCH] ARM: imx6q: update the sata bits definitions of gpr13
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Replace the SATA_PHY_# by the more readable definitons.
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tj: Being routed through libata branch to enable implementation of
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ahci_imx.
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Signed-off-by: Richard Zhu <r65037@freescale.com>
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Acked-by: Shawn Guo <shawn.guo@linaro.org>
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Signed-off-by: Tejun Heo <tj@kernel.org>
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---
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include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 121 +++++++++++++++++++---------
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1 file changed, 84 insertions(+), 37 deletions(-)
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--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
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+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
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@@ -279,41 +279,88 @@
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#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
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#define IMX6Q_GPR13_CAN1_STOP_REQ BIT(28)
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#define IMX6Q_GPR13_ENET_STOP_REQ BIT(27)
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-#define IMX6Q_GPR13_SATA_PHY_8_MASK (0x7 << 24)
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-#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB (0x0 << 24)
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-#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB (0x1 << 24)
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-#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB (0x2 << 24)
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-#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB (0x3 << 24)
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-#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB (0x4 << 24)
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-#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB (0x5 << 24)
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-#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB (0x6 << 24)
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-#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB (0x7 << 24)
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-#define IMX6Q_GPR13_SATA_PHY_7_MASK (0x1f << 19)
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-#define IMX6Q_GPR13_SATA_PHY_7_SATA1I (0x10 << 19)
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-#define IMX6Q_GPR13_SATA_PHY_7_SATA1M (0x10 << 19)
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-#define IMX6Q_GPR13_SATA_PHY_7_SATA1X (0x1a << 19)
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-#define IMX6Q_GPR13_SATA_PHY_7_SATA2I (0x12 << 19)
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-#define IMX6Q_GPR13_SATA_PHY_7_SATA2M (0x12 << 19)
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-#define IMX6Q_GPR13_SATA_PHY_7_SATA2X (0x1a << 19)
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-#define IMX6Q_GPR13_SATA_PHY_6_MASK (0x7 << 16)
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-#define IMX6Q_GPR13_SATA_SPEED_MASK BIT(15)
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-#define IMX6Q_GPR13_SATA_SPEED_1P5G 0x0
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-#define IMX6Q_GPR13_SATA_SPEED_3P0G BIT(15)
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-#define IMX6Q_GPR13_SATA_PHY_5 BIT(14)
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-#define IMX6Q_GPR13_SATA_PHY_4_MASK (0x7 << 11)
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-#define IMX6Q_GPR13_SATA_PHY_4_16_16 (0x0 << 11)
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-#define IMX6Q_GPR13_SATA_PHY_4_14_16 (0x1 << 11)
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-#define IMX6Q_GPR13_SATA_PHY_4_12_16 (0x2 << 11)
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-#define IMX6Q_GPR13_SATA_PHY_4_10_16 (0x3 << 11)
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-#define IMX6Q_GPR13_SATA_PHY_4_9_16 (0x4 << 11)
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-#define IMX6Q_GPR13_SATA_PHY_4_8_16 (0x5 << 11)
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-#define IMX6Q_GPR13_SATA_PHY_3_MASK (0xf << 7)
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-#define IMX6Q_GPR13_SATA_PHY_3_OFF 0x7
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-#define IMX6Q_GPR13_SATA_PHY_2_MASK (0x1f << 2)
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-#define IMX6Q_GPR13_SATA_PHY_2_OFF 0x2
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-#define IMX6Q_GPR13_SATA_PHY_1_MASK (0x3 << 0)
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-#define IMX6Q_GPR13_SATA_PHY_1_FAST (0x0 << 0)
|
||||
-#define IMX6Q_GPR13_SATA_PHY_1_MED (0x1 << 0)
|
||||
-#define IMX6Q_GPR13_SATA_PHY_1_SLOW (0x2 << 0)
|
||||
-
|
||||
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK (0x7 << 24)
|
||||
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB (0x0 << 24)
|
||||
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB (0x1 << 24)
|
||||
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB (0x2 << 24)
|
||||
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB (0x3 << 24)
|
||||
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB (0x4 << 24)
|
||||
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB (0x5 << 24)
|
||||
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB (0x6 << 24)
|
||||
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB (0x7 << 24)
|
||||
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK (0x1f << 19)
|
||||
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1I (0x10 << 19)
|
||||
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1M (0x10 << 19)
|
||||
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1X (0x1a << 19)
|
||||
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2I (0x12 << 19)
|
||||
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M (0x12 << 19)
|
||||
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2X (0x1a << 19)
|
||||
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK (0x7 << 16)
|
||||
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_1F (0x0 << 16)
|
||||
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_2F (0x1 << 16)
|
||||
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_4F (0x2 << 16)
|
||||
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F (0x3 << 16)
|
||||
+#define IMX6Q_GPR13_SATA_SPD_MODE_MASK BIT(15)
|
||||
+#define IMX6Q_GPR13_SATA_SPD_MODE_1P5G 0x0
|
||||
+#define IMX6Q_GPR13_SATA_SPD_MODE_3P0G BIT(15)
|
||||
+#define IMX6Q_GPR13_SATA_MPLL_SS_EN BIT(14)
|
||||
+#define IMX6Q_GPR13_SATA_TX_ATTEN_MASK (0x7 << 11)
|
||||
+#define IMX6Q_GPR13_SATA_TX_ATTEN_16_16 (0x0 << 11)
|
||||
+#define IMX6Q_GPR13_SATA_TX_ATTEN_14_16 (0x1 << 11)
|
||||
+#define IMX6Q_GPR13_SATA_TX_ATTEN_12_16 (0x2 << 11)
|
||||
+#define IMX6Q_GPR13_SATA_TX_ATTEN_10_16 (0x3 << 11)
|
||||
+#define IMX6Q_GPR13_SATA_TX_ATTEN_9_16 (0x4 << 11)
|
||||
+#define IMX6Q_GPR13_SATA_TX_ATTEN_8_16 (0x5 << 11)
|
||||
+#define IMX6Q_GPR13_SATA_TX_BOOST_MASK (0xf << 7)
|
||||
+#define IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB (0x0 << 7)
|
||||
+#define IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB (0x1 << 7)
|
||||
+#define IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB (0x2 << 7)
|
||||
+#define IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB (0x3 << 7)
|
||||
+#define IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB (0x4 << 7)
|
||||
+#define IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB (0x5 << 7)
|
||||
+#define IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB (0x6 << 7)
|
||||
+#define IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB (0x7 << 7)
|
||||
+#define IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB (0x8 << 7)
|
||||
+#define IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB (0x9 << 7)
|
||||
+#define IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB (0xa << 7)
|
||||
+#define IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB (0xb << 7)
|
||||
+#define IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB (0xc << 7)
|
||||
+#define IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB (0xd << 7)
|
||||
+#define IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB (0xe << 7)
|
||||
+#define IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB (0xf << 7)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_MASK (0x1f << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_0_937_V (0x00 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_0_947_V (0x01 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_0_957_V (0x02 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_0_966_V (0x03 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_0_976_V (0x04 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_0_986_V (0x05 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_0_996_V (0x06 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_005_V (0x07 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_015_V (0x08 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_025_V (0x09 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_035_V (0x0a << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_045_V (0x0b << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_054_V (0x0c << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_064_V (0x0d << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_074_V (0x0e << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_084_V (0x0f << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_094_V (0x10 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_104_V (0x11 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_113_V (0x12 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_123_V (0x13 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_133_V (0x14 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_143_V (0x15 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_152_V (0x16 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_162_V (0x17 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_172_V (0x18 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_182_V (0x19 << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_191_V (0x1a << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_201_V (0x1b << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_211_V (0x1c << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_221_V (0x1d << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_230_V (0x1e << 2)
|
||||
+#define IMX6Q_GPR13_SATA_TX_LVL_1_240_V (0x1f << 2)
|
||||
+#define IMX6Q_GPR13_SATA_MPLL_CLK_EN BIT(1)
|
||||
+#define IMX6Q_GPR13_SATA_TX_EDGE_RATE BIT(0)
|
||||
#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
From 0fb1f804269e549b556b475c8655bc862c220622 Mon Sep 17 00:00:00 2001
|
||||
From: Richard Zhu <r65037@freescale.com>
|
||||
Date: Tue, 16 Jul 2013 11:28:46 +0800
|
||||
Subject: [PATCH] ARM: dtsi: enable ahci sata on imx6q platforms
|
||||
|
||||
Only imx6q has the ahci sata controller, enable
|
||||
it on imx6q platforms.
|
||||
|
||||
Signed-off-by: Richard Zhu <r65037@freescale.com>
|
||||
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
||||
---
|
||||
arch/arm/boot/dts/imx6q-sabreauto.dts | 4 ++++
|
||||
arch/arm/boot/dts/imx6q-sabrelite.dts | 4 ++++
|
||||
arch/arm/boot/dts/imx6q-sabresd.dts | 4 ++++
|
||||
arch/arm/boot/dts/imx6q.dtsi | 9 +++++++++
|
||||
4 files changed, 21 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
|
||||
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
|
||||
@@ -33,3 +33,7 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+&sata {
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
|
||||
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
|
||||
@@ -65,6 +65,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&sata {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&ecspi1 {
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio3 19 0>;
|
||||
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
|
||||
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
|
||||
@@ -37,3 +37,7 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+&sata {
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- a/arch/arm/boot/dts/imx6q.dtsi
|
||||
+++ b/arch/arm/boot/dts/imx6q.dtsi
|
||||
@@ -332,6 +332,15 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ sata: sata@02200000 {
|
||||
+ compatible = "fsl,imx6q-ahci";
|
||||
+ reg = <0x02200000 0x4000>;
|
||||
+ interrupts = <0 39 0x04>;
|
||||
+ clocks = <&clks 154>, <&clks 187>, <&clks 105>;
|
||||
+ clock-names = "sata", "sata_ref", "ahb";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
ipu2: ipu@02800000 {
|
||||
#crtc-cells = <1>;
|
||||
compatible = "fsl,imx6q-ipu";
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
From 867974fc09f93bdd7f98d46ac3733934486bbf4a Mon Sep 17 00:00:00 2001
|
||||
From: Tejun Heo <tj@kernel.org>
|
||||
Date: Fri, 26 Jul 2013 08:57:56 -0400
|
||||
Subject: [PATCH] ahci_imx: depend on CONFIG_MFD_SYSCON
|
||||
|
||||
ahci_imx makes use of regmap but the dependency wasn't specified in
|
||||
Kconfig leading build failures if CONFIG_AHCI_IMX is enabled but
|
||||
CONFIG_MFD_SYSCON is not. Add the Kconfig dependency.
|
||||
|
||||
Signed-off-by: Tejun Heo <tj@kernel.org>
|
||||
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
|
||||
---
|
||||
drivers/ata/Kconfig | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/ata/Kconfig
|
||||
+++ b/drivers/ata/Kconfig
|
||||
@@ -99,7 +99,7 @@ config SATA_AHCI_PLATFORM
|
||||
|
||||
config AHCI_IMX
|
||||
tristate "Freescale i.MX AHCI SATA support"
|
||||
- depends on SATA_AHCI_PLATFORM
|
||||
+ depends on SATA_AHCI_PLATFORM && MFD_SYSCON
|
||||
help
|
||||
This option enables support for the Freescale i.MX SoC's
|
||||
onboard AHCI SATA.
|
||||
Loading…
Reference in New Issue