mirror of https://github.com/hak5/openwrt-owl.git
brcm47xx: add support for kernel 2.6.33
Thanks to acoul and tripolar SVN-Revision: 19955owl
Hauke Mehrtens
parent
0e4eaea770
commit
141d53ad07
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@ -0,0 +1,204 @@
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CONFIG_32BIT=y
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# CONFIG_64BIT is not set
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# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
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# CONFIG_AR7 is not set
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# CONFIG_ARCH_HAS_ILOG2_U32 is not set
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# CONFIG_ARCH_HAS_ILOG2_U64 is not set
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_POPULATES_NODE_MAP=y
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# CONFIG_ARCH_SUPPORTS_MSI is not set
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CONFIG_ARCH_SUPPORTS_OPROFILE=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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# CONFIG_ARPD is not set
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CONFIG_B44=y
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CONFIG_B44_PCI=y
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CONFIG_B44_PCICORE_AUTOSELECT=y
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CONFIG_B44_PCI_AUTOSELECT=y
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CONFIG_BCM47XX=y
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CONFIG_BCM47XX_WDT=y
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# CONFIG_BCM63XX is not set
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CONFIG_BITREVERSE=y
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# CONFIG_BSD_PROCESS_ACCT is not set
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# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
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# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
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CONFIG_CEVT_R4K=y
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CONFIG_CEVT_R4K_LIB=y
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CONFIG_CFE=y
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# CONFIG_CPU_BIG_ENDIAN is not set
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# CONFIG_CPU_CAVIUM_OCTEON is not set
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CONFIG_CPU_HAS_PREFETCH=y
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CONFIG_CPU_HAS_SYNC=y
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CONFIG_CPU_LITTLE_ENDIAN=y
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# CONFIG_CPU_LOONGSON2E is not set
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# CONFIG_CPU_LOONGSON2F is not set
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CONFIG_CPU_MIPS32=y
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CONFIG_CPU_MIPS32_R1=y
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# CONFIG_CPU_MIPS32_R2 is not set
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# CONFIG_CPU_MIPS64_R1 is not set
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# CONFIG_CPU_MIPS64_R2 is not set
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CONFIG_CPU_MIPSR1=y
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# CONFIG_CPU_NEVADA is not set
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# CONFIG_CPU_R10000 is not set
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# CONFIG_CPU_R3000 is not set
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# CONFIG_CPU_R4300 is not set
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# CONFIG_CPU_R4X00 is not set
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# CONFIG_CPU_R5000 is not set
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# CONFIG_CPU_R5432 is not set
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# CONFIG_CPU_R5500 is not set
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# CONFIG_CPU_R6000 is not set
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# CONFIG_CPU_R8000 is not set
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# CONFIG_CPU_RM7000 is not set
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# CONFIG_CPU_RM9000 is not set
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# CONFIG_CPU_SB1 is not set
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CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
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CONFIG_CPU_SUPPORTS_HIGHMEM=y
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# CONFIG_CPU_TX39XX is not set
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# CONFIG_CPU_TX49XX is not set
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# CONFIG_CPU_VR41XX is not set
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CONFIG_CSRC_R4K=y
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CONFIG_CSRC_R4K_LIB=y
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CONFIG_DECOMPRESS_LZMA=y
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# CONFIG_DEFAULT_SECURITY_SELINUX is not set
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# CONFIG_DEFAULT_SECURITY_SMACK is not set
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# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
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CONFIG_DEVPORT=y
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# CONFIG_DM9000 is not set
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CONFIG_DMA_NEED_PCI_MAP_STATE=y
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CONFIG_DMA_NONCOHERENT=y
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# CONFIG_FSNOTIFY is not set
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
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CONFIG_GENERIC_CMOS_UPDATE=y
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CONFIG_GENERIC_FIND_LAST_BIT=y
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CONFIG_GENERIC_FIND_NEXT_BIT=y
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CONFIG_GENERIC_GPIO=y
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CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
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# CONFIG_HAMRADIO is not set
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CONFIG_HARDWARE_WATCHPOINTS=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT=y
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CONFIG_HAVE_ARCH_KGDB=y
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CONFIG_HAVE_DYNAMIC_FTRACE=y
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CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
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CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
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CONFIG_HAVE_GENERIC_DMA_COHERENT=y
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CONFIG_HAVE_IDE=y
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CONFIG_HAVE_OPROFILE=y
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CONFIG_HW_HAS_PCI=y
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CONFIG_HW_RANDOM=y
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CONFIG_HZ=250
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# CONFIG_HZ_100 is not set
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CONFIG_HZ_250=y
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CONFIG_INITRAMFS_SOURCE=""
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# CONFIG_INLINE_READ_LOCK is not set
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# CONFIG_INLINE_READ_LOCK_BH is not set
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# CONFIG_INLINE_READ_LOCK_IRQ is not set
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# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
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# CONFIG_INLINE_READ_TRYLOCK is not set
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CONFIG_INLINE_READ_UNLOCK=y
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# CONFIG_INLINE_READ_UNLOCK_BH is not set
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CONFIG_INLINE_READ_UNLOCK_IRQ=y
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# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
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# CONFIG_INLINE_SPIN_LOCK is not set
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# CONFIG_INLINE_SPIN_LOCK_BH is not set
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# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
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# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
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# CONFIG_INLINE_SPIN_TRYLOCK is not set
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# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
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CONFIG_INLINE_SPIN_UNLOCK=y
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# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
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CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
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# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
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# CONFIG_INLINE_WRITE_LOCK is not set
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# CONFIG_INLINE_WRITE_LOCK_BH is not set
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# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
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# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
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# CONFIG_INLINE_WRITE_TRYLOCK is not set
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CONFIG_INLINE_WRITE_UNLOCK=y
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# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
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CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
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# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
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# CONFIG_IP_ROUTE_VERBOSE is not set
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CONFIG_IRQ_CPU=y
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CONFIG_KALLSYMS=y
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CONFIG_LEDS_GPIO=y
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CONFIG_LOONGSON_UART_BASE=y
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# CONFIG_MACH_ALCHEMY is not set
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# CONFIG_MACH_DECSTATION is not set
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# CONFIG_MACH_JAZZ is not set
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# CONFIG_MACH_LOONGSON is not set
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# CONFIG_MACH_TX39XX is not set
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# CONFIG_MACH_TX49XX is not set
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# CONFIG_MACH_VR41XX is not set
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# CONFIG_MIKROTIK_RB532 is not set
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CONFIG_MIPS=y
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# CONFIG_MIPS_COBALT is not set
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CONFIG_MIPS_L1_CACHE_SHIFT=5
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# CONFIG_MIPS_MACHINE is not set
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# CONFIG_MIPS_MALTA is not set
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CONFIG_MIPS_MT_DISABLED=y
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# CONFIG_MIPS_MT_SMP is not set
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# CONFIG_MIPS_MT_SMTC is not set
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# CONFIG_MIPS_SIM is not set
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CONFIG_MTD_BCM47XX=y
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# CONFIG_MUTEX_SPIN_ON_OWNER is not set
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# CONFIG_NO_IOPORT is not set
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# CONFIG_NXP_STB220 is not set
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# CONFIG_NXP_STB225 is not set
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CONFIG_PAGEFLAGS_EXTENDED=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PHYLIB=y
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# CONFIG_PMC_MSP is not set
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# CONFIG_PMC_YOSEMITE is not set
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# CONFIG_PNX8550_JBS is not set
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# CONFIG_PNX8550_STB810 is not set
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# CONFIG_POWERTV is not set
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# CONFIG_PROC_KCORE is not set
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CONFIG_SCHED_OMIT_FRAME_POINTER=y
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# CONFIG_SCSI_DMA is not set
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# CONFIG_SERIAL_8250_DETECT_IRQ is not set
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CONFIG_SERIAL_8250_EXTENDED=y
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# CONFIG_SERIAL_8250_MANY_PORTS is not set
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# CONFIG_SERIAL_8250_RSA is not set
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CONFIG_SERIAL_8250_SHARE_IRQ=y
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# CONFIG_SGI_IP22 is not set
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# CONFIG_SGI_IP27 is not set
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# CONFIG_SGI_IP28 is not set
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# CONFIG_SGI_IP32 is not set
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# CONFIG_SIBYTE_BIGSUR is not set
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# CONFIG_SIBYTE_CARMEL is not set
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# CONFIG_SIBYTE_CRHINE is not set
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# CONFIG_SIBYTE_CRHONE is not set
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# CONFIG_SIBYTE_LITTLESUR is not set
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# CONFIG_SIBYTE_RHONE is not set
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# CONFIG_SIBYTE_SENTOSA is not set
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# CONFIG_SIBYTE_SWARM is not set
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CONFIG_SSB=y
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CONFIG_SSB_B43_PCI_BRIDGE=y
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CONFIG_SSB_DEBUG=y
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CONFIG_SSB_DRIVER_EXTIF=y
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CONFIG_SSB_DRIVER_GIGE=y
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CONFIG_SSB_DRIVER_MIPS=y
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CONFIG_SSB_DRIVER_PCICORE=y
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CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
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CONFIG_SSB_EMBEDDED=y
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CONFIG_SSB_PCICORE_HOSTMODE=y
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CONFIG_SSB_PCIHOST=y
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CONFIG_SSB_PCIHOST_POSSIBLE=y
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CONFIG_SSB_SERIAL=y
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CONFIG_SSB_SPROM=y
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CONFIG_SYS_HAS_CPU_MIPS32_R1=y
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CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
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CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
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CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
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# CONFIG_TC35815 is not set
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# CONFIG_TINY_RCU is not set
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CONFIG_TRAD_SIGNALS=y
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# CONFIG_TREE_PREEMPT_RCU is not set
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CONFIG_TREE_RCU=y
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CONFIG_USB_SUPPORT=y
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CONFIG_WATCHDOG_NOWAYOUT=y
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CONFIG_ZONE_DMA_FLAG=0
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@ -0,0 +1,25 @@
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--- a/drivers/mtd/maps/Kconfig
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+++ b/drivers/mtd/maps/Kconfig
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@@ -325,6 +325,12 @@ config MTD_CFI_FLAGADM
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Mapping for the Flaga digital module. If you don't have one, ignore
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this setting.
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+config MTD_BCM47XX
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+ tristate "BCM47xx flash device"
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+ depends on MIPS && MTD_CFI && BCM47XX
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+ help
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+ Support for the flash chips on the BCM947xx board.
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+
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config MTD_REDWOOD
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tristate "CFI Flash devices mapped on IBM Redwood"
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depends on MTD_CFI && ( REDWOOD_4 || REDWOOD_5 || REDWOOD_6 )
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--- a/drivers/mtd/maps/Makefile
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+++ b/drivers/mtd/maps/Makefile
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@@ -29,6 +29,7 @@ obj-$(CONFIG_MTD_PMC_MSP_EVM) += pmcms
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obj-$(CONFIG_MTD_PCMCIA) += pcmciamtd.o
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obj-$(CONFIG_MTD_RPXLITE) += rpxlite.o
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obj-$(CONFIG_MTD_TQM8XXL) += tqm8xxl.o
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+obj-$(CONFIG_MTD_BCM47XX) += bcm47xx-flash.o
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obj-$(CONFIG_MTD_SA1100) += sa1100-flash.o
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obj-$(CONFIG_MTD_SBC_GXX) += sbc_gxx.o
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obj-$(CONFIG_MTD_SC520CDP) += sc520cdp.o
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@ -0,0 +1,89 @@
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -205,7 +205,6 @@ config MIPS_MALTA
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select I8259
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select MIPS_BOARDS_GEN
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select MIPS_BONITO64
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- select MIPS_CPU_SCACHE
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select PCI_GT64XXX_PCI0
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select MIPS_MSC
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select SWAP_IO_SPACE
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@@ -1561,13 +1560,6 @@ config IP22_CPU_SCACHE
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bool
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select BOARD_SCACHE
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-#
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-# Support for a MIPS32 / MIPS64 style S-caches
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-#
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-config MIPS_CPU_SCACHE
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- bool
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- select BOARD_SCACHE
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-
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config R5000_CPU_SCACHE
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bool
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select BOARD_SCACHE
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--- a/arch/mips/kernel/cpu-probe.c
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+++ b/arch/mips/kernel/cpu-probe.c
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@@ -759,6 +759,8 @@ static inline void cpu_probe_mips(struct
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case PRID_IMP_25KF:
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c->cputype = CPU_25KF;
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__cpu_name[cpu] = "MIPS 25Kc";
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+ /* Probe for L2 cache */
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+ c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
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break;
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case PRID_IMP_34K:
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c->cputype = CPU_34K;
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--- a/arch/mips/mm/Makefile
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+++ b/arch/mips/mm/Makefile
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@@ -33,6 +33,5 @@ obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-oct
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obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
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obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
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obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o
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-obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o
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EXTRA_CFLAGS += -Werror
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--- a/arch/mips/mm/c-r4k.c
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+++ b/arch/mips/mm/c-r4k.c
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@@ -1148,7 +1148,6 @@ static void __init loongson2_sc_init(voi
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extern int r5k_sc_init(void);
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extern int rm7k_sc_init(void);
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-extern int mips_sc_init(void);
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static void __cpuinit setup_scache(void)
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{
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@@ -1202,29 +1201,17 @@ static void __cpuinit setup_scache(void)
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#endif
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default:
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- if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
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- c->isa_level == MIPS_CPU_ISA_M32R2 ||
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- c->isa_level == MIPS_CPU_ISA_M64R1 ||
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- c->isa_level == MIPS_CPU_ISA_M64R2) {
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-#ifdef CONFIG_MIPS_CPU_SCACHE
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- if (mips_sc_init ()) {
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- scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
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- printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
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- scache_size >> 10,
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- way_string[c->scache.ways], c->scache.linesz);
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- }
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-#else
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- if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
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- panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
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-#endif
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- return;
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- }
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sc_present = 0;
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}
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if (!sc_present)
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return;
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+ if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
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+ c->isa_level == MIPS_CPU_ISA_M64R1) &&
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+ !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
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+ panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
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+
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/* compute a couple of other cache variables */
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c->scache.waysize = scache_size / c->scache.ways;
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@ -0,0 +1,367 @@
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--- a/arch/mips/include/asm/r4kcache.h
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+++ b/arch/mips/include/asm/r4kcache.h
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@@ -17,6 +17,20 @@
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#include <asm/cpu-features.h>
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||||||
|
#include <asm/mipsmtregs.h>
|
||||||
|
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+#include <asm/paccess.h>
|
||||||
|
+#include <linux/ssb/ssb.h>
|
||||||
|
+#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE + SSB_IMSTATE)))
|
||||||
|
+
|
||||||
|
+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
|
||||||
|
+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
|
||||||
|
+#else
|
||||||
|
+#define BCM4710_DUMMY_RREG()
|
||||||
|
+
|
||||||
|
+#define BCM4710_FILL_TLB(addr)
|
||||||
|
+#define BCM4710_PROTECTED_FILL_TLB(addr)
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
/*
|
||||||
|
* This macro return a properly sign-extended address suitable as base address
|
||||||
|
* for indexed cache operations. Two issues here:
|
||||||
|
@@ -150,6 +164,7 @@ static inline void flush_icache_line_ind
|
||||||
|
static inline void flush_dcache_line_indexed(unsigned long addr)
|
||||||
|
{
|
||||||
|
__dflush_prologue
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
cache_op(Index_Writeback_Inv_D, addr);
|
||||||
|
__dflush_epilogue
|
||||||
|
}
|
||||||
|
@@ -169,6 +184,7 @@ static inline void flush_icache_line(uns
|
||||||
|
static inline void flush_dcache_line(unsigned long addr)
|
||||||
|
{
|
||||||
|
__dflush_prologue
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
cache_op(Hit_Writeback_Inv_D, addr);
|
||||||
|
__dflush_epilogue
|
||||||
|
}
|
||||||
|
@@ -176,6 +192,7 @@ static inline void flush_dcache_line(uns
|
||||||
|
static inline void invalidate_dcache_line(unsigned long addr)
|
||||||
|
{
|
||||||
|
__dflush_prologue
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
cache_op(Hit_Invalidate_D, addr);
|
||||||
|
__dflush_epilogue
|
||||||
|
}
|
||||||
|
@@ -208,6 +225,7 @@ static inline void flush_scache_line(uns
|
||||||
|
*/
|
||||||
|
static inline void protected_flush_icache_line(unsigned long addr)
|
||||||
|
{
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
protected_cache_op(Hit_Invalidate_I, addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -219,6 +237,7 @@ static inline void protected_flush_icach
|
||||||
|
*/
|
||||||
|
static inline void protected_writeback_dcache_line(unsigned long addr)
|
||||||
|
{
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
protected_cache_op(Hit_Writeback_Inv_D, addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -339,8 +358,52 @@ static inline void invalidate_tcache_pag
|
||||||
|
: "r" (base), \
|
||||||
|
"i" (op));
|
||||||
|
|
||||||
|
+static inline void blast_dcache(void)
|
||||||
|
+{
|
||||||
|
+ unsigned long start = KSEG0;
|
||||||
|
+ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
|
||||||
|
+ unsigned long end = (start + dcache_size);
|
||||||
|
+
|
||||||
|
+ do {
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
+ cache_op(Index_Writeback_Inv_D, start);
|
||||||
|
+ start += current_cpu_data.dcache.linesz;
|
||||||
|
+ } while(start < end);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static inline void blast_dcache_page(unsigned long page)
|
||||||
|
+{
|
||||||
|
+ unsigned long start = page;
|
||||||
|
+ unsigned long end = start + PAGE_SIZE;
|
||||||
|
+
|
||||||
|
+ BCM4710_FILL_TLB(start);
|
||||||
|
+ do {
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
+ cache_op(Hit_Writeback_Inv_D, start);
|
||||||
|
+ start += current_cpu_data.dcache.linesz;
|
||||||
|
+ } while(start < end);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static inline void blast_dcache_page_indexed(unsigned long page)
|
||||||
|
+{
|
||||||
|
+ unsigned long start = page;
|
||||||
|
+ unsigned long end = start + PAGE_SIZE;
|
||||||
|
+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
|
||||||
|
+ unsigned long ws_end = current_cpu_data.dcache.ways <<
|
||||||
|
+ current_cpu_data.dcache.waybit;
|
||||||
|
+ unsigned long ws, addr;
|
||||||
|
+ for (ws = 0; ws < ws_end; ws += ws_inc) {
|
||||||
|
+ start = page + ws;
|
||||||
|
+ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
+ cache_op(Index_Writeback_Inv_D, addr);
|
||||||
|
+ }
|
||||||
|
+ }
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+
|
||||||
|
/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
|
||||||
|
-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
|
||||||
|
+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
|
||||||
|
static inline void blast_##pfx##cache##lsize(void) \
|
||||||
|
{ \
|
||||||
|
unsigned long start = INDEX_BASE; \
|
||||||
|
@@ -352,6 +415,7 @@ static inline void blast_##pfx##cache##l
|
||||||
|
\
|
||||||
|
__##pfx##flush_prologue \
|
||||||
|
\
|
||||||
|
+ war \
|
||||||
|
for (ws = 0; ws < ws_end; ws += ws_inc) \
|
||||||
|
for (addr = start; addr < end; addr += lsize * 32) \
|
||||||
|
cache##lsize##_unroll32(addr|ws, indexop); \
|
||||||
|
@@ -366,6 +430,7 @@ static inline void blast_##pfx##cache##l
|
||||||
|
\
|
||||||
|
__##pfx##flush_prologue \
|
||||||
|
\
|
||||||
|
+ war \
|
||||||
|
do { \
|
||||||
|
cache##lsize##_unroll32(start, hitop); \
|
||||||
|
start += lsize * 32; \
|
||||||
|
@@ -384,6 +449,8 @@ static inline void blast_##pfx##cache##l
|
||||||
|
current_cpu_data.desc.waybit; \
|
||||||
|
unsigned long ws, addr; \
|
||||||
|
\
|
||||||
|
+ war \
|
||||||
|
+ \
|
||||||
|
__##pfx##flush_prologue \
|
||||||
|
\
|
||||||
|
for (ws = 0; ws < ws_end; ws += ws_inc) \
|
||||||
|
@@ -393,36 +460,38 @@ static inline void blast_##pfx##cache##l
|
||||||
|
__##pfx##flush_epilogue \
|
||||||
|
}
|
||||||
|
|
||||||
|
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
|
||||||
|
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
|
||||||
|
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
|
||||||
|
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
|
||||||
|
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
|
||||||
|
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
|
||||||
|
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
|
||||||
|
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
|
||||||
|
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
|
||||||
|
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
|
||||||
|
-
|
||||||
|
-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
|
||||||
|
-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
|
||||||
|
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
|
||||||
|
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
|
||||||
|
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
|
||||||
|
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
|
||||||
|
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
|
||||||
|
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
|
||||||
|
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
|
||||||
|
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
|
||||||
|
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
|
||||||
|
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
|
||||||
|
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
|
||||||
|
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
|
||||||
|
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
|
||||||
|
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
|
||||||
|
+
|
||||||
|
+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
|
||||||
|
+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
|
||||||
|
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
|
||||||
|
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
|
||||||
|
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
|
||||||
|
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
|
||||||
|
|
||||||
|
/* build blast_xxx_range, protected_blast_xxx_range */
|
||||||
|
-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
|
||||||
|
+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
|
||||||
|
static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
|
||||||
|
unsigned long end) \
|
||||||
|
{ \
|
||||||
|
unsigned long lsize = cpu_##desc##_line_size(); \
|
||||||
|
unsigned long addr = start & ~(lsize - 1); \
|
||||||
|
unsigned long aend = (end - 1) & ~(lsize - 1); \
|
||||||
|
+ war \
|
||||||
|
\
|
||||||
|
__##pfx##flush_prologue \
|
||||||
|
\
|
||||||
|
while (1) { \
|
||||||
|
+ war2 \
|
||||||
|
prot##cache_op(hitop, addr); \
|
||||||
|
if (addr == aend) \
|
||||||
|
break; \
|
||||||
|
@@ -432,13 +501,13 @@ static inline void prot##blast_##pfx##ca
|
||||||
|
__##pfx##flush_epilogue \
|
||||||
|
}
|
||||||
|
|
||||||
|
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
|
||||||
|
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
|
||||||
|
-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
|
||||||
|
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
|
||||||
|
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
|
||||||
|
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
|
||||||
|
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
|
||||||
|
+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
|
||||||
|
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
|
||||||
|
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
|
||||||
|
/* blast_inv_dcache_range */
|
||||||
|
-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
|
||||||
|
-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
|
||||||
|
+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
|
||||||
|
+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
|
||||||
|
|
||||||
|
#endif /* _ASM_R4KCACHE_H */
|
||||||
|
--- a/arch/mips/include/asm/stackframe.h
|
||||||
|
+++ b/arch/mips/include/asm/stackframe.h
|
||||||
|
@@ -430,6 +430,10 @@
|
||||||
|
.macro RESTORE_SP_AND_RET
|
||||||
|
LONG_L sp, PT_R29(sp)
|
||||||
|
.set mips3
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ nop
|
||||||
|
+ nop
|
||||||
|
+#endif
|
||||||
|
eret
|
||||||
|
.set mips0
|
||||||
|
.endm
|
||||||
|
--- a/arch/mips/kernel/genex.S
|
||||||
|
+++ b/arch/mips/kernel/genex.S
|
||||||
|
@@ -52,6 +52,10 @@ NESTED(except_vec1_generic, 0, sp)
|
||||||
|
NESTED(except_vec3_generic, 0, sp)
|
||||||
|
.set push
|
||||||
|
.set noat
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ nop
|
||||||
|
+ nop
|
||||||
|
+#endif
|
||||||
|
#if R5432_CP0_INTERRUPT_WAR
|
||||||
|
mfc0 k0, CP0_INDEX
|
||||||
|
#endif
|
||||||
|
--- a/arch/mips/mm/c-r4k.c
|
||||||
|
+++ b/arch/mips/mm/c-r4k.c
|
||||||
|
@@ -35,6 +35,9 @@
|
||||||
|
#include <asm/cacheflush.h> /* for run_uncached() */
|
||||||
|
|
||||||
|
|
||||||
|
+/* For enabling BCM4710 cache workarounds */
|
||||||
|
+int bcm4710 = 0;
|
||||||
|
+
|
||||||
|
/*
|
||||||
|
* Special Variant of smp_call_function for use by cache functions:
|
||||||
|
*
|
||||||
|
@@ -111,6 +114,9 @@ static void __cpuinit r4k_blast_dcache_p
|
||||||
|
{
|
||||||
|
unsigned long dc_lsize = cpu_dcache_line_size();
|
||||||
|
|
||||||
|
+ if (bcm4710)
|
||||||
|
+ r4k_blast_dcache_page = blast_dcache_page;
|
||||||
|
+ else
|
||||||
|
if (dc_lsize == 0)
|
||||||
|
r4k_blast_dcache_page = (void *)cache_noop;
|
||||||
|
else if (dc_lsize == 16)
|
||||||
|
@@ -127,6 +133,9 @@ static void __cpuinit r4k_blast_dcache_p
|
||||||
|
{
|
||||||
|
unsigned long dc_lsize = cpu_dcache_line_size();
|
||||||
|
|
||||||
|
+ if (bcm4710)
|
||||||
|
+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
|
||||||
|
+ else
|
||||||
|
if (dc_lsize == 0)
|
||||||
|
r4k_blast_dcache_page_indexed = (void *)cache_noop;
|
||||||
|
else if (dc_lsize == 16)
|
||||||
|
@@ -143,6 +152,9 @@ static void __cpuinit r4k_blast_dcache_s
|
||||||
|
{
|
||||||
|
unsigned long dc_lsize = cpu_dcache_line_size();
|
||||||
|
|
||||||
|
+ if (bcm4710)
|
||||||
|
+ r4k_blast_dcache = blast_dcache;
|
||||||
|
+ else
|
||||||
|
if (dc_lsize == 0)
|
||||||
|
r4k_blast_dcache = (void *)cache_noop;
|
||||||
|
else if (dc_lsize == 16)
|
||||||
|
@@ -680,6 +692,8 @@ static void local_r4k_flush_cache_sigtra
|
||||||
|
unsigned long addr = (unsigned long) arg;
|
||||||
|
|
||||||
|
R4600_HIT_CACHEOP_WAR_IMPL;
|
||||||
|
+ BCM4710_PROTECTED_FILL_TLB(addr);
|
||||||
|
+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
|
||||||
|
if (dc_lsize)
|
||||||
|
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
|
||||||
|
if (!cpu_icache_snoops_remote_store && scache_size)
|
||||||
|
@@ -1298,6 +1312,17 @@ static void __cpuinit coherency_setup(vo
|
||||||
|
* silly idea of putting something else there ...
|
||||||
|
*/
|
||||||
|
switch (current_cpu_type()) {
|
||||||
|
+ case CPU_BCM3302:
|
||||||
|
+ {
|
||||||
|
+ u32 cm;
|
||||||
|
+ cm = read_c0_diag();
|
||||||
|
+ /* Enable icache */
|
||||||
|
+ cm |= (1 << 31);
|
||||||
|
+ /* Enable dcache */
|
||||||
|
+ cm |= (1 << 30);
|
||||||
|
+ write_c0_diag(cm);
|
||||||
|
+ }
|
||||||
|
+ break;
|
||||||
|
case CPU_R4000PC:
|
||||||
|
case CPU_R4000SC:
|
||||||
|
case CPU_R4000MC:
|
||||||
|
@@ -1354,6 +1379,15 @@ void __cpuinit r4k_cache_init(void)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
+ /* Check if special workarounds are required */
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
|
||||||
|
+ printk("Enabling BCM4710A0 cache workarounds.\n");
|
||||||
|
+ bcm4710 = 1;
|
||||||
|
+ } else
|
||||||
|
+#endif
|
||||||
|
+ bcm4710 = 0;
|
||||||
|
+
|
||||||
|
probe_pcache();
|
||||||
|
setup_scache();
|
||||||
|
|
||||||
|
@@ -1412,5 +1446,13 @@ void __cpuinit r4k_cache_init(void)
|
||||||
|
#if !defined(CONFIG_MIPS_CMP)
|
||||||
|
local_r4k___flush_cache_all(NULL);
|
||||||
|
#endif
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ {
|
||||||
|
+ static void (*_coherency_setup)(void);
|
||||||
|
+ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
|
||||||
|
+ _coherency_setup();
|
||||||
|
+ }
|
||||||
|
+#else
|
||||||
|
coherency_setup();
|
||||||
|
+#endif
|
||||||
|
}
|
||||||
|
--- a/arch/mips/mm/tlbex.c
|
||||||
|
+++ b/arch/mips/mm/tlbex.c
|
||||||
|
@@ -749,6 +749,9 @@ static void __cpuinit build_r4000_tlb_re
|
||||||
|
/* No need for uasm_i_nop */
|
||||||
|
}
|
||||||
|
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ uasm_i_nop(&p);
|
||||||
|
+#endif
|
||||||
|
#ifdef CONFIG_64BIT
|
||||||
|
build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
|
||||||
|
#else
|
||||||
|
@@ -1203,6 +1206,9 @@ build_r4000_tlbchange_handler_head(u32 *
|
||||||
|
struct uasm_reloc **r, unsigned int pte,
|
||||||
|
unsigned int ptr)
|
||||||
|
{
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ uasm_i_nop(p);
|
||||||
|
+#endif
|
||||||
|
#ifdef CONFIG_64BIT
|
||||||
|
build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
|
||||||
|
#else
|
||||||
|
|
@ -0,0 +1,77 @@
|
||||||
|
--- a/arch/mips/include/asm/cpu-features.h
|
||||||
|
+++ b/arch/mips/include/asm/cpu-features.h
|
||||||
|
@@ -107,6 +107,9 @@
|
||||||
|
#ifndef cpu_has_pindexed_dcache
|
||||||
|
#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
|
||||||
|
#endif
|
||||||
|
+#ifndef cpu_use_kmap_coherent
|
||||||
|
+#define cpu_use_kmap_coherent 1
|
||||||
|
+#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
|
||||||
|
@@ -0,0 +1,13 @@
|
||||||
|
+/*
|
||||||
|
+ * This file is subject to the terms and conditions of the GNU General Public
|
||||||
|
+ * License. See the file "COPYING" in the main directory of this archive
|
||||||
|
+ * for more details.
|
||||||
|
+ *
|
||||||
|
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
|
||||||
|
+ */
|
||||||
|
+#ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
|
||||||
|
+#define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
|
||||||
|
+
|
||||||
|
+#define cpu_use_kmap_coherent 0
|
||||||
|
+
|
||||||
|
+#endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
|
||||||
|
--- a/arch/mips/mm/c-r4k.c
|
||||||
|
+++ b/arch/mips/mm/c-r4k.c
|
||||||
|
@@ -507,7 +507,7 @@ static inline void local_r4k_flush_cache
|
||||||
|
*/
|
||||||
|
map_coherent = (cpu_has_dc_aliases &&
|
||||||
|
page_mapped(page) && !Page_dcache_dirty(page));
|
||||||
|
- if (map_coherent)
|
||||||
|
+ if (map_coherent && cpu_use_kmap_coherent)
|
||||||
|
vaddr = kmap_coherent(page, addr);
|
||||||
|
else
|
||||||
|
vaddr = kmap_atomic(page, KM_USER0);
|
||||||
|
@@ -530,7 +530,7 @@ static inline void local_r4k_flush_cache
|
||||||
|
}
|
||||||
|
|
||||||
|
if (vaddr) {
|
||||||
|
- if (map_coherent)
|
||||||
|
+ if (map_coherent && cpu_use_kmap_coherent)
|
||||||
|
kunmap_coherent();
|
||||||
|
else
|
||||||
|
kunmap_atomic(vaddr, KM_USER0);
|
||||||
|
--- a/arch/mips/mm/init.c
|
||||||
|
+++ b/arch/mips/mm/init.c
|
||||||
|
@@ -209,7 +209,7 @@ void copy_user_highpage(struct page *to,
|
||||||
|
void *vfrom, *vto;
|
||||||
|
|
||||||
|
vto = kmap_atomic(to, KM_USER1);
|
||||||
|
- if (cpu_has_dc_aliases &&
|
||||||
|
+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
|
||||||
|
page_mapped(from) && !Page_dcache_dirty(from)) {
|
||||||
|
vfrom = kmap_coherent(from, vaddr);
|
||||||
|
copy_page(vto, vfrom);
|
||||||
|
@@ -231,7 +231,7 @@ void copy_to_user_page(struct vm_area_st
|
||||||
|
struct page *page, unsigned long vaddr, void *dst, const void *src,
|
||||||
|
unsigned long len)
|
||||||
|
{
|
||||||
|
- if (cpu_has_dc_aliases &&
|
||||||
|
+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
|
||||||
|
page_mapped(page) && !Page_dcache_dirty(page)) {
|
||||||
|
void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
|
||||||
|
memcpy(vto, src, len);
|
||||||
|
@@ -249,7 +249,7 @@ void copy_from_user_page(struct vm_area_
|
||||||
|
struct page *page, unsigned long vaddr, void *dst, const void *src,
|
||||||
|
unsigned long len)
|
||||||
|
{
|
||||||
|
- if (cpu_has_dc_aliases &&
|
||||||
|
+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
|
||||||
|
page_mapped(page) && !Page_dcache_dirty(page)) {
|
||||||
|
void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
|
||||||
|
memcpy(dst, vfrom, len);
|
||||||
|
|
@ -0,0 +1,36 @@
|
||||||
|
From 83e34f03ee9b86b49bde4707a1fe03a1837e29be Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jochen Friedrich <jochen@scram.de>
|
||||||
|
Date: Wed, 3 Feb 2010 21:28:11 +0100
|
||||||
|
Subject: [PATCH 1/1] ssb: fix interrupt assignment
|
||||||
|
|
||||||
|
Explicitely enable shared interrupt 2 for any core that didn't get a dedicated IRQ
|
||||||
|
anymore (fallthrough case) and for EXTIF cores to make gpio interrupts work.
|
||||||
|
Also remove a bogus comment.
|
||||||
|
|
||||||
|
Signed-off-by: Jochen Friedrich <jochen@scram.de>
|
||||||
|
Signed-off-by: John W. Linville <linville@tuxdriver.com>
|
||||||
|
---
|
||||||
|
drivers/ssb/driver_mipscore.c | 5 ++++-
|
||||||
|
1 files changed, 4 insertions(+), 1 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/ssb/driver_mipscore.c
|
||||||
|
+++ b/drivers/ssb/driver_mipscore.c
|
||||||
|
@@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
|
||||||
|
set_irq(dev, irq++);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
- /* fallthrough */
|
||||||
|
case SSB_DEV_PCI:
|
||||||
|
case SSB_DEV_ETHERNET:
|
||||||
|
case SSB_DEV_ETHERNET_GBIT:
|
||||||
|
@@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
|
||||||
|
set_irq(dev, irq++);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
+ /* fallthrough */
|
||||||
|
+ case SSB_DEV_EXTIF:
|
||||||
|
+ set_irq(dev, 0);
|
||||||
|
+ break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
|
||||||
|
|
@ -0,0 +1,22 @@
|
||||||
|
--- a/drivers/net/b44.c
|
||||||
|
+++ b/drivers/net/b44.c
|
||||||
|
@@ -339,7 +339,7 @@ static int b44_phy_reset(struct b44 *bp)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
- return 0;
|
||||||
|
+ return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
|
||||||
|
@@ -2223,6 +2223,10 @@ static int __devinit b44_init_one(struct
|
||||||
|
*/
|
||||||
|
b44_chip_reset(bp, B44_CHIP_RESET_FULL);
|
||||||
|
|
||||||
|
+ /* do a phy reset to test if there is an active phy */
|
||||||
|
+ if (b44_phy_reset(bp) < 0)
|
||||||
|
+ bp->phy_addr = B44_PHY_ADDR_NO_PHY;
|
||||||
|
+
|
||||||
|
printk(KERN_INFO "%s: Broadcom 44xx/47xx 10/100BaseT Ethernet %pM\n",
|
||||||
|
dev->name, dev->dev_addr);
|
||||||
|
|
||||||
|
|
@ -0,0 +1,42 @@
|
||||||
|
--- a/drivers/ssb/driver_chipcommon.c
|
||||||
|
+++ b/drivers/ssb/driver_chipcommon.c
|
||||||
|
@@ -258,6 +258,8 @@ void ssb_chipco_resume(struct ssb_chipco
|
||||||
|
void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
|
||||||
|
u32 *plltype, u32 *n, u32 *m)
|
||||||
|
{
|
||||||
|
+ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
|
||||||
|
+ return;
|
||||||
|
*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
|
||||||
|
*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
|
||||||
|
switch (*plltype) {
|
||||||
|
@@ -281,6 +283,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
|
||||||
|
void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
|
||||||
|
u32 *plltype, u32 *n, u32 *m)
|
||||||
|
{
|
||||||
|
+ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
|
||||||
|
+ return;
|
||||||
|
*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
|
||||||
|
*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
|
||||||
|
switch (*plltype) {
|
||||||
|
--- a/drivers/ssb/driver_mipscore.c
|
||||||
|
+++ b/drivers/ssb/driver_mipscore.c
|
||||||
|
@@ -217,6 +217,8 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
|
||||||
|
|
||||||
|
if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
|
||||||
|
rate = 200000000;
|
||||||
|
+ } else if (bus->chip_id == 0x5354) {
|
||||||
|
+ rate = 240000000;
|
||||||
|
} else {
|
||||||
|
rate = ssb_calc_clock_rate(pll_type, n, m);
|
||||||
|
}
|
||||||
|
--- a/drivers/ssb/main.c
|
||||||
|
+++ b/drivers/ssb/main.c
|
||||||
|
@@ -1069,6 +1069,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
|
||||||
|
|
||||||
|
if (bus->chip_id == 0x5365) {
|
||||||
|
rate = 100000000;
|
||||||
|
+ } else if (bus->chip_id == 0x5354) {
|
||||||
|
+ rate = 120000000;
|
||||||
|
} else {
|
||||||
|
rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
|
||||||
|
if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
|
||||||
|
|
@ -0,0 +1,60 @@
|
||||||
|
---
|
||||||
|
drivers/usb/host/ohci-ssb.c | 39 ++++++++++++++++++++++++++++++++++++---
|
||||||
|
1 file changed, 36 insertions(+), 3 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/usb/host/ohci-ssb.c
|
||||||
|
+++ b/drivers/usb/host/ohci-ssb.c
|
||||||
|
@@ -106,10 +106,42 @@ static int ssb_ohci_attach(struct ssb_de
|
||||||
|
int err = -ENOMEM;
|
||||||
|
u32 tmp, flags = 0;
|
||||||
|
|
||||||
|
- if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV)
|
||||||
|
+ if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) {
|
||||||
|
+ /* Put the device into host-mode. */
|
||||||
|
flags |= SSB_OHCI_TMSLOW_HOSTMODE;
|
||||||
|
-
|
||||||
|
- ssb_device_enable(dev, flags);
|
||||||
|
+ ssb_device_enable(dev, flags);
|
||||||
|
+ } else if (dev->id.coreid == SSB_DEV_USB20_HOST) {
|
||||||
|
+ /*
|
||||||
|
+ * USB 2.0 special considerations:
|
||||||
|
+ *
|
||||||
|
+ * 1. Since the core supports both OHCI and EHCI functions, it must
|
||||||
|
+ * only be reset once.
|
||||||
|
+ *
|
||||||
|
+ * 2. In addition to the standard SSB reset sequence, the Host Control
|
||||||
|
+ * Register must be programmed to bring the USB core and various
|
||||||
|
+ * phy components out of reset.
|
||||||
|
+ */
|
||||||
|
+ ssb_device_enable(dev, 0);
|
||||||
|
+ ssb_write32(dev, 0x200, 0x7ff);
|
||||||
|
+ udelay(1);
|
||||||
|
+ if (dev->id.revision == 1) { // bug in rev 1
|
||||||
|
+
|
||||||
|
+ /* Change Flush control reg */
|
||||||
|
+ tmp = ssb_read32(dev, 0x400);
|
||||||
|
+ tmp &= ~8;
|
||||||
|
+ ssb_write32(dev, 0x400, tmp);
|
||||||
|
+ tmp = ssb_read32(dev, 0x400);
|
||||||
|
+ printk("USB20H fcr: 0x%0x\n", tmp);
|
||||||
|
+
|
||||||
|
+ /* Change Shim control reg */
|
||||||
|
+ tmp = ssb_read32(dev, 0x304);
|
||||||
|
+ tmp &= ~0x100;
|
||||||
|
+ ssb_write32(dev, 0x304, tmp);
|
||||||
|
+ tmp = ssb_read32(dev, 0x304);
|
||||||
|
+ printk("USB20H shim: 0x%0x\n", tmp);
|
||||||
|
+ }
|
||||||
|
+ } else
|
||||||
|
+ ssb_device_enable(dev, 0);
|
||||||
|
|
||||||
|
hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev,
|
||||||
|
dev_name(dev->dev));
|
||||||
|
@@ -200,6 +232,7 @@ static int ssb_ohci_resume(struct ssb_de
|
||||||
|
static const struct ssb_device_id ssb_ohci_table[] = {
|
||||||
|
SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV),
|
||||||
|
SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV),
|
||||||
|
+ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV),
|
||||||
|
SSB_DEVTABLE_END
|
||||||
|
};
|
||||||
|
MODULE_DEVICE_TABLE(ssb, ssb_ohci_table);
|
||||||
|
|
@ -0,0 +1,16 @@
|
||||||
|
---
|
||||||
|
drivers/usb/host/ohci-ssb.c | 3 +++
|
||||||
|
1 file changed, 3 insertions(+)
|
||||||
|
|
||||||
|
--- a/drivers/usb/host/ohci-ssb.c
|
||||||
|
+++ b/drivers/usb/host/ohci-ssb.c
|
||||||
|
@@ -106,6 +106,9 @@ static int ssb_ohci_attach(struct ssb_de
|
||||||
|
int err = -ENOMEM;
|
||||||
|
u32 tmp, flags = 0;
|
||||||
|
|
||||||
|
+ if (ssb_dma_set_mask(dev, DMA_BIT_MASK(32)))
|
||||||
|
+ return -EOPNOTSUPP;
|
||||||
|
+
|
||||||
|
if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) {
|
||||||
|
/* Put the device into host-mode. */
|
||||||
|
flags |= SSB_OHCI_TMSLOW_HOSTMODE;
|
||||||
|
|
@ -0,0 +1,314 @@
|
||||||
|
---
|
||||||
|
drivers/usb/host/Kconfig | 13 ++
|
||||||
|
drivers/usb/host/ehci-hcd.c | 12 ++
|
||||||
|
drivers/usb/host/ehci-ssb.c | 201 ++++++++++++++++++++++++++++++++++++++++++++
|
||||||
|
drivers/usb/host/ohci-ssb.c | 23 +++++
|
||||||
|
4 files changed, 247 insertions(+), 2 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/usb/host/Kconfig
|
||||||
|
+++ b/drivers/usb/host/Kconfig
|
||||||
|
@@ -150,6 +150,19 @@ config USB_OXU210HP_HCD
|
||||||
|
To compile this driver as a module, choose M here: the
|
||||||
|
module will be called oxu210hp-hcd.
|
||||||
|
|
||||||
|
+config USB_EHCI_HCD_SSB
|
||||||
|
+ bool "EHCI support for Broadcom SSB EHCI core"
|
||||||
|
+ depends on USB_EHCI_HCD && SSB && EXPERIMENTAL
|
||||||
|
+ default n
|
||||||
|
+ ---help---
|
||||||
|
+ Support for the Sonics Silicon Backplane (SSB) attached
|
||||||
|
+ Broadcom USB EHCI core.
|
||||||
|
+
|
||||||
|
+ This device is present in some embedded devices with
|
||||||
|
+ Broadcom based SSB bus.
|
||||||
|
+
|
||||||
|
+ If unsure, say N.
|
||||||
|
+
|
||||||
|
config USB_ISP116X_HCD
|
||||||
|
tristate "ISP116X HCD support"
|
||||||
|
depends on USB
|
||||||
|
--- a/drivers/usb/host/ehci-hcd.c
|
||||||
|
+++ b/drivers/usb/host/ehci-hcd.c
|
||||||
|
@@ -1158,8 +1158,16 @@ MODULE_LICENSE ("GPL");
|
||||||
|
#define PLATFORM_DRIVER ehci_atmel_driver
|
||||||
|
#endif
|
||||||
|
|
||||||
|
-#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
|
||||||
|
- !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER)
|
||||||
|
+#ifdef CONFIG_USB_EHCI_HCD_SSB
|
||||||
|
+#include "ehci-ssb.c"
|
||||||
|
+#define SSB_EHCI_DRIVER ssb_ehci_driver
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
+#if !defined(PCI_DRIVER) && \
|
||||||
|
+ !defined(PLATFORM_DRIVER) && \
|
||||||
|
+ !defined(PS3_SYSTEM_BUS_DRIVER) && \
|
||||||
|
+ !defined(OF_PLATFORM_DRIVER) && \
|
||||||
|
+ !defined(SSB_EHCI_DRIVER)
|
||||||
|
#error "missing bus glue for ehci-hcd"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/drivers/usb/host/ehci-ssb.c
|
||||||
|
@@ -0,0 +1,201 @@
|
||||||
|
+/*
|
||||||
|
+ * Sonics Silicon Backplane
|
||||||
|
+ * Broadcom USB-core EHCI driver (SSB bus glue)
|
||||||
|
+ *
|
||||||
|
+ * Copyright 2007 Steven Brown <sbrown@cortland.com>
|
||||||
|
+ *
|
||||||
|
+ * Derived from the OHCI-SSB driver
|
||||||
|
+ * Copyright 2007 Michael Buesch <mb@bu3sch.de>
|
||||||
|
+ *
|
||||||
|
+ * Derived from the EHCI-PCI driver
|
||||||
|
+ * Copyright (c) 2000-2004 by David Brownell
|
||||||
|
+ *
|
||||||
|
+ * Derived from the OHCI-PCI driver
|
||||||
|
+ * Copyright 1999 Roman Weissgaerber
|
||||||
|
+ * Copyright 2000-2002 David Brownell
|
||||||
|
+ * Copyright 1999 Linus Torvalds
|
||||||
|
+ * Copyright 1999 Gregory P. Smith
|
||||||
|
+ *
|
||||||
|
+ * Derived from the USBcore related parts of Broadcom-SB
|
||||||
|
+ * Copyright 2005 Broadcom Corporation
|
||||||
|
+ *
|
||||||
|
+ * Licensed under the GNU/GPL. See COPYING for details.
|
||||||
|
+ */
|
||||||
|
+#include <linux/ssb/ssb.h>
|
||||||
|
+
|
||||||
|
+#define SSB_OHCI_TMSLOW_HOSTMODE (1 << 29)
|
||||||
|
+
|
||||||
|
+struct ssb_ehci_device {
|
||||||
|
+ struct ehci_hcd ehci; /* _must_ be at the beginning. */
|
||||||
|
+
|
||||||
|
+ u32 enable_flags;
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static inline
|
||||||
|
+struct ssb_ehci_device *hcd_to_ssb_ehci(struct usb_hcd *hcd)
|
||||||
|
+{
|
||||||
|
+ return (struct ssb_ehci_device *)(hcd->hcd_priv);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+static int ssb_ehci_reset(struct usb_hcd *hcd)
|
||||||
|
+{
|
||||||
|
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
|
||||||
|
+ int err;
|
||||||
|
+
|
||||||
|
+ ehci->caps = hcd->regs;
|
||||||
|
+ ehci->regs = hcd->regs +
|
||||||
|
+ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
|
||||||
|
+
|
||||||
|
+ dbg_hcs_params(ehci, "reset");
|
||||||
|
+ dbg_hcc_params(ehci, "reset");
|
||||||
|
+
|
||||||
|
+ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
|
||||||
|
+
|
||||||
|
+ err = ehci_halt(ehci);
|
||||||
|
+
|
||||||
|
+ if (err)
|
||||||
|
+ return err;
|
||||||
|
+
|
||||||
|
+ err = ehci_init(hcd);
|
||||||
|
+
|
||||||
|
+ if (err)
|
||||||
|
+ return err;
|
||||||
|
+
|
||||||
|
+ ehci_port_power(ehci, 0);
|
||||||
|
+
|
||||||
|
+ return err;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int ssb_ehci_start(struct usb_hcd *hcd)
|
||||||
|
+{
|
||||||
|
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
|
||||||
|
+ int err;
|
||||||
|
+
|
||||||
|
+ err = ehci_run(hcd);
|
||||||
|
+ if (err < 0) {
|
||||||
|
+ ehci_err(ehci, "can't start\n");
|
||||||
|
+ ehci_stop(hcd);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ return err;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+#ifdef CONFIG_PM
|
||||||
|
+static int ssb_ehci_hcd_suspend(struct usb_hcd *hcd, pm_message_t message)
|
||||||
|
+{
|
||||||
|
+ struct ssb_ehci_device *ehcidev = hcd_to_ssb_ehci(hcd);
|
||||||
|
+ struct ehci_hcd *ehci = &ehcidev->ehci;
|
||||||
|
+ unsigned long flags;
|
||||||
|
+
|
||||||
|
+ spin_lock_irqsave(&ehci->lock, flags);
|
||||||
|
+
|
||||||
|
+ ehci_writel(ehci, EHCI_INTR_MIE, &ehci->regs->intrdisable);
|
||||||
|
+ ehci_readl(ehci, &ehci->regs->intrdisable); /* commit write */
|
||||||
|
+
|
||||||
|
+ /* make sure snapshot being resumed re-enumerates everything */
|
||||||
|
+ if (message.event == PM_EVENT_PRETHAW)
|
||||||
|
+ ehci_usb_reset(ehci);
|
||||||
|
+
|
||||||
|
+ clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
|
||||||
|
+
|
||||||
|
+ spin_unlock_irqrestore(&ehci->lock, flags);
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int ssb_ehci_hcd_resume(struct usb_hcd *hcd)
|
||||||
|
+{
|
||||||
|
+ set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
|
||||||
|
+ usb_hcd_resume_root_hub(hcd);
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+#endif /* CONFIG_PM */
|
||||||
|
+
|
||||||
|
+static const struct hc_driver ssb_ehci_hc_driver = {
|
||||||
|
+ .description = "ssb-usb-ehci",
|
||||||
|
+ .product_desc = "SSB EHCI Controller",
|
||||||
|
+ .hcd_priv_size = sizeof(struct ssb_ehci_device),
|
||||||
|
+
|
||||||
|
+ .irq = ehci_irq,
|
||||||
|
+ .flags = HCD_MEMORY | HCD_USB2,
|
||||||
|
+
|
||||||
|
+ .reset = ssb_ehci_reset,
|
||||||
|
+ .start = ssb_ehci_start,
|
||||||
|
+ .stop = ehci_stop,
|
||||||
|
+ .shutdown = ehci_shutdown,
|
||||||
|
+
|
||||||
|
+#ifdef CONFIG_PM
|
||||||
|
+ .suspend = ssb_ehci_hcd_suspend,
|
||||||
|
+ .resume = ssb_ehci_hcd_resume,
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
+ .urb_enqueue = ehci_urb_enqueue,
|
||||||
|
+ .urb_dequeue = ehci_urb_dequeue,
|
||||||
|
+ .endpoint_disable = ehci_endpoint_disable,
|
||||||
|
+
|
||||||
|
+ .get_frame_number = ehci_get_frame,
|
||||||
|
+
|
||||||
|
+ .hub_status_data = ehci_hub_status_data,
|
||||||
|
+ .hub_control = ehci_hub_control,
|
||||||
|
+#ifdef CONFIG_PM
|
||||||
|
+ .bus_suspend = ehci_bus_suspend,
|
||||||
|
+ .bus_resume = ehci_bus_resume,
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static void ssb_ehci_detach(struct ssb_device *dev, struct usb_hcd *hcd)
|
||||||
|
+{
|
||||||
|
+
|
||||||
|
+ usb_remove_hcd(hcd);
|
||||||
|
+ iounmap(hcd->regs);
|
||||||
|
+ usb_put_hcd(hcd);
|
||||||
|
+}
|
||||||
|
+EXPORT_SYMBOL_GPL(ssb_ehci_detach);
|
||||||
|
+
|
||||||
|
+static int ssb_ehci_attach(struct ssb_device *dev, struct usb_hcd **ehci_hcd)
|
||||||
|
+{
|
||||||
|
+ struct ssb_ehci_device *ehcidev;
|
||||||
|
+ struct usb_hcd *hcd;
|
||||||
|
+ int err = -ENOMEM;
|
||||||
|
+ u32 tmp, flags = 0;
|
||||||
|
+
|
||||||
|
+ hcd = usb_create_hcd(&ssb_ehci_hc_driver, dev->dev,
|
||||||
|
+ dev_name(dev->dev));
|
||||||
|
+ if (!hcd)
|
||||||
|
+ goto err_dev_disable;
|
||||||
|
+
|
||||||
|
+ ehcidev = hcd_to_ssb_ehci(hcd);
|
||||||
|
+ ehcidev->enable_flags = flags;
|
||||||
|
+ tmp = ssb_read32(dev, SSB_ADMATCH0);
|
||||||
|
+ hcd->rsrc_start = ssb_admatch_base(tmp) + 0x800; /* ehci core offset */
|
||||||
|
+ hcd->rsrc_len = 0x100; /* ehci reg block size */
|
||||||
|
+ /*
|
||||||
|
+ * start & size modified per sbutils.c
|
||||||
|
+ */
|
||||||
|
+ hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len);
|
||||||
|
+ if (!hcd->regs)
|
||||||
|
+ goto err_put_hcd;
|
||||||
|
+ err = usb_add_hcd(hcd, dev->irq, IRQF_SHARED | IRQF_DISABLED);
|
||||||
|
+ if (err)
|
||||||
|
+ goto err_iounmap;
|
||||||
|
+
|
||||||
|
+ *ehci_hcd = hcd;
|
||||||
|
+
|
||||||
|
+ return err;
|
||||||
|
+
|
||||||
|
+err_iounmap:
|
||||||
|
+ iounmap(hcd->regs);
|
||||||
|
+err_put_hcd:
|
||||||
|
+ usb_put_hcd(hcd);
|
||||||
|
+err_dev_disable:
|
||||||
|
+ ssb_device_disable(dev, flags);
|
||||||
|
+ return err;
|
||||||
|
+}
|
||||||
|
+EXPORT_SYMBOL_GPL(ssb_ehci_attach);
|
||||||
|
+
|
||||||
|
+static const struct ssb_device_id ssb_ehci_table[] = {
|
||||||
|
+ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV),
|
||||||
|
+ SSB_DEVTABLE_END
|
||||||
|
+};
|
||||||
|
+MODULE_DEVICE_TABLE(ssb, ssb_ehci_table);
|
||||||
|
--- a/drivers/usb/host/ohci-ssb.c
|
||||||
|
+++ b/drivers/usb/host/ohci-ssb.c
|
||||||
|
@@ -17,6 +17,8 @@
|
||||||
|
*/
|
||||||
|
#include <linux/ssb/ssb.h>
|
||||||
|
|
||||||
|
+extern int ssb_ehci_attach(struct ssb_device *dev, struct usb_hcd **hcd);
|
||||||
|
+extern void ssb_ehci_detach(struct ssb_device *dev, struct usb_hcd *hcd);
|
||||||
|
|
||||||
|
#define SSB_OHCI_TMSLOW_HOSTMODE (1 << 29)
|
||||||
|
|
||||||
|
@@ -24,6 +26,7 @@ struct ssb_ohci_device {
|
||||||
|
struct ohci_hcd ohci; /* _must_ be at the beginning. */
|
||||||
|
|
||||||
|
u32 enable_flags;
|
||||||
|
+ struct usb_hcd *ehci_hcd;
|
||||||
|
};
|
||||||
|
|
||||||
|
static inline
|
||||||
|
@@ -92,13 +95,25 @@ static const struct hc_driver ssb_ohci_h
|
||||||
|
static void ssb_ohci_detach(struct ssb_device *dev)
|
||||||
|
{
|
||||||
|
struct usb_hcd *hcd = ssb_get_drvdata(dev);
|
||||||
|
+#ifdef CONFIG_USB_EHCI_HCD_SSB
|
||||||
|
+ struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd);
|
||||||
|
+#endif
|
||||||
|
|
||||||
|
usb_remove_hcd(hcd);
|
||||||
|
iounmap(hcd->regs);
|
||||||
|
usb_put_hcd(hcd);
|
||||||
|
+
|
||||||
|
+#ifdef CONFIG_USB_EHCI_HCD_SSB
|
||||||
|
+ /*
|
||||||
|
+ * Also detach ehci function
|
||||||
|
+ */
|
||||||
|
+ if (dev->id.coreid == SSB_DEV_USB20_HOST)
|
||||||
|
+ ssb_ehci_detach(dev, ohcidev->ehci_hcd);
|
||||||
|
+#endif
|
||||||
|
ssb_device_disable(dev, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
+
|
||||||
|
static int ssb_ohci_attach(struct ssb_device *dev)
|
||||||
|
{
|
||||||
|
struct ssb_ohci_device *ohcidev;
|
||||||
|
@@ -165,6 +180,14 @@ static int ssb_ohci_attach(struct ssb_de
|
||||||
|
|
||||||
|
ssb_set_drvdata(dev, hcd);
|
||||||
|
|
||||||
|
+#ifdef CONFIG_USB_EHCI_HCD_SSB
|
||||||
|
+ /*
|
||||||
|
+ * attach ehci function in this core
|
||||||
|
+ */
|
||||||
|
+ if (dev->id.coreid == SSB_DEV_USB20_HOST)
|
||||||
|
+ err = ssb_ehci_attach(dev, &(ohcidev->ehci_hcd));
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
return err;
|
||||||
|
|
||||||
|
err_iounmap:
|
||||||
|
|
@ -0,0 +1,63 @@
|
||||||
|
This patch significantly improves the reliability of high speed
|
||||||
|
usb writes on the bcm5354. It implements a work around for version 2
|
||||||
|
of the usb20 core that was cribbed from the GPL sources for the
|
||||||
|
Asus wl500gpv2 and verified against the wl520gu sources.
|
||||||
|
|
||||||
|
Reference:
|
||||||
|
GPL/WL-520gu-NewUI/src/linux/linux/arch/mips/brcm-boards/bcm947xx/pcibios.c
|
||||||
|
GPL/WL-500gPV2-NewUI/src/linux/linux/arch/mips/brcm-boards/bcm947xx/pcibios.c
|
||||||
|
|
||||||
|
Signed-off-by: Steve Brown <sbrown@cortland.com>
|
||||||
|
|
||||||
|
---
|
||||||
|
drivers/usb/host/ohci-ssb.c | 37 +++++++++++++++++++++++--------------
|
||||||
|
1 file changed, 23 insertions(+), 14 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/usb/host/ohci-ssb.c
|
||||||
|
+++ b/drivers/usb/host/ohci-ssb.c
|
||||||
|
@@ -141,22 +141,31 @@ static int ssb_ohci_attach(struct ssb_de
|
||||||
|
*/
|
||||||
|
ssb_device_enable(dev, 0);
|
||||||
|
ssb_write32(dev, 0x200, 0x7ff);
|
||||||
|
+
|
||||||
|
+ /* Change Flush control reg */
|
||||||
|
+ tmp = ssb_read32(dev, 0x400);
|
||||||
|
+ tmp &= ~8;
|
||||||
|
+ ssb_write32(dev, 0x400, tmp);
|
||||||
|
+ tmp = ssb_read32(dev, 0x400);
|
||||||
|
+
|
||||||
|
+ /* Change Shim control reg */
|
||||||
|
+ tmp = ssb_read32(dev, 0x304);
|
||||||
|
+ tmp &= ~0x100;
|
||||||
|
+ ssb_write32(dev, 0x304, tmp);
|
||||||
|
+ tmp = ssb_read32(dev, 0x304);
|
||||||
|
+
|
||||||
|
udelay(1);
|
||||||
|
- if (dev->id.revision == 1) { // bug in rev 1
|
||||||
|
|
||||||
|
- /* Change Flush control reg */
|
||||||
|
- tmp = ssb_read32(dev, 0x400);
|
||||||
|
- tmp &= ~8;
|
||||||
|
- ssb_write32(dev, 0x400, tmp);
|
||||||
|
- tmp = ssb_read32(dev, 0x400);
|
||||||
|
- printk("USB20H fcr: 0x%0x\n", tmp);
|
||||||
|
-
|
||||||
|
- /* Change Shim control reg */
|
||||||
|
- tmp = ssb_read32(dev, 0x304);
|
||||||
|
- tmp &= ~0x100;
|
||||||
|
- ssb_write32(dev, 0x304, tmp);
|
||||||
|
- tmp = ssb_read32(dev, 0x304);
|
||||||
|
- printk("USB20H shim: 0x%0x\n", tmp);
|
||||||
|
+ /* Work around for 5354 failures */
|
||||||
|
+ if ((dev->id.revision == 2) && (dev->bus->chip_id == 0x5354)) {
|
||||||
|
+ /* Change syn01 reg */
|
||||||
|
+ tmp = 0x00fe00fe;
|
||||||
|
+ ssb_write32(dev, 0x894, tmp);
|
||||||
|
+
|
||||||
|
+ /* Change syn03 reg */
|
||||||
|
+ tmp = ssb_read32(dev, 0x89c);
|
||||||
|
+ tmp |= 0x1;
|
||||||
|
+ ssb_write32(dev, 0x89c, tmp);
|
||||||
|
}
|
||||||
|
} else
|
||||||
|
ssb_device_enable(dev, 0);
|
||||||
|
|
@ -0,0 +1,16 @@
|
||||||
|
This prevents the options from being delete with make kernel_oldconfig.
|
||||||
|
---
|
||||||
|
drivers/ssb/Kconfig | 2 ++
|
||||||
|
1 file changed, 2 insertions(+)
|
||||||
|
|
||||||
|
--- a/drivers/ssb/Kconfig
|
||||||
|
+++ b/drivers/ssb/Kconfig
|
||||||
|
@@ -140,6 +140,8 @@ config SSB_DRIVER_MIPS
|
||||||
|
config SSB_EMBEDDED
|
||||||
|
bool
|
||||||
|
depends on SSB_DRIVER_MIPS
|
||||||
|
+ select USB_EHCI_HCD_SSB if USB_EHCI_HCD
|
||||||
|
+ select USB_OHCI_HCD_SSB if USB_OHCI_HCD
|
||||||
|
default y
|
||||||
|
|
||||||
|
config SSB_DRIVER_EXTIF
|
||||||
|
|
@ -0,0 +1,11 @@
|
||||||
|
--- a/arch/mips/include/asm/cacheflush.h
|
||||||
|
+++ b/arch/mips/include/asm/cacheflush.h
|
||||||
|
@@ -32,7 +32,7 @@
|
||||||
|
extern void (*flush_cache_all)(void);
|
||||||
|
extern void (*__flush_cache_all)(void);
|
||||||
|
extern void (*flush_cache_mm)(struct mm_struct *mm);
|
||||||
|
-#define flush_cache_dup_mm(mm) do { (void) (mm); } while (0)
|
||||||
|
+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
|
||||||
|
extern void (*flush_cache_range)(struct vm_area_struct *vma,
|
||||||
|
unsigned long start, unsigned long end);
|
||||||
|
extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
--- a/arch/mips/mm/c-r4k.c
|
||||||
|
+++ b/arch/mips/mm/c-r4k.c
|
||||||
|
@@ -373,7 +373,7 @@ static inline void local_r4k___flush_cac
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
-static void r4k___flush_cache_all(void)
|
||||||
|
+void r4k___flush_cache_all(void)
|
||||||
|
{
|
||||||
|
r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1);
|
||||||
|
}
|
||||||
|
@@ -537,7 +537,7 @@ static inline void local_r4k_flush_cache
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
-static void r4k_flush_cache_page(struct vm_area_struct *vma,
|
||||||
|
+void r4k_flush_cache_page(struct vm_area_struct *vma,
|
||||||
|
unsigned long addr, unsigned long pfn)
|
||||||
|
{
|
||||||
|
struct flush_cache_page_args args;
|
||||||
|
@@ -1456,3 +1456,10 @@ void __cpuinit r4k_cache_init(void)
|
||||||
|
coherency_setup();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
+
|
||||||
|
+// fuse package DCACHE BUG patch exports
|
||||||
|
+void (*fuse_flush_cache_all)(void) = r4k___flush_cache_all;
|
||||||
|
+void (*fuse_flush_cache_page)(struct vm_area_struct *vma, unsigned long page,
|
||||||
|
+ unsigned long pfn) = r4k_flush_cache_page;
|
||||||
|
+EXPORT_SYMBOL(fuse_flush_cache_page);
|
||||||
|
+EXPORT_SYMBOL(fuse_flush_cache_all);
|
||||||
|
|
@ -0,0 +1,82 @@
|
||||||
|
--- a/fs/fuse/dev.c
|
||||||
|
+++ b/fs/fuse/dev.c
|
||||||
|
@@ -533,6 +533,11 @@ static void fuse_copy_finish(struct fuse
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
+#ifdef DCACHE_BUG
|
||||||
|
+extern void (*fuse_flush_cache_all)(void);
|
||||||
|
+extern void (*fuse_flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
/*
|
||||||
|
* Get another pagefull of userspace buffer, and map it to kernel
|
||||||
|
* address space, and lock request
|
||||||
|
@@ -541,6 +546,9 @@ static int fuse_copy_fill(struct fuse_co
|
||||||
|
{
|
||||||
|
unsigned long offset;
|
||||||
|
int err;
|
||||||
|
+#ifdef DCACHE_BUG
|
||||||
|
+ struct vm_area_struct *vma;
|
||||||
|
+#endif
|
||||||
|
|
||||||
|
unlock_request(cs->fc, cs->req);
|
||||||
|
fuse_copy_finish(cs);
|
||||||
|
@@ -552,14 +560,22 @@ static int fuse_copy_fill(struct fuse_co
|
||||||
|
cs->nr_segs--;
|
||||||
|
}
|
||||||
|
down_read(¤t->mm->mmap_sem);
|
||||||
|
+#ifndef DCACHE_BUG
|
||||||
|
err = get_user_pages(current, current->mm, cs->addr, 1, cs->write, 0,
|
||||||
|
&cs->pg, NULL);
|
||||||
|
+#else
|
||||||
|
+ err = get_user_pages(current, current->mm, cs->addr, 1, cs->write, 0,
|
||||||
|
+ &cs->pg, &vma);
|
||||||
|
+#endif
|
||||||
|
up_read(¤t->mm->mmap_sem);
|
||||||
|
if (err < 0)
|
||||||
|
return err;
|
||||||
|
BUG_ON(err != 1);
|
||||||
|
offset = cs->addr % PAGE_SIZE;
|
||||||
|
cs->mapaddr = kmap_atomic(cs->pg, KM_USER0);
|
||||||
|
+#ifdef DCACHE_BUG
|
||||||
|
+ fuse_flush_cache_page(vma, cs->addr, page_to_pfn(cs->pg));
|
||||||
|
+#endif
|
||||||
|
cs->buf = cs->mapaddr + offset;
|
||||||
|
cs->len = min(PAGE_SIZE - offset, cs->seglen);
|
||||||
|
cs->seglen -= cs->len;
|
||||||
|
@@ -573,6 +589,11 @@ static int fuse_copy_do(struct fuse_copy
|
||||||
|
{
|
||||||
|
unsigned ncpy = min(*size, cs->len);
|
||||||
|
if (val) {
|
||||||
|
+#ifdef DCACHE_BUG
|
||||||
|
+ // patch from mailing list, it is very important, otherwise,
|
||||||
|
+ // can't mount, or ls mount point will hang
|
||||||
|
+ fuse_flush_cache_all();
|
||||||
|
+#endif
|
||||||
|
if (cs->write)
|
||||||
|
memcpy(cs->buf, *val, ncpy);
|
||||||
|
else
|
||||||
|
--- a/fs/fuse/fuse_i.h
|
||||||
|
+++ b/fs/fuse/fuse_i.h
|
||||||
|
@@ -8,6 +8,7 @@
|
||||||
|
|
||||||
|
#ifndef _FS_FUSE_I_H
|
||||||
|
#define _FS_FUSE_I_H
|
||||||
|
+#define DCACHE_BUG
|
||||||
|
|
||||||
|
#include <linux/fuse.h>
|
||||||
|
#include <linux/fs.h>
|
||||||
|
--- a/fs/fuse/inode.c
|
||||||
|
+++ b/fs/fuse/inode.c
|
||||||
|
@@ -1201,6 +1201,10 @@ static int __init fuse_init(void)
|
||||||
|
printk(KERN_INFO "fuse init (API version %i.%i)\n",
|
||||||
|
FUSE_KERNEL_VERSION, FUSE_KERNEL_MINOR_VERSION);
|
||||||
|
|
||||||
|
+#ifdef DCACHE_BUG
|
||||||
|
+printk("fuse init: DCACHE_BUG enabled\n");
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
INIT_LIST_HEAD(&fuse_conn_list);
|
||||||
|
res = fuse_fs_init();
|
||||||
|
if (res)
|
||||||
|
|
@ -0,0 +1,66 @@
|
||||||
|
--- a/arch/mips/include/asm/page.h
|
||||||
|
+++ b/arch/mips/include/asm/page.h
|
||||||
|
@@ -43,6 +43,7 @@
|
||||||
|
#ifndef __ASSEMBLY__
|
||||||
|
|
||||||
|
#include <linux/pfn.h>
|
||||||
|
+#include <asm/cpu-features.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
|
||||||
|
extern void build_clear_page(void);
|
||||||
|
@@ -78,13 +79,16 @@ static inline void clear_user_page(void
|
||||||
|
flush_data_cache_page((unsigned long)addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
-extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
|
||||||
|
- struct page *to);
|
||||||
|
-struct vm_area_struct;
|
||||||
|
-extern void copy_user_highpage(struct page *to, struct page *from,
|
||||||
|
- unsigned long vaddr, struct vm_area_struct *vma);
|
||||||
|
+static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
|
||||||
|
+ struct page *to)
|
||||||
|
+{
|
||||||
|
+ extern void (*flush_data_cache_page)(unsigned long addr);
|
||||||
|
|
||||||
|
-#define __HAVE_ARCH_COPY_USER_HIGHPAGE
|
||||||
|
+ copy_page(vto, vfrom);
|
||||||
|
+ if (!cpu_has_ic_fills_f_dc ||
|
||||||
|
+ pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
|
||||||
|
+ flush_data_cache_page((unsigned long)vto);
|
||||||
|
+}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* These are used to make use of C type-checking..
|
||||||
|
--- a/arch/mips/mm/init.c
|
||||||
|
+++ b/arch/mips/mm/init.c
|
||||||
|
@@ -203,30 +203,6 @@ void kunmap_coherent(void)
|
||||||
|
preempt_check_resched();
|
||||||
|
}
|
||||||
|
|
||||||
|
-void copy_user_highpage(struct page *to, struct page *from,
|
||||||
|
- unsigned long vaddr, struct vm_area_struct *vma)
|
||||||
|
-{
|
||||||
|
- void *vfrom, *vto;
|
||||||
|
-
|
||||||
|
- vto = kmap_atomic(to, KM_USER1);
|
||||||
|
- if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
|
||||||
|
- page_mapped(from) && !Page_dcache_dirty(from)) {
|
||||||
|
- vfrom = kmap_coherent(from, vaddr);
|
||||||
|
- copy_page(vto, vfrom);
|
||||||
|
- kunmap_coherent();
|
||||||
|
- } else {
|
||||||
|
- vfrom = kmap_atomic(from, KM_USER0);
|
||||||
|
- copy_page(vto, vfrom);
|
||||||
|
- kunmap_atomic(vfrom, KM_USER0);
|
||||||
|
- }
|
||||||
|
- if ((!cpu_has_ic_fills_f_dc) ||
|
||||||
|
- pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
|
||||||
|
- flush_data_cache_page((unsigned long)vto);
|
||||||
|
- kunmap_atomic(vto, KM_USER1);
|
||||||
|
- /* Make sure this page is cleared on other CPU's too before using it */
|
||||||
|
- smp_wmb();
|
||||||
|
-}
|
||||||
|
-
|
||||||
|
void copy_to_user_page(struct vm_area_struct *vma,
|
||||||
|
struct page *page, unsigned long vaddr, void *dst, const void *src,
|
||||||
|
unsigned long len)
|
||||||
|
|
@ -0,0 +1,319 @@
|
||||||
|
--- a/arch/mips/Kconfig
|
||||||
|
+++ b/arch/mips/Kconfig
|
||||||
|
@@ -62,6 +62,7 @@ config BCM47XX
|
||||||
|
select SSB_DRIVER_MIPS
|
||||||
|
select SSB_DRIVER_EXTIF
|
||||||
|
select SSB_EMBEDDED
|
||||||
|
+ select SSB_B43_PCI_BRIDGE if PCI
|
||||||
|
select SSB_PCICORE_HOSTMODE if PCI
|
||||||
|
select GENERIC_GPIO
|
||||||
|
select SYS_HAS_EARLY_PRINTK
|
||||||
|
--- a/arch/mips/bcm47xx/Makefile
|
||||||
|
+++ b/arch/mips/bcm47xx/Makefile
|
||||||
|
@@ -3,4 +3,4 @@
|
||||||
|
# under Linux.
|
||||||
|
#
|
||||||
|
|
||||||
|
-obj-y := gpio.o irq.o prom.o serial.o setup.o time.o wgt634u.o
|
||||||
|
+obj-y := cfe_env.o gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o
|
||||||
|
--- a/arch/mips/bcm47xx/irq.c
|
||||||
|
+++ b/arch/mips/bcm47xx/irq.c
|
||||||
|
@@ -1,5 +1,6 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
|
||||||
|
+ * Copyright (C) 2008 Michael Buesch <mb@bu3sch.de>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License as published by the
|
||||||
|
@@ -23,10 +24,19 @@
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/types.h>
|
||||||
|
+#include <linux/errno.h>
|
||||||
|
+#include <linux/init.h>
|
||||||
|
#include <linux/interrupt.h>
|
||||||
|
#include <linux/irq.h>
|
||||||
|
+#include <linux/pci.h>
|
||||||
|
+#include <linux/ssb/ssb.h>
|
||||||
|
+
|
||||||
|
#include <asm/irq_cpu.h>
|
||||||
|
|
||||||
|
+
|
||||||
|
+extern struct ssb_bus ssb_bcm47xx;
|
||||||
|
+
|
||||||
|
+
|
||||||
|
void plat_irq_dispatch(void)
|
||||||
|
{
|
||||||
|
u32 cause;
|
||||||
|
--- a/arch/mips/bcm47xx/nvram.c
|
||||||
|
+++ b/arch/mips/bcm47xx/nvram.c
|
||||||
|
@@ -24,10 +24,10 @@
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <asm/uaccess.h>
|
||||||
|
|
||||||
|
-#include <nvram.h>
|
||||||
|
+#include "include/nvram.h"
|
||||||
|
|
||||||
|
#define MB * 1048576
|
||||||
|
-extern struct ssb_bus ssb;
|
||||||
|
+extern struct ssb_bus ssb_bcm47xx;
|
||||||
|
|
||||||
|
static char nvram_buf[NVRAM_SPACE];
|
||||||
|
static int cfe_env;
|
||||||
|
@@ -36,7 +36,7 @@ extern char *cfe_env_get(char *nv_buf, c
|
||||||
|
/* Probe for NVRAM header */
|
||||||
|
static void __init early_nvram_init(void)
|
||||||
|
{
|
||||||
|
- struct ssb_mipscore *mcore = &ssb.mipscore;
|
||||||
|
+ struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore;
|
||||||
|
struct nvram_header *header;
|
||||||
|
int i;
|
||||||
|
u32 base, lim, off;
|
||||||
|
--- a/arch/mips/bcm47xx/setup.c
|
||||||
|
+++ b/arch/mips/bcm47xx/setup.c
|
||||||
|
@@ -2,7 +2,7 @@
|
||||||
|
* Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
|
||||||
|
* Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
|
||||||
|
* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
|
||||||
|
- * Copyright (C) 2006 Michael Buesch <mb@bu3sch.de>
|
||||||
|
+ * Copyright (C) 2006-2008 Michael Buesch <mb@bu3sch.de>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License as published by the
|
||||||
|
@@ -25,18 +25,28 @@
|
||||||
|
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||||
|
*/
|
||||||
|
|
||||||
|
+#include <linux/init.h>
|
||||||
|
#include <linux/types.h>
|
||||||
|
#include <linux/ssb/ssb.h>
|
||||||
|
#include <linux/ssb/ssb_embedded.h>
|
||||||
|
+#include <linux/tty.h>
|
||||||
|
+#include <linux/serial.h>
|
||||||
|
+#include <linux/serial_core.h>
|
||||||
|
+#include <linux/serial_reg.h>
|
||||||
|
+#include <linux/serial_8250.h>
|
||||||
|
#include <asm/bootinfo.h>
|
||||||
|
#include <asm/reboot.h>
|
||||||
|
#include <asm/time.h>
|
||||||
|
-#include <bcm47xx.h>
|
||||||
|
#include <asm/fw/cfe/cfe_api.h>
|
||||||
|
+#include <linux/pm.h>
|
||||||
|
+
|
||||||
|
+#include "include/nvram.h"
|
||||||
|
|
||||||
|
struct ssb_bus ssb_bcm47xx;
|
||||||
|
EXPORT_SYMBOL(ssb_bcm47xx);
|
||||||
|
|
||||||
|
+extern void bcm47xx_pci_init(void);
|
||||||
|
+
|
||||||
|
static void bcm47xx_machine_restart(char *command)
|
||||||
|
{
|
||||||
|
printk(KERN_ALERT "Please stand by while rebooting the system...\n");
|
||||||
|
@@ -56,7 +66,7 @@ static void bcm47xx_machine_halt(void)
|
||||||
|
cpu_relax();
|
||||||
|
}
|
||||||
|
|
||||||
|
-static void str2eaddr(char *str, char *dest)
|
||||||
|
+static void e_aton(char *str, char *dest)
|
||||||
|
{
|
||||||
|
int i = 0;
|
||||||
|
|
||||||
|
@@ -73,52 +83,142 @@ static void str2eaddr(char *str, char *d
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
-static int bcm47xx_get_invariants(struct ssb_bus *bus,
|
||||||
|
- struct ssb_init_invariants *iv)
|
||||||
|
+static void bcm47xx_fill_sprom(struct ssb_sprom *sprom)
|
||||||
|
{
|
||||||
|
- char buf[100];
|
||||||
|
+ char *s;
|
||||||
|
|
||||||
|
- /* Fill boardinfo structure */
|
||||||
|
- memset(&(iv->boardinfo), 0 , sizeof(struct ssb_boardinfo));
|
||||||
|
+ memset(sprom, 0xFF, sizeof(struct ssb_sprom));
|
||||||
|
|
||||||
|
- if (cfe_getenv("boardvendor", buf, sizeof(buf)) >= 0)
|
||||||
|
- iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
|
||||||
|
- if (cfe_getenv("boardtype", buf, sizeof(buf)) >= 0)
|
||||||
|
- iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
|
||||||
|
- if (cfe_getenv("boardrev", buf, sizeof(buf)) >= 0)
|
||||||
|
- iv->boardinfo.rev = (u16)simple_strtoul(buf, NULL, 0);
|
||||||
|
-
|
||||||
|
- /* Fill sprom structure */
|
||||||
|
- memset(&(iv->sprom), 0, sizeof(struct ssb_sprom));
|
||||||
|
- iv->sprom.revision = 3;
|
||||||
|
-
|
||||||
|
- if (cfe_getenv("et0macaddr", buf, sizeof(buf)) >= 0)
|
||||||
|
- str2eaddr(buf, iv->sprom.et0mac);
|
||||||
|
- if (cfe_getenv("et1macaddr", buf, sizeof(buf)) >= 0)
|
||||||
|
- str2eaddr(buf, iv->sprom.et1mac);
|
||||||
|
- if (cfe_getenv("et0phyaddr", buf, sizeof(buf)) >= 0)
|
||||||
|
- iv->sprom.et0phyaddr = simple_strtoul(buf, NULL, 10);
|
||||||
|
- if (cfe_getenv("et1phyaddr", buf, sizeof(buf)) >= 0)
|
||||||
|
- iv->sprom.et1phyaddr = simple_strtoul(buf, NULL, 10);
|
||||||
|
- if (cfe_getenv("et0mdcport", buf, sizeof(buf)) >= 0)
|
||||||
|
- iv->sprom.et0mdcport = simple_strtoul(buf, NULL, 10);
|
||||||
|
- if (cfe_getenv("et1mdcport", buf, sizeof(buf)) >= 0)
|
||||||
|
- iv->sprom.et1mdcport = simple_strtoul(buf, NULL, 10);
|
||||||
|
+ sprom->revision = 1;
|
||||||
|
+ if ((s = nvram_get("il0macaddr")))
|
||||||
|
+ e_aton(s, sprom->il0mac);
|
||||||
|
+ if ((s = nvram_get("et0macaddr")))
|
||||||
|
+ e_aton(s, sprom->et0mac);
|
||||||
|
+ if ((s = nvram_get("et1macaddr")))
|
||||||
|
+ e_aton(s, sprom->et1mac);
|
||||||
|
+ if ((s = nvram_get("et0phyaddr")))
|
||||||
|
+ sprom->et0phyaddr = simple_strtoul(s, NULL, 0);
|
||||||
|
+ if ((s = nvram_get("et1phyaddr")))
|
||||||
|
+ sprom->et1phyaddr = simple_strtoul(s, NULL, 0);
|
||||||
|
+ if ((s = nvram_get("et0mdcport")))
|
||||||
|
+ sprom->et0mdcport = !!simple_strtoul(s, NULL, 10);
|
||||||
|
+ if ((s = nvram_get("et1mdcport")))
|
||||||
|
+ sprom->et1mdcport = !!simple_strtoul(s, NULL, 10);
|
||||||
|
+ if ((s = nvram_get("pa0b0")))
|
||||||
|
+ sprom->pa0b0 = simple_strtoul(s, NULL, 0);
|
||||||
|
+ if ((s = nvram_get("pa0b1")))
|
||||||
|
+ sprom->pa0b1 = simple_strtoul(s, NULL, 0);
|
||||||
|
+ if ((s = nvram_get("pa0b2")))
|
||||||
|
+ sprom->pa0b2 = simple_strtoul(s, NULL, 0);
|
||||||
|
+ if ((s = nvram_get("pa1b0")))
|
||||||
|
+ sprom->pa1b0 = simple_strtoul(s, NULL, 0);
|
||||||
|
+ if ((s = nvram_get("pa1b1")))
|
||||||
|
+ sprom->pa1b1 = simple_strtoul(s, NULL, 0);
|
||||||
|
+ if ((s = nvram_get("pa1b2")))
|
||||||
|
+ sprom->pa1b2 = simple_strtoul(s, NULL, 0);
|
||||||
|
+ if ((s = nvram_get("wl0gpio0")))
|
||||||
|
+ sprom->gpio0 = simple_strtoul(s, NULL, 0);
|
||||||
|
+ if ((s = nvram_get("wl0gpio1")))
|
||||||
|
+ sprom->gpio1 = simple_strtoul(s, NULL, 0);
|
||||||
|
+ if ((s = nvram_get("wl0gpio2")))
|
||||||
|
+ sprom->gpio2 = simple_strtoul(s, NULL, 0);
|
||||||
|
+ if ((s = nvram_get("wl0gpio3")))
|
||||||
|
+ sprom->gpio3 = simple_strtoul(s, NULL, 0);
|
||||||
|
+ if ((s = nvram_get("pa0maxpwr")))
|
||||||
|
+ sprom->maxpwr_bg = simple_strtoul(s, NULL, 0);
|
||||||
|
+ if ((s = nvram_get("pa1maxpwr")))
|
||||||
|
+ sprom->maxpwr_a = simple_strtoul(s, NULL, 0);
|
||||||
|
+ if ((s = nvram_get("pa0itssit")))
|
||||||
|
+ sprom->itssi_bg = simple_strtoul(s, NULL, 0);
|
||||||
|
+ if ((s = nvram_get("pa1itssit")))
|
||||||
|
+ sprom->itssi_a = simple_strtoul(s, NULL, 0);
|
||||||
|
+ sprom->boardflags_lo = 0;
|
||||||
|
+ if ((s = nvram_get("boardflags")))
|
||||||
|
+ sprom->boardflags_lo = simple_strtoul(s, NULL, 0);
|
||||||
|
+ sprom->boardflags_hi = 0;
|
||||||
|
+ if ((s = nvram_get("boardflags2")))
|
||||||
|
+ sprom->boardflags_hi = simple_strtoul(s, NULL, 0);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int bcm47xx_get_invariants(struct ssb_bus *bus, struct ssb_init_invariants *iv)
|
||||||
|
+{
|
||||||
|
+ char *s;
|
||||||
|
+
|
||||||
|
+ iv->boardinfo.vendor = SSB_BOARDVENDOR_BCM;
|
||||||
|
+ if ((s = nvram_get("boardtype")))
|
||||||
|
+ iv->boardinfo.type = (u16)simple_strtoul(s, NULL, 0);
|
||||||
|
+ if ((s = nvram_get("boardrev")))
|
||||||
|
+ iv->boardinfo.rev = (u16)simple_strtoul(s, NULL, 0);
|
||||||
|
+
|
||||||
|
+ bcm47xx_fill_sprom(&iv->sprom);
|
||||||
|
+
|
||||||
|
+ if ((s = nvram_get("cardbus")))
|
||||||
|
+ iv->has_cardbus_slot = !!simple_strtoul(s, NULL, 10);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void __init plat_mem_setup(void)
|
||||||
|
{
|
||||||
|
- int err;
|
||||||
|
+ int i, err;
|
||||||
|
+ char *s;
|
||||||
|
+ struct ssb_mipscore *mcore;
|
||||||
|
+
|
||||||
|
+ err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE, bcm47xx_get_invariants);
|
||||||
|
+ if (err) {
|
||||||
|
+ const char *msg = "Failed to initialize SSB bus (err %d)\n";
|
||||||
|
+ printk(msg, err); /* Make sure the message gets out of the box. */
|
||||||
|
+ panic(msg, err);
|
||||||
|
+ }
|
||||||
|
+ mcore = &ssb_bcm47xx.mipscore;
|
||||||
|
|
||||||
|
- err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE,
|
||||||
|
- bcm47xx_get_invariants);
|
||||||
|
- if (err)
|
||||||
|
- panic("Failed to initialize SSB bus (err %d)\n", err);
|
||||||
|
+ s = nvram_get("kernel_args");
|
||||||
|
+ if (s && !strncmp(s, "console=ttyS1", 13)) {
|
||||||
|
+ struct ssb_serial_port port;
|
||||||
|
+
|
||||||
|
+ printk("Swapping serial ports!\n");
|
||||||
|
+ /* swap serial ports */
|
||||||
|
+ memcpy(&port, &mcore->serial_ports[0], sizeof(port));
|
||||||
|
+ memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1], sizeof(port));
|
||||||
|
+ memcpy(&mcore->serial_ports[1], &port, sizeof(port));
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ for (i = 0; i < mcore->nr_serial_ports; i++) {
|
||||||
|
+ struct ssb_serial_port *port = &(mcore->serial_ports[i]);
|
||||||
|
+ struct uart_port s;
|
||||||
|
+
|
||||||
|
+ memset(&s, 0, sizeof(s));
|
||||||
|
+ s.line = i;
|
||||||
|
+ s.mapbase = (unsigned int) port->regs;
|
||||||
|
+ s.membase = port->regs;
|
||||||
|
+ s.irq = port->irq + 2;
|
||||||
|
+ s.uartclk = port->baud_base;
|
||||||
|
+ s.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
|
||||||
|
+ s.iotype = SERIAL_IO_MEM;
|
||||||
|
+ s.regshift = port->reg_shift;
|
||||||
|
+
|
||||||
|
+ early_serial_setup(&s);
|
||||||
|
+ }
|
||||||
|
+ printk("Serial init done.\n");
|
||||||
|
|
||||||
|
_machine_restart = bcm47xx_machine_restart;
|
||||||
|
_machine_halt = bcm47xx_machine_halt;
|
||||||
|
pm_power_off = bcm47xx_machine_halt;
|
||||||
|
}
|
||||||
|
|
||||||
|
+static int __init bcm47xx_register_gpiodev(void)
|
||||||
|
+{
|
||||||
|
+ static struct resource res = {
|
||||||
|
+ .start = 0xFFFFFFFF,
|
||||||
|
+ };
|
||||||
|
+ struct platform_device *pdev;
|
||||||
|
+
|
||||||
|
+ pdev = platform_device_register_simple("GPIODEV", 0, &res, 1);
|
||||||
|
+ if (!pdev) {
|
||||||
|
+ printk(KERN_ERR "bcm47xx: GPIODEV init failed\n");
|
||||||
|
+ return -ENODEV;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+device_initcall(bcm47xx_register_gpiodev);
|
||||||
|
--- a/arch/mips/bcm47xx/time.c
|
||||||
|
+++ b/arch/mips/bcm47xx/time.c
|
||||||
|
@@ -22,11 +22,17 @@
|
||||||
|
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||||
|
*/
|
||||||
|
|
||||||
|
-
|
||||||
|
#include <linux/init.h>
|
||||||
|
+#include <linux/kernel.h>
|
||||||
|
+#include <linux/sched.h>
|
||||||
|
+#include <linux/serial_reg.h>
|
||||||
|
+#include <linux/interrupt.h>
|
||||||
|
#include <linux/ssb/ssb.h>
|
||||||
|
+#include <asm/addrspace.h>
|
||||||
|
+#include <asm/io.h>
|
||||||
|
#include <asm/time.h>
|
||||||
|
-#include <bcm47xx.h>
|
||||||
|
+
|
||||||
|
+extern struct ssb_bus ssb_bcm47xx;
|
||||||
|
|
||||||
|
void __init plat_time_init(void)
|
||||||
|
{
|
||||||
|
|
@ -0,0 +1,18 @@
|
||||||
|
--- a/arch/mips/pci/pci.c
|
||||||
|
+++ b/arch/mips/pci/pci.c
|
||||||
|
@@ -185,12 +185,10 @@ static int pcibios_enable_resources(stru
|
||||||
|
if ((idx == PCI_ROM_RESOURCE) &&
|
||||||
|
(!(r->flags & IORESOURCE_ROM_ENABLE)))
|
||||||
|
continue;
|
||||||
|
- if (!r->start && r->end) {
|
||||||
|
- printk(KERN_ERR "PCI: Device %s not available "
|
||||||
|
- "because of resource collisions\n",
|
||||||
|
+ if (!r->start && r->end)
|
||||||
|
+ printk(KERN_WARNING "PCI: Device %s resource"
|
||||||
|
+ "collisions detected. Ignoring...\n",
|
||||||
|
pci_name(dev));
|
||||||
|
- return -EINVAL;
|
||||||
|
- }
|
||||||
|
if (r->flags & IORESOURCE_IO)
|
||||||
|
cmd |= PCI_COMMAND_IO;
|
||||||
|
if (r->flags & IORESOURCE_MEM)
|
||||||
|
|
@ -0,0 +1,329 @@
|
||||||
|
--- a/drivers/net/tg3.c
|
||||||
|
+++ b/drivers/net/tg3.c
|
||||||
|
@@ -41,6 +41,7 @@
|
||||||
|
#include <linux/prefetch.h>
|
||||||
|
#include <linux/dma-mapping.h>
|
||||||
|
#include <linux/firmware.h>
|
||||||
|
+#include <linux/ssb/ssb_driver_gige.h>
|
||||||
|
|
||||||
|
#include <net/checksum.h>
|
||||||
|
#include <net/ip.h>
|
||||||
|
@@ -466,8 +467,9 @@ static void _tw32_flush(struct tg3 *tp,
|
||||||
|
static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
|
||||||
|
{
|
||||||
|
tp->write32_mbox(tp, off, val);
|
||||||
|
- if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
|
||||||
|
- !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
|
||||||
|
+ if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) ||
|
||||||
|
+ (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
|
||||||
|
+ !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)))
|
||||||
|
tp->read32_mbox(tp, off);
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -477,7 +479,7 @@ static void tg3_write32_tx_mbox(struct t
|
||||||
|
writel(val, mbox);
|
||||||
|
if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
|
||||||
|
writel(val, mbox);
|
||||||
|
- if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
|
||||||
|
+ if ((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES))
|
||||||
|
readl(mbox);
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -777,7 +779,7 @@ static void tg3_switch_clocks(struct tg3
|
||||||
|
|
||||||
|
#define PHY_BUSY_LOOPS 5000
|
||||||
|
|
||||||
|
-static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
|
||||||
|
+static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
|
||||||
|
{
|
||||||
|
u32 frame_val;
|
||||||
|
unsigned int loops;
|
||||||
|
@@ -791,7 +793,7 @@ static int tg3_readphy(struct tg3 *tp, i
|
||||||
|
|
||||||
|
*val = 0x0;
|
||||||
|
|
||||||
|
- frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
|
||||||
|
+ frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
|
||||||
|
MI_COM_PHY_ADDR_MASK);
|
||||||
|
frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
|
||||||
|
MI_COM_REG_ADDR_MASK);
|
||||||
|
@@ -826,7 +828,12 @@ static int tg3_readphy(struct tg3 *tp, i
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
-static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
|
||||||
|
+static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
|
||||||
|
+{
|
||||||
|
+ return __tg3_readphy(tp, tp->phy_addr, reg, val);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
|
||||||
|
{
|
||||||
|
u32 frame_val;
|
||||||
|
unsigned int loops;
|
||||||
|
@@ -842,7 +849,7 @@ static int tg3_writephy(struct tg3 *tp,
|
||||||
|
udelay(80);
|
||||||
|
}
|
||||||
|
|
||||||
|
- frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
|
||||||
|
+ frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
|
||||||
|
MI_COM_PHY_ADDR_MASK);
|
||||||
|
frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
|
||||||
|
MI_COM_REG_ADDR_MASK);
|
||||||
|
@@ -875,6 +882,11 @@ static int tg3_writephy(struct tg3 *tp,
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
+static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
|
||||||
|
+{
|
||||||
|
+ return __tg3_writephy(tp, tp->phy_addr, reg, val);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static int tg3_bmcr_reset(struct tg3 *tp)
|
||||||
|
{
|
||||||
|
u32 phy_control;
|
||||||
|
@@ -2381,6 +2393,9 @@ static int tg3_nvram_read(struct tg3 *tp
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
|
||||||
|
+ return -ENODEV;
|
||||||
|
+
|
||||||
|
if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
|
||||||
|
return tg3_nvram_read_using_eeprom(tp, offset, val);
|
||||||
|
|
||||||
|
@@ -2712,8 +2727,10 @@ static int tg3_set_power_state(struct tg
|
||||||
|
tg3_frob_aux_power(tp);
|
||||||
|
|
||||||
|
/* Workaround for unstable PLL clock */
|
||||||
|
- if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
|
||||||
|
- (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
|
||||||
|
+ if ((tp->phy_id & PHY_ID_MASK) != PHY_ID_BCM5750_2 &&
|
||||||
|
+ /* !!! FIXME !!! */
|
||||||
|
+ ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
|
||||||
|
+ (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
|
||||||
|
u32 val = tr32(0x7d00);
|
||||||
|
|
||||||
|
val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
|
||||||
|
@@ -3205,6 +3222,14 @@ relink:
|
||||||
|
|
||||||
|
tg3_phy_copper_begin(tp);
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_ROBOSWITCH) {
|
||||||
|
+ current_link_up = 1;
|
||||||
|
+ current_speed = SPEED_1000; //FIXME
|
||||||
|
+ current_duplex = DUPLEX_FULL;
|
||||||
|
+ tp->link_config.active_speed = current_speed;
|
||||||
|
+ tp->link_config.active_duplex = current_duplex;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
tg3_readphy(tp, MII_BMSR, &tmp);
|
||||||
|
if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
|
||||||
|
(tmp & BMSR_LSTATUS))
|
||||||
|
@@ -6633,6 +6658,11 @@ static int tg3_poll_fw(struct tg3 *tp)
|
||||||
|
int i;
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
|
||||||
|
+ /* We don't use firmware. */
|
||||||
|
+ return 0;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
|
||||||
|
/* Wait up to 20ms for init done. */
|
||||||
|
for (i = 0; i < 200; i++) {
|
||||||
|
@@ -6910,6 +6940,14 @@ static int tg3_chip_reset(struct tg3 *tp
|
||||||
|
tw32(0x5000, 0x400);
|
||||||
|
}
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
|
||||||
|
+ /* BCM4785: In order to avoid repercussions from using potentially
|
||||||
|
+ * defective internal ROM, stop the Rx RISC CPU, which is not
|
||||||
|
+ * required. */
|
||||||
|
+ tg3_stop_fw(tp);
|
||||||
|
+ tg3_halt_cpu(tp, RX_CPU_BASE);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
tw32(GRC_MODE, tp->grc_mode);
|
||||||
|
|
||||||
|
if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
|
||||||
|
@@ -7089,9 +7127,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
|
||||||
|
- /* Clear firmware's nvram arbitration. */
|
||||||
|
- if (tp->tg3_flags & TG3_FLAG_NVRAM)
|
||||||
|
- tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
|
||||||
|
+ if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) {
|
||||||
|
+ /* Clear firmware's nvram arbitration. */
|
||||||
|
+ if (tp->tg3_flags & TG3_FLAG_NVRAM)
|
||||||
|
+ tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -7154,6 +7195,11 @@ static int tg3_load_5701_a0_firmware_fix
|
||||||
|
const __be32 *fw_data;
|
||||||
|
int err, i;
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
|
||||||
|
+ /* We don't use firmware. */
|
||||||
|
+ return 0;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
fw_data = (void *)tp->fw->data;
|
||||||
|
|
||||||
|
/* Firmware blob starts with version numbers, followed by
|
||||||
|
@@ -7213,6 +7259,11 @@ static int tg3_load_tso_firmware(struct
|
||||||
|
unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
|
||||||
|
int err, i;
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
|
||||||
|
+ /* We don't use firmware. */
|
||||||
|
+ return 0;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
@@ -8317,6 +8368,11 @@ static void tg3_timer(unsigned long __op
|
||||||
|
|
||||||
|
spin_lock(&tp->lock);
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
|
||||||
|
+ /* BCM4785: Flush posted writes from GbE to host memory. */
|
||||||
|
+ tr32(HOSTCC_MODE);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
|
||||||
|
/* All of this garbage is because when using non-tagged
|
||||||
|
* IRQ status the mailbox/status_block protocol the chip
|
||||||
|
@@ -10214,6 +10270,11 @@ static int tg3_test_nvram(struct tg3 *tp
|
||||||
|
if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
|
||||||
|
+ /* We don't have NVRAM. */
|
||||||
|
+ return 0;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
if (tg3_nvram_read(tp, 0, &magic) != 0)
|
||||||
|
return -EIO;
|
||||||
|
|
||||||
|
@@ -11014,7 +11075,7 @@ static int tg3_ioctl(struct net_device *
|
||||||
|
return -EAGAIN;
|
||||||
|
|
||||||
|
spin_lock_bh(&tp->lock);
|
||||||
|
- err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
|
||||||
|
+ err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
|
||||||
|
spin_unlock_bh(&tp->lock);
|
||||||
|
|
||||||
|
data->val_out = mii_regval;
|
||||||
|
@@ -11030,7 +11091,7 @@ static int tg3_ioctl(struct net_device *
|
||||||
|
return -EAGAIN;
|
||||||
|
|
||||||
|
spin_lock_bh(&tp->lock);
|
||||||
|
- err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
|
||||||
|
+ err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
|
||||||
|
spin_unlock_bh(&tp->lock);
|
||||||
|
|
||||||
|
return err;
|
||||||
|
@@ -11675,6 +11736,12 @@ static void __devinit tg3_get_5717_nvram
|
||||||
|
/* Chips other than 5700/5701 use the NVRAM for fetching info. */
|
||||||
|
static void __devinit tg3_nvram_init(struct tg3 *tp)
|
||||||
|
{
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
|
||||||
|
+ /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
|
||||||
|
+ tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
|
||||||
|
+ return;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
tw32_f(GRC_EEPROM_ADDR,
|
||||||
|
(EEPROM_ADDR_FSM_RESET |
|
||||||
|
(EEPROM_DEFAULT_CLOCK_PERIOD <<
|
||||||
|
@@ -11936,6 +12003,9 @@ static int tg3_nvram_write_block(struct
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
|
||||||
|
+ return -ENODEV;
|
||||||
|
+
|
||||||
|
if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
|
||||||
|
tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
|
||||||
|
~GRC_LCLCTRL_GPIO_OUTPUT1);
|
||||||
|
@@ -13246,6 +13316,11 @@ static int __devinit tg3_get_invariants(
|
||||||
|
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
|
||||||
|
tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
|
||||||
|
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
|
||||||
|
+ tp->write32_tx_mbox = tg3_write_flush_reg32;
|
||||||
|
+ tp->write32_rx_mbox = tg3_write_flush_reg32;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
/* Get eeprom hw config before calling tg3_set_power_state().
|
||||||
|
* In particular, the TG3_FLG2_IS_NIC flag must be
|
||||||
|
* determined before calling tg3_set_power_state() so that
|
||||||
|
@@ -13637,6 +13712,10 @@ static int __devinit tg3_get_device_addr
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!is_valid_ether_addr(&dev->dev_addr[0])) {
|
||||||
|
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
|
||||||
|
+ ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
|
||||||
|
+ }
|
||||||
|
+ if (!is_valid_ether_addr(&dev->dev_addr[0])) {
|
||||||
|
#ifdef CONFIG_SPARC
|
||||||
|
if (!tg3_get_default_macaddr_sparc(tp))
|
||||||
|
return 0;
|
||||||
|
@@ -14139,6 +14218,7 @@ static char * __devinit tg3_phy_string(s
|
||||||
|
case PHY_ID_BCM5704: return "5704";
|
||||||
|
case PHY_ID_BCM5705: return "5705";
|
||||||
|
case PHY_ID_BCM5750: return "5750";
|
||||||
|
+ case PHY_ID_BCM5750_2: return "5750-2";
|
||||||
|
case PHY_ID_BCM5752: return "5752";
|
||||||
|
case PHY_ID_BCM5714: return "5714";
|
||||||
|
case PHY_ID_BCM5780: return "5780";
|
||||||
|
@@ -14351,6 +14431,13 @@ static int __devinit tg3_init_one(struct
|
||||||
|
tp->msg_enable = tg3_debug;
|
||||||
|
else
|
||||||
|
tp->msg_enable = TG3_DEF_MSG_ENABLE;
|
||||||
|
+ if (pdev_is_ssb_gige_core(pdev)) {
|
||||||
|
+ tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE;
|
||||||
|
+ if (ssb_gige_must_flush_posted_writes(pdev))
|
||||||
|
+ tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES;
|
||||||
|
+ if (ssb_gige_have_roboswitch(pdev))
|
||||||
|
+ tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH;
|
||||||
|
+ }
|
||||||
|
|
||||||
|
/* The word/byte swap controls here control register access byte
|
||||||
|
* swapping. DMA data byte swapping is controlled in the GRC_MODE
|
||||||
|
--- a/drivers/net/tg3.h
|
||||||
|
+++ b/drivers/net/tg3.h
|
||||||
|
@@ -1959,6 +1959,9 @@
|
||||||
|
#define NIC_SRAM_RGMII_STD_IBND_DISABLE 0x00000004
|
||||||
|
#define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
|
||||||
|
#define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
|
||||||
|
+#define TG3_FLG3_IS_SSB_CORE 0x00000800
|
||||||
|
+#define TG3_FLG3_FLUSH_POSTED_WRITES 0x00001000
|
||||||
|
+#define TG3_FLG3_ROBOSWITCH 0x00002000
|
||||||
|
|
||||||
|
#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
|
||||||
|
|
||||||
|
@@ -2874,6 +2877,7 @@ struct tg3 {
|
||||||
|
#define PHY_ID_BCM5714 0x60008340
|
||||||
|
#define PHY_ID_BCM5780 0x60008350
|
||||||
|
#define PHY_ID_BCM5755 0xbc050cc0
|
||||||
|
+#define PHY_ID_BCM5750_2 0xbc050cd0
|
||||||
|
#define PHY_ID_BCM5787 0xbc050ce0
|
||||||
|
#define PHY_ID_BCM5756 0xbc050ed0
|
||||||
|
#define PHY_ID_BCM5784 0xbc050fa0
|
||||||
|
@@ -2921,7 +2925,8 @@ struct tg3 {
|
||||||
|
(X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
|
||||||
|
(X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
|
||||||
|
(X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
|
||||||
|
- (X) == PHY_ID_BCM5717 || (X) == PHY_ID_BCM8002)
|
||||||
|
+ (X) == PHY_ID_BCM5717 || (X) == PHY_ID_BCM8002 || \
|
||||||
|
+ (X) == PHY_ID_BCM5750_2)
|
||||||
|
|
||||||
|
struct tg3_hw_stats *hw_stats;
|
||||||
|
dma_addr_t stats_mapping;
|
||||||
|
|
@ -0,0 +1,108 @@
|
||||||
|
--- a/arch/mips/bcm47xx/prom.c
|
||||||
|
+++ b/arch/mips/bcm47xx/prom.c
|
||||||
|
@@ -32,6 +32,7 @@
|
||||||
|
#include <asm/fw/cfe/cfe_error.h>
|
||||||
|
|
||||||
|
static int cfe_cons_handle;
|
||||||
|
+static void (* __prom_putchar)(char c);
|
||||||
|
|
||||||
|
const char *get_system_type(void)
|
||||||
|
{
|
||||||
|
@@ -40,65 +41,40 @@ const char *get_system_type(void)
|
||||||
|
|
||||||
|
void prom_putchar(char c)
|
||||||
|
{
|
||||||
|
+ if (__prom_putchar)
|
||||||
|
+ __prom_putchar(c);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+void prom_putchar_cfe(char c)
|
||||||
|
+{
|
||||||
|
while (cfe_write(cfe_cons_handle, &c, 1) == 0)
|
||||||
|
;
|
||||||
|
}
|
||||||
|
|
||||||
|
-static __init void prom_init_cfe(void)
|
||||||
|
+static __init int prom_init_cfe(void)
|
||||||
|
{
|
||||||
|
uint32_t cfe_ept;
|
||||||
|
uint32_t cfe_handle;
|
||||||
|
uint32_t cfe_eptseal;
|
||||||
|
- int argc = fw_arg0;
|
||||||
|
- char **envp = (char **) fw_arg2;
|
||||||
|
- int *prom_vec = (int *) fw_arg3;
|
||||||
|
-
|
||||||
|
- /*
|
||||||
|
- * Check if a loader was used; if NOT, the 4 arguments are
|
||||||
|
- * what CFE gives us (handle, 0, EPT and EPTSEAL)
|
||||||
|
- */
|
||||||
|
- if (argc < 0) {
|
||||||
|
- cfe_handle = (uint32_t)argc;
|
||||||
|
- cfe_ept = (uint32_t)envp;
|
||||||
|
- cfe_eptseal = (uint32_t)prom_vec;
|
||||||
|
- } else {
|
||||||
|
- if ((int)prom_vec < 0) {
|
||||||
|
- /*
|
||||||
|
- * Old loader; all it gives us is the handle,
|
||||||
|
- * so use the "known" entrypoint and assume
|
||||||
|
- * the seal.
|
||||||
|
- */
|
||||||
|
- cfe_handle = (uint32_t)prom_vec;
|
||||||
|
- cfe_ept = 0xBFC00500;
|
||||||
|
- cfe_eptseal = CFE_EPTSEAL;
|
||||||
|
- } else {
|
||||||
|
- /*
|
||||||
|
- * Newer loaders bundle the handle/ept/eptseal
|
||||||
|
- * Note: prom_vec is in the loader's useg
|
||||||
|
- * which is still alive in the TLB.
|
||||||
|
- */
|
||||||
|
- cfe_handle = prom_vec[0];
|
||||||
|
- cfe_ept = prom_vec[2];
|
||||||
|
- cfe_eptseal = prom_vec[3];
|
||||||
|
- }
|
||||||
|
- }
|
||||||
|
|
||||||
|
- if (cfe_eptseal != CFE_EPTSEAL) {
|
||||||
|
- /* too early for panic to do any good */
|
||||||
|
- printk(KERN_ERR "CFE's entrypoint seal doesn't match.");
|
||||||
|
- while (1) ;
|
||||||
|
- }
|
||||||
|
+ cfe_eptseal = (uint32_t) fw_arg3;
|
||||||
|
+ cfe_handle = (uint32_t) fw_arg0;
|
||||||
|
+ cfe_ept = (uint32_t) fw_arg2;
|
||||||
|
+
|
||||||
|
+ if (cfe_eptseal != CFE_EPTSEAL)
|
||||||
|
+ return -1;
|
||||||
|
|
||||||
|
cfe_init(cfe_handle, cfe_ept);
|
||||||
|
+ return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
-static __init void prom_init_console(void)
|
||||||
|
+static __init void prom_init_console_cfe(void)
|
||||||
|
{
|
||||||
|
/* Initialize CFE console */
|
||||||
|
cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
-static __init void prom_init_cmdline(void)
|
||||||
|
+static __init void prom_init_cmdline_cfe(void)
|
||||||
|
{
|
||||||
|
static char buf[COMMAND_LINE_SIZE] __initdata;
|
||||||
|
|
||||||
|
@@ -154,9 +130,12 @@ static __init void prom_init_mem(void)
|
||||||
|
|
||||||
|
void __init prom_init(void)
|
||||||
|
{
|
||||||
|
- prom_init_cfe();
|
||||||
|
- prom_init_console();
|
||||||
|
- prom_init_cmdline();
|
||||||
|
+ if (prom_init_cfe() == 0) {
|
||||||
|
+ //prom_init_console_cfe();
|
||||||
|
+ //prom_init_cmdline_cfe();
|
||||||
|
+ __prom_putchar = prom_putchar_cfe;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
prom_init_mem();
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,178 @@
|
||||||
|
--- a/arch/mips/bcm47xx/Makefile
|
||||||
|
+++ b/arch/mips/bcm47xx/Makefile
|
||||||
|
@@ -3,4 +3,4 @@
|
||||||
|
# under Linux.
|
||||||
|
#
|
||||||
|
|
||||||
|
-obj-y := cfe_env.o gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o
|
||||||
|
+obj-y := cfe_env.o gpio.o irq.o nvram.o prom.o serial.o setup.o time.o
|
||||||
|
--- a/arch/mips/bcm47xx/wgt634u.c
|
||||||
|
+++ /dev/null
|
||||||
|
@@ -1,167 +0,0 @@
|
||||||
|
-/*
|
||||||
|
- * This file is subject to the terms and conditions of the GNU General Public
|
||||||
|
- * License. See the file "COPYING" in the main directory of this archive
|
||||||
|
- * for more details.
|
||||||
|
- *
|
||||||
|
- * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
|
||||||
|
- */
|
||||||
|
-
|
||||||
|
-#include <linux/platform_device.h>
|
||||||
|
-#include <linux/module.h>
|
||||||
|
-#include <linux/leds.h>
|
||||||
|
-#include <linux/mtd/physmap.h>
|
||||||
|
-#include <linux/ssb/ssb.h>
|
||||||
|
-#include <linux/interrupt.h>
|
||||||
|
-#include <linux/reboot.h>
|
||||||
|
-#include <linux/gpio.h>
|
||||||
|
-#include <asm/mach-bcm47xx/bcm47xx.h>
|
||||||
|
-
|
||||||
|
-/* GPIO definitions for the WGT634U */
|
||||||
|
-#define WGT634U_GPIO_LED 3
|
||||||
|
-#define WGT634U_GPIO_RESET 2
|
||||||
|
-#define WGT634U_GPIO_TP1 7
|
||||||
|
-#define WGT634U_GPIO_TP2 6
|
||||||
|
-#define WGT634U_GPIO_TP3 5
|
||||||
|
-#define WGT634U_GPIO_TP4 4
|
||||||
|
-#define WGT634U_GPIO_TP5 1
|
||||||
|
-
|
||||||
|
-static struct gpio_led wgt634u_leds[] = {
|
||||||
|
- {
|
||||||
|
- .name = "power",
|
||||||
|
- .gpio = WGT634U_GPIO_LED,
|
||||||
|
- .active_low = 1,
|
||||||
|
- .default_trigger = "heartbeat",
|
||||||
|
- },
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static struct gpio_led_platform_data wgt634u_led_data = {
|
||||||
|
- .num_leds = ARRAY_SIZE(wgt634u_leds),
|
||||||
|
- .leds = wgt634u_leds,
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static struct platform_device wgt634u_gpio_leds = {
|
||||||
|
- .name = "leds-gpio",
|
||||||
|
- .id = -1,
|
||||||
|
- .dev = {
|
||||||
|
- .platform_data = &wgt634u_led_data,
|
||||||
|
- }
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-
|
||||||
|
-/* 8MiB flash. The struct mtd_partition matches original Netgear WGT634U
|
||||||
|
- firmware. */
|
||||||
|
-static struct mtd_partition wgt634u_partitions[] = {
|
||||||
|
- {
|
||||||
|
- .name = "cfe",
|
||||||
|
- .offset = 0,
|
||||||
|
- .size = 0x60000, /* 384k */
|
||||||
|
- .mask_flags = MTD_WRITEABLE /* force read-only */
|
||||||
|
- },
|
||||||
|
- {
|
||||||
|
- .name = "config",
|
||||||
|
- .offset = 0x60000,
|
||||||
|
- .size = 0x20000 /* 128k */
|
||||||
|
- },
|
||||||
|
- {
|
||||||
|
- .name = "linux",
|
||||||
|
- .offset = 0x80000,
|
||||||
|
- .size = 0x140000 /* 1280k */
|
||||||
|
- },
|
||||||
|
- {
|
||||||
|
- .name = "jffs",
|
||||||
|
- .offset = 0x1c0000,
|
||||||
|
- .size = 0x620000 /* 6272k */
|
||||||
|
- },
|
||||||
|
- {
|
||||||
|
- .name = "nvram",
|
||||||
|
- .offset = 0x7e0000,
|
||||||
|
- .size = 0x20000 /* 128k */
|
||||||
|
- },
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static struct physmap_flash_data wgt634u_flash_data = {
|
||||||
|
- .parts = wgt634u_partitions,
|
||||||
|
- .nr_parts = ARRAY_SIZE(wgt634u_partitions)
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static struct resource wgt634u_flash_resource = {
|
||||||
|
- .flags = IORESOURCE_MEM,
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static struct platform_device wgt634u_flash = {
|
||||||
|
- .name = "physmap-flash",
|
||||||
|
- .id = 0,
|
||||||
|
- .dev = { .platform_data = &wgt634u_flash_data, },
|
||||||
|
- .resource = &wgt634u_flash_resource,
|
||||||
|
- .num_resources = 1,
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-/* Platform devices */
|
||||||
|
-static struct platform_device *wgt634u_devices[] __initdata = {
|
||||||
|
- &wgt634u_flash,
|
||||||
|
- &wgt634u_gpio_leds,
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-static irqreturn_t gpio_interrupt(int irq, void *ignored)
|
||||||
|
-{
|
||||||
|
- int state;
|
||||||
|
-
|
||||||
|
- /* Interrupts are shared, check if the current one is
|
||||||
|
- a GPIO interrupt. */
|
||||||
|
- if (!ssb_chipco_irq_status(&ssb_bcm47xx.chipco,
|
||||||
|
- SSB_CHIPCO_IRQ_GPIO))
|
||||||
|
- return IRQ_NONE;
|
||||||
|
-
|
||||||
|
- state = gpio_get_value(WGT634U_GPIO_RESET);
|
||||||
|
-
|
||||||
|
- /* Interrupt are level triggered, revert the interrupt polarity
|
||||||
|
- to clear the interrupt. */
|
||||||
|
- gpio_polarity(WGT634U_GPIO_RESET, state);
|
||||||
|
-
|
||||||
|
- if (!state) {
|
||||||
|
- printk(KERN_INFO "Reset button pressed");
|
||||||
|
- ctrl_alt_del();
|
||||||
|
- }
|
||||||
|
-
|
||||||
|
- return IRQ_HANDLED;
|
||||||
|
-}
|
||||||
|
-
|
||||||
|
-static int __init wgt634u_init(void)
|
||||||
|
-{
|
||||||
|
- /* There is no easy way to detect that we are running on a WGT634U
|
||||||
|
- * machine. Use the MAC address as an heuristic. Netgear Inc. has
|
||||||
|
- * been allocated ranges 00:09:5b:xx:xx:xx and 00:0f:b5:xx:xx:xx.
|
||||||
|
- */
|
||||||
|
-
|
||||||
|
- u8 *et0mac = ssb_bcm47xx.sprom.et0mac;
|
||||||
|
-
|
||||||
|
- if (et0mac[0] == 0x00 &&
|
||||||
|
- ((et0mac[1] == 0x09 && et0mac[2] == 0x5b) ||
|
||||||
|
- (et0mac[1] == 0x0f && et0mac[2] == 0xb5))) {
|
||||||
|
- struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore;
|
||||||
|
-
|
||||||
|
- printk(KERN_INFO "WGT634U machine detected.\n");
|
||||||
|
-
|
||||||
|
- if (!request_irq(gpio_to_irq(WGT634U_GPIO_RESET),
|
||||||
|
- gpio_interrupt, IRQF_SHARED,
|
||||||
|
- "WGT634U GPIO", &ssb_bcm47xx.chipco)) {
|
||||||
|
- gpio_direction_input(WGT634U_GPIO_RESET);
|
||||||
|
- gpio_intmask(WGT634U_GPIO_RESET, 1);
|
||||||
|
- ssb_chipco_irq_mask(&ssb_bcm47xx.chipco,
|
||||||
|
- SSB_CHIPCO_IRQ_GPIO,
|
||||||
|
- SSB_CHIPCO_IRQ_GPIO);
|
||||||
|
- }
|
||||||
|
-
|
||||||
|
- wgt634u_flash_data.width = mcore->flash_buswidth;
|
||||||
|
- wgt634u_flash_resource.start = mcore->flash_window;
|
||||||
|
- wgt634u_flash_resource.end = mcore->flash_window
|
||||||
|
- + mcore->flash_window_size
|
||||||
|
- - 1;
|
||||||
|
- return platform_add_devices(wgt634u_devices,
|
||||||
|
- ARRAY_SIZE(wgt634u_devices));
|
||||||
|
- } else
|
||||||
|
- return -ENODEV;
|
||||||
|
-}
|
||||||
|
-
|
||||||
|
-module_init(wgt634u_init);
|
||||||
|
-
|
||||||
|
|
@ -0,0 +1,11 @@
|
||||||
|
--- a/drivers/net/b44.c
|
||||||
|
+++ b/drivers/net/b44.c
|
||||||
|
@@ -815,7 +815,7 @@ static int b44_rx(struct b44 *bp, int bu
|
||||||
|
struct sk_buff *copy_skb;
|
||||||
|
|
||||||
|
b44_recycle_rx(bp, cons, bp->rx_prod);
|
||||||
|
- copy_skb = dev_alloc_skb(len + 2);
|
||||||
|
+ copy_skb = netdev_alloc_skb(bp->dev, len + 2);
|
||||||
|
if (copy_skb == NULL)
|
||||||
|
goto drop_it_no_recycle;
|
||||||
|
|
||||||
|
|
@ -0,0 +1,10 @@
|
||||||
|
--- a/arch/mips/Kconfig
|
||||||
|
+++ b/arch/mips/Kconfig
|
||||||
|
@@ -65,7 +65,6 @@ config BCM47XX
|
||||||
|
select SSB_B43_PCI_BRIDGE if PCI
|
||||||
|
select SSB_PCICORE_HOSTMODE if PCI
|
||||||
|
select GENERIC_GPIO
|
||||||
|
- select SYS_HAS_EARLY_PRINTK
|
||||||
|
select CFE
|
||||||
|
help
|
||||||
|
Support for BCM47XX based boards
|
||||||
|
|
@ -0,0 +1,135 @@
|
||||||
|
--- a/arch/mips/include/asm/r4kcache.h
|
||||||
|
+++ b/arch/mips/include/asm/r4kcache.h
|
||||||
|
@@ -20,10 +20,25 @@
|
||||||
|
#ifdef CONFIG_BCM47XX
|
||||||
|
#include <asm/paccess.h>
|
||||||
|
#include <linux/ssb/ssb.h>
|
||||||
|
-#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE + SSB_IMSTATE)))
|
||||||
|
+#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg()
|
||||||
|
+
|
||||||
|
+static inline unsigned long bcm4710_dummy_rreg(void) {
|
||||||
|
+ return (*(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE + SSB_IMSTATE)));
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void*)(addr))
|
||||||
|
+
|
||||||
|
+static inline unsigned long bcm4710_fill_tlb(void *addr) {
|
||||||
|
+ return (*(unsigned long *)addr);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void*)(addr))
|
||||||
|
+
|
||||||
|
+static inline void bcm4710_protected_fill_tlb(void *addr) {
|
||||||
|
+ unsigned long x;
|
||||||
|
+ get_dbe(x, (unsigned long *)addr);;
|
||||||
|
+}
|
||||||
|
|
||||||
|
-#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
|
||||||
|
-#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
|
||||||
|
#else
|
||||||
|
#define BCM4710_DUMMY_RREG()
|
||||||
|
|
||||||
|
--- a/arch/mips/mm/tlbex.c
|
||||||
|
+++ b/arch/mips/mm/tlbex.c
|
||||||
|
@@ -611,6 +611,9 @@ build_get_pgde32(u32 **p, unsigned int t
|
||||||
|
#endif
|
||||||
|
uasm_i_addu(p, ptr, tmp, ptr);
|
||||||
|
#else
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ uasm_i_nop(p);
|
||||||
|
+#endif
|
||||||
|
UASM_i_LA_mostly(p, ptr, pgdc);
|
||||||
|
#endif
|
||||||
|
uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
|
||||||
|
@@ -749,12 +752,12 @@ static void __cpuinit build_r4000_tlb_re
|
||||||
|
/* No need for uasm_i_nop */
|
||||||
|
}
|
||||||
|
|
||||||
|
-#ifdef CONFIG_BCM47XX
|
||||||
|
- uasm_i_nop(&p);
|
||||||
|
-#endif
|
||||||
|
#ifdef CONFIG_64BIT
|
||||||
|
build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
|
||||||
|
#else
|
||||||
|
+# ifdef CONFIG_BCM47XX
|
||||||
|
+ uasm_i_nop(&p);
|
||||||
|
+# endif
|
||||||
|
build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
@@ -766,6 +769,9 @@ static void __cpuinit build_r4000_tlb_re
|
||||||
|
build_update_entries(&p, K0, K1);
|
||||||
|
build_tlb_write_entry(&p, &l, &r, tlb_random);
|
||||||
|
uasm_l_leave(&l, p);
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ uasm_i_nop(&p);
|
||||||
|
+#endif
|
||||||
|
uasm_i_eret(&p); /* return from trap */
|
||||||
|
|
||||||
|
#ifdef CONFIG_HUGETLB_PAGE
|
||||||
|
@@ -1206,12 +1212,12 @@ build_r4000_tlbchange_handler_head(u32 *
|
||||||
|
struct uasm_reloc **r, unsigned int pte,
|
||||||
|
unsigned int ptr)
|
||||||
|
{
|
||||||
|
-#ifdef CONFIG_BCM47XX
|
||||||
|
- uasm_i_nop(p);
|
||||||
|
-#endif
|
||||||
|
#ifdef CONFIG_64BIT
|
||||||
|
build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
|
||||||
|
#else
|
||||||
|
+# ifdef CONFIG_BCM47XX
|
||||||
|
+ uasm_i_nop(p);
|
||||||
|
+# endif
|
||||||
|
build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
@@ -1248,6 +1254,9 @@ build_r4000_tlbchange_handler_tail(u32 *
|
||||||
|
build_update_entries(p, tmp, ptr);
|
||||||
|
build_tlb_write_entry(p, l, r, tlb_indexed);
|
||||||
|
uasm_l_leave(l, *p);
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ uasm_i_nop(p);
|
||||||
|
+#endif
|
||||||
|
uasm_i_eret(p); /* return from trap */
|
||||||
|
|
||||||
|
#ifdef CONFIG_64BIT
|
||||||
|
--- a/arch/mips/kernel/genex.S
|
||||||
|
+++ b/arch/mips/kernel/genex.S
|
||||||
|
@@ -22,6 +22,19 @@
|
||||||
|
#include <asm/page.h>
|
||||||
|
#include <asm/thread_info.h>
|
||||||
|
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+# ifdef eret
|
||||||
|
+# undef eret
|
||||||
|
+# endif
|
||||||
|
+# define eret \
|
||||||
|
+ .set push; \
|
||||||
|
+ .set noreorder; \
|
||||||
|
+ nop; \
|
||||||
|
+ nop; \
|
||||||
|
+ eret; \
|
||||||
|
+ .set pop;
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
#define PANIC_PIC(msg) \
|
||||||
|
.set push; \
|
||||||
|
.set reorder; \
|
||||||
|
@@ -54,7 +67,6 @@ NESTED(except_vec3_generic, 0, sp)
|
||||||
|
.set noat
|
||||||
|
#ifdef CONFIG_BCM47XX
|
||||||
|
nop
|
||||||
|
- nop
|
||||||
|
#endif
|
||||||
|
#if R5432_CP0_INTERRUPT_WAR
|
||||||
|
mfc0 k0, CP0_INDEX
|
||||||
|
@@ -79,6 +91,9 @@ NESTED(except_vec3_r4000, 0, sp)
|
||||||
|
.set push
|
||||||
|
.set mips3
|
||||||
|
.set noat
|
||||||
|
+#ifdef CONFIG_BCM47XX
|
||||||
|
+ nop
|
||||||
|
+#endif
|
||||||
|
mfc0 k1, CP0_CAUSE
|
||||||
|
li k0, 31<<2
|
||||||
|
andi k1, k1, 0x7c
|
||||||
Loading…
Reference in New Issue