mirror of https://github.com/hak5/openwrt-owl.git
imx6: remove support for 4.9
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Koen Vandeputte <koen.vandeputte@ncentric.com>openwrt-18.06
Tim Harvey
John Crispin
parent
8f9668f46c
commit
1188f35a98
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@ -1,497 +0,0 @@
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CONFIG_AHCI_IMX=y
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CONFIG_ALIGNMENT_TRAP=y
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CONFIG_ARCH_CLOCKSOURCE_DATA=y
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CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
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CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
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CONFIG_ARCH_HAS_RESET_CONTROLLER=y
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CONFIG_ARCH_HAS_SG_CHAIN=y
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CONFIG_ARCH_HAS_TICK_BROADCAST=y
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CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
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CONFIG_ARCH_MMAP_RND_BITS_MAX=15
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CONFIG_ARCH_MULTIPLATFORM=y
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# CONFIG_ARCH_MULTI_CPU_AUTO is not set
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CONFIG_ARCH_MULTI_V6_V7=y
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CONFIG_ARCH_MULTI_V7=y
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CONFIG_ARCH_MXC=y
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CONFIG_ARCH_NR_GPIO=0
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# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
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# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
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CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
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CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
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CONFIG_ARCH_SUPPORTS_UPROBES=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARCH_USE_BUILTIN_BSWAP=y
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CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
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CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
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CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
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CONFIG_ARM=y
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CONFIG_ARM_CPU_SUSPEND=y
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CONFIG_ARM_CRYPTO=y
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CONFIG_ARM_ERRATA_754322=y
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CONFIG_ARM_ERRATA_764369=y
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CONFIG_ARM_ERRATA_775420=y
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CONFIG_ARM_GIC=y
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CONFIG_ARM_HAS_SG_CHAIN=y
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CONFIG_ARM_HEAVY_MB=y
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CONFIG_ARM_IMX6Q_CPUFREQ=y
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CONFIG_ARM_L1_CACHE_SHIFT=6
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CONFIG_ARM_L1_CACHE_SHIFT_6=y
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# CONFIG_ARM_LPAE is not set
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CONFIG_ARM_PATCH_IDIV=y
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CONFIG_ARM_PATCH_PHYS_VIRT=y
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CONFIG_ARM_THUMB=y
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# CONFIG_ARM_THUMBEE is not set
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CONFIG_ARM_VIRT_EXT=y
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CONFIG_ASN1=y
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CONFIG_ASSOCIATIVE_ARRAY=y
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CONFIG_ATA=y
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CONFIG_ATAGS=y
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CONFIG_AUTO_ZRELADDR=y
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CONFIG_BLK_MQ_PCI=y
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CONFIG_CACHE_L2X0=y
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CONFIG_CLKDEV_LOOKUP=y
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CONFIG_CLKSRC_IMX_GPT=y
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CONFIG_CLKSRC_MMIO=y
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CONFIG_CLKSRC_OF=y
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CONFIG_CLKSRC_PROBE=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CLZ_TAB=y
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CONFIG_COMMON_CLK=y
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CONFIG_CPUFREQ_DT=y
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CONFIG_CPUFREQ_DT_PLATDEV=y
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CONFIG_CPU_32v6K=y
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CONFIG_CPU_32v7=y
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CONFIG_CPU_ABRT_EV7=y
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# CONFIG_CPU_BIG_ENDIAN is not set
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# CONFIG_CPU_BPREDICT_DISABLE is not set
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CONFIG_CPU_CACHE_V7=y
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CONFIG_CPU_CACHE_VIPT=y
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CONFIG_CPU_COPY_V6=y
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CONFIG_CPU_CP15=y
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CONFIG_CPU_CP15_MMU=y
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CONFIG_CPU_FREQ=y
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CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
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CONFIG_CPU_FREQ_GOV_ATTR_SET=y
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CONFIG_CPU_FREQ_GOV_COMMON=y
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CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
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CONFIG_CPU_FREQ_GOV_ONDEMAND=y
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CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
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CONFIG_CPU_FREQ_GOV_POWERSAVE=y
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CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
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CONFIG_CPU_FREQ_GOV_USERSPACE=y
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CONFIG_CPU_FREQ_STAT=y
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CONFIG_CPU_FREQ_STAT_DETAILS=y
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CONFIG_CPU_HAS_ASID=y
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# CONFIG_CPU_ICACHE_DISABLE is not set
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CONFIG_CPU_PABRT_V7=y
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CONFIG_CPU_RMAP=y
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CONFIG_CPU_THERMAL=y
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CONFIG_CPU_TLB_V7=y
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CONFIG_CPU_V7=y
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# CONFIG_CRASHLOG is not set
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CONFIG_CRC16=y
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CONFIG_CRYPTO_ABLK_HELPER=y
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CONFIG_CRYPTO_AEAD=y
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CONFIG_CRYPTO_AEAD2=y
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CONFIG_CRYPTO_AES_ARM=y
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CONFIG_CRYPTO_AES_ARM_BS=y
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# CONFIG_CRYPTO_AES_ARM_CE is not set
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CONFIG_CRYPTO_AKCIPHER=y
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CONFIG_CRYPTO_AKCIPHER2=y
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CONFIG_CRYPTO_AUTHENC=y
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CONFIG_CRYPTO_CBC=y
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CONFIG_CRYPTO_CRC32C=y
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CONFIG_CRYPTO_CRYPTD=y
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CONFIG_CRYPTO_CTR=y
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CONFIG_CRYPTO_CTS=y
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CONFIG_CRYPTO_DEFLATE=y
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CONFIG_CRYPTO_DEV_FSL_CAAM=y
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CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
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CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
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# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set
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CONFIG_CRYPTO_DEV_FSL_CAAM_IMX=y
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# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set
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CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y
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CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y
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CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
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CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
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# CONFIG_CRYPTO_DEV_MXC_SCC is not set
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CONFIG_CRYPTO_DRBG=y
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CONFIG_CRYPTO_DRBG_HMAC=y
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CONFIG_CRYPTO_DRBG_MENU=y
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CONFIG_CRYPTO_ECB=y
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CONFIG_CRYPTO_GF128MUL=y
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# CONFIG_CRYPTO_GHASH_ARM_CE is not set
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CONFIG_CRYPTO_HASH=y
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CONFIG_CRYPTO_HASH2=y
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CONFIG_CRYPTO_HMAC=y
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CONFIG_CRYPTO_HW=y
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CONFIG_CRYPTO_JITTERENTROPY=y
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CONFIG_CRYPTO_LZO=y
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CONFIG_CRYPTO_MANAGER=y
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CONFIG_CRYPTO_MANAGER2=y
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CONFIG_CRYPTO_NULL=y
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CONFIG_CRYPTO_NULL2=y
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CONFIG_CRYPTO_RNG=y
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CONFIG_CRYPTO_RNG2=y
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CONFIG_CRYPTO_RNG_DEFAULT=y
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CONFIG_CRYPTO_RSA=y
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CONFIG_CRYPTO_SEQIV=y
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# CONFIG_CRYPTO_SHA1_ARM_CE is not set
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# CONFIG_CRYPTO_SHA1_ARM_NEON is not set
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CONFIG_CRYPTO_SHA256=y
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# CONFIG_CRYPTO_SHA256_ARM is not set
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# CONFIG_CRYPTO_SHA2_ARM_CE is not set
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# CONFIG_CRYPTO_SHA512_ARM is not set
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CONFIG_CRYPTO_WORKQUEUE=y
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CONFIG_CRYPTO_XTS=y
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CONFIG_DCACHE_WORD_ACCESS=y
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CONFIG_DEBUG_IMX_UART_PORT=1
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CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
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# CONFIG_DEBUG_UART_8250 is not set
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# CONFIG_DEBUG_USER is not set
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CONFIG_DECOMPRESS_BZIP2=y
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CONFIG_DECOMPRESS_GZIP=y
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CONFIG_DECOMPRESS_LZO=y
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CONFIG_DECOMPRESS_XZ=y
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CONFIG_DMADEVICES=y
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CONFIG_DMA_ENGINE=y
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CONFIG_DMA_OF=y
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CONFIG_DTC=y
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CONFIG_E1000E=y
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CONFIG_EDAC_ATOMIC_SCRUB=y
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CONFIG_EDAC_SUPPORT=y
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# CONFIG_ENABLE_DEFAULT_TRACERS is not set
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CONFIG_ENCRYPTED_KEYS=y
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CONFIG_EXT2_FS=y
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CONFIG_EXT2_FS_POSIX_ACL=y
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CONFIG_EXT2_FS_SECURITY=y
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CONFIG_EXT2_FS_XATTR=y
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CONFIG_EXT3_FS=y
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CONFIG_EXT3_FS_POSIX_ACL=y
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CONFIG_EXT3_FS_SECURITY=y
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CONFIG_EXT4_ENCRYPTION=y
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CONFIG_EXT4_FS=y
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CONFIG_EXT4_FS_ENCRYPTION=y
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CONFIG_EXT4_FS_POSIX_ACL=y
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CONFIG_EXT4_FS_SECURITY=y
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CONFIG_EXTCON=y
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CONFIG_FEC=y
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CONFIG_FIXED_PHY=y
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CONFIG_FIX_EARLYCON_MEM=y
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CONFIG_FRAME_POINTER=y
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CONFIG_FS_ENCRYPTION=y
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CONFIG_FS_MBCACHE=y
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CONFIG_FS_POSIX_ACL=y
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CONFIG_FTRACE=y
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# CONFIG_FTRACE_SYSCALLS is not set
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CONFIG_GENERIC_ALLOCATOR=y
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CONFIG_GENERIC_BUG=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
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CONFIG_GENERIC_EARLY_IOREMAP=y
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CONFIG_GENERIC_IDLE_POLL_SETUP=y
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CONFIG_GENERIC_IO=y
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CONFIG_GENERIC_IRQ_CHIP=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_PINCONF=y
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CONFIG_GENERIC_SCHED_CLOCK=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_STRNCPY_FROM_USER=y
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CONFIG_GENERIC_STRNLEN_USER=y
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# CONFIG_GIANFAR is not set
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CONFIG_GLOB=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIOLIB_IRQCHIP=y
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CONFIG_GPIO_GENERIC=y
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CONFIG_GPIO_MXC=y
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CONFIG_GPIO_PCA953X=y
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CONFIG_GPIO_PCA953X_IRQ=y
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CONFIG_GPIO_SYSFS=y
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CONFIG_HANDLE_DOMAIN_IRQ=y
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CONFIG_HARDIRQS_SW_RESEND=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT_MAP=y
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# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
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CONFIG_HAVE_ARCH_AUDITSYSCALL=y
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CONFIG_HAVE_ARCH_BITREVERSE=y
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CONFIG_HAVE_ARCH_JUMP_LABEL=y
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CONFIG_HAVE_ARCH_KGDB=y
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CONFIG_HAVE_ARCH_PFN_VALID=y
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CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
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CONFIG_HAVE_ARCH_TRACEHOOK=y
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CONFIG_HAVE_ARM_SCU=y
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CONFIG_HAVE_ARM_SMCCC=y
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CONFIG_HAVE_ARM_TWD=y
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# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
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CONFIG_HAVE_CBPF_JIT=y
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CONFIG_HAVE_CC_STACKPROTECTOR=y
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CONFIG_HAVE_CLK=y
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CONFIG_HAVE_CLK_PREPARE=y
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CONFIG_HAVE_CONTEXT_TRACKING=y
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CONFIG_HAVE_C_RECORDMCOUNT=y
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CONFIG_HAVE_DEBUG_KMEMLEAK=y
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CONFIG_HAVE_DMA_API_DEBUG=y
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CONFIG_HAVE_DMA_CONTIGUOUS=y
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CONFIG_HAVE_DYNAMIC_FTRACE=y
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CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
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CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
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CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACER=y
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CONFIG_HAVE_GENERIC_DMA_COHERENT=y
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CONFIG_HAVE_IDE=y
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CONFIG_HAVE_IMX_ANATOP=y
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CONFIG_HAVE_IMX_GPC=y
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CONFIG_HAVE_IMX_MMDC=y
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CONFIG_HAVE_IMX_SRC=y
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CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
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CONFIG_HAVE_MEMBLOCK=y
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CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
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CONFIG_HAVE_NET_DSA=y
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CONFIG_HAVE_OPROFILE=y
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CONFIG_HAVE_OPTPROBES=y
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CONFIG_HAVE_PERF_EVENTS=y
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CONFIG_HAVE_PERF_REGS=y
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CONFIG_HAVE_PERF_USER_STACK_DUMP=y
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CONFIG_HAVE_PROC_CPU=y
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CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
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CONFIG_HAVE_SMP=y
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CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
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CONFIG_HAVE_UID16=y
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CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
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CONFIG_HWMON=y
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CONFIG_HW_RANDOM=y
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CONFIG_HZ_FIXED=0
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CONFIG_HZ_PERIODIC=y
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CONFIG_I2C=y
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CONFIG_I2C_BOARDINFO=y
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CONFIG_I2C_CHARDEV=y
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CONFIG_I2C_IMX=y
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CONFIG_IMX2_WDT=y
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CONFIG_IMX_DMA=y
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CONFIG_IMX_SDMA=y
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CONFIG_IMX_THERMAL=y
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# CONFIG_IMX_WEIM is not set
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_IOMMU_HELPER=y
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CONFIG_IRQCHIP=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_DOMAIN_HIERARCHY=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_WORK=y
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CONFIG_JBD2=y
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# CONFIG_JFFS2_FS is not set
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CONFIG_KEYS=y
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CONFIG_LIBFDT=y
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CONFIG_LOCK_SPIN_ON_OWNER=y
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CONFIG_LZO_COMPRESS=y
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CONFIG_LZO_DECOMPRESS=y
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CONFIG_MARVELL_PHY=y
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CONFIG_MDIO_BOARDINFO=y
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CONFIG_MFD_SYSCON=y
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CONFIG_MICREL_PHY=y
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CONFIG_MIGHT_HAVE_CACHE_L2X0=y
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CONFIG_MIGHT_HAVE_PCI=y
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CONFIG_MMC=y
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CONFIG_MMC_BLOCK=y
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# CONFIG_MMC_MXC is not set
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ESDHC_IMX=y
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CONFIG_MMC_SDHCI_IO_ACCESSORS=y
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CONFIG_MMC_SDHCI_OF_ESDHC=y
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# CONFIG_MMC_SDHCI_PCI is not set
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CONFIG_MMC_SDHCI_PLTFM=y
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# CONFIG_MMC_TIFM_SD is not set
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CONFIG_MODULES_USE_ELF_REL=y
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CONFIG_MPILIB=y
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CONFIG_MTD_NAND=y
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CONFIG_MTD_NAND_ECC=y
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CONFIG_MTD_NAND_GPMI_NAND=y
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CONFIG_MTD_UBI=y
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CONFIG_MTD_UBI_BEB_LIMIT=20
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CONFIG_MTD_UBI_BLOCK=y
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# CONFIG_MTD_UBI_FASTMAP is not set
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# CONFIG_MTD_UBI_GLUEBI is not set
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CONFIG_MTD_UBI_WL_THRESHOLD=4096
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CONFIG_MULTI_IRQ_HANDLER=y
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CONFIG_MUTEX_SPIN_ON_OWNER=y
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# CONFIG_MX3_IPU is not set
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CONFIG_MXS_DMA=y
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CONFIG_NEED_DMA_MAP_STATE=y
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CONFIG_NEON=y
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CONFIG_NET_DSA=y
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CONFIG_NET_DSA_HWMON=y
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CONFIG_NET_DSA_MV88E6XXX=y
|
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CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y
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CONFIG_NET_DSA_TAG_DSA=y
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CONFIG_NET_DSA_TAG_EDSA=y
|
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CONFIG_NET_FLOW_LIMIT=y
|
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CONFIG_NET_PTP_CLASSIFY=y
|
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CONFIG_NET_SWITCHDEV=y
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CONFIG_NLS=y
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||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NO_BOOTMEM=y
|
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CONFIG_NR_CPUS=4
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||||
CONFIG_NVMEM=y
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||||
CONFIG_NVMEM_IMX_OCOTP=y
|
||||
CONFIG_OF=y
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||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_ADDRESS_PCI=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_NET=y
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||||
CONFIG_OF_PCI=y
|
||||
CONFIG_OF_PCI_IRQ=y
|
||||
CONFIG_OF_RESERVED_MEM=y
|
||||
CONFIG_OLD_SIGACTION=y
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||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
CONFIG_OUTER_CACHE=y
|
||||
CONFIG_OUTER_CACHE_SYNC=y
|
||||
CONFIG_PADATA=y
|
||||
CONFIG_PAGE_OFFSET=0x80000000
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEAER=y
|
||||
CONFIG_PCIEPORTBUS=y
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||||
CONFIG_PCIE_DW=y
|
||||
CONFIG_PCIE_PME=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||
CONFIG_PCI_IMX6=y
|
||||
CONFIG_PERF_USE_VMALLOC=y
|
||||
CONFIG_PGTABLE_LEVELS=2
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX=y
|
||||
CONFIG_PINCTRL_IMX6Q=y
|
||||
CONFIG_PINCTRL_IMX6SL=y
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||||
CONFIG_PINCTRL_IMX6SX=y
|
||||
CONFIG_PINCTRL_IMX6UL=y
|
||||
# CONFIG_PL310_ERRATA_588369 is not set
|
||||
# CONFIG_PL310_ERRATA_727915 is not set
|
||||
# CONFIG_PL310_ERRATA_753970 is not set
|
||||
CONFIG_PL310_ERRATA_769419=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_CLK=y
|
||||
# CONFIG_PM_DEBUG is not set
|
||||
CONFIG_PM_GENERIC_DOMAINS=y
|
||||
CONFIG_PM_GENERIC_DOMAINS_OF=y
|
||||
CONFIG_PM_OPP=y
|
||||
CONFIG_PPS=y
|
||||
# CONFIG_PROBE_EVENTS is not set
|
||||
CONFIG_PTP_1588_CLOCK=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_IMX=y
|
||||
CONFIG_PWM_SYSFS=y
|
||||
CONFIG_RAS=y
|
||||
CONFIG_RATIONAL=y
|
||||
CONFIG_RCU_STALL_COMMON=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_GZIP=y
|
||||
CONFIG_RD_LZO=y
|
||||
CONFIG_RD_XZ=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_I2C=y
|
||||
CONFIG_REGMAP_MMIO=y
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||||
CONFIG_REGMAP_SPI=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_ANATOP=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_LTC3676=y
|
||||
CONFIG_REGULATOR_PFUZE100=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
# CONFIG_RTC_DRV_CMOS is not set
|
||||
CONFIG_RTC_DRV_DS1307=y
|
||||
CONFIG_RTC_DRV_DS1672=y
|
||||
# CONFIG_RTC_DRV_IMXDI is not set
|
||||
# CONFIG_RTC_DRV_MXC is not set
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
|
||||
# CONFIG_SCHED_INFO is not set
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SENSORS_AD7418=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_IMX=y
|
||||
CONFIG_SERIAL_IMX_CONSOLE=y
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
CONFIG_SG_POOL=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SMP_ON_UP=y
|
||||
CONFIG_SOC_BUS=y
|
||||
# CONFIG_SOC_IMX50 is not set
|
||||
# CONFIG_SOC_IMX51 is not set
|
||||
# CONFIG_SOC_IMX53 is not set
|
||||
CONFIG_SOC_IMX6=y
|
||||
CONFIG_SOC_IMX6Q=y
|
||||
CONFIG_SOC_IMX6SL=y
|
||||
CONFIG_SOC_IMX6SX=y
|
||||
CONFIG_SOC_IMX6UL=y
|
||||
# CONFIG_SOC_IMX7D is not set
|
||||
# CONFIG_SOC_LS1021A is not set
|
||||
# CONFIG_SOC_VF610 is not set
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_BITBANG=y
|
||||
CONFIG_SPI_IMX=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SRAM=y
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_STMP_DEVICE=y
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SWP_EMULATE=y
|
||||
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_OF=y
|
||||
# CONFIG_THUMB2_KERNEL is not set
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TREE_RCU=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
|
||||
CONFIG_UBIFS_FS_LZO=y
|
||||
CONFIG_UBIFS_FS_ZLIB=y
|
||||
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_CHIPIDEA=y
|
||||
CONFIG_USB_CHIPIDEA_HOST=y
|
||||
CONFIG_USB_CHIPIDEA_OF=y
|
||||
CONFIG_USB_CHIPIDEA_UDC=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
# CONFIG_USB_EHCI_HCD_PLATFORM is not set
|
||||
# CONFIG_USB_EHCI_MXC is not set
|
||||
CONFIG_USB_EHCI_PCI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
# CONFIG_USB_IMX21_HCD is not set
|
||||
CONFIG_USB_MXS_PHY=y
|
||||
CONFIG_USB_OTG=y
|
||||
CONFIG_USB_PHY=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
# CONFIG_USB_UHCI_HCD is not set
|
||||
CONFIG_USE_OF=y
|
||||
CONFIG_VECTORS_BASE=0xffff0000
|
||||
CONFIG_VFP=y
|
||||
CONFIG_VFPv3=y
|
||||
CONFIG_VMSPLIT_2G=y
|
||||
# CONFIG_VMSPLIT_3G is not set
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
CONFIG_ZBOOT_ROM_BSS=0
|
||||
CONFIG_ZBOOT_ROM_TEXT=0
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
/*
|
||||
* Copyright 2017 Gateworks Corporation
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-gw5904.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Gateworks Ventana i.MX6 DualLite/Solo GW5904";
|
||||
compatible = "gw,imx6dl-gw5904", "gw,ventana", "fsl,imx6dl";
|
||||
};
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
/*
|
||||
* Copyright 2017 Gateworks Corporation
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-gw5904.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Gateworks Ventana i.MX6 Dual/Quad GW5904";
|
||||
compatible = "gw,imx6q-gw5904", "gw,ventana", "fsl,imx6q";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1,629 +0,0 @@
|
|||
/*
|
||||
* Copyright 2017 Gateworks Corporation
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
/* these are used by bootloader for disabling nodes */
|
||||
aliases {
|
||||
led0 = &led0;
|
||||
led1 = &led1;
|
||||
led2 = &led2;
|
||||
usb0 = &usbh1;
|
||||
usb1 = &usbotg;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttymxc1,115200";
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm4 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <7>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_leds>;
|
||||
|
||||
led0: user1 {
|
||||
label = "user1";
|
||||
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
|
||||
default-state = "on";
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
led1: user2 {
|
||||
label = "user2";
|
||||
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led2: user3 {
|
||||
label = "user3";
|
||||
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
user_pb {
|
||||
label = "user_pb";
|
||||
|
||||
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <256>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
|
||||
pps {
|
||||
compatible = "pps-gpio";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pps>;
|
||||
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
reg_1p0v: regulator-1p0v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "1P0V";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usb_h1_vbus: regulator-usb-h1-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_h1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usb_otg_vbus: regulator-usb-otg-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
dsa {
|
||||
compatible = "marvell,dsa";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dsa,ethernet = <&fec>;
|
||||
dsa,mii-bus = <&mdio>;
|
||||
|
||||
switch@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0 0>; /* MDIO address 0, switch 0 in tree */
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "cpu";
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&clks {
|
||||
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
|
||||
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
|
||||
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
|
||||
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
|
||||
mdio: mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
eeprom1: eeprom@50 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
|
||||
eeprom2: eeprom@51 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x51>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
|
||||
eeprom3: eeprom@52 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x52>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
|
||||
eeprom4: eeprom@53 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x53>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
|
||||
gsc: gsc@20 {
|
||||
compatible = "gw,gsc";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <4 1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
/* GSC watchdog */
|
||||
watchdog {
|
||||
compatible = "gw,gsc_wdt";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Linux input events from GSC interrupt events */
|
||||
input {
|
||||
compatible = "gw,gsc_input";
|
||||
interrupt-parent = <&gsc>;
|
||||
interrupts = <0 1 2 5 7>;
|
||||
interrupt-names = "button", "key-erased", "eeprom-wp", "tamper", "button-held";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
gsc_gpio: pca9555@23 {
|
||||
compatible = "nxp,pca9555";
|
||||
reg = <0x23>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&gsc>;
|
||||
interrupts = <4>;
|
||||
};
|
||||
|
||||
gsc_hwmon: hwmon@29 {
|
||||
compatible = "gw,gsc_hwmon";
|
||||
reg = <0x29>;
|
||||
};
|
||||
|
||||
gsc_rtc: ds1672@68 {
|
||||
compatible = "dallas,ds1672";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
/* LSM9DS1 magnetic sensor */
|
||||
lsm9ds1-m@0x1c {
|
||||
compatible = "st,lsm9ds1-mag";
|
||||
reg = <0x1C>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_imu_mag>;
|
||||
gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; /* IRQ */
|
||||
rot-matrix = /bits/ 16 <(1) (0) (0)
|
||||
(0) (1) (0)
|
||||
(0) (0) (1)>;
|
||||
poll-interval = <100>;
|
||||
min-interval = <13>;
|
||||
fs-range = <0>;
|
||||
};
|
||||
|
||||
/* LSM9DS1 accelerometer/gyroscope sensor */
|
||||
lsm9ds1-ag@0x6a {
|
||||
compatible = "st,lsm9ds1-acc-gyr";
|
||||
reg = <0x6A>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_imu_acc>;
|
||||
gpios = <&gpio4 18 GPIO_ACTIVE_LOW>, /* INT1 */
|
||||
<&gpio4 19 GPIO_ACTIVE_LOW>; /* INT2 */
|
||||
rot-matrix = /bits/ 16 <(1) (0) (0)
|
||||
(0) (1) (0)
|
||||
(0) (0) (1)>;
|
||||
g-poll-interval = <100>;
|
||||
g-min-interval = <2>;
|
||||
g-fs-range = <0>;
|
||||
x-poll-interval = <100>;
|
||||
x-min-interval = <1>;
|
||||
x-fs-range = <0>;
|
||||
aa-filter-bw = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
|
||||
touchscreen: egalax_ts@04 {
|
||||
compatible = "eeti,egalax_ts";
|
||||
reg = <0x04>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
|
||||
wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
|
||||
lvds-channel@0 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: hsd100pxn1 {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
hback-porch = <220>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <21>;
|
||||
vfront-porch = <7>;
|
||||
hsync-len = <60>;
|
||||
vsync-len = <10>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie>;
|
||||
reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart5>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
vbus-supply = <®_usb_h1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
non-removable;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
keep-power-in-suspend;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx6qdl-gw5904 {
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_leds: gpioledsgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
|
||||
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
|
||||
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_imu_acc: gpioimxaccgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 /* INT1 */
|
||||
MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 /* INT2 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_imu_mag: gpioimxmaggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 /* IRQ */
|
||||
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* data ready */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie: pciegrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* PMIC_IRQ# */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pps: ppsgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm2: pwm2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm3: pwm3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm4: pwm4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
|
||||
MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart5: uart5grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
|
||||
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
|
||||
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
|
||||
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
|
||||
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
|
||||
MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
|
||||
MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
--- a/arch/arm/boot/dts/Makefile
|
||||
+++ b/arch/arm/boot/dts/Makefile
|
||||
@@ -339,6 +339,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
|
||||
imx6dl-gw551x.dtb \
|
||||
imx6dl-gw552x.dtb \
|
||||
imx6dl-gw553x.dtb \
|
||||
+ imx6dl-gw5904.dtb \
|
||||
imx6dl-hummingboard.dtb \
|
||||
imx6dl-nit6xlite.dtb \
|
||||
imx6dl-nitrogen6x.dtb \
|
||||
@@ -379,6 +380,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
|
||||
imx6q-gw551x.dtb \
|
||||
imx6q-gw552x.dtb \
|
||||
imx6q-gw553x.dtb \
|
||||
+ imx6q-gw5904.dtb \
|
||||
imx6q-h100.dtb \
|
||||
imx6q-hummingboard.dtb \
|
||||
imx6q-icore-rqs.dtb \
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
--- a/arch/arm/boot/dts/imx6dl-wandboard.dts
|
||||
+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts
|
||||
@@ -19,4 +19,8 @@
|
||||
memory {
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
+
|
||||
+ chosen {
|
||||
+ bootargs = "console=ttymxc0,115200";
|
||||
+ };
|
||||
};
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
The IMX6 PCIe host controller does not fire legacy interrupts when MSI is
|
||||
enabled. A patch is being worked on upstream to only enable MSI at runtime
|
||||
when needed, but until that is ready we will allow MSI to be disabled.
|
||||
|
||||
--- a/drivers/pci/host/Kconfig
|
||||
+++ b/drivers/pci/host/Kconfig
|
||||
@@ -51,7 +51,6 @@ config PCIE_DW_PLAT
|
||||
|
||||
config PCIE_DW
|
||||
bool
|
||||
- depends on PCI_MSI_IRQ_DOMAIN
|
||||
|
||||
config PCI_EXYNOS
|
||||
bool "Samsung Exynos PCIe controller"
|
||||
@@ -63,7 +62,6 @@ config PCI_EXYNOS
|
||||
config PCI_IMX6
|
||||
bool "Freescale i.MX6 PCIe controller"
|
||||
depends on SOC_IMX6Q
|
||||
- depends on PCI_MSI_IRQ_DOMAIN
|
||||
select PCIEPORTBUS
|
||||
select PCIE_DW
|
||||
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
Based on following upstream patch by Tim Harvey (Gateworks):
|
||||
|
||||
https://github.com/Gateworks/openwrt/commit/80a01b6582f94c4547f39d3a25e0a1e9b6eb9877
|
||||
|
||||
TX complete DMA messages are getting missed.
|
||||
This is also currently an issue in mainline.
|
||||
For now we will disable DMA in serial/imx.c.
|
||||
|
||||
This resolves an issue encountered with RS485 transmit.
|
||||
|
||||
--- a/drivers/tty/serial/imx.c
|
||||
+++ b/drivers/tty/serial/imx.c
|
||||
@@ -1268,10 +1268,6 @@ static int imx_startup(struct uart_port
|
||||
|
||||
writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
|
||||
|
||||
- /* Can we enable the DMA support? */
|
||||
- if (!uart_console(port) && !sport->dma_is_inited)
|
||||
- imx_uart_dma_init(sport);
|
||||
-
|
||||
spin_lock_irqsave(&sport->port.lock, flags);
|
||||
/* Reset fifo's and state machines */
|
||||
i = 100;
|
||||
Loading…
Reference in New Issue