mirror of https://github.com/hak5/openwrt-owl.git
Florian Fainelli
parent
c89e87d186
commit
0f0e42f28e
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@ -32,15 +32,30 @@
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#define MAC_BASE_ADDR ((priv->mac_base))
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#define CTRL_REG (MAC_BASE_ADDR)
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#define MII_BUSY 0x00000001
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#define MII_WRITE 0x00000002
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#define MII_BUSY (1 << 0)
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#define MII_WRITE (1 << 1)
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#define RX_ENABLE (1 << 2)
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#define TX_ENABLE (1 << 3)
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#define DEFER_CHECK (1 << 5)
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#define STRIP_PAD (1 << 8)
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#define DRTRY_DISABLE (1 << 10)
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#define FULL_DUPLEX (1 << 20)
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#define HBD_DISABLE (1 << 28)
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#define MAC_ADDR_HIGH_REG (MAC_BASE_ADDR + 0x04)
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#define MAC_ADDR_LOW_REG (MAC_BASE_ADDR + 0x08)
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#define MII_ADDR_REG (MAC_BASE_ADDR + 0x14)
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#define MII_ADDR_SHIFT (11)
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#define MII_REG_SHIFT (6)
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#define MII_DATA_REG (MAC_BASE_ADDR + 0x18)
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/* Link interrupt registers */
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#define LINK_INT_CSR (MAC_BASE_ADDR + 0xD0)
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#define LINK_INT_EN (1 << 0)
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#define LINK_PHY_ADDR_SHIFT (1)
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#define LINK_PHY_REG_SHIFT (6)
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#define LINK_BIT_UP_SHIFT (11)
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#define LINK_UP (1 << 16)
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#define LINK_INT_POLL_TIME (MAC_BASE_ADDR + 0xD4)
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#define LINK_POLL_MASK ((1 << 20) - 1)
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#define DMA_CHAN_WIDTH 32
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#define DMA_RX_CHAN 0
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@ -53,7 +68,11 @@
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#define RX_MAX_BYTES (RX_DMA_BASE + 0x04)
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#define RX_ACT_BYTES (RX_DMA_BASE + 0x08)
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#define RX_START_DMA (RX_DMA_BASE + 0x0C)
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#define RX_DMA_ENABLE (1 << 0)
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#define RX_DMA_RESET (1 << 1)
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#define RX_DMA_STATUS_FIFO (1 << 12)
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#define RX_DMA_ENH (RX_DMA_BASE + 0x14)
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#define RX_DMA_INT_ENABLE (1 << 1)
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/* Transmit DMA registers */
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#define TX_DMA_BASE ((priv->dma_base) + \
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@ -62,8 +81,19 @@
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#define TX_PKT_BYTES (TX_DMA_BASE + 0x04)
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#define TX_BYTES_SENT (TX_DMA_BASE + 0x08)
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#define TX_START_DMA (TX_DMA_BASE + 0x0C)
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#define TX_DMA_ENABLE (1 << 0)
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#define TX_DMA_START_FRAME (1 << 2)
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#define TX_DMA_END_FRAME (1 << 3)
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#define TX_DMA_PAD_DISABLE (1 << 8)
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#define TX_DMA_CRC_DISABLE (1 << 9)
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#define TX_DMA_FIFO_FULL (1 << 16)
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#define TX_DMA_FIFO_EMPTY (1 << 17)
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#define TX_DMA_STATUS_AVAIL (1 << 18)
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#define TX_DMA_RESET (1 << 24)
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#define TX_DMA_STATUS (TX_DMA_BASE + 0x10)
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#define TX_DMA_ENH (TX_DMA_BASE + 0x14)
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#define TX_DMA_ENH_ENABLE (1 << 0)
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#define TX_DMA_INT_FIFO (1 << 1)
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#define RX_ALLOC_SIZE SZ_2K
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#define MAX_ETH_FRAME_SIZE 1536
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@ -170,7 +200,7 @@ static int nuport_mac_mii_read(struct mii_bus *bus,
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if (ret)
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return ret;
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val |= (mii_id << 11) | (regnum << 6) | MII_BUSY;
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val |= (mii_id << MII_ADDR_SHIFT) | (regnum << MII_REG_SHIFT) | MII_BUSY;
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nuport_mac_writel(val, MII_ADDR_REG);
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ret = nuport_mac_mii_busy_wait(priv);
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if (ret)
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@ -191,7 +221,8 @@ static int nuport_mac_mii_write(struct mii_bus *bus, int mii_id,
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if (ret)
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return ret;
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val |= (mii_id << 11) | (regnum << 6) | MII_BUSY | MII_WRITE;
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val |= (mii_id << MII_ADDR_SHIFT) | (regnum << MII_REG_SHIFT);
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val |= MII_BUSY | MII_WRITE;
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nuport_mac_writel(value, MII_DATA_REG);
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nuport_mac_writel(val, MII_ADDR_REG);
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@ -212,7 +243,7 @@ static int nuport_mac_start_tx_dma(struct nuport_mac_priv *priv,
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while (timeout--) {
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reg = nuport_mac_readl(TX_START_DMA);
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if (!(reg & 0x01)) {
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if (!(reg & TX_DMA_ENABLE)) {
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netdev_dbg(priv->dev, "dma ready\n");
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break;
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}
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@ -226,11 +257,12 @@ static int nuport_mac_start_tx_dma(struct nuport_mac_priv *priv,
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skb->len, DMA_TO_DEVICE);
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/* enable enhanced mode */
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nuport_mac_writel(0x01, TX_DMA_ENH);
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nuport_mac_writel(TX_DMA_ENH_ENABLE, TX_DMA_ENH);
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nuport_mac_writel(p, TX_BUFFER_ADDR);
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nuport_mac_writel((skb->len) - 1, TX_PKT_BYTES);
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wmb();
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nuport_mac_writel(0x0D, TX_START_DMA);
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reg = TX_DMA_ENABLE | TX_DMA_START_FRAME | TX_DMA_END_FRAME;
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nuport_mac_writel(reg, TX_START_DMA);
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return 0;
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}
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@ -240,7 +272,7 @@ static void nuport_mac_reset_tx_dma(struct nuport_mac_priv *priv)
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u32 reg;
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reg = nuport_mac_readl(TX_START_DMA);
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reg |= (1 << 24);
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reg |= TX_DMA_RESET;
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nuport_mac_writel(reg, TX_START_DMA);
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}
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@ -253,7 +285,7 @@ static int nuport_mac_start_rx_dma(struct nuport_mac_priv *priv,
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while (timeout--) {
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reg = nuport_mac_readl(RX_START_DMA);
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if (!(reg & 0x01)) {
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if (!(reg & RX_DMA_ENABLE)) {
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netdev_dbg(priv->dev, "dma ready\n");
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break;
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}
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@ -268,7 +300,7 @@ static int nuport_mac_start_rx_dma(struct nuport_mac_priv *priv,
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nuport_mac_writel(p, RX_BUFFER_ADDR);
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wmb();
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nuport_mac_writel(0x01, RX_START_DMA);
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nuport_mac_writel(RX_DMA_ENABLE, RX_START_DMA);
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return 0;
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}
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@ -278,7 +310,7 @@ static void nuport_mac_reset_rx_dma(struct nuport_mac_priv *priv)
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u32 reg;
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reg = nuport_mac_readl(RX_START_DMA);
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reg |= (1 << 1);
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reg |= RX_DMA_RESET;
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nuport_mac_writel(reg, RX_START_DMA);
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}
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@ -288,7 +320,7 @@ static void nuport_mac_disable_rx_dma(struct nuport_mac_priv *priv)
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u32 reg;
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reg = nuport_mac_readl(RX_DMA_ENH);
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reg &= ~(1 << 1);
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reg &= ~RX_DMA_INT_ENABLE;
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nuport_mac_writel(reg, RX_DMA_ENH);
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}
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@ -297,7 +329,7 @@ static void nuport_mac_enable_rx_dma(struct nuport_mac_priv *priv)
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u32 reg;
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reg = nuport_mac_readl(RX_DMA_ENH);
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reg |= (1 << 1);
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reg |= RX_DMA_INT_ENABLE;
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nuport_mac_writel(reg, RX_DMA_ENH);
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}
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@ -363,9 +395,9 @@ static void nuport_mac_adjust_link(struct net_device *dev)
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if (phydev->link & (priv->old_duplex != phydev->duplex)) {
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reg = nuport_mac_readl(CTRL_REG);
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if (phydev->duplex == DUPLEX_FULL)
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reg |= (1 << 20);
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reg |= DUPLEX_FULL;
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else
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reg &= ~(1 << 20);
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reg &= ~DUPLEX_FULL;
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nuport_mac_writel(reg, CTRL_REG);
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status_changed = 1;
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@ -392,14 +424,14 @@ static irqreturn_t nuport_mac_link_interrupt(int irq, void *dev_id)
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u8 phy_addr;
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reg = nuport_mac_readl(LINK_INT_CSR);
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phy_addr = (reg >> 1) & 0x0f;
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phy_addr = (reg >> LINK_PHY_ADDR_SHIFT) & (PHY_MAX_ADDR - 1);
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if (phy_addr != priv->phydev->addr) {
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netdev_err(dev, "spurious PHY irq (phy: %d)\n", phy_addr);
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return IRQ_NONE;
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}
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priv->phydev->link = (reg & (1 << 16));
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priv->phydev->link = (reg & LINK_UP);
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nuport_mac_adjust_link(dev);
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return IRQ_HANDLED;
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@ -417,7 +449,7 @@ static irqreturn_t nuport_mac_tx_interrupt(int irq, void *dev_id)
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spin_lock_irqsave(&priv->lock, flags);
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/* clear status word available if ready */
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reg = nuport_mac_readl(TX_START_DMA);
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if (reg & (1 << 18)) {
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if (reg & TX_DMA_STATUS_AVAIL) {
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nuport_mac_writel(reg, TX_START_DMA);
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reg = nuport_mac_readl(TX_DMA_STATUS);
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@ -690,6 +722,7 @@ static int nuport_mac_open(struct net_device *dev)
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int ret;
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struct nuport_mac_priv *priv = netdev_priv(dev);
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unsigned long flags;
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u32 reg = 0;
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ret = clk_enable(priv->emac_clk);
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if (ret) {
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@ -698,7 +731,10 @@ static int nuport_mac_open(struct net_device *dev)
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}
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/* Set MAC into full duplex mode by default */
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nuport_mac_writel(0x1010052C, CTRL_REG);
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reg |= RX_ENABLE | TX_ENABLE;
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reg |= DEFER_CHECK | STRIP_PAD | DRTRY_DISABLE;
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reg |= FULL_DUPLEX | HBD_DISABLE;
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nuport_mac_writel(reg, CTRL_REG);
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/* set mac address in hardware in case it was not already */
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nuport_mac_change_mac_address(dev, dev->dev_addr);
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@ -712,10 +748,16 @@ static int nuport_mac_open(struct net_device *dev)
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phy_start(priv->phydev);
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/* Enable link interrupt monitoring */
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/* Enable link interrupt monitoring for our PHY address */
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reg = LINK_INT_EN | (priv->phydev->addr << LINK_PHY_ADDR_SHIFT);
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/* MII_BMSR register to be watched */
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reg |= (1 << LINK_PHY_REG_SHIFT);
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/* BMSR_STATUS to be watched in particular */
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reg |= (2 << LINK_BIT_UP_SHIFT);
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spin_lock_irqsave(&priv->lock, flags);
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nuport_mac_writel(0x1041 | (priv->phydev->addr << 1), LINK_INT_CSR);
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nuport_mac_writel(0xFFFFF, LINK_INT_POLL_TIME);
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nuport_mac_writel(reg, LINK_INT_CSR);
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nuport_mac_writel(LINK_POLL_MASK, LINK_INT_POLL_TIME);
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spin_unlock_irqrestore(&priv->lock, flags);
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ret = request_irq(priv->tx_irq, &nuport_mac_tx_interrupt,
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@ -771,8 +813,9 @@ static int nuport_mac_close(struct net_device *dev)
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netif_stop_queue(dev);
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free_irq(priv->link_irq, dev);
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nuport_mac_writel(0x00, LINK_INT_CSR);
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nuport_mac_writel(0x00, LINK_INT_POLL_TIME);
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/* disable PHY polling */
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nuport_mac_writel(0, LINK_INT_CSR);
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nuport_mac_writel(0, LINK_INT_POLL_TIME);
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phy_stop(priv->phydev);
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free_irq(priv->tx_irq, dev);
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