mirror of https://github.com/hak5/openwrt-owl.git
spi driver: remove bcm_rset usage
Since bcm636x platform embeds two spi master device, the attached patch removes static bcm_rset usage, replaced by "bs->regs" field for all I/O operation. Signed-off-by: Miguel Gaio <miguel.gaio@efixo.com> SVN-Revision: 24840owl
Florian Fainelli
parent
600b8aba3f
commit
093ebfe217
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@ -318,7 +318,7 @@
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#endif /* BCM63XX_REGS_H_ */
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--- /dev/null
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+++ b/drivers/spi/bcm63xx_spi.c
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@@ -0,0 +1,479 @@
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@@ -0,0 +1,501 @@
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+/*
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+ * Broadcom BCM63xx SPI controller support
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+ *
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@ -376,6 +376,30 @@
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+ struct platform_device *pdev;
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+};
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+
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+static inline u8 bcm_spi_readb(struct bcm63xx_hsspi *bs,
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+ unsigned int offset)
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+{
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+ return bcm_readw(bs->regs + bcm63xx_spireg(offset));
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+}
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+
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+static inline u16 bcm_spi_readw(struct bcm63xx_hsspi *bs,
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+ unsigned int offset)
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+{
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+ return bcm_readw(bs->regs + bcm63xx_spireg(offset));
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+}
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+
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+static inline void bcm_spi_writeb(struct bcm63xx_hsspi *bs,
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+ u8 value, unsigned int offset)
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+{
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+ bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
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+}
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+
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+static inline void bcm_spi_writew(struct bcm63xx_hsspi *bs,
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+ u16 value, unsigned int offset)
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+{
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+ bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
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+}
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+
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+static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
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+ struct spi_transfer *t)
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+{
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@ -428,7 +452,7 @@
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+ break;
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+ }
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+
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+ bcm_spi_writeb(clk_cfg, SPI_CLK_CFG);
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+ bcm_spi_writeb(bs, clk_cfg, SPI_CLK_CFG);
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+ dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n",
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+ div, hz, clk_cfg);
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+
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@ -441,7 +465,7 @@
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+static int bcm63xx_spi_setup(struct spi_device *spi)
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+{
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+ struct bcm63xx_spi *bs;
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+ int retval;
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+ int ret;
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+
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+ bs = spi_master_get_devdata(spi->master);
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+
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@ -457,11 +481,11 @@
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+ return -EINVAL;
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+ }
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+
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+ retval = bcm63xx_spi_setup_transfer(spi, NULL);
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+ if (retval < 0) {
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+ ret = bcm63xx_spi_setup_transfer(spi, NULL);
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+ if (ret < 0) {
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+ dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
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+ spi->mode & ~MODEBITS);
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+ return retval;
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+ return ret;
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+ }
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+
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+ dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
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@ -476,16 +500,16 @@
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+ u8 tail;
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+
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+ /* Fill the Tx FIFO with as many bytes as possible */
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+ tail = bcm_spi_readb(SPI_MSG_TAIL);
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+ tail = bcm_spi_readb(bs, SPI_MSG_TAIL);
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+
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+ while ((tail < bs->fifo_size) && (bs->remaining_bytes > 0)) {
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+ if (bs->tx_ptr)
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+ bcm_spi_writeb(*bs->tx_ptr++, SPI_MSG_DATA);
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+ bcm_spi_writeb(bs, *bs->tx_ptr++, SPI_MSG_DATA);
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+ else
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+ bcm_spi_writeb(0, SPI_MSG_DATA);
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+ bcm_spi_writeb(bs, 0, SPI_MSG_DATA);
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+
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+ bs->remaining_bytes--;
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+ tail = bcm_spi_readb(SPI_MSG_TAIL);
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+ tail = bcm_spi_readb(bs, SPI_MSG_TAIL);
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+ }
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+}
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+
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@ -510,7 +534,7 @@
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+
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+ /* Enable the command done interrupt which
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+ * we use to determine completion of a command */
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+ bcm_spi_writeb(SPI_INTR_CMD_DONE, SPI_INT_MASK);
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+ bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
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+
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+ /* Fill in the Message control register */
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+ msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
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@ -522,37 +546,37 @@
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+ else if (t->tx_buf)
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+ msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT);
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+
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+ bcm_spi_writew(msg_ctl, SPI_MSG_CTL);
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+ bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
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+
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+ /* Issue the transfer */
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+ cmd = SPI_CMD_START_IMMEDIATE;
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+ cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
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+ bcm_spi_writew(cmd, SPI_CMD);
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+ bcm_spi_writew(bs, cmd, SPI_CMD);
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+ wait_for_completion(&bs->done);
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+
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+ /* Disable the CMD_DONE interrupt */
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+ bcm_spi_writeb(0, SPI_INT_MASK);
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+ bcm_spi_writeb(bs, 0, SPI_INT_MASK);
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+
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+ return t->len - bs->remaining_bytes;
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+}
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+
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+static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *msg)
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+static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m)
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+{
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+ struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
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+ struct spi_transfer *xfer;
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+ struct spi_transfer *t;
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+ int ret = 0;
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+
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+ if (unlikely(list_empty(&msg->transfers)))
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+ if (unlikely(list_empty(&m->transfers)))
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+ return -EINVAL;
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+
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+ if (bs->stopping)
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+ return -ESHUTDOWN;
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+
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+ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
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+ ret += bcm63xx_txrx_bufs(spi, xfer);
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+ list_for_each_entry(t, &m->transfers, transfer_list) {
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+ ret += bcm63xx_txrx_bufs(spi, t);
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+ }
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+
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+ msg->complete(msg->context);
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+ m->complete(m->context);
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+
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+ return ret;
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+}
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@ -568,15 +592,15 @@
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+ u16 cmd;
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+
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+ /* Read interupts and clear them immediately */
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+ intr = bcm_spi_readb(SPI_INT_STATUS);
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+ bcm_spi_writeb(SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
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+ bcm_spi_writeb(0, SPI_INT_MASK);
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+ intr = bcm_spi_readb(bs, SPI_INT_STATUS);
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+ bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
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+ bcm_spi_writeb(bs, 0, SPI_INT_MASK);
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+
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+ /* A tansfer completed */
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+ if (intr & SPI_INTR_CMD_DONE) {
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+ u8 rx_tail;
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+
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+ rx_tail = bcm_spi_readb(SPI_RX_TAIL);
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+ rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
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+
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+ /* Read out all the data */
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+ if (rx_tail) {
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@ -584,7 +608,7 @@
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+ u8 i = 0;
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+
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+ for(i = 0; i < rx_tail; i++) {
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+ data = bcm_spi_readb(SPI_RX_DATA);
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+ data = bcm_spi_readb(bs, SPI_RX_DATA);
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+ if (bs->rx_ptr)
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+ *bs->rx_ptr++ = data;
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+ }
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@ -595,13 +619,13 @@
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+ bcm63xx_spi_fill_tx_fifo(bs);
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+
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+ /* Start the transfer */
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+ bcm_spi_writew(SPI_HD_W << SPI_MSG_TYPE_SHIFT,
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+ bcm_spi_writew(bs, SPI_HD_W << SPI_MSG_TYPE_SHIFT,
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+ SPI_MSG_CTL);
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+ cmd = bcm_spi_readw(SPI_CMD);
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+ cmd = bcm_spi_readw(bs, SPI_CMD);
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+ cmd |= SPI_CMD_START_IMMEDIATE;
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+ cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
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+ bcm_spi_writeb(SPI_INTR_CMD_DONE, SPI_INT_MASK);
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+ bcm_spi_writew(cmd, SPI_CMD);
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+ bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
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+ bcm_spi_writew(bs, cmd, SPI_CMD);
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+ } else {
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+ complete(&bs->done);
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+ }
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@ -636,14 +660,14 @@
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+ goto out;
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+ }
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+
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+ clk = clk_get(&pdev->dev, "spi");
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+ clk = clk_get(dev, "spi");
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+ if (IS_ERR(clk)) {
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+ dev_err(dev, "no clock for device\n");
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+ ret = -ENODEV;
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+ goto out;
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+ }
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+
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+ master = spi_alloc_master(&pdev->dev, sizeof(struct bcm63xx_spi));
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+ master = spi_alloc_master(dev, sizeof(*bs));
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+ if (!master) {
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+ dev_err(dev, "out of memory\n");
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+ ret = -ENOMEM;
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@ -656,8 +680,7 @@
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+ platform_set_drvdata(pdev, master);
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+ bs->pdev = pdev;
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+
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+ if (!request_mem_region(r->start,
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+ r->end - r->start, PFX)) {
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+ if (!request_mem_region(r->start, r->end - r->start, PFX)) {
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+ dev_err(dev, "iomem request failed\n");
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+ ret = -ENXIO;
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+ goto out_put_master;
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@ -673,8 +696,7 @@
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+ bs->clk = clk;
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+ bs->fifo_size = pdata->fifo_size;
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+
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+ ret = request_irq(irq, bcm63xx_spi_interrupt, 0,
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+ pdev->name, master);
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+ ret = request_irq(irq, bcm63xx_spi_interrupt, 0, pdev->name, master);
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+ if (ret) {
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+ dev_err(dev, "unable to request irq\n");
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+ goto out_unmap;
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@ -690,7 +712,7 @@
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+
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+ /* Initialize hardware */
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+ clk_enable(bs->clk);
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+ bcm_spi_writeb(SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
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+ bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
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+
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+ /* register and we are done */
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+ ret = spi_register_master(master);
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@ -702,7 +724,7 @@
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+ dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n",
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+ r->start, irq, bs->fifo_size, DRV_VER);
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+
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+ return ret;
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+ return 0;
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+
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+out_reset_hw:
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+ clk_disable(clk);
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@ -724,7 +746,7 @@
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+ struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+
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+ /* reset spi block */
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+ bcm_spi_writeb(0, SPI_INT_MASK);
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+ bcm_spi_writeb(bs, 0, SPI_INT_MASK);
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+ spin_lock(&bs->lock);
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+ bs->stopping = 1;
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+
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@ -825,7 +847,7 @@
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spi_s3c24xx_hw-y := spi_s3c24xx.o
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
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@@ -0,0 +1,136 @@
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@@ -0,0 +1,126 @@
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+#ifndef BCM63XX_DEV_SPI_H
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+#define BCM63XX_DEV_SPI_H
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+
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@ -951,16 +973,6 @@
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+ return 0;
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+}
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+
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+/*
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+ * helpers for the SPI register sets
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+ */
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+#define bcm_spi_readb(o) bcm_rset_readb(RSET_SPI, bcm63xx_spireg(o))
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+#define bcm_spi_readw(o) bcm_rset_readw(RSET_SPI, bcm63xx_spireg(o))
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+#define bcm_spi_readl(o) bcm_rset_readl(RSET_SPI, bcm63xx_spireg(o))
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+#define bcm_spi_writeb(v,o) bcm_rset_writeb(RSET_SPI, (v), bcm63xx_spireg(o))
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+#define bcm_spi_writew(v,o) bcm_rset_writew(RSET_SPI, (v), bcm63xx_spireg(o))
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+#define bcm_spi_writel(v,o) bcm_rset_writel(RSET_SPI, (v), bcm63xx_spireg(o))
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+
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+#endif /* BCM63XX_DEV_SPI_H */
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--- a/arch/mips/bcm63xx/Makefile
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+++ b/arch/mips/bcm63xx/Makefile
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