hak5
/
openwrt-owl
mirror of https://github.com/hak5/openwrt-owl.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

ramips: remove interrupt coalescing, it is unnecessary with napi polling and could reduce throughput 

Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 43952
owl
Felix Fietkau 2015-01-13 00:34:38 +00:00
parent adaac86c7f
commit 05d4b8c79b
7 changed files with 40 additions and 78 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

50
target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_ethtool.c
View File

@ -140,54 +140,6 @@ static void fe_get_ringparam(struct net_device *dev,
ring->tx_pending = NUM_DMA_DESC;
}
static int fe_get_coalesce(struct net_device *dev,
struct ethtool_coalesce *coal)
{
u32 delay_cfg = fe_reg_r32(FE_REG_DLY_INT_CFG);
coal->rx_coalesce_usecs = (delay_cfg & 0xff) * FE_DELAY_TIME;
coal->rx_max_coalesced_frames = ((delay_cfg >> 8) & 0x7f);
coal->use_adaptive_rx_coalesce = (delay_cfg >> 15) & 0x1;
coal->tx_coalesce_usecs = ((delay_cfg >> 16 )& 0xff) * FE_DELAY_TIME;
coal->tx_max_coalesced_frames = ((delay_cfg >> 24) & 0x7f);
coal->use_adaptive_tx_coalesce = (delay_cfg >> 31) & 0x1;
return 0;
}
static int fe_set_coalesce(struct net_device *dev,
struct ethtool_coalesce *coal)
{
u32 delay_cfg;
u32 rx_usecs, tx_usecs;
u32 rx_frames, tx_frames;
if (!coal->use_adaptive_rx_coalesce || !coal->use_adaptive_tx_coalesce)
return -EINVAL;
rx_usecs = DIV_ROUND_UP(coal->rx_coalesce_usecs, FE_DELAY_TIME);
rx_frames = coal->rx_max_coalesced_frames;
tx_usecs = DIV_ROUND_UP(coal->tx_coalesce_usecs, FE_DELAY_TIME);
tx_frames = coal->tx_max_coalesced_frames;
if (((tx_usecs == 0) && (tx_frames ==0)) ||
((rx_usecs == 0) && (rx_frames ==0)))
return -EINVAL;
if (rx_usecs > 0xff) rx_usecs = 0xff;
if (rx_frames > 0x7f) rx_frames = 0x7f;
if (tx_usecs > 0xff) tx_usecs = 0xff;
if (tx_frames > 0x7f) tx_frames = 0x7f;
delay_cfg = ((((FE_DELAY_EN_INT | tx_frames) << 8) | tx_usecs) << 16) |
(((FE_DELAY_EN_INT | rx_frames) << 8) | rx_usecs);
fe_reg_w32(delay_cfg, FE_REG_DLY_INT_CFG);
return 0;
}
static void fe_get_strings(struct net_device *dev, u32 stringset, u8 *data)
{
switch (stringset) {
@ -243,8 +195,6 @@ static struct ethtool_ops fe_ethtool_ops = {
.nway_reset = fe_nway_reset,
.get_link = fe_get_link,
.get_ringparam = fe_get_ringparam,
.get_coalesce = fe_get_coalesce,
.set_coalesce = fe_set_coalesce,
};
void fe_set_ethtool_ops(struct net_device *netdev)

26
target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.c
View File

@ -842,8 +842,8 @@ static int fe_poll(struct napi_struct *napi, int budget)
u32 tx_intr, rx_intr;
status = fe_reg_r32(FE_REG_FE_INT_STATUS);
tx_intr = priv->soc->tx_dly_int;
rx_intr = priv->soc->rx_dly_int;
tx_intr = priv->soc->tx_int;
rx_intr = priv->soc->rx_int;
tx_done = rx_done = 0;
poll_again:
@ -907,16 +907,16 @@ static void fe_tx_timeout(struct net_device *dev)
static irqreturn_t fe_handle_irq(int irq, void *dev)
{
struct fe_priv *priv = netdev_priv(dev);
u32 status, dly_int;
u32 status, int_mask;
status = fe_reg_r32(FE_REG_FE_INT_STATUS);
if (unlikely(!status))
return IRQ_NONE;
dly_int = (priv->soc->rx_dly_int | priv->soc->tx_dly_int);
if (likely(status & dly_int)) {
fe_int_disable(dly_int);
int_mask = (priv->soc->rx_int | priv->soc->tx_int);
if (likely(status & int_mask)) {
fe_int_disable(int_mask);
napi_schedule(&priv->rx_napi);
} else {
fe_reg_w32(status, FE_REG_FE_INT_STATUS);
@ -929,11 +929,11 @@ static irqreturn_t fe_handle_irq(int irq, void *dev)
static void fe_poll_controller(struct net_device *dev)
{
struct fe_priv *priv = netdev_priv(dev);
u32 dly_int = priv->soc->tx_dly_int | priv->soc->rx_dly_int;
u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
fe_int_disable(dly_int);
fe_int_disable(int_mask);
fe_handle_irq(dev->irq, dev);
fe_int_enable(dly_int);
fe_int_enable(int_mask);
}
#endif
@ -1018,9 +1018,7 @@ static int fe_hw_init(struct net_device *dev)
else
fe_hw_set_macaddr(priv, dev->dev_addr);
fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
/* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
@ -1068,7 +1066,7 @@ static int fe_open(struct net_device *dev)
netif_carrier_on(dev);
netif_start_queue(dev);
fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
return 0;
@ -1083,7 +1081,7 @@ static int fe_stop(struct net_device *dev)
unsigned long flags;
int i;
fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
netif_tx_disable(dev);

18
target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.h
View File

@ -79,8 +79,22 @@ enum fe_reg {
#define FE_TX_DLY_INT BIT(1)
#define FE_RX_DLY_INT BIT(0)
#define FE_RX_DONE_INT FE_RX_DONE_INT0
#define FE_TX_DONE_INT (FE_TX_DONE_INT0 | FE_TX_DONE_INT1 | \
FE_TX_DONE_INT2 | FE_TX_DONE_INT3)
#define RT5350_RX_DLY_INT BIT(30)
#define RT5350_TX_DLY_INT BIT(28)
#define RT5350_RX_DONE_INT1 BIT(17)
#define RT5350_RX_DONE_INT0 BIT(16)
#define RT5350_TX_DONE_INT3 BIT(3)
#define RT5350_TX_DONE_INT2 BIT(2)
#define RT5350_TX_DONE_INT1 BIT(1)
#define RT5350_TX_DONE_INT0 BIT(0)
#define RT5350_RX_DONE_INT (RT5350_RX_DONE_INT0 | RT5350_RX_DONE_INT1)
#define RT5350_TX_DONE_INT (RT5350_TX_DONE_INT0 | RT5350_TX_DONE_INT1 | \
RT5350_TX_DONE_INT2 | RT5350_TX_DONE_INT3)
/* registers */
#define FE_FE_OFFSET 0x0000
@ -367,8 +381,8 @@ struct fe_soc_data
void *swpriv;
u32 pdma_glo_cfg;
u32 rx_dly_int;
u32 tx_dly_int;
u32 rx_int;
u32 tx_int;
u32 checksum_bit;
u32 tx_udf_bit;
};

8
target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
View File

@ -225,8 +225,8 @@ static struct fe_soc_data mt7620_data = {
.port_init = mt7620_port_init,
.reg_table = mt7620_reg_table,
.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
.rx_dly_int = RT5350_RX_DLY_INT,
.tx_dly_int = RT5350_TX_DLY_INT,
.rx_int = RT5350_RX_DONE_INT,
.tx_int = RT5350_TX_DONE_INT,
.checksum_bit = MT7620_L4_VALID,
.tx_udf_bit = MT7620_TX_DMA_UDF,
.has_carrier = mt7620a_has_carrier,
@ -247,8 +247,8 @@ static struct fe_soc_data mt7621_data = {
.switch_config = mt7621_gsw_config,
.reg_table = mt7621_reg_table,
.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
.rx_dly_int = RT5350_RX_DLY_INT,
.tx_dly_int = RT5350_TX_DLY_INT,
.rx_int = RT5350_RX_DONE_INT,
.tx_int = RT5350_TX_DONE_INT,
.checksum_bit = MT7621_L4_VALID,
.tx_udf_bit = MT7621_TX_DMA_UDF,
.has_carrier = mt7620a_has_carrier,

4
target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt2880.c
View File

@ -65,8 +65,8 @@ struct fe_soc_data rt2880_data = {
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
.checksum_bit = RX_DMA_L4VALID,
.tx_udf_bit = TX_DMA_UDF,
.rx_dly_int = FE_RX_DLY_INT,
.tx_dly_int = FE_TX_DLY_INT,
.rx_int = FE_RX_DONE_INT,
.tx_int = FE_TX_DONE_INT,
.mdio_read = rt2880_mdio_read,
.mdio_write = rt2880_mdio_write,
.mdio_adjust_link = rt2880_mdio_link_adjust,

8
target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt305x.c
View File

@ -133,8 +133,8 @@ static struct fe_soc_data rt3050_data = {
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
.checksum_bit = RX_DMA_L4VALID,
.tx_udf_bit = TX_DMA_UDF,
.rx_dly_int = FE_RX_DLY_INT,
.tx_dly_int = FE_TX_DLY_INT,
.rx_int = FE_RX_DONE_INT,
.tx_int = FE_TX_DONE_INT,
};
static struct fe_soc_data rt5350_data = {
@ -148,8 +148,8 @@ static struct fe_soc_data rt5350_data = {
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
.checksum_bit = RX_DMA_L4VALID,
.tx_udf_bit = TX_DMA_UDF,
.rx_dly_int = RT5350_RX_DLY_INT,
.tx_dly_int = RT5350_TX_DLY_INT,
.rx_int = RT5350_RX_DONE_INT,
.tx_int = RT5350_TX_DONE_INT,
};
const struct of_device_id of_fe_match[] = {

4
target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt3883.c
View File

@ -69,8 +69,8 @@ static struct fe_soc_data rt3883_data = {
.reset_fe = rt3883_fe_reset,
.fwd_config = rt3883_fwd_config,
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
.rx_dly_int = FE_RX_DLY_INT,
.tx_dly_int = FE_TX_DLY_INT,
.rx_int = FE_RX_DONE_INT,
.tx_int = FE_TX_DONE_INT,
.checksum_bit = RX_DMA_L4VALID,
.tx_udf_bit = TX_DMA_UDF,
.mdio_read = rt2880_mdio_read,