mirror of https://github.com/hak5/openwrt-owl.git
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/*
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* Ralink RT288x specific CPU feature overrides
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*
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* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* This file was derived from: include/asm-mips/cpu-features.h
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* Copyright (C) 2003, 2004 Ralf Baechle
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* Copyright (C) 2004 Maciej W. Rozycki
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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*/
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#ifndef __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
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#define __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
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#define cpu_has_tlb 1
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#define cpu_has_4kex 1
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#define cpu_has_3k_cache 0
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#define cpu_has_4k_cache 1
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#define cpu_has_tx39_cache 0
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#define cpu_has_sb1_cache 0
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#define cpu_has_fpu 0
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#define cpu_has_32fpr 0
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#define cpu_has_counter 1
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#define cpu_has_watch 1
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#define cpu_has_divec 1
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#define cpu_has_prefetch 1
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#define cpu_has_ejtag 1
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#define cpu_has_llsc 1
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#define cpu_has_mips16 1
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#define cpu_has_mdmx 0
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#define cpu_has_mips3d 0
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#define cpu_has_smartmips 0
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#define cpu_has_mips32r1 1
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#define cpu_has_mips32r2 1
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#define cpu_has_mips64r1 0
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#define cpu_has_mips64r2 0
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#define cpu_has_dsp 0
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#define cpu_has_mipsmt 0
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#define cpu_has_64bits 0
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#define cpu_has_64bit_zero_reg 0
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#define cpu_has_64bit_gp_regs 0
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#define cpu_has_64bit_addresses 0
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#define cpu_dcache_line_size() 16
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#define cpu_icache_line_size() 16
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#endif /* __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H */
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@ -1,5 +1,5 @@
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/*
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* Ralink RT288x/RT305x specific CPU feature overrides
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* Ralink RT305x specific CPU feature overrides
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*
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* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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@ -47,3 +47,12 @@
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source "arch/mips/sgi-ip27/Kconfig"
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source "arch/mips/sibyte/Kconfig"
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source "arch/mips/txx9/Kconfig"
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@@ -988,7 +992,7 @@
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config MIPS_L1_CACHE_SHIFT
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int
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- default "4" if MACH_DECSTATION || MIKROTIK_RB532
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+ default "4" if MACH_DECSTATION || MIKROTIK_RB532 || RALINK_RT288X
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default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
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default "4" if PMC_MSP4200_EVAL
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default "5"
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