mirror of https://github.com/hak5/openwrt-owl.git
85 lines
2.9 KiB
Diff
85 lines
2.9 KiB
Diff
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From aaf22ab4e916afa68a2e1aed4e913b76cbd58276 Mon Sep 17 00:00:00 2001
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From: Ray Jui <rjui@broadcom.com>
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Date: Tue, 15 Sep 2015 17:39:19 -0700
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Subject: [PATCH 144/147] PCI: iproc: Improve link detection logic
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Improve the link detection logic by explicitly querying the link status
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register to ensure link is active.
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Also force class to PCI_CLASS_BRIDGE_PCI (0x0604) through the host
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configuration space register.
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Signed-off-by: Ray Jui <rjui@broadcom.com>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Reviewed-by: Anup Patel <anup.patel@broadcom.com>
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Reviewed-by: Scott Branden <sbranden@broadcom.com>
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---
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drivers/pci/host/pcie-iproc.c | 29 +++++++++++++++++++++++------
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1 file changed, 23 insertions(+), 6 deletions(-)
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--- a/drivers/pci/host/pcie-iproc.c
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+++ b/drivers/pci/host/pcie-iproc.c
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@@ -60,6 +60,12 @@
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#define SYS_RC_INTX_EN 0x330
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#define SYS_RC_INTX_MASK 0xf
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+#define PCIE_LINK_STATUS_OFFSET 0xf0c
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+#define PCIE_PHYLINKUP_SHIFT 3
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+#define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT)
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+#define PCIE_DL_ACTIVE_SHIFT 2
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+#define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT)
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+
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static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
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{
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struct iproc_pcie *pcie;
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@@ -138,9 +144,15 @@ static void iproc_pcie_reset(struct ipro
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static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus)
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{
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u8 hdr_type;
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- u32 link_ctrl;
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+ u32 link_ctrl, class, val;
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u16 pos, link_status;
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- int link_is_active = 0;
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+ bool link_is_active = false;
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+
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+ val = readl(pcie->base + PCIE_LINK_STATUS_OFFSET);
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+ if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) {
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+ dev_err(pcie->dev, "PHY or data link is INACTIVE!\n");
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+ return -ENODEV;
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+ }
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/* make sure we are not in EP mode */
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pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type);
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@@ -150,14 +162,19 @@ static int iproc_pcie_check_link(struct
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}
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/* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
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- pci_bus_write_config_word(bus, 0, PCI_CLASS_DEVICE,
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- PCI_CLASS_BRIDGE_PCI);
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+#define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c
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+#define PCI_CLASS_BRIDGE_MASK 0xffff00
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+#define PCI_CLASS_BRIDGE_SHIFT 8
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+ pci_bus_read_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, &class);
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+ class &= ~PCI_CLASS_BRIDGE_MASK;
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+ class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);
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+ pci_bus_write_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, class);
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/* check link status to see if link is active */
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pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
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pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status);
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if (link_status & PCI_EXP_LNKSTA_NLW)
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- link_is_active = 1;
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+ link_is_active = true;
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if (!link_is_active) {
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/* try GEN 1 link speed */
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@@ -181,7 +198,7 @@ static int iproc_pcie_check_link(struct
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pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA,
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&link_status);
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if (link_status & PCI_EXP_LNKSTA_NLW)
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- link_is_active = 1;
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+ link_is_active = true;
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}
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}
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