mirror of https://github.com/hak5/openwrt-owl.git
109 lines
3.6 KiB
Diff
109 lines
3.6 KiB
Diff
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From bd428b9b18c2dffb8c9d737e99adfd145822e502 Mon Sep 17 00:00:00 2001
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From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Date: Thu, 14 Nov 2013 18:25:28 -0300
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Subject: [PATCH 142/203] mtd: nand: pxa3xx: Add bad block handling
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Add support for flash-based bad block table using Marvell's
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custom in-flash bad block table layout. The support is enabled
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a 'flash_bbt' platform data or device tree parameter.
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Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Tested-by: Daniel Mack <zonque@gmail.com>
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Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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---
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.../devicetree/bindings/mtd/pxa3xx-nand.txt | 2 ++
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drivers/mtd/nand/pxa3xx_nand.c | 37 ++++++++++++++++++++++
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include/linux/platform_data/mtd-nand-pxa3xx.h | 3 ++
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3 files changed, 42 insertions(+)
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--- a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
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+++ b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
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@@ -13,6 +13,8 @@ Optional properties:
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- marvell,nand-keep-config: Set to keep the NAND controller config as set
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by the bootloader
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- num-cs: Number of chipselect lines to usw
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+ - nand-on-flash-bbt: boolean to enable on flash bbt option if
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+ not present false
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Example:
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--- a/drivers/mtd/nand/pxa3xx_nand.c
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+++ b/drivers/mtd/nand/pxa3xx_nand.c
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@@ -26,6 +26,7 @@
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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+#include <linux/of_mtd.h>
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#if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP)
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#define ARCH_HAS_DMA
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@@ -241,6 +242,29 @@ static struct pxa3xx_nand_flash builtin_
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{ "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] },
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};
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+static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
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+static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
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+
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+static struct nand_bbt_descr bbt_main_descr = {
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+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
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+ | NAND_BBT_2BIT | NAND_BBT_VERSION,
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+ .offs = 8,
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+ .len = 6,
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+ .veroffs = 14,
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+ .maxblocks = 8, /* Last 8 blocks in each chip */
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+ .pattern = bbt_pattern
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+};
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+
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+static struct nand_bbt_descr bbt_mirror_descr = {
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+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
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+ | NAND_BBT_2BIT | NAND_BBT_VERSION,
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+ .offs = 8,
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+ .len = 6,
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+ .veroffs = 14,
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+ .maxblocks = 8, /* Last 8 blocks in each chip */
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+ .pattern = bbt_mirror_pattern
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+};
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+
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/* Define a default flash type setting serve as flash detecting only */
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#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
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@@ -1126,6 +1150,18 @@ KEEP_CONFIG:
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if (nand_scan_ident(mtd, 1, def))
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return -ENODEV;
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+
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+ if (pdata->flash_bbt) {
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+ /*
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+ * We'll use a bad block table stored in-flash and don't
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+ * allow writing the bad block marker to the flash.
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+ */
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+ chip->bbt_options |= NAND_BBT_USE_FLASH |
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+ NAND_BBT_NO_OOB_BBM;
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+ chip->bbt_td = &bbt_main_descr;
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+ chip->bbt_md = &bbt_mirror_descr;
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+ }
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+
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/* calculate addressing information */
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if (mtd->writesize >= 2048)
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host->col_addr_cycles = 2;
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@@ -1320,6 +1356,7 @@ static int pxa3xx_nand_probe_dt(struct p
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if (of_get_property(np, "marvell,nand-keep-config", NULL))
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pdata->keep_config = 1;
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of_property_read_u32(np, "num-cs", &pdata->num_cs);
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+ pdata->flash_bbt = of_get_nand_on_flash_bbt(np);
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pdev->dev.platform_data = pdata;
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--- a/include/linux/platform_data/mtd-nand-pxa3xx.h
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+++ b/include/linux/platform_data/mtd-nand-pxa3xx.h
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@@ -55,6 +55,9 @@ struct pxa3xx_nand_platform_data {
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/* indicate how many chip selects will be used */
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int num_cs;
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+ /* use an flash-based bad block table */
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+ bool flash_bbt;
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+
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const struct mtd_partition *parts[NUM_CHIP_SELECT];
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unsigned int nr_parts[NUM_CHIP_SELECT];
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