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openwrt-owl/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock...

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ar71xx: fix ar724x clock calculation According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz input clock as the REF_CLK instead of 5MHz. The correct CPU PLL calculation procedure is as follows: CPU_PLL = (DIV * REF_CLK) / REF_DIV / 2. This patch is compatible with the current calculation procedure with default DIV and REF_DIV values. Test on both AR7240, AR7241 and AR7242. Signed-off-by: Weijie Gao <hackpascal@gmail.com> SVN-Revision: 46856
2015-09-11 16:32:45 +00:00
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -25,7 +25,7 @@
#include "common.h"
#define AR71XX_BASE_FREQ 40000000
-#define AR724X_BASE_FREQ 5000000
+#define AR724X_BASE_FREQ 40000000
#define AR913X_BASE_FREQ 5000000
struct clk {
kernel: update 4.1 to 4.1.10 Fixes a regression on spi flash devices (upstream commit 1583eaece6fa). Changelogs: * https://www.kernel.org/pub/linux/kernel/v4.x/ChangeLog-4.1.7 * https://www.kernel.org/pub/linux/kernel/v4.x/ChangeLog-4.1.8 * https://www.kernel.org/pub/linux/kernel/v4.x/ChangeLog-4.1.9 * https://www.kernel.org/pub/linux/kernel/v4.x/ChangeLog-4.1.10 096-ipv4-off-by-one-in-continuation-handling-in-proc-net.patch was applied upstream and dropped. Signed-off-by: Mathias Kresin <openwrt@kresin.me> [update from 4.1.9 to 4.1.10] Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> SVN-Revision: 47104
2015-10-04 11:34:39 +00:00
@@ -99,8 +99,8 @@ static void __init ar724x_clocks_init(vo
ar71xx: fix ar724x clock calculation According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz input clock as the REF_CLK instead of 5MHz. The correct CPU PLL calculation procedure is as follows: CPU_PLL = (DIV * REF_CLK) / REF_DIV / 2. This patch is compatible with the current calculation procedure with default DIV and REF_DIV values. Test on both AR7240, AR7241 and AR7242. Signed-off-by: Weijie Gao <hackpascal@gmail.com> SVN-Revision: 46856
2015-09-11 16:32:45 +00:00
div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
freq = div * ref_rate;
- div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
- freq *= div;
+ div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
+ freq /= div;
cpu_rate = freq;