2012-10-25 21:16:51 +00:00
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From eef84812bc7ffd590da6ad6b83bfeebaa43a7055 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Thu, 5 Jul 2012 21:19:20 +0200
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Subject: [PATCH 58/84] MIPS: BCM63XX: enable SPI controller for BCM6362
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---
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arch/mips/bcm63xx/clk.c | 2 ++
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arch/mips/bcm63xx/dev-spi.c | 11 ++++++++++-
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.../include/asm/mach-bcm63xx/bcm63xx_dev_spi.h | 3 +++
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 16 ++++++++++++++++
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4 files changed, 31 insertions(+), 1 deletions(-)
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--- a/arch/mips/bcm63xx/clk.c
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+++ b/arch/mips/bcm63xx/clk.c
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@@ -199,6 +199,8 @@ static void spi_set(struct clk *clk, int
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mask = CKCTL_6348_SPI_EN;
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else if (BCMCPU_IS_6358())
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mask = CKCTL_6358_SPI_EN;
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+ else if (BCMCPU_IS_6362())
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+ mask = CKCTL_6362_SPI_EN;
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else
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/* BCMCPU_IS_6368 */
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mask = CKCTL_6368_SPI_EN;
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--- a/arch/mips/bcm63xx/dev-spi.c
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+++ b/arch/mips/bcm63xx/dev-spi.c
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@@ -34,6 +34,10 @@ static const unsigned long bcm6358_regs_
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__GEN_SPI_REGS_TABLE(6358)
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};
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+static const unsigned long bcm6362_regs_spi[] = {
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+ __GEN_SPI_REGS_TABLE(6362)
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+};
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+
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static const unsigned long bcm6368_regs_spi[] = {
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__GEN_SPI_REGS_TABLE(6368)
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};
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@@ -49,6 +53,8 @@ static __init void bcm63xx_spi_regs_init
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bcm63xx_regs_spi = bcm6348_regs_spi;
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if (BCMCPU_IS_6358())
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bcm63xx_regs_spi = bcm6358_regs_spi;
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+ if (BCMCPU_IS_6362())
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+ bcm63xx_regs_spi = bcm6362_regs_spi;
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if (BCMCPU_IS_6368())
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bcm63xx_regs_spi = bcm6368_regs_spi;
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}
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@@ -99,6 +105,9 @@ int __init bcm63xx_spi_register(void)
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/* Set bus frequency */
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spi_pdata.speed_hz = clk_get_rate(periph_clk);
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+ if (BCMCPU_IS_6362())
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+ spi_pdata.bus_num = 1;
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+
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spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
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spi_resources[0].end = spi_resources[0].start;
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spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
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@@ -110,7 +119,7 @@ int __init bcm63xx_spi_register(void)
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spi_pdata.msg_ctl_width = SPI_6338_MSG_CTL_WIDTH;
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}
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- if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
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+ if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
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spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
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spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
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spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
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@@ -81,6 +81,9 @@ static inline unsigned long bcm63xx_spir
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#ifdef CONFIG_BCM63XX_CPU_6358
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__GEN_SPI_RSET(6358)
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#endif
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+#ifdef CONFIG_BCM63XX_CPU_6362
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+ __GEN_SPI_RSET(6362)
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+#endif
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#ifdef CONFIG_BCM63XX_CPU_6368
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__GEN_SPI_RSET(6368)
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#endif
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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2012-11-10 19:59:16 +00:00
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@@ -1223,6 +1223,22 @@
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2012-10-25 21:16:51 +00:00
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#define SPI_6358_MSG_TAIL 0x709
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#define SPI_6358_RX_TAIL 0x70B
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+/* BCM 6362 SPI core */
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+#define SPI_6362_MSG_CTL 0x00 /* 16-bits register */
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+#define SPI_6362_MSG_DATA 0x02
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+#define SPI_6362_MSG_DATA_SIZE 0x21e
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+#define SPI_6362_RX_DATA 0x400
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+#define SPI_6362_RX_DATA_SIZE 0x220
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+#define SPI_6362_CMD 0x700 /* 16-bits register */
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+#define SPI_6362_INT_STATUS 0x702
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+#define SPI_6362_INT_MASK_ST 0x703
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+#define SPI_6362_INT_MASK 0x704
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+#define SPI_6362_ST 0x705
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+#define SPI_6362_CLK_CFG 0x706
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+#define SPI_6362_FILL_BYTE 0x707
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+#define SPI_6362_MSG_TAIL 0x709
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+#define SPI_6362_RX_TAIL 0x70B
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+
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/* BCM 6358 SPI core */
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#define SPI_6368_MSG_CTL 0x00 /* 16-bits register */
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#define SPI_6368_MSG_CTL_WIDTH 16
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