mirror of https://github.com/hak5/openwrt-owl.git
53 lines
1.8 KiB
Diff
53 lines
1.8 KiB
Diff
|
--- a/drivers/bcma/Kconfig
|
||
|
|
+++ b/drivers/bcma/Kconfig
|
||
|
|
@@ -76,9 +76,16 @@ config BCMA_PFLASH
|
||
|
|
default y
|
||
|
|
|
||
|
|
config BCMA_SFLASH
|
||
|
|
- bool
|
||
|
|
- depends on BCMA_DRIVER_MIPS
|
||
|
|
+ bool "ChipCommon-attached serial flash support"
|
||
|
|
+ depends on BCMA_HOST_SOC
|
||
|
|
default y
|
||
|
|
+ help
|
||
|
|
+ Some cheap devices have serial flash connected to the ChipCommon
|
||
|
|
+ instead of independent SPI controller. It requires using a separated
|
||
|
|
+ driver that implements ChipCommon specific interface communication.
|
||
|
|
+
|
||
|
|
+ Enabling this symbol will let bcma recognize serial flash and register
|
||
|
|
+ it as platform device.
|
||
|
|
|
||
|
|
config BCMA_NFLASH
|
||
|
|
bool
|
||
|
|
--- a/drivers/bcma/driver_chipcommon_b.c
|
||
|
|
+++ b/drivers/bcma/driver_chipcommon_b.c
|
||
|
|
@@ -33,11 +33,12 @@ static bool bcma_wait_reg(struct bcma_bu
|
||
|
|
void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value)
|
||
|
|
{
|
||
|
|
struct bcma_bus *bus = ccb->core->bus;
|
||
|
|
+ void __iomem *mii = ccb->mii;
|
||
|
|
|
||
|
|
- writel(offset, ccb->mii + 0x00);
|
||
|
|
- bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
|
||
|
|
- writel(value, ccb->mii + 0x04);
|
||
|
|
- bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
|
||
|
|
+ writel(offset, mii + BCMA_CCB_MII_MNG_CTL);
|
||
|
|
+ bcma_wait_reg(bus, mii + BCMA_CCB_MII_MNG_CTL, 0x0100, 0x0000, 100);
|
||
|
|
+ writel(value, mii + BCMA_CCB_MII_MNG_CMD_DATA);
|
||
|
|
+ bcma_wait_reg(bus, mii + BCMA_CCB_MII_MNG_CTL, 0x0100, 0x0000, 100);
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write);
|
||
|
|
|
||
|
|
--- a/include/linux/bcma/bcma_driver_chipcommon.h
|
||
|
|
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
|
||
|
|
@@ -504,6 +504,9 @@
|
||
|
|
#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
|
||
|
|
#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
|
||
|
|
|
||
|
|
+#define BCMA_CCB_MII_MNG_CTL 0x0000
|
||
|
|
+#define BCMA_CCB_MII_MNG_CMD_DATA 0x0004
|
||
|
|
+
|
||
|
|
/* BCM4331 ChipControl numbers. */
|
||
|
|
#define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
|
||
|
|
#define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
|